1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/malloc.h> 37 #include <sys/resource.h> 38 #include <sys/time.h> 39 #include <sys/callout.h> 40 #include <sys/signalvar.h> 41 #include <sys/eventhandler.h> 42 #include <sys/proc.h> 43 #include <sys/kthread.h> 44 45 #include <sys/mutex.h> 46 #include <sys/module.h> 47 #include <sys/sx.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #ifndef __KERNEL__ 53 #define __KERNEL__ 54 #endif 55 56 #include <dev/hptmv/global.h> 57 #include <dev/hptmv/hptintf.h> 58 #include <dev/hptmv/osbsd.h> 59 #include <dev/hptmv/access601.h> 60 61 62 #ifdef DEBUG 63 #ifdef DEBUG_LEVEL 64 int hpt_dbg_level = DEBUG_LEVEL; 65 #else 66 int hpt_dbg_level = 0; 67 #endif 68 #endif 69 70 #define MV_ERROR printf 71 72 /* 73 * CAM SIM entry points 74 */ 75 static int hpt_probe (device_t dev); 76 static void launch_worker_thread(void); 77 static int hpt_attach(device_t dev); 78 static int hpt_detach(device_t dev); 79 static int hpt_shutdown(device_t dev); 80 static void hpt_poll(struct cam_sim *sim); 81 static void hpt_intr(void *arg); 82 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 83 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 84 85 static device_method_t driver_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, hpt_probe), 88 DEVMETHOD(device_attach, hpt_attach), 89 DEVMETHOD(device_detach, hpt_detach), 90 91 DEVMETHOD(device_shutdown, hpt_shutdown), 92 DEVMETHOD_END 93 }; 94 95 static driver_t hpt_pci_driver = { 96 __str(PROC_DIR_NAME), 97 driver_methods, 98 sizeof(IAL_ADAPTER_T) 99 }; 100 101 static devclass_t hpt_devclass; 102 103 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 104 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 105 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1); 106 107 #define ccb_ccb_ptr spriv_ptr0 108 #define ccb_adapter ccb_h.spriv_ptr1 109 110 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 111 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 112 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 113 static void ccb_done(union ccb *ccb); 114 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 115 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 116 static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter); 117 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 118 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 119 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 120 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 121 static int fResetActiveCommands(PVBus _vbus_p); 122 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 123 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 124 static void hptmv_handle_event_disconnect(void *data); 125 static void hptmv_handle_event_connect(void *data); 126 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 127 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 128 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 129 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 130 int logical); 131 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 132 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 133 MV_U16 responseFlags, MV_U32 timeStamp, 134 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 135 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 136 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 137 138 #define ccb_ccb_ptr spriv_ptr0 139 #define ccb_adapter ccb_h.spriv_ptr1 140 141 static struct sx hptmv_list_lock; 142 SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list"); 143 IAL_ADAPTER_T *gIal_Adapter = NULL; 144 IAL_ADAPTER_T *pCurAdapter = NULL; 145 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 146 147 typedef struct st_HPT_DPC { 148 IAL_ADAPTER_T *pAdapter; 149 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 150 void *arg; 151 UCHAR flags; 152 } ST_HPT_DPC; 153 154 #define MAX_DPC 16 155 UCHAR DPC_Request_Nums = 0; 156 static ST_HPT_DPC DpcQueue[MAX_DPC]; 157 static int DpcQueue_First=0; 158 static int DpcQueue_Last = 0; 159 static struct mtx DpcQueue_Lock; 160 MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF); 161 162 char DRIVER_VERSION[] = "v1.16"; 163 164 /******************************************************************************* 165 * Name: hptmv_free_channel 166 * 167 * Description: free allocated queues for the given channel 168 * 169 * Parameters: pMvSataAdapter - pointer to the RR18xx controller this 170 * channel connected to. 171 * channelNum - channel number. 172 * 173 ******************************************************************************/ 174 static void 175 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 176 { 177 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 178 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 179 } 180 181 static void failDevice(PVDevice pVDev) 182 { 183 PVBus _vbus_p = pVDev->pVBus; 184 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 185 186 pVDev->u.disk.df_on_line = 0; 187 pVDev->vf_online = 0; 188 if (pVDev->pfnDeviceFailed) 189 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 190 191 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 192 193 #ifndef FOR_DEMO 194 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 195 pAdapter->beeping = 1; 196 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 197 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 198 } 199 #endif 200 } 201 202 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 203 204 static void 205 handleEdmaError(_VBUS_ARG PCommand pCmd) 206 { 207 PDevice pDevice = &pCmd->pVDevice->u.disk; 208 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 209 210 if (!pDevice->df_on_line) { 211 KdPrint(("Device is offline")); 212 pCmd->Result = RETURN_BAD_DEVICE; 213 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 214 return; 215 } 216 217 if (pCmd->RetryCount++>5) { 218 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 219 failed: 220 failDevice(pCmd->pVDevice); 221 pCmd->Result = RETURN_IDE_ERROR; 222 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 223 return; 224 } 225 226 /* reset the channel and retry the command */ 227 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 228 goto failed; 229 230 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 231 232 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 233 fDeviceSendCommand(_VBUS_P pCmd); 234 } 235 236 /**************************************************************** 237 * Name: hptmv_init_channel 238 * 239 * Description: allocate request and response queues for the EDMA of the 240 * given channel and sets other fields. 241 * 242 * Parameters: 243 * pAdapter - pointer to the emulated adapter data structure 244 * channelNum - channel number. 245 * Return: 0 on success, otherwise on failure 246 ****************************************************************/ 247 static int 248 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 249 { 250 MV_SATA_CHANNEL *pMvSataChannel; 251 dma_addr_t req_dma_addr; 252 dma_addr_t rsp_dma_addr; 253 254 if (channelNum >= MV_SATA_CHANNELS_NUM) 255 { 256 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 257 pAdapter->mvSataAdapter.adapterId, channelNum); 258 return -1; 259 } 260 261 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 262 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 263 pMvSataChannel->channelNumber = channelNum; 264 pMvSataChannel->lba48Address = MV_FALSE; 265 pMvSataChannel->maxReadTransfer = MV_FALSE; 266 267 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 268 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 269 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 270 271 272 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 273 274 /* check the 1K alignment of the request queue*/ 275 if (req_dma_addr & 0x3ff) 276 { 277 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 278 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 279 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 280 return -1; 281 } 282 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 283 pMvSataChannel->requestQueuePciHiAddress = 0; 284 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 285 pAdapter->mvSataAdapter.adapterId, channelNum, 286 pMvSataChannel->requestQueue)); 287 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 288 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 289 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 290 291 /* check the 256 alignment of the response queue*/ 292 if (rsp_dma_addr & 0xff) 293 { 294 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 295 "aligned, dma_addr=%llx\n", 296 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 297 return -1; 298 } 299 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 300 pMvSataChannel->responseQueuePciHiAddress = 0; 301 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 302 pAdapter->mvSataAdapter.adapterId, channelNum, 303 pMvSataChannel->responseQueue)); 304 305 pAdapter->mvChannel[channelNum].online = MV_TRUE; 306 return 0; 307 } 308 309 /****************************************************************************** 310 * Name: hptmv_parse_identify_results 311 * 312 * Description: this functions parses the identify command results, checks 313 * that the connected deives can be accesed by RR18xx EDMA, 314 * and updates the channel structure accordingly. 315 * 316 * Parameters: pMvSataChannel, pointer to the channel data structure. 317 * 318 * Returns: =0 ->success, < 0 ->failure. 319 * 320 ******************************************************************************/ 321 static int 322 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 323 { 324 MV_U16 *iden = pMvSataChannel->identifyDevice; 325 326 /*LBA addressing*/ 327 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 328 { 329 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 330 return -1; 331 } 332 else 333 { 334 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 335 } 336 /*DMA support*/ 337 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 338 { 339 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 340 return -1; 341 } 342 else 343 { 344 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 345 } 346 /* PIO */ 347 if ((iden[IDEN_VALID] & 2) == 0) 348 { 349 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 350 return -1; 351 } 352 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 353 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 354 355 /*UDMA*/ 356 if ((iden[IDEN_VALID] & 4) == 0) 357 { 358 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 359 return -1; 360 } 361 362 /* 48 bit address */ 363 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 364 { 365 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 366 pMvSataChannel->lba48Address = MV_TRUE; 367 } 368 else 369 { 370 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 371 pMvSataChannel->lba48Address = MV_FALSE; 372 } 373 return 0; 374 } 375 376 static void 377 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 378 { 379 PVDevice pVDev = &pAdapter->VDevices[channel]; 380 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 381 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 382 383 pMvSataChannel->outstandingCommands = 0; 384 385 pVDev->u.disk.mv = pMvSataChannel; 386 pVDev->u.disk.df_on_line = 1; 387 pVDev->u.disk.pVBus = &pAdapter->VBus; 388 pVDev->pVBus = &pAdapter->VBus; 389 390 #ifdef SUPPORT_48BIT_LBA 391 if (pMvSataChannel->lba48Address == MV_TRUE) 392 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 393 else 394 #endif 395 if(IdentifyData[53] & 1) { 396 pVDev->u.disk.dDeRealCapacity = 397 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 398 (IdentifyData[61]<<16 | IdentifyData[60]) : 399 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 400 } else 401 pVDev->u.disk.dDeRealCapacity = 402 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 403 404 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 405 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 406 407 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 408 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 409 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 410 } 411 } 412 413 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 414 { 415 PVDevice pVDev; 416 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 417 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 418 419 if (!pMvSataChannel) return; 420 421 if (plugged) 422 { 423 pVDev = &(pAdapter->VDevices[channelIndex]); 424 init_vdev_params(pAdapter, channelIndex); 425 426 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 427 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 428 429 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 430 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 431 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 432 pVDev->vf_online = 1; 433 434 #ifdef SUPPORT_ARRAY 435 if(pVDev->pParent) 436 { 437 int iMember; 438 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 439 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 440 pVDev->pParent->u.array.pMember[iMember] = NULL; 441 pVDev->pParent = NULL; 442 } 443 #endif 444 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 445 fCheckBootable(pVDev); 446 RegisterVDevice(pVDev); 447 448 #ifndef FOR_DEMO 449 if (pAdapter->beeping) { 450 pAdapter->beeping = 0; 451 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 452 } 453 #endif 454 455 } 456 else 457 { 458 pVDev = &(pAdapter->VDevices[channelIndex]); 459 failDevice(pVDev); 460 } 461 } 462 463 static int 464 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 465 { 466 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 467 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 468 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 469 MV_U32 udmaMode,pioMode; 470 471 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 472 channelNum)); 473 474 475 /* Software reset channel */ 476 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 477 { 478 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 479 pMvSataAdapter->adapterId, channelNum); 480 return -1; 481 } 482 483 /* Hardware reset channel */ 484 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 485 { 486 /* If failed, try again - this is when trying to hardreset a channel */ 487 /* when drive is just spinning up */ 488 StallExec(5000000); /* wait 5 sec before trying again */ 489 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 490 { 491 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 492 pMvSataAdapter->adapterId, channelNum); 493 return -1; 494 } 495 } 496 497 /* identify device*/ 498 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 499 { 500 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 501 , pMvSataAdapter->adapterId, channelNum); 502 return -1; 503 } 504 if (hptmv_parse_identify_results(pMvSataChannel)) 505 { 506 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 507 , pMvSataAdapter->adapterId, channelNum); 508 return -1; 509 } 510 511 /* mvStorageDevATASetFeatures */ 512 /* Disable 8 bit PIO in case CFA enabled */ 513 if (pMvSataChannel->identifyDevice[86] & 4) 514 { 515 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 516 pMvSataAdapter->adapterId)); 517 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 518 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 519 0, 0, 0) == MV_FALSE) 520 { 521 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 522 " failed\n", pMvSataAdapter->adapterId, channelNum); 523 return -1; 524 } 525 } 526 /* Write cache */ 527 #ifdef ENABLE_WRITE_CACHE 528 if (pMvSataChannel->identifyDevice[82] & 0x20) 529 { 530 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 531 { 532 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 533 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 534 0, 0, 0) == MV_FALSE) 535 { 536 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 537 pMvSataAdapter->adapterId, channelNum); 538 return -1; 539 } 540 } 541 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 542 pMvSataAdapter->adapterId, channelNum)); 543 } 544 else 545 { 546 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 547 pMvSataAdapter->adapterId, channelNum)); 548 } 549 #else /* disable write cache */ 550 { 551 if (pMvSataChannel->identifyDevice[85] & 0x20) 552 { 553 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 554 pMvSataAdapter->adapterId, channelNum)); 555 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 556 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 557 0, 0, 0) == MV_FALSE) 558 { 559 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 560 pMvSataAdapter->adapterId, channelNum); 561 return -1; 562 } 563 } 564 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 565 pMvSataAdapter->adapterId, channelNum)); 566 } 567 #endif 568 569 /* Set transfer mode */ 570 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 571 pMvSataAdapter->adapterId)); 572 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 573 MV_ATA_SET_FEATURES_TRANSFER, 574 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 575 MV_FALSE) 576 { 577 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 578 pMvSataAdapter->adapterId, channelNum); 579 return -1; 580 } 581 582 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 583 { 584 pioMode = MV_ATA_TRANSFER_PIO_4; 585 } 586 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 587 { 588 pioMode = MV_ATA_TRANSFER_PIO_3; 589 } 590 else 591 { 592 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 593 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 594 } 595 596 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 597 pMvSataAdapter->adapterId)); 598 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 599 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 600 MV_ATA_SET_FEATURES_TRANSFER, 601 pioMode, 0, 0, 0) == MV_FALSE) 602 { 603 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 604 pMvSataAdapter->adapterId, channelNum); 605 return -1; 606 } 607 608 udmaMode = MV_ATA_TRANSFER_UDMA_0; 609 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 610 { 611 udmaMode = MV_ATA_TRANSFER_UDMA_6; 612 } 613 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 614 { 615 udmaMode = MV_ATA_TRANSFER_UDMA_5; 616 } 617 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 618 { 619 udmaMode = MV_ATA_TRANSFER_UDMA_4; 620 } 621 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 622 { 623 udmaMode = MV_ATA_TRANSFER_UDMA_3; 624 } 625 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 626 { 627 udmaMode = MV_ATA_TRANSFER_UDMA_2; 628 } 629 630 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 631 pMvSataAdapter->adapterId, udmaMode & 0xf)); 632 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 633 634 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 635 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 636 0, 0, 0) == MV_FALSE) 637 { 638 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 639 pMvSataAdapter->adapterId, channelNum); 640 return -1; 641 }*/ 642 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 643 return TRUE; 644 else 645 do 646 { 647 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 648 MV_ATA_SET_FEATURES_TRANSFER, 649 pChannelInfo->maxUltraDmaModeSupported, 650 0, 0, 0) == MV_FALSE) 651 { 652 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 653 { 654 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 655 { 656 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 657 pMvSataChannel->eDmaRegsOffset + 658 0x11c, /* command reg */ 659 MV_ATA_COMMAND_IDLE_IMMEDIATE); 660 mvMicroSecondsDelay(10000); 661 mvSataChannelHardReset(pMvSataAdapter, channelNum); 662 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 663 return FALSE; 664 } 665 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 666 return FALSE; 667 pChannelInfo->maxUltraDmaModeSupported--; 668 continue; 669 } 670 else return FALSE; 671 } 672 break; 673 }while (1); 674 675 /* Read look ahead */ 676 #ifdef ENABLE_READ_AHEAD 677 if (pMvSataChannel->identifyDevice[82] & 0x40) 678 { 679 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 680 { 681 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 682 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 683 0, 0) == MV_FALSE) 684 { 685 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 686 pMvSataAdapter->adapterId, channelNum); 687 return -1; 688 } 689 } 690 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 691 pMvSataAdapter->adapterId, channelNum)); 692 } 693 else 694 { 695 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 696 pMvSataAdapter->adapterId, channelNum)); 697 } 698 #else 699 { 700 if (pMvSataChannel->identifyDevice[86] & 0x20) 701 { 702 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 703 pMvSataAdapter->adapterId, channelNum)); 704 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 705 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 706 0, 0) == MV_FALSE) 707 { 708 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 709 pMvSataAdapter->adapterId, channelNum); 710 return -1; 711 } 712 } 713 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 714 pMvSataAdapter->adapterId, channelNum)); 715 } 716 #endif 717 718 719 { 720 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 721 pMvSataAdapter->adapterId, 722 channelNum)); 723 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 724 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 725 { 726 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 727 pMvSataAdapter->adapterId, channelNum); 728 return -1; 729 } 730 } 731 /* Enable EDMA */ 732 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 733 { 734 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 735 pMvSataAdapter->adapterId, channelNum); 736 return -1; 737 } 738 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 739 pMvSataAdapter->adapterId, channelNum); 740 741 #ifndef FOR_DEMO 742 set_fail_led(pMvSataAdapter, channelNum, 0); 743 #endif 744 return 0; 745 } 746 747 static void 748 hptmv_handle_event(void * data, int flag) 749 { 750 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 751 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 752 MV_U8 channelIndex; 753 754 mtx_assert(&pAdapter->lock, MA_OWNED); 755 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 756 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 757 { 758 switch(pAdapter->sataEvents[channelIndex]) 759 { 760 case SATA_EVENT_CHANNEL_CONNECTED: 761 /* Handle only connects */ 762 if (flag == 1) 763 break; 764 KdPrint(("RR18xx [%d,%d]: new device connected\n", 765 pMvSataAdapter->adapterId, channelIndex)); 766 hptmv_init_channel(pAdapter, channelIndex); 767 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 768 { 769 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 770 pMvSataAdapter->adapterId, channelIndex); 771 hptmv_free_channel(pAdapter, channelIndex); 772 } 773 else 774 { 775 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 776 if (start_channel( pAdapter, channelIndex)) 777 { 778 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 779 pMvSataAdapter->adapterId, channelIndex); 780 hptmv_free_channel(pAdapter, channelIndex); 781 } 782 else 783 { 784 device_change(pAdapter, channelIndex, TRUE); 785 } 786 } 787 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 788 break; 789 790 case SATA_EVENT_CHANNEL_DISCONNECTED: 791 /* Handle only disconnects */ 792 if (flag == 0) 793 break; 794 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 795 pMvSataAdapter->adapterId, channelIndex)); 796 /* Flush pending commands */ 797 if(pMvSataAdapter->sataChannel[channelIndex]) 798 { 799 _VBUS_INST(&pAdapter->VBus) 800 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 801 MV_FLUSH_TYPE_CALLBACK); 802 CheckPendingCall(_VBUS_P0); 803 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 804 hptmv_free_channel(pAdapter, channelIndex); 805 pMvSataAdapter->sataChannel[channelIndex] = NULL; 806 KdPrint(("RR18xx [%d,%d]: channel removed\n", 807 pMvSataAdapter->adapterId, channelIndex)); 808 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 809 Check_Idle_Call(pAdapter); 810 } 811 else 812 { 813 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 814 pMvSataAdapter->adapterId, channelIndex)); 815 } 816 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 817 break; 818 819 case SATA_EVENT_NO_CHANGE: 820 break; 821 822 default: 823 break; 824 } 825 } 826 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 827 } 828 829 #define EVENT_CONNECT 1 830 #define EVENT_DISCONNECT 0 831 832 static void 833 hptmv_handle_event_connect(void *data) 834 { 835 hptmv_handle_event (data, 0); 836 } 837 838 static void 839 hptmv_handle_event_disconnect(void *data) 840 { 841 hptmv_handle_event (data, 1); 842 } 843 844 static MV_BOOLEAN 845 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 846 MV_U32 param1, MV_U32 param2) 847 { 848 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 849 850 switch (eventType) 851 { 852 case MV_EVENT_TYPE_SATA_CABLE: 853 { 854 MV_U8 channel = param2; 855 856 if (param1 == EVENT_CONNECT) 857 { 858 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 859 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 860 pMvSataAdapter->adapterId, channel)); 861 /* Delete previous timers (if multiple drives connected in the same time */ 862 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter); 863 } 864 else if (param1 == EVENT_DISCONNECT) 865 { 866 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 867 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 868 pMvSataAdapter->adapterId, channel)); 869 device_change(pAdapter, channel, FALSE); 870 /* Delete previous timers (if multiple drives disconnected in the same time */ 871 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */ 872 /*It is not necessary to wait, handle it directly*/ 873 hptmv_handle_event_disconnect(pAdapter); 874 } 875 else 876 { 877 878 MV_ERROR("RR18xx: illegal value for param1(%d) at " 879 "connect/disconnect event, host=%d\n", param1, 880 pMvSataAdapter->adapterId ); 881 882 } 883 } 884 break; 885 case MV_EVENT_TYPE_ADAPTER_ERROR: 886 KdPrint(("RR18xx: DEVICE error event received, pci cause " 887 "reg=%x, don't how to handle this\n", param1)); 888 return MV_TRUE; 889 default: 890 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 891 pMvSataAdapter->adapterId, eventType); 892 return MV_FALSE; 893 } 894 return MV_TRUE; 895 } 896 897 static int 898 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 899 { 900 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 901 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 902 if (pAdapter->requestsArrayBaseAddr == NULL) 903 { 904 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 905 " queues\n", pAdapter->mvSataAdapter.adapterId); 906 return -1; 907 } 908 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 909 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 910 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 911 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 912 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 913 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 914 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 915 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 916 917 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 918 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 919 { 920 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 921 pAdapter->mvSataAdapter.adapterId); 922 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 923 return -1; 924 } 925 /* response queues */ 926 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 927 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 928 if (pAdapter->responsesArrayBaseAddr == NULL) 929 { 930 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 931 " queues\n", pAdapter->mvSataAdapter.adapterId); 932 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 933 return -1; 934 } 935 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 936 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 937 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 938 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 939 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 940 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 941 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 942 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 943 944 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 945 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 946 { 947 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n", 948 pAdapter->mvSataAdapter.adapterId); 949 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 950 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 951 return -1; 952 } 953 return 0; 954 } 955 956 static void 957 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 958 { 959 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 960 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 961 } 962 963 static PVOID 964 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 965 { 966 PVOID ret; 967 if (pAdapter->pFreePRDLink) { 968 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 969 ret = pAdapter->pFreePRDLink; 970 pAdapter->pFreePRDLink = *(void**)ret; 971 return ret; 972 } 973 return NULL; 974 } 975 976 static void 977 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 978 { 979 *(void**)PRDTable = pAdapter->pFreePRDLink; 980 pAdapter->pFreePRDLink = PRDTable; 981 } 982 983 extern PVDevice fGetFirstChild(PVDevice pLogical); 984 extern void fResetBootMark(PVDevice pLogical); 985 static void 986 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 987 { 988 PVDevice pPhysical, pLogical; 989 PVBus pVBus; 990 int i,j; 991 992 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 993 pPhysical = &(pAdapter->VDevices[i]); 994 pLogical = pPhysical; 995 while (pLogical->pParent) pLogical = pLogical->pParent; 996 if (pLogical->vf_online==0) { 997 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 998 continue; 999 } 1000 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1001 continue; 1002 1003 pVBus = &pAdapter->VBus; 1004 if(pVBus) 1005 { 1006 j=0; 1007 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1008 if(j<MAX_VDEVICE_PER_VBUS){ 1009 pVBus->pVDevice[j] = pLogical; 1010 pLogical->pVBus = pVBus; 1011 1012 if (j>0 && pLogical->vf_bootmark) { 1013 if (pVBus->pVDevice[0]->vf_bootmark) { 1014 fResetBootMark(pLogical); 1015 } 1016 else { 1017 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1018 pVBus->pVDevice[0] = pLogical; 1019 } 1020 } 1021 } 1022 } 1023 } 1024 } 1025 1026 PVDevice 1027 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1028 { 1029 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1030 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1031 LBA_T thiscap, maxcap = MAX_LBA_T; 1032 PVDevice pVDevice, pFind = NULL; 1033 int i; 1034 1035 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1036 { 1037 pVDevice = &pAdapter->VDevices[i]; 1038 if(!pVDevice) 1039 continue; 1040 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1041 /* find the smallest usable spare disk */ 1042 if (pVDevice->VDeviceType==VD_SPARE && 1043 pVDevice->u.disk.df_on_line && 1044 thiscap < maxcap && 1045 thiscap >= capacity) 1046 { 1047 maxcap = pVDevice->VDeviceCapacity; 1048 pFind = pVDevice; 1049 } 1050 } 1051 return pFind; 1052 } 1053 1054 /****************************************************************** 1055 * IO ATA Command 1056 *******************************************************************/ 1057 int HPTLIBAPI 1058 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1059 { 1060 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1061 } 1062 1063 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1064 { 1065 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1066 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1067 MV_U8 channelIndex = pSataChannel->channelNumber; 1068 UCHAR mvMode; 1069 /* 508x don't use MW-DMA? */ 1070 if (NewMode>4 && NewMode<8) NewMode = 4; 1071 pDev->bDeModeSetting = NewMode; 1072 if (NewMode<=4) 1073 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1074 else 1075 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1076 1077 /*To fix 88i8030 bug*/ 1078 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1079 mvMode = MV_ATA_TRANSFER_UDMA_0; 1080 1081 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1082 /* Flush pending commands */ 1083 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1084 1085 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1086 MV_ATA_SET_FEATURES_TRANSFER, 1087 mvMode, 0, 0, 0) == MV_FALSE) 1088 { 1089 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1090 } 1091 /* Enable EDMA */ 1092 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1093 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1094 } 1095 1096 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1097 { 1098 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1099 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1100 MV_U8 channelIndex = pSataChannel->channelNumber; 1101 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1102 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1103 int dmaActive = pSataChannel->queueCommandsEnabled; 1104 int ret = 0; 1105 1106 if (dmaActive) { 1107 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1108 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1109 } 1110 1111 if (enable) { 1112 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1113 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1114 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1115 channelInfo->queueDepth = (depth==32)? 31 : depth; 1116 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1117 ret = 1; 1118 } 1119 } 1120 else 1121 { 1122 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1123 channelInfo->queueDepth = 2; 1124 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1125 ret = 1; 1126 } 1127 } 1128 1129 if (dmaActive) 1130 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1131 return ret; 1132 } 1133 1134 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1135 { 1136 return 0; 1137 } 1138 1139 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1140 { 1141 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1142 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1143 MV_U8 channelIndex = pSataChannel->channelNumber; 1144 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1145 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1146 int dmaActive = pSataChannel->queueCommandsEnabled; 1147 int ret = 0; 1148 1149 if (dmaActive) { 1150 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1151 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1152 } 1153 1154 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1155 if (enable) { 1156 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1157 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1158 { 1159 channelInfo->writeCacheEnabled = MV_TRUE; 1160 ret = 1; 1161 } 1162 } 1163 else { 1164 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1165 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1166 { 1167 channelInfo->writeCacheEnabled = MV_FALSE; 1168 ret = 1; 1169 } 1170 } 1171 } 1172 1173 if (dmaActive) 1174 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1175 return ret; 1176 } 1177 1178 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1179 { 1180 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1181 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1182 MV_U8 channelIndex = pSataChannel->channelNumber; 1183 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1184 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1185 int dmaActive = pSataChannel->queueCommandsEnabled; 1186 int ret = 0; 1187 1188 if (dmaActive) { 1189 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1190 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1191 } 1192 1193 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1194 if (enable) { 1195 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1196 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1197 { 1198 channelInfo->readAheadEnabled = MV_TRUE; 1199 ret = 1; 1200 } 1201 } 1202 else { 1203 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1204 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1205 { 1206 channelInfo->readAheadEnabled = MV_FALSE; 1207 ret = 1; 1208 } 1209 } 1210 } 1211 1212 if (dmaActive) 1213 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1214 return ret; 1215 } 1216 1217 #ifdef SUPPORT_ARRAY 1218 #define IdeRegisterVDevice fCheckArray 1219 #else 1220 void 1221 IdeRegisterVDevice(PDevice pDev) 1222 { 1223 PVDevice pVDev = Map2pVDevice(pDev); 1224 1225 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1226 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1227 pVDev->vf_online = 1; 1228 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1229 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1230 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1231 } 1232 #endif 1233 1234 static __inline PBUS_DMAMAP 1235 dmamap_get(struct IALAdapter * pAdapter) 1236 { 1237 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1238 if (p) 1239 pAdapter->pbus_dmamap_list = p-> next; 1240 return p; 1241 } 1242 1243 static __inline void 1244 dmamap_put(PBUS_DMAMAP p) 1245 { 1246 p->next = p->pAdapter->pbus_dmamap_list; 1247 p->pAdapter->pbus_dmamap_list = p; 1248 } 1249 1250 static int num_adapters = 0; 1251 static int 1252 init_adapter(IAL_ADAPTER_T *pAdapter) 1253 { 1254 PVBus _vbus_p = &pAdapter->VBus; 1255 MV_SATA_ADAPTER *pMvSataAdapter; 1256 int i, channel, rid; 1257 1258 PVDevice pVDev; 1259 1260 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF); 1261 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0); 1262 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0); 1263 1264 sx_xlock(&hptmv_list_lock); 1265 pAdapter->next = 0; 1266 1267 if(gIal_Adapter == NULL){ 1268 gIal_Adapter = pAdapter; 1269 pCurAdapter = gIal_Adapter; 1270 } 1271 else { 1272 pCurAdapter->next = pAdapter; 1273 pCurAdapter = pAdapter; 1274 } 1275 sx_xunlock(&hptmv_list_lock); 1276 1277 pAdapter->outstandingCommands = 0; 1278 1279 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1280 _vbus_p->OsExt = (void *)pAdapter; 1281 pMvSataAdapter->IALData = pAdapter; 1282 1283 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */ 1284 4, /* alignment */ 1285 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1286 BUS_SPACE_MAXADDR, /* lowaddr */ 1287 BUS_SPACE_MAXADDR, /* highaddr */ 1288 NULL, NULL, /* filter, filterarg */ 1289 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1290 MAX_SG_DESCRIPTORS, /* nsegments */ 1291 0x10000, /* maxsegsize */ 1292 BUS_DMA_WAITOK, /* flags */ 1293 busdma_lock_mutex, /* lockfunc */ 1294 &pAdapter->lock, /* lockfuncarg */ 1295 &pAdapter->io_dma_parent /* tag */)) 1296 { 1297 return ENXIO; 1298 } 1299 1300 1301 if (hptmv_allocate_edma_queues(pAdapter)) 1302 { 1303 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1304 return ENOMEM; 1305 } 1306 1307 /* also map EPROM address */ 1308 rid = 0x10; 1309 if (!(pAdapter->mem_res = bus_alloc_resource_any(pAdapter->hpt_dev, 1310 SYS_RES_MEMORY, &rid, RF_ACTIVE)) 1311 || 1312 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1313 { 1314 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1315 hptmv_free_edma_queues(pAdapter); 1316 return ENXIO; 1317 } 1318 else 1319 { 1320 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1321 } 1322 1323 pMvSataAdapter->adapterId = num_adapters++; 1324 /* get the revision ID */ 1325 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1326 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1327 1328 /* init RR18xx */ 1329 pMvSataAdapter->intCoalThre[0]= 1; 1330 pMvSataAdapter->intCoalThre[1]= 1; 1331 pMvSataAdapter->intTimeThre[0] = 1; 1332 pMvSataAdapter->intTimeThre[1] = 1; 1333 pMvSataAdapter->pciCommand = 0x0107E371; 1334 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1335 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1336 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1337 1338 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1339 { 1340 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1341 pMvSataAdapter->adapterId); 1342 unregister: 1343 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1344 hptmv_free_edma_queues(pAdapter); 1345 return ENXIO; 1346 } 1347 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1348 1349 #ifndef FOR_DEMO 1350 set_fail_leds(pMvSataAdapter, 0); 1351 #endif 1352 1353 /* setup command blocks */ 1354 KdPrint(("Allocate command blocks\n")); 1355 _vbus_(pFreeCommands) = 0; 1356 pAdapter->pCommandBlocks = 1357 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1358 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1359 if (!pAdapter->pCommandBlocks) { 1360 MV_ERROR("insufficient memory\n"); 1361 goto unregister; 1362 } 1363 1364 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1365 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1366 } 1367 1368 /*Set up the bus_dmamap*/ 1369 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1370 if(!pAdapter->pbus_dmamap) { 1371 MV_ERROR("insufficient memory\n"); 1372 free(pAdapter->pCommandBlocks, M_DEVBUF); 1373 goto unregister; 1374 } 1375 1376 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1377 pAdapter->pbus_dmamap_list = 0; 1378 for (i=0; i < MAX_QUEUE_COMM; i++) { 1379 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1380 pmap->pAdapter = pAdapter; 1381 dmamap_put(pmap); 1382 1383 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1384 MV_ERROR("Can not allocate dma map\n"); 1385 free(pAdapter->pCommandBlocks, M_DEVBUF); 1386 free(pAdapter->pbus_dmamap, M_DEVBUF); 1387 goto unregister; 1388 } 1389 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0); 1390 } 1391 /* setup PRD Tables */ 1392 KdPrint(("Allocate PRD Tables\n")); 1393 pAdapter->pFreePRDLink = 0; 1394 1395 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1396 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1397 1398 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1399 if (!pAdapter->prdTableAddr) { 1400 MV_ERROR("insufficient PRD Tables\n"); 1401 goto unregister; 1402 } 1403 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1404 { 1405 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1406 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1407 { 1408 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1409 FreePRDTable(pAdapter, PRDTable); 1410 PRDTable += PRD_ENTRIES_SIZE; 1411 } 1412 } 1413 1414 /* enable the adapter interrupts */ 1415 1416 /* configure and start the connected channels*/ 1417 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1418 { 1419 pAdapter->mvChannel[channel].online = MV_FALSE; 1420 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1421 == MV_TRUE) 1422 { 1423 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1424 pMvSataAdapter->adapterId, channel)); 1425 1426 if (hptmv_init_channel(pAdapter, channel) == 0) 1427 { 1428 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1429 { 1430 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1431 " %d\n",pMvSataAdapter->adapterId, channel); 1432 hptmv_free_channel(pAdapter, channel); 1433 } 1434 else 1435 { 1436 if (start_channel(pAdapter, channel)) 1437 { 1438 MV_ERROR("RR18xx[%d]: Failed to start channel," 1439 " channel=%d\n",pMvSataAdapter->adapterId, 1440 channel); 1441 hptmv_free_channel(pAdapter, channel); 1442 } 1443 pAdapter->mvChannel[channel].online = MV_TRUE; 1444 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1445 channel, 1446 MV_TRUE);*/ 1447 } 1448 } 1449 } 1450 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1451 pAdapter->mvChannel[channel].online, channel)); 1452 } 1453 1454 #ifdef SUPPORT_ARRAY 1455 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1456 pVDev = ArrayTables(i); 1457 mArFreeArrayTable(pVDev); 1458 } 1459 #endif 1460 1461 KdPrint(("Initialize Devices\n")); 1462 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1463 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1464 if (pMvSataChannel) { 1465 init_vdev_params(pAdapter, channel); 1466 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1467 } 1468 } 1469 #ifdef SUPPORT_ARRAY 1470 CheckArrayCritical(_VBUS_P0); 1471 #endif 1472 _vbus_p->nInstances = 1; 1473 fRegisterVdevice(pAdapter); 1474 1475 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1476 pVDev = _vbus_p->pVDevice[channel]; 1477 if (pVDev && pVDev->vf_online) 1478 fCheckBootable(pVDev); 1479 } 1480 1481 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1482 init_raid5_memory(_VBUS_P0); 1483 _vbus_(r5).enable_write_back = 1; 1484 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1485 #endif 1486 1487 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1488 return 0; 1489 } 1490 1491 int 1492 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1493 { 1494 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1495 1496 mvSataDisableChannelDma(pMvSataAdapter, channel); 1497 /* Flush pending commands */ 1498 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1499 1500 /* Software reset channel */ 1501 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1502 { 1503 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1504 pMvSataAdapter->adapterId, channel); 1505 hptmv_free_channel(pAdapter, channel); 1506 return -1; 1507 } 1508 1509 /* Hardware reset channel */ 1510 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1511 { 1512 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1513 pMvSataAdapter->adapterId, channel); 1514 hptmv_free_channel(pAdapter, channel); 1515 return -1; 1516 } 1517 1518 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1519 { 1520 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1521 pMvSataAdapter->adapterId, channel); 1522 hptmv_free_channel(pAdapter, channel); 1523 return -1; 1524 }else 1525 { 1526 MV_ERROR("channel %d: perform recalibrate command", channel); 1527 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1528 MV_NON_UDMA_PROTOCOL_NON_DATA, 1529 MV_FALSE, 1530 NULL, /* pBuffer*/ 1531 0, /* count */ 1532 0, /*features*/ 1533 /* sectorCount */ 1534 0, 1535 0, /* lbaLow */ 1536 0, /* lbaMid */ 1537 /* lbaHigh */ 1538 0, 1539 0, /* device */ 1540 /* command */ 1541 0x10)) 1542 MV_ERROR("channel %d: recalibrate failed", channel); 1543 1544 /* Set transfer mode */ 1545 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1546 MV_ATA_SET_FEATURES_TRANSFER, 1547 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1548 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1549 MV_ATA_SET_FEATURES_TRANSFER, 1550 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1551 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1552 MV_ATA_SET_FEATURES_TRANSFER, 1553 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1554 { 1555 MV_ERROR("channel %d: Set Features failed", channel); 1556 hptmv_free_channel(pAdapter, channel); 1557 return -1; 1558 } 1559 /* Enable EDMA */ 1560 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1561 { 1562 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1563 hptmv_free_channel(pAdapter, channel); 1564 return -1; 1565 } 1566 } 1567 return 0; 1568 } 1569 1570 static int 1571 fResetActiveCommands(PVBus _vbus_p) 1572 { 1573 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1574 MV_U8 channel; 1575 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1576 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1577 MvSataResetChannel(pMvSataAdapter,channel); 1578 } 1579 return 0; 1580 } 1581 1582 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1583 { 1584 UINT cont; 1585 ULONG ticks = 0; 1586 MV_U8 channel; 1587 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1588 MV_SATA_CHANNEL *pMvSataChannel; 1589 1590 do { 1591 check_cmds: 1592 cont = 0; 1593 CheckPendingCall(_VBUS_P0); 1594 #ifdef _RAID5N_ 1595 dataxfer_poll(); 1596 xor_poll(); 1597 #endif 1598 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1599 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1600 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1601 { 1602 while (pMvSataChannel->outstandingCommands) { 1603 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1604 StallExec(1000); 1605 if (ticks++ > 3000) { 1606 MvSataResetChannel(pMvSataAdapter,channel); 1607 goto check_cmds; 1608 } 1609 } 1610 else 1611 ticks = 0; 1612 } 1613 cont = 1; 1614 } 1615 } 1616 } while (cont); 1617 } 1618 1619 void 1620 fResetVBus(_VBUS_ARG0) 1621 { 1622 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1623 1624 /* some commands may already finished. */ 1625 CheckPendingCall(_VBUS_P0); 1626 1627 fResetActiveCommands(_vbus_p); 1628 /* 1629 * the other pending commands may still be finished successfully. 1630 */ 1631 fCompleteAllCommandsSynchronously(_vbus_p); 1632 1633 /* Now there should be no pending commands. No more action needed. */ 1634 CheckIdleCall(_VBUS_P0); 1635 1636 KdPrint(("fMvResetBus() done")); 1637 } 1638 1639 /*No rescan function*/ 1640 void 1641 fRescanAllDevice(_VBUS_ARG0) 1642 { 1643 } 1644 1645 static MV_BOOLEAN 1646 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1647 MV_U8 channelNum, 1648 MV_COMPLETION_TYPE comp_type, 1649 MV_VOID_PTR commandId, 1650 MV_U16 responseFlags, 1651 MV_U32 timeStamp, 1652 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1653 { 1654 PCommand pCmd = (PCommand) commandId; 1655 _VBUS_INST(pCmd->pVDevice->pVBus) 1656 1657 if (pCmd->uScratch.sata_param.prdAddr) 1658 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1659 1660 switch (comp_type) 1661 { 1662 case MV_COMPLETION_TYPE_NORMAL: 1663 pCmd->Result = RETURN_SUCCESS; 1664 break; 1665 case MV_COMPLETION_TYPE_ABORT: 1666 pCmd->Result = RETURN_BUS_RESET; 1667 break; 1668 case MV_COMPLETION_TYPE_ERROR: 1669 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1670 pMvSataAdapter->adapterId, channelNum, responseFlags); 1671 1672 if (responseFlags & 4) { 1673 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1674 " LBA high %x, device %x, status %x\n", 1675 registerStruct->errorRegister, 1676 registerStruct->sectorCountRegister, 1677 registerStruct->lbaLowRegister, 1678 registerStruct->lbaMidRegister, 1679 registerStruct->lbaHighRegister, 1680 registerStruct->deviceRegister, 1681 registerStruct->statusRegister); 1682 } 1683 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1684 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1685 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1686 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1687 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1688 pCmd->pVDevice->u.disk.QueueLength--; 1689 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1690 return TRUE; 1691 1692 default: 1693 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1694 return MV_FALSE; 1695 } 1696 1697 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1698 pCmd->uScratch.sata_param.cmd_priv --; 1699 return TRUE; 1700 } 1701 pCmd->pVDevice->u.disk.QueueLength--; 1702 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1703 return TRUE; 1704 } 1705 1706 void 1707 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1708 { 1709 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1710 MV_SATA_ADAPTER *pMvSataAdapter; 1711 MV_SATA_CHANNEL *pMvSataChannel; 1712 PVDevice pVDevice = pCmd->pVDevice; 1713 PDevice pDevice = &pVDevice->u.disk; 1714 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1715 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1716 1717 MV_QUEUE_COMMAND_RESULT result; 1718 MV_QUEUE_COMMAND_INFO commandInfo; 1719 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1720 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1721 1722 MV_BOOLEAN is48bit; 1723 MV_U8 channel; 1724 int i=0; 1725 1726 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1727 1728 if (!pDevice->df_on_line) { 1729 MV_ERROR("Device is offline"); 1730 pCmd->Result = RETURN_BAD_DEVICE; 1731 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1732 return; 1733 } 1734 1735 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1736 pMvSataChannel = pDevice->mv; 1737 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1738 channel = pMvSataChannel->channelNumber; 1739 1740 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1741 Lba += pDevice->dDeHiddenLba; 1742 /* check LBA */ 1743 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1744 pCmd->Result = RETURN_INVALID_REQUEST; 1745 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1746 return; 1747 } 1748 1749 /* 1750 * always use 48bit LBA if drive supports it. 1751 * Some Seagate drives report error if you use a 28-bit command 1752 * to access sector 0xfffffff. 1753 */ 1754 is48bit = pMvSataChannel->lba48Address; 1755 1756 switch (pCmd->uCmd.Ide.Command) 1757 { 1758 case IDE_COMMAND_READ: 1759 case IDE_COMMAND_WRITE: 1760 if (pDevice->bDeModeSetting<8) goto pio; 1761 1762 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1763 pUdmaParams->isEXT = is48bit; 1764 pUdmaParams->numOfSectors = nSector; 1765 pUdmaParams->lowLBAAddress = Lba; 1766 pUdmaParams->highLBAAddress = 0; 1767 pUdmaParams->prdHighAddr = 0; 1768 pUdmaParams->callBack = CommandCompletionCB; 1769 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1770 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1771 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1772 else 1773 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1774 1775 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1776 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1777 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1778 } 1779 else { 1780 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1781 pio: 1782 mvSataDisableChannelDma(pMvSataAdapter, channel); 1783 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1784 1785 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1786 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1787 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1788 } 1789 else { 1790 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1791 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1792 goto finish_cmd; 1793 } 1794 } 1795 1796 do { 1797 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1798 ULONG_PTR addr = tmpSg->dSgAddress; 1799 if (size & 0x1ff) { 1800 pCmd->Result = RETURN_INVALID_REQUEST; 1801 goto finish_cmd; 1802 } 1803 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1804 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1805 is48bit, 1806 (MV_U16_PTR)addr, 1807 size >> 1, /* count */ 1808 0, /* features N/A */ 1809 (MV_U16)(size>>9), /*sector count*/ 1810 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1811 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1812 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1813 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1814 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1815 )==MV_FALSE) 1816 { 1817 pCmd->Result = RETURN_IDE_ERROR; 1818 goto finish_cmd; 1819 } 1820 Lba += size>>9; 1821 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1822 } 1823 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1824 pCmd->Result = RETURN_SUCCESS; 1825 finish_cmd: 1826 mvSataEnableChannelDma(pMvSataAdapter,channel); 1827 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1828 return; 1829 } 1830 } 1831 1832 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1833 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1834 if (!pPRDTable) { 1835 pCmd->Result = RETURN_DEVICE_BUSY; 1836 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1837 HPT_ASSERT(0); 1838 return; 1839 } 1840 1841 do{ 1842 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1843 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1844 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1845 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1846 pPRDTable[i].reserved = 0; 1847 i++; 1848 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1849 1850 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1851 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1852 pUdmaParams->numOfSectors = 0; 1853 } 1854 1855 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1856 1857 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1858 1859 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1860 { 1861 queue_failed: 1862 switch (result) 1863 { 1864 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1865 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1866 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1867 pCmd->Result = RETURN_IDE_ERROR; 1868 break; 1869 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1870 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1871 " disabled adapter %d channel %d\n", 1872 pMvSataAdapter->adapterId, channel); 1873 mvSataEnableChannelDma(pMvSataAdapter,channel); 1874 pCmd->Result = RETURN_IDE_ERROR; 1875 break; 1876 case MV_QUEUE_COMMAND_RESULT_FULL: 1877 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1878 " Full adapter %d channel %d\n", 1879 pMvSataAdapter->adapterId, channel); 1880 pCmd->Result = RETURN_DEVICE_BUSY; 1881 break; 1882 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1883 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1884 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1885 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1886 pCmd->Result = RETURN_IDE_ERROR; 1887 break; 1888 default: 1889 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1890 " command\n", result); 1891 pCmd->Result = RETURN_IDE_ERROR; 1892 } 1893 if(pPRDTable) 1894 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1895 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1896 } 1897 pDevice->QueueLength++; 1898 return; 1899 1900 case IDE_COMMAND_VERIFY: 1901 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1902 pNoUdmaParams->bufPtr = NULL; 1903 pNoUdmaParams->callBack = CommandCompletionCB; 1904 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1905 pNoUdmaParams->count = 0; 1906 pNoUdmaParams->features = 0; 1907 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1908 1909 pCmd->uScratch.sata_param.cmd_priv = 1; 1910 if (pMvSataChannel->lba48Address == MV_TRUE){ 1911 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1912 pNoUdmaParams->isEXT = MV_TRUE; 1913 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1914 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1915 pNoUdmaParams->lbaLow = 1916 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1917 pNoUdmaParams->sectorCount = nSector; 1918 pNoUdmaParams->device = 0x40; 1919 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1920 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1921 goto queue_failed; 1922 } 1923 return; 1924 } 1925 else{ 1926 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1927 pNoUdmaParams->isEXT = MV_FALSE; 1928 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1929 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1930 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1931 pNoUdmaParams->sectorCount = 0xff & nSector; 1932 pNoUdmaParams->device = (MV_U8)(0x40 | 1933 ((Lba & 0xf000000) >> 24)); 1934 pNoUdmaParams->callBack = CommandCompletionCB; 1935 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1936 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1937 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1938 goto queue_failed; 1939 } 1940 } 1941 break; 1942 default: 1943 pCmd->Result = RETURN_INVALID_REQUEST; 1944 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1945 break; 1946 } 1947 } 1948 1949 /********************************************************** 1950 * 1951 * Probe the hostadapter. 1952 * 1953 **********************************************************/ 1954 static int 1955 hpt_probe(device_t dev) 1956 { 1957 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1958 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1959 #ifdef FOR_DEMO 1960 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1961 #endif 1962 )) 1963 { 1964 KdPrintI((CONTROLLER_NAME " found\n")); 1965 device_set_desc(dev, CONTROLLER_NAME); 1966 return (BUS_PROBE_DEFAULT); 1967 } 1968 else 1969 return(ENXIO); 1970 } 1971 1972 /*********************************************************** 1973 * 1974 * Auto configuration: attach and init a host adapter. 1975 * 1976 ***********************************************************/ 1977 static int 1978 hpt_attach(device_t dev) 1979 { 1980 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1981 int rid; 1982 union ccb *ccb; 1983 struct cam_devq *devq; 1984 struct cam_sim *hpt_vsim; 1985 1986 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1987 1988 pAdapter->hpt_dev = dev; 1989 1990 rid = init_adapter(pAdapter); 1991 if (rid) 1992 return rid; 1993 1994 rid = 0; 1995 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) 1996 { 1997 hpt_printk(("can't allocate interrupt\n")); 1998 return(ENXIO); 1999 } 2000 2001 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 2002 INTR_TYPE_CAM | INTR_MPSAFE, 2003 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 2004 { 2005 hpt_printk(("can't set up interrupt\n")); 2006 free(pAdapter, M_DEVBUF); 2007 return(ENXIO); 2008 } 2009 2010 2011 ccb = xpt_alloc_ccb(); 2012 ccb->ccb_h.pinfo.priority = 1; 2013 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2014 2015 /* 2016 * Create the device queue for our SIM(s). 2017 */ 2018 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2019 { 2020 KdPrint(("ENXIO\n")); 2021 return ENOMEM; 2022 } 2023 2024 /* 2025 * Construct our SIM entry 2026 */ 2027 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2028 pAdapter, device_get_unit(pAdapter->hpt_dev), 2029 &pAdapter->lock, 1, 8, devq); 2030 if (hpt_vsim == NULL) { 2031 cam_simq_free(devq); 2032 return ENOMEM; 2033 } 2034 2035 mtx_lock(&pAdapter->lock); 2036 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS) 2037 { 2038 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 2039 mtx_unlock(&pAdapter->lock); 2040 hpt_vsim = NULL; 2041 return ENXIO; 2042 } 2043 2044 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2045 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2046 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2047 { 2048 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2049 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 2050 mtx_unlock(&pAdapter->lock); 2051 hpt_vsim = NULL; 2052 return ENXIO; 2053 } 2054 mtx_unlock(&pAdapter->lock); 2055 2056 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2057 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2058 ccb->csa.event_enable = AC_LOST_DEVICE; 2059 ccb->csa.callback = hpt_async; 2060 ccb->csa.callback_arg = hpt_vsim; 2061 xpt_action((union ccb *)ccb); 2062 xpt_free_ccb(ccb); 2063 2064 if (device_get_unit(dev) == 0) { 2065 /* Start the work thread. XXX */ 2066 launch_worker_thread(); 2067 } 2068 2069 return 0; 2070 } 2071 2072 static int 2073 hpt_detach(device_t dev) 2074 { 2075 return (EBUSY); 2076 } 2077 2078 2079 /*************************************************************** 2080 * The poll function is used to simulate the interrupt when 2081 * the interrupt subsystem is not functioning. 2082 * 2083 ***************************************************************/ 2084 static void 2085 hpt_poll(struct cam_sim *sim) 2086 { 2087 IAL_ADAPTER_T *pAdapter; 2088 2089 pAdapter = cam_sim_softc(sim); 2090 2091 hpt_intr_locked((void *)cam_sim_softc(sim)); 2092 } 2093 2094 /**************************************************************** 2095 * Name: hpt_intr 2096 * Description: Interrupt handler. 2097 ****************************************************************/ 2098 static void 2099 hpt_intr(void *arg) 2100 { 2101 IAL_ADAPTER_T *pAdapter; 2102 2103 pAdapter = arg; 2104 mtx_lock(&pAdapter->lock); 2105 hpt_intr_locked(pAdapter); 2106 mtx_unlock(&pAdapter->lock); 2107 } 2108 2109 static void 2110 hpt_intr_locked(IAL_ADAPTER_T *pAdapter) 2111 { 2112 2113 mtx_assert(&pAdapter->lock, MA_OWNED); 2114 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2115 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2116 { 2117 _VBUS_INST(&pAdapter->VBus) 2118 CheckPendingCall(_VBUS_P0); 2119 } 2120 2121 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2122 } 2123 2124 /********************************************************** 2125 * Asynchronous Events 2126 *********************************************************/ 2127 #if (!defined(UNREFERENCED_PARAMETER)) 2128 #define UNREFERENCED_PARAMETER(x) (void)(x) 2129 #endif 2130 2131 static void 2132 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2133 void * arg) 2134 { 2135 /* debug XXXX */ 2136 panic("Here"); 2137 UNREFERENCED_PARAMETER(callback_arg); 2138 UNREFERENCED_PARAMETER(code); 2139 UNREFERENCED_PARAMETER(path); 2140 UNREFERENCED_PARAMETER(arg); 2141 2142 } 2143 2144 static void 2145 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2146 { 2147 int i; 2148 2149 hpt_printk(("flush all devices\n")); 2150 2151 /* flush all devices */ 2152 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2153 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2154 if(pVDev) fFlushVDev(pVDev); 2155 } 2156 } 2157 2158 static int 2159 hpt_shutdown(device_t dev) 2160 { 2161 IAL_ADAPTER_T *pAdapter; 2162 2163 pAdapter = device_get_softc(dev); 2164 2165 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2166 mtx_lock(&pAdapter->lock); 2167 FlushAdapter(pAdapter); 2168 mtx_unlock(&pAdapter->lock); 2169 /* give the flush some time to happen, 2170 *otherwise "shutdown -p now" will make file system corrupted */ 2171 DELAY(1000 * 1000 * 5); 2172 return 0; 2173 } 2174 2175 void 2176 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2177 { 2178 _VBUS_INST(&pAdapter->VBus) 2179 2180 if (mWaitingForIdle(_VBUS_P0)) { 2181 CheckIdleCall(_VBUS_P0); 2182 #ifdef SUPPORT_ARRAY 2183 { 2184 int i; 2185 PVDevice pArray; 2186 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2187 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2188 continue; 2189 else if (pArray->u.array.rf_auto_rebuild) { 2190 KdPrint(("auto rebuild.\n")); 2191 pArray->u.array.rf_auto_rebuild = 0; 2192 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2193 } 2194 } 2195 } 2196 #endif 2197 } 2198 /* launch the awaiting commands blocked by mWaitingForIdle */ 2199 while(pAdapter->pending_Q!= NULL) 2200 { 2201 _VBUS_INST(&pAdapter->VBus) 2202 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2203 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2204 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2205 } 2206 } 2207 2208 static void 2209 ccb_done(union ccb *ccb) 2210 { 2211 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2212 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2213 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2214 2215 dmamap_put(pmap); 2216 xpt_done(ccb); 2217 2218 pAdapter->outstandingCommands--; 2219 2220 if (pAdapter->outstandingCommands == 0) 2221 { 2222 if(DPC_Request_Nums == 0) 2223 Check_Idle_Call(pAdapter); 2224 wakeup(pAdapter); 2225 } 2226 } 2227 2228 /**************************************************************** 2229 * Name: hpt_action 2230 * Description: Process a queued command from the CAM layer. 2231 * Parameters: sim - Pointer to SIM object 2232 * ccb - Pointer to SCSI command structure. 2233 ****************************************************************/ 2234 2235 void 2236 hpt_action(struct cam_sim *sim, union ccb *ccb) 2237 { 2238 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2239 PBUS_DMAMAP pmap; 2240 _VBUS_INST(&pAdapter->VBus) 2241 2242 mtx_assert(&pAdapter->lock, MA_OWNED); 2243 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2244 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2245 2246 switch (ccb->ccb_h.func_code) 2247 { 2248 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2249 { 2250 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2251 2252 if (ccb->ccb_h.target_lun) { 2253 ccb->ccb_h.status = CAM_LUN_INVALID; 2254 xpt_done(ccb); 2255 return; 2256 } 2257 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2258 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2259 ccb->ccb_h.status = CAM_TID_INVALID; 2260 xpt_done(ccb); 2261 return; 2262 } 2263 2264 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2265 Check_Idle_Call(pAdapter); 2266 2267 pmap = dmamap_get(pAdapter); 2268 HPT_ASSERT(pmap); 2269 ccb->ccb_adapter = pmap; 2270 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2271 2272 if (mWaitingForIdle(_VBUS_P0)) 2273 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2274 else 2275 OsSendCommand(_VBUS_P ccb); 2276 2277 /* KdPrint(("leave scsiio\n")); */ 2278 break; 2279 } 2280 2281 case XPT_RESET_BUS: 2282 KdPrint(("reset bus\n")); 2283 fResetVBus(_VBUS_P0); 2284 xpt_done(ccb); 2285 break; 2286 2287 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2288 case XPT_ABORT: /* Abort the specified CCB */ 2289 case XPT_TERM_IO: /* Terminate the I/O process */ 2290 /* XXX Implement */ 2291 ccb->ccb_h.status = CAM_REQ_INVALID; 2292 xpt_done(ccb); 2293 break; 2294 2295 case XPT_GET_TRAN_SETTINGS: 2296 case XPT_SET_TRAN_SETTINGS: 2297 /* XXX Implement */ 2298 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2299 xpt_done(ccb); 2300 break; 2301 2302 case XPT_CALC_GEOMETRY: 2303 cam_calc_geometry(&ccb->ccg, 1); 2304 xpt_done(ccb); 2305 break; 2306 2307 case XPT_PATH_INQ: /* Path routing inquiry */ 2308 { 2309 struct ccb_pathinq *cpi = &ccb->cpi; 2310 2311 cpi->version_num = 1; /* XXX??? */ 2312 cpi->hba_inquiry = PI_SDTR_ABLE; 2313 cpi->target_sprt = 0; 2314 /* Not necessary to reset bus */ 2315 cpi->hba_misc = PIM_NOBUSRESET; 2316 cpi->hba_eng_cnt = 0; 2317 2318 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2319 cpi->max_lun = 0; 2320 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2321 2322 cpi->bus_id = cam_sim_bus(sim); 2323 cpi->base_transfer_speed = 3300; 2324 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2325 strlcpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2326 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2327 cpi->unit_number = cam_sim_unit(sim); 2328 cpi->transport = XPORT_SPI; 2329 cpi->transport_version = 2; 2330 cpi->protocol = PROTO_SCSI; 2331 cpi->protocol_version = SCSI_REV_2; 2332 cpi->ccb_h.status = CAM_REQ_CMP; 2333 xpt_done(ccb); 2334 break; 2335 } 2336 2337 default: 2338 KdPrint(("invalid cmd\n")); 2339 ccb->ccb_h.status = CAM_REQ_INVALID; 2340 xpt_done(ccb); 2341 break; 2342 } 2343 /* KdPrint(("leave hpt_action..............\n")); */ 2344 } 2345 2346 /* shall be called at lock_driver() */ 2347 static void 2348 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2349 { 2350 if(*ccb_Q == NULL) 2351 ccb->ccb_h.ccb_ccb_ptr = ccb; 2352 else { 2353 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2354 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2355 } 2356 2357 *ccb_Q = ccb; 2358 } 2359 2360 /* shall be called at lock_driver() */ 2361 static void 2362 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2363 { 2364 union ccb *TempCCB; 2365 2366 TempCCB = *ccb_Q; 2367 2368 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2369 *ccb_Q = NULL; 2370 else { 2371 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2372 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2373 2374 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2375 2376 if(*ccb_Q == ccb) 2377 *ccb_Q = TempCCB; 2378 } 2379 } 2380 2381 #ifdef SUPPORT_ARRAY 2382 /*************************************************************************** 2383 * Function: hpt_worker_thread 2384 * Description: Do background rebuilding. Execute in kernel thread context. 2385 * Returns: None 2386 ***************************************************************************/ 2387 static void hpt_worker_thread(void) 2388 { 2389 2390 for(;;) { 2391 mtx_lock(&DpcQueue_Lock); 2392 while (DpcQueue_First!=DpcQueue_Last) { 2393 ST_HPT_DPC p; 2394 p = DpcQueue[DpcQueue_First]; 2395 DpcQueue_First++; 2396 DpcQueue_First %= MAX_DPC; 2397 DPC_Request_Nums++; 2398 mtx_unlock(&DpcQueue_Lock); 2399 p.dpc(p.pAdapter, p.arg, p.flags); 2400 2401 mtx_lock(&p.pAdapter->lock); 2402 mtx_lock(&DpcQueue_Lock); 2403 DPC_Request_Nums--; 2404 /* since we may have prevented Check_Idle_Call, do it here */ 2405 if (DPC_Request_Nums==0) { 2406 if (p.pAdapter->outstandingCommands == 0) { 2407 _VBUS_INST(&p.pAdapter->VBus); 2408 Check_Idle_Call(p.pAdapter); 2409 CheckPendingCall(_VBUS_P0); 2410 } 2411 } 2412 mtx_unlock(&p.pAdapter->lock); 2413 mtx_unlock(&DpcQueue_Lock); 2414 2415 /*Schedule out*/ 2416 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2417 /* abort rebuilding process. */ 2418 IAL_ADAPTER_T *pAdapter; 2419 PVDevice pArray; 2420 PVBus _vbus_p; 2421 int i; 2422 2423 sx_slock(&hptmv_list_lock); 2424 pAdapter = gIal_Adapter; 2425 2426 while(pAdapter != NULL){ 2427 mtx_lock(&pAdapter->lock); 2428 _vbus_p = &pAdapter->VBus; 2429 2430 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2431 { 2432 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2433 continue; 2434 else if (pArray->u.array.rf_rebuilding || 2435 pArray->u.array.rf_verifying || 2436 pArray->u.array.rf_initializing) 2437 { 2438 pArray->u.array.rf_abort_rebuild = 1; 2439 } 2440 } 2441 mtx_unlock(&pAdapter->lock); 2442 pAdapter = pAdapter->next; 2443 } 2444 sx_sunlock(&hptmv_list_lock); 2445 } 2446 mtx_lock(&DpcQueue_Lock); 2447 } 2448 mtx_unlock(&DpcQueue_Lock); 2449 2450 /*Remove this debug option*/ 2451 /* 2452 #ifdef DEBUG 2453 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2454 pause("hptrdy", 2*hz); 2455 #endif 2456 */ 2457 kproc_suspend_check(curproc); 2458 pause("-", 2*hz); /* wait for something to do */ 2459 } 2460 } 2461 2462 static struct proc *hptdaemonproc; 2463 static struct kproc_desc hpt_kp = { 2464 "hpt_wt", 2465 hpt_worker_thread, 2466 &hptdaemonproc 2467 }; 2468 2469 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2470 static void 2471 launch_worker_thread(void) 2472 { 2473 IAL_ADAPTER_T *pAdapTemp; 2474 2475 kproc_start(&hpt_kp); 2476 2477 sx_slock(&hptmv_list_lock); 2478 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2479 2480 _VBUS_INST(&pAdapTemp->VBus) 2481 int i; 2482 PVDevice pVDev; 2483 2484 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2485 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2486 continue; 2487 else{ 2488 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2489 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2490 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2491 } 2492 } 2493 sx_sunlock(&hptmv_list_lock); 2494 2495 /* 2496 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2497 */ 2498 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, 2499 SHUTDOWN_PRI_LAST); 2500 } 2501 /* 2502 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2503 */ 2504 2505 #endif 2506 2507 /********************************************************************************/ 2508 2509 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2510 { 2511 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2512 2513 if (logical) { 2514 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2515 pSg->wSgSize = ccb->csio.dxfer_len; 2516 pSg->wSgFlag = SG_FLAG_EOT; 2517 return TRUE; 2518 } 2519 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2520 HPT_ASSERT(0); 2521 return FALSE; 2522 } 2523 2524 /*******************************************************************************/ 2525 ULONG HPTLIBAPI 2526 GetStamp(void) 2527 { 2528 /* 2529 * the system variable, ticks, can't be used since it hasn't yet been active 2530 * when our driver starts (ticks==0, it's a invalid stamp value) 2531 */ 2532 ULONG stamp; 2533 do { stamp = random(); } while (stamp==0); 2534 return stamp; 2535 } 2536 2537 2538 static void 2539 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2540 { 2541 int i; 2542 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2543 2544 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2545 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2546 #ifndef SERIAL_CMDS 2547 inquiryData->CommandQueue = 1; 2548 #endif 2549 2550 switch(pVDev->VDeviceType) { 2551 case VD_SINGLE_DISK: 2552 case VD_ATAPI: 2553 case VD_REMOVABLE: 2554 /* Set the removable bit, if applicable. */ 2555 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2556 inquiryData->RemovableMedia = 1; 2557 2558 /* Fill in vendor identification fields. */ 2559 for (i = 0; i < 20; i += 2) { 2560 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2561 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2562 2563 } 2564 2565 /* Initialize unused portion of product id. */ 2566 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2567 2568 /* firmware revision */ 2569 for (i = 0; i < 4; i += 2) 2570 { 2571 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2572 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2573 } 2574 break; 2575 default: 2576 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2577 #ifdef SUPPORT_ARRAY 2578 switch(pVDev->VDeviceType){ 2579 case VD_RAID_0: 2580 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2581 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2582 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2583 else 2584 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2585 break; 2586 case VD_RAID_1: 2587 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2588 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2589 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2590 else 2591 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2592 break; 2593 case VD_RAID_5: 2594 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2595 break; 2596 case VD_JBOD: 2597 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2598 break; 2599 } 2600 #endif 2601 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2602 break; 2603 } 2604 } 2605 2606 static void 2607 hpt_timeout(void *arg) 2608 { 2609 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter; 2610 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2611 _VBUS_INST(&pAdapter->VBus) 2612 2613 mtx_assert(&pAdapter->lock, MA_OWNED); 2614 fResetVBus(_VBUS_P0); 2615 } 2616 2617 static void 2618 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2619 { 2620 PCommand pCmd = (PCommand)arg; 2621 union ccb *ccb = pCmd->pOrgCommand; 2622 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2623 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2624 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2625 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2626 FPSCAT_GATH psg = pCmd->pSgTable; 2627 int idx; 2628 _VBUS_INST(pVDev->pVBus) 2629 2630 HPT_ASSERT(pCmd->cf_physical_sg); 2631 2632 if (error) 2633 panic("busdma error"); 2634 2635 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2636 2637 if (nsegs != 0) { 2638 for (idx = 0; idx < nsegs; idx++, psg++) { 2639 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2640 psg->wSgSize = segs[idx].ds_len; 2641 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2642 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2643 } 2644 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2645 2646 if (pCmd->cf_data_in) { 2647 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2648 BUS_DMASYNC_PREREAD); 2649 } 2650 else if (pCmd->cf_data_out) { 2651 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2652 BUS_DMASYNC_PREWRITE); 2653 } 2654 } 2655 2656 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb); 2657 pVDev->pfnSendCommand(_VBUS_P pCmd); 2658 CheckPendingCall(_VBUS_P0); 2659 } 2660 2661 2662 2663 static void HPTLIBAPI 2664 OsSendCommand(_VBUS_ARG union ccb *ccb) 2665 { 2666 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2667 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2668 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2669 struct ccb_scsiio *csio = &ccb->csio; 2670 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2671 2672 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2673 ccb, 2674 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2675 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2676 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2677 )); 2678 2679 pAdapter->outstandingCommands++; 2680 2681 if (pVDev == NULL || pVDev->vf_online == 0) { 2682 ccb->ccb_h.status = CAM_REQ_INVALID; 2683 ccb_done(ccb); 2684 goto Command_Complished; 2685 } 2686 2687 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2688 { 2689 case TEST_UNIT_READY: 2690 case START_STOP_UNIT: 2691 case SYNCHRONIZE_CACHE: 2692 /* FALLTHROUGH */ 2693 ccb->ccb_h.status = CAM_REQ_CMP; 2694 break; 2695 2696 case INQUIRY: 2697 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2698 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2699 ccb_h->status = CAM_REQ_CMP; 2700 break; 2701 2702 case READ_CAPACITY: 2703 { 2704 UCHAR *rbuf=csio->data_ptr; 2705 unsigned int cap; 2706 2707 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2708 cap = 0xfffffffful; 2709 } else { 2710 cap = pVDev->VDeviceCapacity - 1; 2711 } 2712 2713 rbuf[0] = (UCHAR)(cap>>24); 2714 rbuf[1] = (UCHAR)(cap>>16); 2715 rbuf[2] = (UCHAR)(cap>>8); 2716 rbuf[3] = (UCHAR)cap; 2717 /* Claim 512 byte blocks (big-endian). */ 2718 rbuf[4] = 0; 2719 rbuf[5] = 0; 2720 rbuf[6] = 2; 2721 rbuf[7] = 0; 2722 2723 ccb_h->status = CAM_REQ_CMP; 2724 break; 2725 } 2726 2727 case 0x9e: /*SERVICE_ACTION_IN*/ 2728 { 2729 UCHAR *rbuf = csio->data_ptr; 2730 LBA_T cap = pVDev->VDeviceCapacity - 1; 2731 2732 rbuf[0] = (UCHAR)(cap>>56); 2733 rbuf[1] = (UCHAR)(cap>>48); 2734 rbuf[2] = (UCHAR)(cap>>40); 2735 rbuf[3] = (UCHAR)(cap>>32); 2736 rbuf[4] = (UCHAR)(cap>>24); 2737 rbuf[5] = (UCHAR)(cap>>16); 2738 rbuf[6] = (UCHAR)(cap>>8); 2739 rbuf[7] = (UCHAR)cap; 2740 rbuf[8] = 0; 2741 rbuf[9] = 0; 2742 rbuf[10] = 2; 2743 rbuf[11] = 0; 2744 2745 ccb_h->status = CAM_REQ_CMP; 2746 break; 2747 } 2748 2749 case READ_6: 2750 case WRITE_6: 2751 case READ_10: 2752 case WRITE_10: 2753 case 0x88: /* READ_16 */ 2754 case 0x8a: /* WRITE_16 */ 2755 case 0x13: 2756 case 0x2f: 2757 { 2758 UCHAR Cdb[16]; 2759 UCHAR CdbLength; 2760 _VBUS_INST(pVDev->pVBus) 2761 PCommand pCmd = AllocateCommand(_VBUS_P0); 2762 int error; 2763 HPT_ASSERT(pCmd); 2764 2765 CdbLength = csio->cdb_len; 2766 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2767 { 2768 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2769 { 2770 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2771 } 2772 else 2773 { 2774 KdPrintE(("ERROR!!!\n")); 2775 ccb->ccb_h.status = CAM_REQ_INVALID; 2776 break; 2777 } 2778 } 2779 else 2780 { 2781 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2782 } 2783 2784 pCmd->pOrgCommand = ccb; 2785 pCmd->pVDevice = pVDev; 2786 pCmd->pfnCompletion = fOsCommandDone; 2787 pCmd->pfnBuildSgl = fOsBuildSgl; 2788 pCmd->pSgTable = pmap->psg; 2789 2790 switch (Cdb[0]) 2791 { 2792 case READ_6: 2793 case WRITE_6: 2794 case 0x13: 2795 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2796 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2797 break; 2798 2799 case 0x88: /* READ_16 */ 2800 case 0x8a: /* WRITE_16 */ 2801 pCmd->uCmd.Ide.Lba = 2802 (HPT_U64)Cdb[2] << 56 | 2803 (HPT_U64)Cdb[3] << 48 | 2804 (HPT_U64)Cdb[4] << 40 | 2805 (HPT_U64)Cdb[5] << 32 | 2806 (HPT_U64)Cdb[6] << 24 | 2807 (HPT_U64)Cdb[7] << 16 | 2808 (HPT_U64)Cdb[8] << 8 | 2809 (HPT_U64)Cdb[9]; 2810 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2811 break; 2812 2813 default: 2814 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2815 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2816 break; 2817 } 2818 2819 switch (Cdb[0]) 2820 { 2821 case READ_6: 2822 case READ_10: 2823 case 0x88: /* READ_16 */ 2824 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2825 pCmd->cf_data_in = 1; 2826 break; 2827 2828 case WRITE_6: 2829 case WRITE_10: 2830 case 0x8a: /* WRITE_16 */ 2831 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2832 pCmd->cf_data_out = 1; 2833 break; 2834 case 0x13: 2835 case 0x2f: 2836 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2837 break; 2838 } 2839 /*///////////////////////// */ 2840 pCmd->cf_physical_sg = 1; 2841 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent, 2842 pmap->dma_map, 2843 ccb, 2844 hpt_io_dmamap_callback, 2845 pCmd, BUS_DMA_WAITOK 2846 ); 2847 KdPrint(("bus_dmamap_load return %d\n", error)); 2848 if (error && error!=EINPROGRESS) { 2849 hpt_printk(("bus_dmamap_load error %d\n", error)); 2850 FreeCommand(_VBUS_P pCmd); 2851 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2852 dmamap_put(pmap); 2853 pAdapter->outstandingCommands--; 2854 if (pAdapter->outstandingCommands == 0) 2855 wakeup(pAdapter); 2856 xpt_done(ccb); 2857 } 2858 goto Command_Complished; 2859 } 2860 2861 default: 2862 ccb->ccb_h.status = CAM_REQ_INVALID; 2863 break; 2864 } 2865 ccb_done(ccb); 2866 Command_Complished: 2867 CheckPendingCall(_VBUS_P0); 2868 return; 2869 } 2870 2871 static void HPTLIBAPI 2872 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2873 { 2874 union ccb *ccb = pCmd->pOrgCommand; 2875 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2876 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2877 2878 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2879 2880 callout_stop(&pmap->timeout); 2881 2882 switch(pCmd->Result) { 2883 case RETURN_SUCCESS: 2884 ccb->ccb_h.status = CAM_REQ_CMP; 2885 break; 2886 case RETURN_BAD_DEVICE: 2887 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2888 break; 2889 case RETURN_DEVICE_BUSY: 2890 ccb->ccb_h.status = CAM_BUSY; 2891 break; 2892 case RETURN_INVALID_REQUEST: 2893 ccb->ccb_h.status = CAM_REQ_INVALID; 2894 break; 2895 case RETURN_SELECTION_TIMEOUT: 2896 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2897 break; 2898 case RETURN_RETRY: 2899 ccb->ccb_h.status = CAM_BUSY; 2900 break; 2901 default: 2902 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2903 break; 2904 } 2905 2906 if (pCmd->cf_data_in) { 2907 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2908 } 2909 else if (pCmd->cf_data_out) { 2910 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2911 } 2912 2913 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2914 2915 FreeCommand(_VBUS_P pCmd); 2916 ccb_done(ccb); 2917 } 2918 2919 int 2920 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2921 { 2922 int p; 2923 2924 mtx_lock(&DpcQueue_Lock); 2925 p = (DpcQueue_Last + 1) % MAX_DPC; 2926 if (p==DpcQueue_First) { 2927 KdPrint(("DPC Queue full!\n")); 2928 mtx_unlock(&DpcQueue_Lock); 2929 return -1; 2930 } 2931 2932 DpcQueue[DpcQueue_Last].dpc = dpc; 2933 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2934 DpcQueue[DpcQueue_Last].arg = arg; 2935 DpcQueue[DpcQueue_Last].flags = flags; 2936 DpcQueue_Last = p; 2937 mtx_unlock(&DpcQueue_Lock); 2938 2939 return 0; 2940 } 2941 2942 #ifdef _RAID5N_ 2943 /* 2944 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2945 * How about the memory for 5081 request/response array and PRD table? 2946 */ 2947 void 2948 *os_alloc_page(_VBUS_ARG0) 2949 { 2950 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2951 } 2952 2953 void 2954 *os_alloc_dma_page(_VBUS_ARG0) 2955 { 2956 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2957 } 2958 2959 void 2960 os_free_page(_VBUS_ARG void *p) 2961 { 2962 contigfree(p, 0x1000, M_DEVBUF); 2963 } 2964 2965 void 2966 os_free_dma_page(_VBUS_ARG void *p) 2967 { 2968 contigfree(p, 0x1000, M_DEVBUF); 2969 } 2970 2971 void 2972 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2973 { 2974 UINT i; 2975 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 2976 } 2977 2978 void 2979 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 2980 { 2981 UINT i; 2982 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 2983 } 2984 #endif 2985