1 /* 2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/malloc.h> 35 #include <sys/resource.h> 36 #include <sys/time.h> 37 #include <sys/callout.h> 38 #include <sys/signalvar.h> 39 #include <sys/eventhandler.h> 40 #include <sys/proc.h> 41 #include <sys/kthread.h> 42 43 #if (__FreeBSD_version >= 500000) 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #endif 47 48 #if (__FreeBSD_version >= 500000) 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #else 52 #include <pci/pcireg.h> 53 #include <pci/pcivar.h> 54 #include <sys/wait.h> 55 #include <sys/sysproto.h> 56 #endif 57 58 #ifndef __KERNEL__ 59 #define __KERNEL__ 60 #endif 61 62 #include <dev/hptmv/global.h> 63 #include <dev/hptmv/hptintf.h> 64 #include <dev/hptmv/osbsd.h> 65 #include <dev/hptmv/access601.h> 66 67 68 #ifdef DEBUG 69 #ifdef DEBUG_LEVEL 70 int hpt_dbg_level = DEBUG_LEVEL; 71 #else 72 int hpt_dbg_level = 0; 73 #endif 74 #endif 75 76 #define MV_ERROR printf 77 78 /* 79 * CAM SIM entry points 80 */ 81 static int hpt_probe (device_t dev); 82 static void launch_worker_thread(void); 83 static int hpt_attach(device_t dev); 84 static int hpt_detach(device_t dev); 85 static int hpt_shutdown(device_t dev); 86 static void hpt_poll(struct cam_sim *sim); 87 static void hpt_intr(void *arg); 88 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 89 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 90 91 static device_method_t driver_methods[] = { 92 /* Device interface */ 93 DEVMETHOD(device_probe, hpt_probe), 94 DEVMETHOD(device_attach, hpt_attach), 95 DEVMETHOD(device_detach, hpt_detach), 96 97 DEVMETHOD(device_shutdown, hpt_shutdown), 98 DEVMETHOD_END 99 }; 100 101 static driver_t hpt_pci_driver = { 102 __str(PROC_DIR_NAME), 103 driver_methods, 104 sizeof(IAL_ADAPTER_T) 105 }; 106 107 static devclass_t hpt_devclass; 108 109 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 110 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 111 112 #define ccb_ccb_ptr spriv_ptr0 113 #define ccb_adapter ccb_h.spriv_ptr1 114 115 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 116 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 117 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 118 static void ccb_done(union ccb *ccb); 119 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 120 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 121 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 122 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 123 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 124 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 125 static int fResetActiveCommands(PVBus _vbus_p); 126 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 127 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 128 static void hptmv_handle_event_disconnect(void *data); 129 static void hptmv_handle_event_connect(void *data); 130 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 131 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 132 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 133 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 134 int logical); 135 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 136 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 137 MV_U16 responseFlags, MV_U32 timeStamp, 138 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 139 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 140 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 141 142 #define ccb_ccb_ptr spriv_ptr0 143 #define ccb_adapter ccb_h.spriv_ptr1 144 145 IAL_ADAPTER_T *gIal_Adapter = 0; 146 IAL_ADAPTER_T *pCurAdapter = 0; 147 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 148 149 typedef struct st_HPT_DPC { 150 IAL_ADAPTER_T *pAdapter; 151 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 152 void *arg; 153 UCHAR flags; 154 } ST_HPT_DPC; 155 156 #define MAX_DPC 16 157 UCHAR DPC_Request_Nums = 0; 158 static ST_HPT_DPC DpcQueue[MAX_DPC]; 159 static int DpcQueue_First=0; 160 static int DpcQueue_Last = 0; 161 162 char DRIVER_VERSION[] = "v1.16"; 163 164 #if (__FreeBSD_version >= 500000) 165 static struct mtx driver_lock; 166 intrmask_t lock_driver() 167 { 168 169 intrmask_t spl = 0; 170 mtx_lock(&driver_lock); 171 return spl; 172 } 173 void unlock_driver(intrmask_t spl) 174 { 175 mtx_unlock(&driver_lock); 176 } 177 #else 178 static int driver_locked = 0; 179 intrmask_t lock_driver() 180 { 181 intrmask_t spl = splcam(); 182 loop: 183 while (driver_locked) 184 tsleep(&driver_locked, PRIBIO, "hptlck", hz); 185 atomic_add_int(&driver_locked, 1); 186 if (driver_locked>1) { 187 atomic_subtract_int(&driver_locked, 1); 188 goto loop; 189 } 190 return spl; 191 } 192 193 void unlock_driver(intrmask_t spl) 194 { 195 atomic_subtract_int(&driver_locked, 1); 196 if (driver_locked==0) { 197 wakeup(&driver_locked); 198 } 199 splx(spl); 200 } 201 #endif 202 203 /******************************************************************************* 204 * Name: hptmv_free_channel 205 * 206 * Description: free allocated queues for the given channel 207 * 208 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this 209 * channel connected to. 210 * channelNum - channel number. 211 * 212 ******************************************************************************/ 213 static void 214 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 215 { 216 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 217 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 218 } 219 220 static void failDevice(PVDevice pVDev) 221 { 222 PVBus _vbus_p = pVDev->pVBus; 223 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 224 225 pVDev->u.disk.df_on_line = 0; 226 pVDev->vf_online = 0; 227 if (pVDev->pfnDeviceFailed) 228 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 229 230 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 231 232 #ifndef FOR_DEMO 233 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 234 pAdapter->beeping = 1; 235 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 236 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 237 } 238 #endif 239 } 240 241 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 242 243 static void 244 handleEdmaError(_VBUS_ARG PCommand pCmd) 245 { 246 PDevice pDevice = &pCmd->pVDevice->u.disk; 247 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 248 249 if (!pDevice->df_on_line) { 250 KdPrint(("Device is offline")); 251 pCmd->Result = RETURN_BAD_DEVICE; 252 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 253 return; 254 } 255 256 if (pCmd->RetryCount++>5) { 257 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 258 failed: 259 failDevice(pCmd->pVDevice); 260 pCmd->Result = RETURN_IDE_ERROR; 261 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 262 return; 263 } 264 265 /* reset the channel and retry the command */ 266 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 267 goto failed; 268 269 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 270 271 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 272 fDeviceSendCommand(_VBUS_P pCmd); 273 } 274 275 /**************************************************************** 276 * Name: hptmv_init_channel 277 * 278 * Description: allocate request and response queues for the EDMA of the 279 * given channel and sets other fields. 280 * 281 * Parameters: 282 * pAdapter - pointer to the emulated adapter data structure 283 * channelNum - channel number. 284 * Return: 0 on success, otherwise on failure 285 ****************************************************************/ 286 static int 287 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 288 { 289 MV_SATA_CHANNEL *pMvSataChannel; 290 dma_addr_t req_dma_addr; 291 dma_addr_t rsp_dma_addr; 292 293 if (channelNum >= MV_SATA_CHANNELS_NUM) 294 { 295 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 296 pAdapter->mvSataAdapter.adapterId, channelNum); 297 return -1; 298 } 299 300 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 301 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 302 pMvSataChannel->channelNumber = channelNum; 303 pMvSataChannel->lba48Address = MV_FALSE; 304 pMvSataChannel->maxReadTransfer = MV_FALSE; 305 306 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 307 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 308 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 309 310 311 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 312 313 /* check the 1K alignment of the request queue*/ 314 if (req_dma_addr & 0x3ff) 315 { 316 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 317 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 318 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 319 return -1; 320 } 321 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 322 pMvSataChannel->requestQueuePciHiAddress = 0; 323 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 324 pAdapter->mvSataAdapter.adapterId, channelNum, 325 pMvSataChannel->requestQueue)); 326 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 327 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 328 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 329 330 /* check the 256 alignment of the response queue*/ 331 if (rsp_dma_addr & 0xff) 332 { 333 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 334 "aligned, dma_addr=%llx\n", 335 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 336 return -1; 337 } 338 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 339 pMvSataChannel->responseQueuePciHiAddress = 0; 340 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 341 pAdapter->mvSataAdapter.adapterId, channelNum, 342 pMvSataChannel->responseQueue)); 343 344 pAdapter->mvChannel[channelNum].online = MV_TRUE; 345 return 0; 346 } 347 348 /****************************************************************************** 349 * Name: hptmv_parse_identify_results 350 * 351 * Description: this functions parses the identify command results, checks 352 * that the connected deives can be accesed by RR18xx EDMA, 353 * and updates the channel stucture accordingly. 354 * 355 * Parameters: pMvSataChannel, pointer to the channel data structure. 356 * 357 * Returns: =0 ->success, < 0 ->failure. 358 * 359 ******************************************************************************/ 360 static int 361 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 362 { 363 MV_U16 *iden = pMvSataChannel->identifyDevice; 364 365 /*LBA addressing*/ 366 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 367 { 368 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 369 return -1; 370 } 371 else 372 { 373 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 374 } 375 /*DMA support*/ 376 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 377 { 378 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 379 return -1; 380 } 381 else 382 { 383 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 384 } 385 /* PIO */ 386 if ((iden[IDEN_VALID] & 2) == 0) 387 { 388 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 389 return -1; 390 } 391 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 392 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 393 394 /*UDMA*/ 395 if ((iden[IDEN_VALID] & 4) == 0) 396 { 397 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 398 return -1; 399 } 400 401 /* 48 bit address */ 402 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 403 { 404 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 405 pMvSataChannel->lba48Address = MV_TRUE; 406 } 407 else 408 { 409 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 410 pMvSataChannel->lba48Address = MV_FALSE; 411 } 412 return 0; 413 } 414 415 static void 416 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 417 { 418 PVDevice pVDev = &pAdapter->VDevices[channel]; 419 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 420 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 421 422 pMvSataChannel->outstandingCommands = 0; 423 424 pVDev->u.disk.mv = pMvSataChannel; 425 pVDev->u.disk.df_on_line = 1; 426 pVDev->u.disk.pVBus = &pAdapter->VBus; 427 pVDev->pVBus = &pAdapter->VBus; 428 429 #ifdef SUPPORT_48BIT_LBA 430 if (pMvSataChannel->lba48Address == MV_TRUE) 431 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 432 else 433 #endif 434 if(IdentifyData[53] & 1) { 435 pVDev->u.disk.dDeRealCapacity = 436 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 437 (IdentifyData[61]<<16 | IdentifyData[60]) : 438 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 439 } else 440 pVDev->u.disk.dDeRealCapacity = 441 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 442 443 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 444 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 445 446 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 447 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 448 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 449 } 450 } 451 452 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 453 { 454 PVDevice pVDev; 455 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 456 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 457 458 if (!pMvSataChannel) return; 459 460 if (plugged) 461 { 462 pVDev = &(pAdapter->VDevices[channelIndex]); 463 init_vdev_params(pAdapter, channelIndex); 464 465 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 466 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 467 468 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 469 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 470 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 471 pVDev->vf_online = 1; 472 473 #ifdef SUPPORT_ARRAY 474 if(pVDev->pParent) 475 { 476 int iMember; 477 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 478 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 479 pVDev->pParent->u.array.pMember[iMember] = NULL; 480 pVDev->pParent = NULL; 481 } 482 #endif 483 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 484 fCheckBootable(pVDev); 485 RegisterVDevice(pVDev); 486 487 #ifndef FOR_DEMO 488 if (pAdapter->beeping) { 489 pAdapter->beeping = 0; 490 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 491 } 492 #endif 493 494 } 495 else 496 { 497 pVDev = &(pAdapter->VDevices[channelIndex]); 498 failDevice(pVDev); 499 } 500 } 501 502 static int 503 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 504 { 505 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 506 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 507 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 508 MV_U32 udmaMode,pioMode; 509 510 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 511 channelNum)); 512 513 514 /* Software reset channel */ 515 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 516 { 517 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 518 pMvSataAdapter->adapterId, channelNum); 519 return -1; 520 } 521 522 /* Hardware reset channel */ 523 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 524 { 525 /* If failed, try again - this is when trying to hardreset a channel */ 526 /* when drive is just spinning up */ 527 StallExec(5000000); /* wait 5 sec before trying again */ 528 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 529 { 530 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 531 pMvSataAdapter->adapterId, channelNum); 532 return -1; 533 } 534 } 535 536 /* identify device*/ 537 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 538 { 539 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 540 , pMvSataAdapter->adapterId, channelNum); 541 return -1; 542 } 543 if (hptmv_parse_identify_results(pMvSataChannel)) 544 { 545 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 546 , pMvSataAdapter->adapterId, channelNum); 547 return -1; 548 } 549 550 /* mvStorageDevATASetFeatures */ 551 /* Disable 8 bit PIO in case CFA enabled */ 552 if (pMvSataChannel->identifyDevice[86] & 4) 553 { 554 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 555 pMvSataAdapter->adapterId)); 556 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 557 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 558 0, 0, 0) == MV_FALSE) 559 { 560 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 561 " failed\n", pMvSataAdapter->adapterId, channelNum); 562 return -1; 563 } 564 } 565 /* Write cache */ 566 #ifdef ENABLE_WRITE_CACHE 567 if (pMvSataChannel->identifyDevice[82] & 0x20) 568 { 569 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 570 { 571 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 572 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 573 0, 0, 0) == MV_FALSE) 574 { 575 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 576 pMvSataAdapter->adapterId, channelNum); 577 return -1; 578 } 579 } 580 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 581 pMvSataAdapter->adapterId, channelNum)); 582 } 583 else 584 { 585 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 586 pMvSataAdapter->adapterId, channelNum)); 587 } 588 #else /* disable write cache */ 589 { 590 if (pMvSataChannel->identifyDevice[85] & 0x20) 591 { 592 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 593 pMvSataAdapter->adapterId, channelNum)); 594 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 595 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 596 0, 0, 0) == MV_FALSE) 597 { 598 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 599 pMvSataAdapter->adapterId, channelNum); 600 return -1; 601 } 602 } 603 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 604 pMvSataAdapter->adapterId, channelNum)); 605 } 606 #endif 607 608 /* Set transfer mode */ 609 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 610 pMvSataAdapter->adapterId)); 611 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 612 MV_ATA_SET_FEATURES_TRANSFER, 613 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 614 MV_FALSE) 615 { 616 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 617 pMvSataAdapter->adapterId, channelNum); 618 return -1; 619 } 620 621 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 622 { 623 pioMode = MV_ATA_TRANSFER_PIO_4; 624 } 625 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 626 { 627 pioMode = MV_ATA_TRANSFER_PIO_3; 628 } 629 else 630 { 631 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 632 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 633 } 634 635 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 636 pMvSataAdapter->adapterId)); 637 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 638 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 639 MV_ATA_SET_FEATURES_TRANSFER, 640 pioMode, 0, 0, 0) == MV_FALSE) 641 { 642 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 643 pMvSataAdapter->adapterId, channelNum); 644 return -1; 645 } 646 647 udmaMode = MV_ATA_TRANSFER_UDMA_0; 648 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 649 { 650 udmaMode = MV_ATA_TRANSFER_UDMA_6; 651 } 652 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 653 { 654 udmaMode = MV_ATA_TRANSFER_UDMA_5; 655 } 656 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 657 { 658 udmaMode = MV_ATA_TRANSFER_UDMA_4; 659 } 660 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 661 { 662 udmaMode = MV_ATA_TRANSFER_UDMA_3; 663 } 664 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 665 { 666 udmaMode = MV_ATA_TRANSFER_UDMA_2; 667 } 668 669 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 670 pMvSataAdapter->adapterId, udmaMode & 0xf)); 671 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 672 673 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 674 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 675 0, 0, 0) == MV_FALSE) 676 { 677 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 678 pMvSataAdapter->adapterId, channelNum); 679 return -1; 680 }*/ 681 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 682 return TRUE; 683 else 684 do 685 { 686 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 687 MV_ATA_SET_FEATURES_TRANSFER, 688 pChannelInfo->maxUltraDmaModeSupported, 689 0, 0, 0) == MV_FALSE) 690 { 691 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 692 { 693 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 694 { 695 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 696 pMvSataChannel->eDmaRegsOffset + 697 0x11c, /* command reg */ 698 MV_ATA_COMMAND_IDLE_IMMEDIATE); 699 mvMicroSecondsDelay(10000); 700 mvSataChannelHardReset(pMvSataAdapter, channelNum); 701 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 702 return FALSE; 703 } 704 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 705 return FALSE; 706 pChannelInfo->maxUltraDmaModeSupported--; 707 continue; 708 } 709 else return FALSE; 710 } 711 break; 712 }while (1); 713 714 /* Read look ahead */ 715 #ifdef ENABLE_READ_AHEAD 716 if (pMvSataChannel->identifyDevice[82] & 0x40) 717 { 718 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 719 { 720 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 721 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 722 0, 0) == MV_FALSE) 723 { 724 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 725 pMvSataAdapter->adapterId, channelNum); 726 return -1; 727 } 728 } 729 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 730 pMvSataAdapter->adapterId, channelNum)); 731 } 732 else 733 { 734 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 735 pMvSataAdapter->adapterId, channelNum)); 736 } 737 #else 738 { 739 if (pMvSataChannel->identifyDevice[86] & 0x20) 740 { 741 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 742 pMvSataAdapter->adapterId, channelNum)); 743 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 744 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 745 0, 0) == MV_FALSE) 746 { 747 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 748 pMvSataAdapter->adapterId, channelNum); 749 return -1; 750 } 751 } 752 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 753 pMvSataAdapter->adapterId, channelNum)); 754 } 755 #endif 756 757 758 { 759 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 760 pMvSataAdapter->adapterId, 761 channelNum)); 762 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 763 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 764 { 765 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 766 pMvSataAdapter->adapterId, channelNum); 767 return -1; 768 } 769 } 770 /* Enable EDMA */ 771 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 772 { 773 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 774 pMvSataAdapter->adapterId, channelNum); 775 return -1; 776 } 777 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 778 pMvSataAdapter->adapterId, channelNum); 779 780 #ifndef FOR_DEMO 781 set_fail_led(pMvSataAdapter, channelNum, 0); 782 #endif 783 return 0; 784 } 785 786 static void 787 hptmv_handle_event(void * data, int flag) 788 { 789 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 790 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 791 MV_U8 channelIndex; 792 793 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 794 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 795 { 796 switch(pAdapter->sataEvents[channelIndex]) 797 { 798 case SATA_EVENT_CHANNEL_CONNECTED: 799 /* Handle only connects */ 800 if (flag == 1) 801 break; 802 KdPrint(("RR18xx [%d,%d]: new device connected\n", 803 pMvSataAdapter->adapterId, channelIndex)); 804 hptmv_init_channel(pAdapter, channelIndex); 805 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 806 { 807 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 808 pMvSataAdapter->adapterId, channelIndex); 809 hptmv_free_channel(pAdapter, channelIndex); 810 } 811 else 812 { 813 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 814 if (start_channel( pAdapter, channelIndex)) 815 { 816 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 817 pMvSataAdapter->adapterId, channelIndex); 818 hptmv_free_channel(pAdapter, channelIndex); 819 } 820 else 821 { 822 device_change(pAdapter, channelIndex, TRUE); 823 } 824 } 825 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 826 break; 827 828 case SATA_EVENT_CHANNEL_DISCONNECTED: 829 /* Handle only disconnects */ 830 if (flag == 0) 831 break; 832 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 833 pMvSataAdapter->adapterId, channelIndex)); 834 /* Flush pending commands */ 835 if(pMvSataAdapter->sataChannel[channelIndex]) 836 { 837 _VBUS_INST(&pAdapter->VBus) 838 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 839 MV_FLUSH_TYPE_CALLBACK); 840 CheckPendingCall(_VBUS_P0); 841 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 842 hptmv_free_channel(pAdapter, channelIndex); 843 pMvSataAdapter->sataChannel[channelIndex] = NULL; 844 KdPrint(("RR18xx [%d,%d]: channel removed\n", 845 pMvSataAdapter->adapterId, channelIndex)); 846 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 847 Check_Idle_Call(pAdapter); 848 } 849 else 850 { 851 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 852 pMvSataAdapter->adapterId, channelIndex)); 853 } 854 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 855 break; 856 857 case SATA_EVENT_NO_CHANGE: 858 break; 859 860 default: 861 break; 862 } 863 } 864 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 865 } 866 867 #define EVENT_CONNECT 1 868 #define EVENT_DISCONNECT 0 869 870 static void 871 hptmv_handle_event_connect(void *data) 872 { 873 hptmv_handle_event (data, 0); 874 } 875 876 static void 877 hptmv_handle_event_disconnect(void *data) 878 { 879 hptmv_handle_event (data, 1); 880 } 881 882 static MV_BOOLEAN 883 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 884 MV_U32 param1, MV_U32 param2) 885 { 886 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 887 888 switch (eventType) 889 { 890 case MV_EVENT_TYPE_SATA_CABLE: 891 { 892 MV_U8 channel = param2; 893 894 if (param1 == EVENT_CONNECT) 895 { 896 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 897 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 898 pMvSataAdapter->adapterId, channel)); 899 /* Delete previous timers (if multiple drives connected in the same time */ 900 pAdapter->event_timer_connect = timeout(hptmv_handle_event_connect, pAdapter, 10*hz); 901 } 902 else if (param1 == EVENT_DISCONNECT) 903 { 904 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 905 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 906 pMvSataAdapter->adapterId, channel)); 907 device_change(pAdapter, channel, FALSE); 908 /* Delete previous timers (if multiple drives disconnected in the same time */ 909 /*pAdapter->event_timer_disconnect = timeout(hptmv_handle_event_disconnect, pAdapter, 10*hz); */ 910 /*It is not necessary to wait, handle it directly*/ 911 hptmv_handle_event_disconnect(pAdapter); 912 } 913 else 914 { 915 916 MV_ERROR("RR18xx: illigal value for param1(%d) at " 917 "connect/disconect event, host=%d\n", param1, 918 pMvSataAdapter->adapterId ); 919 920 } 921 } 922 break; 923 case MV_EVENT_TYPE_ADAPTER_ERROR: 924 KdPrint(("RR18xx: DEVICE error event received, pci cause " 925 "reg=%x, don't how to handle this\n", param1)); 926 return MV_TRUE; 927 default: 928 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 929 pMvSataAdapter->adapterId, eventType); 930 return MV_FALSE; 931 } 932 return MV_TRUE; 933 } 934 935 static int 936 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 937 { 938 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 939 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 940 if (pAdapter->requestsArrayBaseAddr == NULL) 941 { 942 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 943 " queues\n", pAdapter->mvSataAdapter.adapterId); 944 return -1; 945 } 946 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 947 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 948 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 949 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 950 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 951 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 952 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 953 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 954 955 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 956 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 957 { 958 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 959 pAdapter->mvSataAdapter.adapterId); 960 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 961 return -1; 962 } 963 /* response queues */ 964 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 965 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 966 if (pAdapter->responsesArrayBaseAddr == NULL) 967 { 968 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 969 " queues\n", pAdapter->mvSataAdapter.adapterId); 970 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 971 return -1; 972 } 973 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 974 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 975 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 976 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 977 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 978 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 979 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 980 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 981 982 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 983 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 984 { 985 MV_ERROR("RR18xx[%d]: Error in Response Quueues Alignment\n", 986 pAdapter->mvSataAdapter.adapterId); 987 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 988 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 989 return -1; 990 } 991 return 0; 992 } 993 994 static void 995 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 996 { 997 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 998 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 999 } 1000 1001 static PVOID 1002 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 1003 { 1004 PVOID ret; 1005 if (pAdapter->pFreePRDLink) { 1006 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 1007 ret = pAdapter->pFreePRDLink; 1008 pAdapter->pFreePRDLink = *(void**)ret; 1009 return ret; 1010 } 1011 return NULL; 1012 } 1013 1014 static void 1015 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 1016 { 1017 *(void**)PRDTable = pAdapter->pFreePRDLink; 1018 pAdapter->pFreePRDLink = PRDTable; 1019 } 1020 1021 extern PVDevice fGetFirstChild(PVDevice pLogical); 1022 extern void fResetBootMark(PVDevice pLogical); 1023 static void 1024 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 1025 { 1026 PVDevice pPhysical, pLogical; 1027 PVBus pVBus; 1028 int i,j; 1029 1030 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 1031 pPhysical = &(pAdapter->VDevices[i]); 1032 pLogical = pPhysical; 1033 while (pLogical->pParent) pLogical = pLogical->pParent; 1034 if (pLogical->vf_online==0) { 1035 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 1036 continue; 1037 } 1038 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1039 continue; 1040 1041 pVBus = &pAdapter->VBus; 1042 if(pVBus) 1043 { 1044 j=0; 1045 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1046 if(j<MAX_VDEVICE_PER_VBUS){ 1047 pVBus->pVDevice[j] = pLogical; 1048 pLogical->pVBus = pVBus; 1049 1050 if (j>0 && pLogical->vf_bootmark) { 1051 if (pVBus->pVDevice[0]->vf_bootmark) { 1052 fResetBootMark(pLogical); 1053 } 1054 else { 1055 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1056 pVBus->pVDevice[0] = pLogical; 1057 } 1058 } 1059 } 1060 } 1061 } 1062 } 1063 1064 PVDevice 1065 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1066 { 1067 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1068 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1069 LBA_T thiscap, maxcap = MAX_LBA_T; 1070 PVDevice pVDevice, pFind = NULL; 1071 int i; 1072 1073 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1074 { 1075 pVDevice = &pAdapter->VDevices[i]; 1076 if(!pVDevice) 1077 continue; 1078 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1079 /* find the smallest usable spare disk */ 1080 if (pVDevice->VDeviceType==VD_SPARE && 1081 pVDevice->u.disk.df_on_line && 1082 thiscap < maxcap && 1083 thiscap >= capacity) 1084 { 1085 maxcap = pVDevice->VDeviceCapacity; 1086 pFind = pVDevice; 1087 } 1088 } 1089 return pFind; 1090 } 1091 1092 /****************************************************************** 1093 * IO ATA Command 1094 *******************************************************************/ 1095 int HPTLIBAPI 1096 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1097 { 1098 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1099 } 1100 1101 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1102 { 1103 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1104 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1105 MV_U8 channelIndex = pSataChannel->channelNumber; 1106 UCHAR mvMode; 1107 /* 508x don't use MW-DMA? */ 1108 if (NewMode>4 && NewMode<8) NewMode = 4; 1109 pDev->bDeModeSetting = NewMode; 1110 if (NewMode<=4) 1111 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1112 else 1113 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1114 1115 /*To fix 88i8030 bug*/ 1116 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1117 mvMode = MV_ATA_TRANSFER_UDMA_0; 1118 1119 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1120 /* Flush pending commands */ 1121 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1122 1123 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1124 MV_ATA_SET_FEATURES_TRANSFER, 1125 mvMode, 0, 0, 0) == MV_FALSE) 1126 { 1127 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1128 } 1129 /* Enable EDMA */ 1130 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1131 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1132 } 1133 1134 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1135 { 1136 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1137 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1138 MV_U8 channelIndex = pSataChannel->channelNumber; 1139 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1140 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1141 int dmaActive = pSataChannel->queueCommandsEnabled; 1142 int ret = 0; 1143 1144 if (dmaActive) { 1145 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1146 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1147 } 1148 1149 if (enable) { 1150 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1151 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1152 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1153 channelInfo->queueDepth = (depth==32)? 31 : depth; 1154 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1155 ret = 1; 1156 } 1157 } 1158 else 1159 { 1160 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1161 channelInfo->queueDepth = 2; 1162 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1163 ret = 1; 1164 } 1165 } 1166 1167 if (dmaActive) 1168 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1169 return ret; 1170 } 1171 1172 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1173 { 1174 return 0; 1175 } 1176 1177 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1178 { 1179 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1180 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1181 MV_U8 channelIndex = pSataChannel->channelNumber; 1182 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1183 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1184 int dmaActive = pSataChannel->queueCommandsEnabled; 1185 int ret = 0; 1186 1187 if (dmaActive) { 1188 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1189 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1190 } 1191 1192 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1193 if (enable) { 1194 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1195 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1196 { 1197 channelInfo->writeCacheEnabled = MV_TRUE; 1198 ret = 1; 1199 } 1200 } 1201 else { 1202 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1203 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1204 { 1205 channelInfo->writeCacheEnabled = MV_FALSE; 1206 ret = 1; 1207 } 1208 } 1209 } 1210 1211 if (dmaActive) 1212 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1213 return ret; 1214 } 1215 1216 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1217 { 1218 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1219 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1220 MV_U8 channelIndex = pSataChannel->channelNumber; 1221 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1222 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1223 int dmaActive = pSataChannel->queueCommandsEnabled; 1224 int ret = 0; 1225 1226 if (dmaActive) { 1227 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1228 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1229 } 1230 1231 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1232 if (enable) { 1233 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1234 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1235 { 1236 channelInfo->readAheadEnabled = MV_TRUE; 1237 ret = 1; 1238 } 1239 } 1240 else { 1241 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1242 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1243 { 1244 channelInfo->readAheadEnabled = MV_FALSE; 1245 ret = 1; 1246 } 1247 } 1248 } 1249 1250 if (dmaActive) 1251 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1252 return ret; 1253 } 1254 1255 #ifdef SUPPORT_ARRAY 1256 #define IdeRegisterVDevice fCheckArray 1257 #else 1258 void 1259 IdeRegisterVDevice(PDevice pDev) 1260 { 1261 PVDevice pVDev = Map2pVDevice(pDev); 1262 1263 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1264 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1265 pVDev->vf_online = 1; 1266 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1267 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1268 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1269 } 1270 #endif 1271 1272 static __inline PBUS_DMAMAP 1273 dmamap_get(struct IALAdapter * pAdapter) 1274 { 1275 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1276 if (p) 1277 pAdapter->pbus_dmamap_list = p-> next; 1278 return p; 1279 } 1280 1281 static __inline void 1282 dmamap_put(PBUS_DMAMAP p) 1283 { 1284 p->next = p->pAdapter->pbus_dmamap_list; 1285 p->pAdapter->pbus_dmamap_list = p; 1286 } 1287 1288 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/ 1289 #if __FreeBSD_version >= 500000 1290 #define override_kernel_driver() 1291 1292 static void hpt_init(void *dummy) 1293 { 1294 override_kernel_driver(); 1295 mtx_init(&driver_lock, "hptsleeplock", NULL, MTX_DEF); 1296 } 1297 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL); 1298 #endif 1299 1300 static int num_adapters = 0; 1301 static int 1302 init_adapter(IAL_ADAPTER_T *pAdapter) 1303 { 1304 PVBus _vbus_p = &pAdapter->VBus; 1305 MV_SATA_ADAPTER *pMvSataAdapter; 1306 int i, channel, rid; 1307 1308 PVDevice pVDev; 1309 1310 intrmask_t oldspl = lock_driver(); 1311 1312 pAdapter->next = 0; 1313 1314 if(gIal_Adapter == 0){ 1315 gIal_Adapter = pAdapter; 1316 pCurAdapter = gIal_Adapter; 1317 } 1318 else { 1319 pCurAdapter->next = pAdapter; 1320 pCurAdapter = pAdapter; 1321 } 1322 1323 pAdapter->outstandingCommands = 0; 1324 1325 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1326 _vbus_p->OsExt = (void *)pAdapter; 1327 pMvSataAdapter->IALData = pAdapter; 1328 1329 if (bus_dma_tag_create(NULL,/* parent */ 1330 4, /* alignment */ 1331 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1332 BUS_SPACE_MAXADDR, /* lowaddr */ 1333 BUS_SPACE_MAXADDR, /* highaddr */ 1334 NULL, NULL, /* filter, filterarg */ 1335 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1336 MAX_SG_DESCRIPTORS, /* nsegments */ 1337 0x10000, /* maxsegsize */ 1338 BUS_DMA_WAITOK, /* flags */ 1339 #if __FreeBSD_version>502000 1340 busdma_lock_mutex, /* lockfunc */ 1341 &driver_lock, /* lockfuncarg */ 1342 #endif 1343 &pAdapter->io_dma_parent /* tag */)) 1344 { 1345 return ENXIO; 1346 } 1347 1348 1349 if (hptmv_allocate_edma_queues(pAdapter)) 1350 { 1351 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1352 unlock_driver(oldspl); 1353 return ENOMEM; 1354 } 1355 1356 /* also map EPROM address */ 1357 rid = 0x10; 1358 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid, 1359 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE)) 1360 || 1361 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1362 { 1363 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1364 hptmv_free_edma_queues(pAdapter); 1365 unlock_driver(oldspl); 1366 return ENXIO; 1367 } 1368 else 1369 { 1370 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1371 } 1372 1373 pMvSataAdapter->adapterId = num_adapters++; 1374 /* get the revision ID */ 1375 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1376 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1377 1378 /* init RR18xx */ 1379 pMvSataAdapter->intCoalThre[0]= 1; 1380 pMvSataAdapter->intCoalThre[1]= 1; 1381 pMvSataAdapter->intTimeThre[0] = 1; 1382 pMvSataAdapter->intTimeThre[1] = 1; 1383 pMvSataAdapter->pciCommand = 0x0107E371; 1384 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1385 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1386 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1387 1388 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1389 { 1390 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1391 pMvSataAdapter->adapterId); 1392 unregister: 1393 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1394 hptmv_free_edma_queues(pAdapter); 1395 unlock_driver(oldspl); 1396 return ENXIO; 1397 } 1398 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1399 1400 #ifndef FOR_DEMO 1401 set_fail_leds(pMvSataAdapter, 0); 1402 #endif 1403 1404 /* setup command blocks */ 1405 KdPrint(("Allocate command blocks\n")); 1406 _vbus_(pFreeCommands) = 0; 1407 pAdapter->pCommandBlocks = 1408 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1409 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1410 if (!pAdapter->pCommandBlocks) { 1411 MV_ERROR("insufficient memory\n"); 1412 goto unregister; 1413 } 1414 1415 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1416 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1417 } 1418 1419 /*Set up the bus_dmamap*/ 1420 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1421 if(!pAdapter->pbus_dmamap) { 1422 MV_ERROR("insufficient memory\n"); 1423 free(pAdapter->pCommandBlocks, M_DEVBUF); 1424 goto unregister; 1425 } 1426 1427 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1428 pAdapter->pbus_dmamap_list = 0; 1429 for (i=0; i < MAX_QUEUE_COMM; i++) { 1430 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1431 pmap->pAdapter = pAdapter; 1432 dmamap_put(pmap); 1433 1434 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1435 MV_ERROR("Can not allocate dma map\n"); 1436 free(pAdapter->pCommandBlocks, M_DEVBUF); 1437 free(pAdapter->pbus_dmamap, M_DEVBUF); 1438 goto unregister; 1439 } 1440 } 1441 /* setup PRD Tables */ 1442 KdPrint(("Allocate PRD Tables\n")); 1443 pAdapter->pFreePRDLink = 0; 1444 1445 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1446 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1447 1448 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1449 if (!pAdapter->prdTableAddr) { 1450 MV_ERROR("insufficient PRD Tables\n"); 1451 goto unregister; 1452 } 1453 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1454 { 1455 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1456 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1457 { 1458 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1459 FreePRDTable(pAdapter, PRDTable); 1460 PRDTable += PRD_ENTRIES_SIZE; 1461 } 1462 } 1463 1464 /* enable the adapter interrupts */ 1465 1466 /* configure and start the connected channels*/ 1467 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1468 { 1469 pAdapter->mvChannel[channel].online = MV_FALSE; 1470 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1471 == MV_TRUE) 1472 { 1473 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1474 pMvSataAdapter->adapterId, channel)); 1475 1476 if (hptmv_init_channel(pAdapter, channel) == 0) 1477 { 1478 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1479 { 1480 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1481 " %d\n",pMvSataAdapter->adapterId, channel); 1482 hptmv_free_channel(pAdapter, channel); 1483 } 1484 else 1485 { 1486 if (start_channel(pAdapter, channel)) 1487 { 1488 MV_ERROR("RR18xx[%d]: Failed to start channel," 1489 " channel=%d\n",pMvSataAdapter->adapterId, 1490 channel); 1491 hptmv_free_channel(pAdapter, channel); 1492 } 1493 pAdapter->mvChannel[channel].online = MV_TRUE; 1494 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1495 channel, 1496 MV_TRUE);*/ 1497 } 1498 } 1499 } 1500 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1501 pAdapter->mvChannel[channel].online, channel)); 1502 } 1503 1504 #ifdef SUPPORT_ARRAY 1505 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1506 pVDev = ArrayTables(i); 1507 mArFreeArrayTable(pVDev); 1508 } 1509 #endif 1510 1511 KdPrint(("Initialize Devices\n")); 1512 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1513 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1514 if (pMvSataChannel) { 1515 init_vdev_params(pAdapter, channel); 1516 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1517 } 1518 } 1519 #ifdef SUPPORT_ARRAY 1520 CheckArrayCritical(_VBUS_P0); 1521 #endif 1522 _vbus_p->nInstances = 1; 1523 fRegisterVdevice(pAdapter); 1524 1525 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1526 pVDev = _vbus_p->pVDevice[channel]; 1527 if (pVDev && pVDev->vf_online) 1528 fCheckBootable(pVDev); 1529 } 1530 1531 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1532 init_raid5_memory(_VBUS_P0); 1533 _vbus_(r5).enable_write_back = 1; 1534 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1535 #endif 1536 1537 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1538 unlock_driver(oldspl); 1539 return 0; 1540 } 1541 1542 int 1543 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1544 { 1545 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1546 1547 mvSataDisableChannelDma(pMvSataAdapter, channel); 1548 /* Flush pending commands */ 1549 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1550 1551 /* Software reset channel */ 1552 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1553 { 1554 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1555 pMvSataAdapter->adapterId, channel); 1556 hptmv_free_channel(pAdapter, channel); 1557 return -1; 1558 } 1559 1560 /* Hardware reset channel */ 1561 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1562 { 1563 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1564 pMvSataAdapter->adapterId, channel); 1565 hptmv_free_channel(pAdapter, channel); 1566 return -1; 1567 } 1568 1569 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1570 { 1571 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1572 pMvSataAdapter->adapterId, channel); 1573 hptmv_free_channel(pAdapter, channel); 1574 return -1; 1575 }else 1576 { 1577 MV_ERROR("channel %d: perform recalibrate command", channel); 1578 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1579 MV_NON_UDMA_PROTOCOL_NON_DATA, 1580 MV_FALSE, 1581 NULL, /* pBuffer*/ 1582 0, /* count */ 1583 0, /*features*/ 1584 /* sectorCount */ 1585 0, 1586 0, /* lbaLow */ 1587 0, /* lbaMid */ 1588 /* lbaHigh */ 1589 0, 1590 0, /* device */ 1591 /* command */ 1592 0x10)) 1593 MV_ERROR("channel %d: recalibrate failed", channel); 1594 1595 /* Set transfer mode */ 1596 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1597 MV_ATA_SET_FEATURES_TRANSFER, 1598 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1599 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1600 MV_ATA_SET_FEATURES_TRANSFER, 1601 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1602 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1603 MV_ATA_SET_FEATURES_TRANSFER, 1604 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1605 { 1606 MV_ERROR("channel %d: Set Features failed", channel); 1607 hptmv_free_channel(pAdapter, channel); 1608 return -1; 1609 } 1610 /* Enable EDMA */ 1611 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1612 { 1613 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1614 hptmv_free_channel(pAdapter, channel); 1615 return -1; 1616 } 1617 } 1618 return 0; 1619 } 1620 1621 static int 1622 fResetActiveCommands(PVBus _vbus_p) 1623 { 1624 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1625 MV_U8 channel; 1626 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1627 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1628 MvSataResetChannel(pMvSataAdapter,channel); 1629 } 1630 return 0; 1631 } 1632 1633 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1634 { 1635 UINT cont; 1636 ULONG ticks = 0; 1637 MV_U8 channel; 1638 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1639 MV_SATA_CHANNEL *pMvSataChannel; 1640 1641 do { 1642 check_cmds: 1643 cont = 0; 1644 CheckPendingCall(_VBUS_P0); 1645 #ifdef _RAID5N_ 1646 dataxfer_poll(); 1647 xor_poll(); 1648 #endif 1649 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1650 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1651 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1652 { 1653 while (pMvSataChannel->outstandingCommands) { 1654 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1655 StallExec(1000); 1656 if (ticks++ > 3000) { 1657 MvSataResetChannel(pMvSataAdapter,channel); 1658 goto check_cmds; 1659 } 1660 } 1661 else 1662 ticks = 0; 1663 } 1664 cont = 1; 1665 } 1666 } 1667 } while (cont); 1668 } 1669 1670 void 1671 fResetVBus(_VBUS_ARG0) 1672 { 1673 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1674 1675 /* some commands may already finished. */ 1676 CheckPendingCall(_VBUS_P0); 1677 1678 fResetActiveCommands(_vbus_p); 1679 /* 1680 * the other pending commands may still be finished successfully. 1681 */ 1682 fCompleteAllCommandsSynchronously(_vbus_p); 1683 1684 /* Now there should be no pending commands. No more action needed. */ 1685 CheckIdleCall(_VBUS_P0); 1686 1687 KdPrint(("fMvResetBus() done")); 1688 } 1689 1690 /*No rescan function*/ 1691 void 1692 fRescanAllDevice(_VBUS_ARG0) 1693 { 1694 } 1695 1696 static MV_BOOLEAN 1697 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1698 MV_U8 channelNum, 1699 MV_COMPLETION_TYPE comp_type, 1700 MV_VOID_PTR commandId, 1701 MV_U16 responseFlags, 1702 MV_U32 timeStamp, 1703 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1704 { 1705 PCommand pCmd = (PCommand) commandId; 1706 _VBUS_INST(pCmd->pVDevice->pVBus) 1707 1708 if (pCmd->uScratch.sata_param.prdAddr) 1709 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1710 1711 switch (comp_type) 1712 { 1713 case MV_COMPLETION_TYPE_NORMAL: 1714 pCmd->Result = RETURN_SUCCESS; 1715 break; 1716 case MV_COMPLETION_TYPE_ABORT: 1717 pCmd->Result = RETURN_BUS_RESET; 1718 break; 1719 case MV_COMPLETION_TYPE_ERROR: 1720 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1721 pMvSataAdapter->adapterId, channelNum, responseFlags); 1722 1723 if (responseFlags & 4) { 1724 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1725 " LBA high %x, device %x, status %x\n", 1726 registerStruct->errorRegister, 1727 registerStruct->sectorCountRegister, 1728 registerStruct->lbaLowRegister, 1729 registerStruct->lbaMidRegister, 1730 registerStruct->lbaHighRegister, 1731 registerStruct->deviceRegister, 1732 registerStruct->statusRegister); 1733 } 1734 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1735 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1736 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1737 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1738 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1739 pCmd->pVDevice->u.disk.QueueLength--; 1740 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1741 return TRUE; 1742 1743 default: 1744 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1745 return MV_FALSE; 1746 } 1747 1748 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1749 pCmd->uScratch.sata_param.cmd_priv --; 1750 return TRUE; 1751 } 1752 pCmd->pVDevice->u.disk.QueueLength--; 1753 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1754 return TRUE; 1755 } 1756 1757 void 1758 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1759 { 1760 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1761 MV_SATA_ADAPTER *pMvSataAdapter; 1762 MV_SATA_CHANNEL *pMvSataChannel; 1763 PVDevice pVDevice = pCmd->pVDevice; 1764 PDevice pDevice = &pVDevice->u.disk; 1765 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1766 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1767 1768 MV_QUEUE_COMMAND_RESULT result; 1769 MV_QUEUE_COMMAND_INFO commandInfo; 1770 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1771 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1772 1773 MV_BOOLEAN is48bit; 1774 MV_U8 channel; 1775 int i=0; 1776 1777 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1778 1779 if (!pDevice->df_on_line) { 1780 MV_ERROR("Device is offline"); 1781 pCmd->Result = RETURN_BAD_DEVICE; 1782 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1783 return; 1784 } 1785 1786 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1787 pMvSataChannel = pDevice->mv; 1788 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1789 channel = pMvSataChannel->channelNumber; 1790 1791 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1792 Lba += pDevice->dDeHiddenLba; 1793 /* check LBA */ 1794 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1795 pCmd->Result = RETURN_INVALID_REQUEST; 1796 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1797 return; 1798 } 1799 1800 /* 1801 * always use 48bit LBA if drive supports it. 1802 * Some Seagate drives report error if you use a 28-bit command 1803 * to access sector 0xfffffff. 1804 */ 1805 is48bit = pMvSataChannel->lba48Address; 1806 1807 switch (pCmd->uCmd.Ide.Command) 1808 { 1809 case IDE_COMMAND_READ: 1810 case IDE_COMMAND_WRITE: 1811 if (pDevice->bDeModeSetting<8) goto pio; 1812 1813 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1814 pUdmaParams->isEXT = is48bit; 1815 pUdmaParams->numOfSectors = nSector; 1816 pUdmaParams->lowLBAAddress = Lba; 1817 pUdmaParams->highLBAAddress = 0; 1818 pUdmaParams->prdHighAddr = 0; 1819 pUdmaParams->callBack = CommandCompletionCB; 1820 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1821 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1822 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1823 else 1824 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1825 1826 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1827 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1828 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1829 } 1830 else { 1831 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1832 pio: 1833 mvSataDisableChannelDma(pMvSataAdapter, channel); 1834 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1835 1836 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1837 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1838 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1839 } 1840 else { 1841 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1842 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1843 goto finish_cmd; 1844 } 1845 } 1846 1847 do { 1848 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1849 ULONG_PTR addr = tmpSg->dSgAddress; 1850 if (size & 0x1ff) { 1851 pCmd->Result = RETURN_INVALID_REQUEST; 1852 goto finish_cmd; 1853 } 1854 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1855 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1856 is48bit, 1857 (MV_U16_PTR)addr, 1858 size >> 1, /* count */ 1859 0, /* features N/A */ 1860 (MV_U16)(size>>9), /*sector count*/ 1861 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1862 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1863 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1864 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1865 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1866 )==MV_FALSE) 1867 { 1868 pCmd->Result = RETURN_IDE_ERROR; 1869 goto finish_cmd; 1870 } 1871 Lba += size>>9; 1872 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1873 } 1874 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1875 pCmd->Result = RETURN_SUCCESS; 1876 finish_cmd: 1877 mvSataEnableChannelDma(pMvSataAdapter,channel); 1878 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1879 return; 1880 } 1881 } 1882 1883 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1884 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1885 if (!pPRDTable) { 1886 pCmd->Result = RETURN_DEVICE_BUSY; 1887 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1888 HPT_ASSERT(0); 1889 return; 1890 } 1891 1892 do{ 1893 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1894 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1895 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1896 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1897 pPRDTable[i].reserved = 0; 1898 i++; 1899 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1900 1901 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1902 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1903 pUdmaParams->numOfSectors = 0; 1904 } 1905 1906 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1907 1908 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1909 1910 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1911 { 1912 queue_failed: 1913 switch (result) 1914 { 1915 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1916 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1917 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1918 pCmd->Result = RETURN_IDE_ERROR; 1919 break; 1920 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1921 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1922 " disabled adapter %d channel %d\n", 1923 pMvSataAdapter->adapterId, channel); 1924 mvSataEnableChannelDma(pMvSataAdapter,channel); 1925 pCmd->Result = RETURN_IDE_ERROR; 1926 break; 1927 case MV_QUEUE_COMMAND_RESULT_FULL: 1928 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1929 " Full adapter %d channel %d\n", 1930 pMvSataAdapter->adapterId, channel); 1931 pCmd->Result = RETURN_DEVICE_BUSY; 1932 break; 1933 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1934 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1935 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1936 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1937 pCmd->Result = RETURN_IDE_ERROR; 1938 break; 1939 default: 1940 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1941 " command\n", result); 1942 pCmd->Result = RETURN_IDE_ERROR; 1943 } 1944 if(pPRDTable) 1945 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1946 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1947 } 1948 pDevice->QueueLength++; 1949 return; 1950 1951 case IDE_COMMAND_VERIFY: 1952 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1953 pNoUdmaParams->bufPtr = NULL; 1954 pNoUdmaParams->callBack = CommandCompletionCB; 1955 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1956 pNoUdmaParams->count = 0; 1957 pNoUdmaParams->features = 0; 1958 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1959 1960 pCmd->uScratch.sata_param.cmd_priv = 1; 1961 if (pMvSataChannel->lba48Address == MV_TRUE){ 1962 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1963 pNoUdmaParams->isEXT = MV_TRUE; 1964 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1965 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1966 pNoUdmaParams->lbaLow = 1967 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1968 pNoUdmaParams->sectorCount = nSector; 1969 pNoUdmaParams->device = 0x40; 1970 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1971 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1972 goto queue_failed; 1973 } 1974 return; 1975 } 1976 else{ 1977 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1978 pNoUdmaParams->isEXT = MV_FALSE; 1979 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1980 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1981 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1982 pNoUdmaParams->sectorCount = 0xff & nSector; 1983 pNoUdmaParams->device = (MV_U8)(0x40 | 1984 ((Lba & 0xf000000) >> 24)); 1985 pNoUdmaParams->callBack = CommandCompletionCB; 1986 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1987 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1988 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1989 goto queue_failed; 1990 } 1991 } 1992 break; 1993 default: 1994 pCmd->Result = RETURN_INVALID_REQUEST; 1995 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1996 break; 1997 } 1998 } 1999 2000 /********************************************************** 2001 * 2002 * Probe the hostadapter. 2003 * 2004 **********************************************************/ 2005 static int 2006 hpt_probe(device_t dev) 2007 { 2008 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 2009 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 2010 #ifdef FOR_DEMO 2011 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 2012 #endif 2013 )) 2014 { 2015 KdPrintI((CONTROLLER_NAME " found\n")); 2016 device_set_desc(dev, CONTROLLER_NAME); 2017 return 0; 2018 } 2019 else 2020 return(ENXIO); 2021 } 2022 2023 /*********************************************************** 2024 * 2025 * Auto configuration: attach and init a host adapter. 2026 * 2027 ***********************************************************/ 2028 static int 2029 hpt_attach(device_t dev) 2030 { 2031 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 2032 int rid; 2033 union ccb *ccb; 2034 struct cam_devq *devq; 2035 struct cam_sim *hpt_vsim; 2036 2037 printf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 2038 2039 if (!pAdapter) 2040 { 2041 pAdapter = (IAL_ADAPTER_T *)malloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT); 2042 #if __FreeBSD_version > 410000 2043 device_set_softc(dev, (void *)pAdapter); 2044 #else 2045 device_set_driver(dev, (driver_t *)pAdapter); 2046 #endif 2047 } 2048 2049 if (!pAdapter) return (ENOMEM); 2050 bzero(pAdapter, sizeof(IAL_ADAPTER_T)); 2051 2052 pAdapter->hpt_dev = dev; 2053 2054 rid = init_adapter(pAdapter); 2055 if (rid) 2056 return rid; 2057 2058 rid = 0; 2059 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) 2060 { 2061 hpt_printk(("can't allocate interrupt\n")); 2062 return(ENXIO); 2063 } 2064 2065 #if __FreeBSD_version <700000 2066 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, 2067 hpt_intr, pAdapter, &pAdapter->hpt_intr)) 2068 #else 2069 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, 2070 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 2071 #endif 2072 { 2073 hpt_printk(("can't set up interrupt\n")); 2074 free(pAdapter, M_DEVBUF); 2075 return(ENXIO); 2076 } 2077 2078 2079 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL) 2080 { 2081 bzero(ccb, sizeof(*ccb)); 2082 ccb->ccb_h.pinfo.priority = 1; 2083 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2084 } 2085 else 2086 { 2087 return ENOMEM; 2088 } 2089 /* 2090 * Create the device queue for our SIM(s). 2091 */ 2092 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2093 { 2094 KdPrint(("ENXIO\n")); 2095 return ENOMEM; 2096 } 2097 2098 /* 2099 * Construct our SIM entry 2100 */ 2101 #if __FreeBSD_version <700000 2102 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2103 pAdapter, device_get_unit(pAdapter->hpt_dev), 1, 8, devq); 2104 #else 2105 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2106 pAdapter, device_get_unit(pAdapter->hpt_dev), &Giant, 1, 8, devq); 2107 #endif 2108 if (hpt_vsim == NULL) { 2109 cam_simq_free(devq); 2110 return ENOMEM; 2111 } 2112 2113 #if __FreeBSD_version <700000 2114 if (xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) 2115 #else 2116 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS) 2117 #endif 2118 { 2119 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 2120 hpt_vsim = NULL; 2121 return ENXIO; 2122 } 2123 2124 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2125 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2126 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2127 { 2128 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2129 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 2130 hpt_vsim = NULL; 2131 return ENXIO; 2132 } 2133 2134 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2135 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2136 ccb->csa.event_enable = AC_LOST_DEVICE; 2137 ccb->csa.callback = hpt_async; 2138 ccb->csa.callback_arg = hpt_vsim; 2139 xpt_action((union ccb *)ccb); 2140 free(ccb, M_DEVBUF); 2141 2142 if (device_get_unit(dev) == 0) { 2143 /* Start the work thread. XXX */ 2144 launch_worker_thread(); 2145 } 2146 2147 return 0; 2148 } 2149 2150 static int 2151 hpt_detach(device_t dev) 2152 { 2153 return (EBUSY); 2154 } 2155 2156 2157 /*************************************************************** 2158 * The poll function is used to simulate the interrupt when 2159 * the interrupt subsystem is not functioning. 2160 * 2161 ***************************************************************/ 2162 static void 2163 hpt_poll(struct cam_sim *sim) 2164 { 2165 hpt_intr((void *)cam_sim_softc(sim)); 2166 } 2167 2168 /**************************************************************** 2169 * Name: hpt_intr 2170 * Description: Interrupt handler. 2171 ****************************************************************/ 2172 static void 2173 hpt_intr(void *arg) 2174 { 2175 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg; 2176 intrmask_t oldspl = lock_driver(); 2177 2178 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2179 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2180 { 2181 _VBUS_INST(&pAdapter->VBus) 2182 CheckPendingCall(_VBUS_P0); 2183 } 2184 2185 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2186 unlock_driver(oldspl); 2187 } 2188 2189 /********************************************************** 2190 * Asynchronous Events 2191 *********************************************************/ 2192 #if (!defined(UNREFERENCED_PARAMETER)) 2193 #define UNREFERENCED_PARAMETER(x) (void)(x) 2194 #endif 2195 2196 static void 2197 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2198 void * arg) 2199 { 2200 /* debug XXXX */ 2201 panic("Here"); 2202 UNREFERENCED_PARAMETER(callback_arg); 2203 UNREFERENCED_PARAMETER(code); 2204 UNREFERENCED_PARAMETER(path); 2205 UNREFERENCED_PARAMETER(arg); 2206 2207 } 2208 2209 static void 2210 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2211 { 2212 int i; 2213 2214 hpt_printk(("flush all devices\n")); 2215 2216 /* flush all devices */ 2217 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2218 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2219 if(pVDev) fFlushVDev(pVDev); 2220 } 2221 } 2222 2223 static int 2224 hpt_shutdown(device_t dev) 2225 { 2226 IAL_ADAPTER_T *pAdapter; 2227 2228 pAdapter = device_get_softc(dev); 2229 if (pAdapter == NULL) 2230 return (EINVAL); 2231 2232 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2233 FlushAdapter(pAdapter); 2234 /* give the flush some time to happen, 2235 *otherwise "shutdown -p now" will make file system corrupted */ 2236 DELAY(1000 * 1000 * 5); 2237 return 0; 2238 } 2239 2240 void 2241 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2242 { 2243 _VBUS_INST(&pAdapter->VBus) 2244 2245 if (mWaitingForIdle(_VBUS_P0)) { 2246 CheckIdleCall(_VBUS_P0); 2247 #ifdef SUPPORT_ARRAY 2248 { 2249 int i; 2250 PVDevice pArray; 2251 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2252 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2253 continue; 2254 else if (pArray->u.array.rf_auto_rebuild) { 2255 KdPrint(("auto rebuild.\n")); 2256 pArray->u.array.rf_auto_rebuild = 0; 2257 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2258 } 2259 } 2260 } 2261 #endif 2262 } 2263 /* launch the awaiting commands blocked by mWaitingForIdle */ 2264 while(pAdapter->pending_Q!= NULL) 2265 { 2266 _VBUS_INST(&pAdapter->VBus) 2267 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2268 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2269 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2270 } 2271 } 2272 2273 static void 2274 ccb_done(union ccb *ccb) 2275 { 2276 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2277 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2278 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2279 2280 dmamap_put(pmap); 2281 xpt_done(ccb); 2282 2283 pAdapter->outstandingCommands--; 2284 2285 if (pAdapter->outstandingCommands == 0) 2286 { 2287 if(DPC_Request_Nums == 0) 2288 Check_Idle_Call(pAdapter); 2289 } 2290 } 2291 2292 /**************************************************************** 2293 * Name: hpt_action 2294 * Description: Process a queued command from the CAM layer. 2295 * Parameters: sim - Pointer to SIM object 2296 * ccb - Pointer to SCSI command structure. 2297 ****************************************************************/ 2298 2299 void 2300 hpt_action(struct cam_sim *sim, union ccb *ccb) 2301 { 2302 intrmask_t oldspl; 2303 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2304 PBUS_DMAMAP pmap; 2305 _VBUS_INST(&pAdapter->VBus) 2306 2307 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2308 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2309 2310 switch (ccb->ccb_h.func_code) 2311 { 2312 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2313 { 2314 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2315 2316 if (ccb->ccb_h.target_lun) { 2317 ccb->ccb_h.status = CAM_LUN_INVALID; 2318 xpt_done(ccb); 2319 return; 2320 } 2321 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2322 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2323 ccb->ccb_h.status = CAM_TID_INVALID; 2324 xpt_done(ccb); 2325 return; 2326 } 2327 2328 oldspl = lock_driver(); 2329 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2330 Check_Idle_Call(pAdapter); 2331 2332 pmap = dmamap_get(pAdapter); 2333 HPT_ASSERT(pmap); 2334 ccb->ccb_adapter = pmap; 2335 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2336 2337 if (mWaitingForIdle(_VBUS_P0)) 2338 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2339 else 2340 OsSendCommand(_VBUS_P ccb); 2341 unlock_driver(oldspl); 2342 2343 /* KdPrint(("leave scsiio\n")); */ 2344 break; 2345 } 2346 2347 case XPT_RESET_BUS: 2348 KdPrint(("reset bus\n")); 2349 oldspl = lock_driver(); 2350 fResetVBus(_VBUS_P0); 2351 unlock_driver(oldspl); 2352 xpt_done(ccb); 2353 break; 2354 2355 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2356 case XPT_EN_LUN: /* Enable LUN as a target */ 2357 case XPT_TARGET_IO: /* Execute target I/O request */ 2358 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2359 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2360 case XPT_ABORT: /* Abort the specified CCB */ 2361 case XPT_TERM_IO: /* Terminate the I/O process */ 2362 /* XXX Implement */ 2363 ccb->ccb_h.status = CAM_REQ_INVALID; 2364 xpt_done(ccb); 2365 break; 2366 2367 case XPT_GET_TRAN_SETTINGS: 2368 case XPT_SET_TRAN_SETTINGS: 2369 /* XXX Implement */ 2370 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2371 xpt_done(ccb); 2372 break; 2373 2374 case XPT_CALC_GEOMETRY: 2375 #if __FreeBSD_version >= 500000 2376 cam_calc_geometry(&ccb->ccg, 1); 2377 #else 2378 { 2379 struct ccb_calc_geometry *ccg; 2380 u_int32_t size_mb; 2381 u_int32_t secs_per_cylinder; 2382 2383 ccg = &ccb->ccg; 2384 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size); 2385 2386 if (size_mb > 1024 ) { 2387 ccg->heads = 255; 2388 ccg->secs_per_track = 63; 2389 } else { 2390 ccg->heads = 64; 2391 ccg->secs_per_track = 32; 2392 } 2393 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2394 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2395 ccb->ccb_h.status = CAM_REQ_CMP; 2396 } 2397 #endif 2398 xpt_done(ccb); 2399 break; 2400 2401 case XPT_PATH_INQ: /* Path routing inquiry */ 2402 { 2403 struct ccb_pathinq *cpi = &ccb->cpi; 2404 2405 cpi->version_num = 1; /* XXX??? */ 2406 cpi->hba_inquiry = PI_SDTR_ABLE; 2407 cpi->target_sprt = 0; 2408 /* Not necessary to reset bus */ 2409 cpi->hba_misc = PIM_NOBUSRESET; 2410 cpi->hba_eng_cnt = 0; 2411 2412 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2413 cpi->max_lun = 0; 2414 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2415 2416 cpi->bus_id = cam_sim_bus(sim); 2417 cpi->base_transfer_speed = 3300; 2418 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2419 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2420 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2421 cpi->unit_number = cam_sim_unit(sim); 2422 cpi->transport = XPORT_SPI; 2423 cpi->transport_version = 2; 2424 cpi->protocol = PROTO_SCSI; 2425 cpi->protocol_version = SCSI_REV_2; 2426 cpi->ccb_h.status = CAM_REQ_CMP; 2427 xpt_done(ccb); 2428 break; 2429 } 2430 2431 default: 2432 KdPrint(("invalid cmd\n")); 2433 ccb->ccb_h.status = CAM_REQ_INVALID; 2434 xpt_done(ccb); 2435 break; 2436 } 2437 /* KdPrint(("leave hpt_action..............\n")); */ 2438 } 2439 2440 /* shall be called at lock_driver() */ 2441 static void 2442 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2443 { 2444 if(*ccb_Q == NULL) 2445 ccb->ccb_h.ccb_ccb_ptr = ccb; 2446 else { 2447 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2448 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2449 } 2450 2451 *ccb_Q = ccb; 2452 } 2453 2454 /* shall be called at lock_driver() */ 2455 static void 2456 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2457 { 2458 union ccb *TempCCB; 2459 2460 TempCCB = *ccb_Q; 2461 2462 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2463 *ccb_Q = NULL; 2464 else { 2465 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2466 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2467 2468 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2469 2470 if(*ccb_Q == ccb) 2471 *ccb_Q = TempCCB; 2472 } 2473 } 2474 2475 #ifdef SUPPORT_ARRAY 2476 /*************************************************************************** 2477 * Function: hpt_worker_thread 2478 * Description: Do background rebuilding. Execute in kernel thread context. 2479 * Returns: None 2480 ***************************************************************************/ 2481 static void hpt_worker_thread(void) 2482 { 2483 intrmask_t oldspl; 2484 2485 for(;;) { 2486 while (DpcQueue_First!=DpcQueue_Last) { 2487 ST_HPT_DPC p; 2488 oldspl = lock_driver(); 2489 p = DpcQueue[DpcQueue_First]; 2490 DpcQueue_First++; 2491 DpcQueue_First %= MAX_DPC; 2492 DPC_Request_Nums++; 2493 unlock_driver(oldspl); 2494 p.dpc(p.pAdapter, p.arg, p.flags); 2495 2496 oldspl = lock_driver(); 2497 DPC_Request_Nums--; 2498 /* since we may have prevented Check_Idle_Call, do it here */ 2499 if (DPC_Request_Nums==0) { 2500 if (p.pAdapter->outstandingCommands == 0) { 2501 _VBUS_INST(&p.pAdapter->VBus); 2502 Check_Idle_Call(p.pAdapter); 2503 CheckPendingCall(_VBUS_P0); 2504 } 2505 } 2506 unlock_driver(oldspl); 2507 2508 /*Schedule out*/ 2509 #if (__FreeBSD_version < 500000) 2510 YIELD_THREAD; 2511 #else 2512 #if (__FreeBSD_version > 700033) 2513 pause("sched", 1); 2514 #else 2515 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "sched", 1); 2516 #endif 2517 #endif 2518 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2519 /* abort rebuilding process. */ 2520 IAL_ADAPTER_T *pAdapter; 2521 PVDevice pArray; 2522 PVBus _vbus_p; 2523 int i; 2524 pAdapter = gIal_Adapter; 2525 2526 while(pAdapter != 0){ 2527 2528 _vbus_p = &pAdapter->VBus; 2529 2530 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2531 { 2532 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2533 continue; 2534 else if (pArray->u.array.rf_rebuilding || 2535 pArray->u.array.rf_verifying || 2536 pArray->u.array.rf_initializing) 2537 { 2538 pArray->u.array.rf_abort_rebuild = 1; 2539 } 2540 } 2541 pAdapter = pAdapter->next; 2542 } 2543 } 2544 } 2545 2546 /*Remove this debug option*/ 2547 /* 2548 #ifdef DEBUG 2549 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2550 #if (__FreeBSD_version > 700033) 2551 pause("hptrdy", 2*hz); 2552 #else 2553 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); 2554 #endif 2555 #endif 2556 */ 2557 #if (__FreeBSD_version >= 800002) 2558 kproc_suspend_check(curproc); 2559 #elif (__FreeBSD_version >= 500043) 2560 kthread_suspend_check(curproc); 2561 #else 2562 kproc_suspend_loop(curproc); 2563 #endif 2564 #if (__FreeBSD_version > 700033) 2565 pause("hptrdy", 2*hz); /* wait for something to do */ 2566 #else 2567 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); /* wait for something to do */ 2568 #endif 2569 } 2570 } 2571 2572 static struct proc *hptdaemonproc; 2573 static struct kproc_desc hpt_kp = { 2574 "hpt_wt", 2575 hpt_worker_thread, 2576 &hptdaemonproc 2577 }; 2578 2579 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2580 static void 2581 launch_worker_thread(void) 2582 { 2583 IAL_ADAPTER_T *pAdapTemp; 2584 2585 kproc_start(&hpt_kp); 2586 2587 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2588 2589 _VBUS_INST(&pAdapTemp->VBus) 2590 int i; 2591 PVDevice pVDev; 2592 2593 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2594 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2595 continue; 2596 else{ 2597 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2598 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2599 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2600 } 2601 } 2602 2603 /* 2604 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2605 */ 2606 #if (__FreeBSD_version < 500043) 2607 EVENTHANDLER_REGISTER(shutdown_post_sync, shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2608 #else 2609 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2610 #endif 2611 } 2612 /* 2613 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2614 */ 2615 2616 #endif 2617 2618 /********************************************************************************/ 2619 2620 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2621 { 2622 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2623 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2624 int idx; 2625 2626 if(logical) { 2627 if (ccb->ccb_h.flags & CAM_DATA_PHYS) 2628 panic("physical address unsupported"); 2629 2630 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2631 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2632 panic("physical address unsupported"); 2633 2634 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2635 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2636 pSg[idx].wSgSize = sgList[idx].ds_len; 2637 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0; 2638 } 2639 } 2640 else { 2641 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2642 pSg->wSgSize = ccb->csio.dxfer_len; 2643 pSg->wSgFlag = SG_FLAG_EOT; 2644 } 2645 return TRUE; 2646 } 2647 2648 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2649 HPT_ASSERT(0); 2650 return FALSE; 2651 } 2652 2653 /*******************************************************************************/ 2654 ULONG HPTLIBAPI 2655 GetStamp(void) 2656 { 2657 /* 2658 * the system variable, ticks, can't be used since it hasn't yet been active 2659 * when our driver starts (ticks==0, it's a invalid stamp value) 2660 */ 2661 ULONG stamp; 2662 do { stamp = random(); } while (stamp==0); 2663 return stamp; 2664 } 2665 2666 2667 static void 2668 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2669 { 2670 int i; 2671 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2672 2673 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2674 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2675 #ifndef SERIAL_CMDS 2676 inquiryData->CommandQueue = 1; 2677 #endif 2678 2679 switch(pVDev->VDeviceType) { 2680 case VD_SINGLE_DISK: 2681 case VD_ATAPI: 2682 case VD_REMOVABLE: 2683 /* Set the removable bit, if applicable. */ 2684 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2685 inquiryData->RemovableMedia = 1; 2686 2687 /* Fill in vendor identification fields. */ 2688 for (i = 0; i < 20; i += 2) { 2689 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2690 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2691 2692 } 2693 2694 /* Initialize unused portion of product id. */ 2695 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2696 2697 /* firmware revision */ 2698 for (i = 0; i < 4; i += 2) 2699 { 2700 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2701 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2702 } 2703 break; 2704 default: 2705 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2706 #ifdef SUPPORT_ARRAY 2707 switch(pVDev->VDeviceType){ 2708 case VD_RAID_0: 2709 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2710 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2711 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2712 else 2713 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2714 break; 2715 case VD_RAID_1: 2716 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2717 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2718 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2719 else 2720 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2721 break; 2722 case VD_RAID_5: 2723 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2724 break; 2725 case VD_JBOD: 2726 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2727 break; 2728 } 2729 #endif 2730 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2731 break; 2732 } 2733 } 2734 2735 static void 2736 hpt_timeout(void *arg) 2737 { 2738 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus) 2739 intrmask_t oldspl = lock_driver(); 2740 fResetVBus(_VBUS_P0); 2741 unlock_driver(oldspl); 2742 } 2743 2744 static void 2745 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2746 { 2747 PCommand pCmd = (PCommand)arg; 2748 union ccb *ccb = pCmd->pOrgCommand; 2749 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2750 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2751 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2752 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2753 FPSCAT_GATH psg = pCmd->pSgTable; 2754 int idx; 2755 _VBUS_INST(pVDev->pVBus) 2756 2757 HPT_ASSERT(pCmd->cf_physical_sg); 2758 2759 if (error || nsegs == 0) 2760 panic("busdma error"); 2761 2762 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2763 2764 for (idx = 0; idx < nsegs; idx++, psg++) { 2765 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2766 psg->wSgSize = segs[idx].ds_len; 2767 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2768 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2769 } 2770 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2771 2772 if (pCmd->cf_data_in) { 2773 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD); 2774 } 2775 else if (pCmd->cf_data_out) { 2776 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE); 2777 } 2778 2779 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2780 pVDev->pfnSendCommand(_VBUS_P pCmd); 2781 CheckPendingCall(_VBUS_P0); 2782 } 2783 2784 2785 2786 static void HPTLIBAPI 2787 OsSendCommand(_VBUS_ARG union ccb *ccb) 2788 { 2789 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2790 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2791 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2792 struct ccb_scsiio *csio = &ccb->csio; 2793 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2794 2795 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2796 ccb, 2797 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2798 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2799 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2800 )); 2801 2802 pAdapter->outstandingCommands++; 2803 2804 if (pVDev == NULL || pVDev->vf_online == 0) { 2805 ccb->ccb_h.status = CAM_REQ_INVALID; 2806 ccb_done(ccb); 2807 goto Command_Complished; 2808 } 2809 2810 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2811 { 2812 case TEST_UNIT_READY: 2813 case START_STOP_UNIT: 2814 case SYNCHRONIZE_CACHE: 2815 /* FALLTHROUGH */ 2816 ccb->ccb_h.status = CAM_REQ_CMP; 2817 break; 2818 2819 case INQUIRY: 2820 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2821 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2822 ccb_h->status = CAM_REQ_CMP; 2823 break; 2824 2825 case READ_CAPACITY: 2826 { 2827 UCHAR *rbuf=csio->data_ptr; 2828 unsigned int cap; 2829 2830 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2831 cap = 0xfffffffful; 2832 } else { 2833 cap = pVDev->VDeviceCapacity - 1; 2834 } 2835 2836 rbuf[0] = (UCHAR)(cap>>24); 2837 rbuf[1] = (UCHAR)(cap>>16); 2838 rbuf[2] = (UCHAR)(cap>>8); 2839 rbuf[3] = (UCHAR)cap; 2840 /* Claim 512 byte blocks (big-endian). */ 2841 rbuf[4] = 0; 2842 rbuf[5] = 0; 2843 rbuf[6] = 2; 2844 rbuf[7] = 0; 2845 2846 ccb_h->status = CAM_REQ_CMP; 2847 break; 2848 } 2849 2850 case 0x9e: /*SERVICE_ACTION_IN*/ 2851 { 2852 UCHAR *rbuf = csio->data_ptr; 2853 LBA_T cap = pVDev->VDeviceCapacity - 1; 2854 2855 rbuf[0] = (UCHAR)(cap>>56); 2856 rbuf[1] = (UCHAR)(cap>>48); 2857 rbuf[2] = (UCHAR)(cap>>40); 2858 rbuf[3] = (UCHAR)(cap>>32); 2859 rbuf[4] = (UCHAR)(cap>>24); 2860 rbuf[5] = (UCHAR)(cap>>16); 2861 rbuf[6] = (UCHAR)(cap>>8); 2862 rbuf[7] = (UCHAR)cap; 2863 rbuf[8] = 0; 2864 rbuf[9] = 0; 2865 rbuf[10] = 2; 2866 rbuf[11] = 0; 2867 2868 ccb_h->status = CAM_REQ_CMP; 2869 break; 2870 } 2871 2872 case READ_6: 2873 case WRITE_6: 2874 case READ_10: 2875 case WRITE_10: 2876 case 0x88: /* READ_16 */ 2877 case 0x8a: /* WRITE_16 */ 2878 case 0x13: 2879 case 0x2f: 2880 { 2881 UCHAR Cdb[16]; 2882 UCHAR CdbLength; 2883 _VBUS_INST(pVDev->pVBus) 2884 PCommand pCmd = AllocateCommand(_VBUS_P0); 2885 HPT_ASSERT(pCmd); 2886 2887 CdbLength = csio->cdb_len; 2888 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2889 { 2890 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2891 { 2892 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2893 } 2894 else 2895 { 2896 KdPrintE(("ERROR!!!\n")); 2897 ccb->ccb_h.status = CAM_REQ_INVALID; 2898 break; 2899 } 2900 } 2901 else 2902 { 2903 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2904 } 2905 2906 pCmd->pOrgCommand = ccb; 2907 pCmd->pVDevice = pVDev; 2908 pCmd->pfnCompletion = fOsCommandDone; 2909 pCmd->pfnBuildSgl = fOsBuildSgl; 2910 pCmd->pSgTable = pmap->psg; 2911 2912 switch (Cdb[0]) 2913 { 2914 case READ_6: 2915 case WRITE_6: 2916 case 0x13: 2917 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2918 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2919 break; 2920 2921 case 0x88: /* READ_16 */ 2922 case 0x8a: /* WRITE_16 */ 2923 pCmd->uCmd.Ide.Lba = 2924 (HPT_U64)Cdb[2] << 56 | 2925 (HPT_U64)Cdb[3] << 48 | 2926 (HPT_U64)Cdb[4] << 40 | 2927 (HPT_U64)Cdb[5] << 32 | 2928 (HPT_U64)Cdb[6] << 24 | 2929 (HPT_U64)Cdb[7] << 16 | 2930 (HPT_U64)Cdb[8] << 8 | 2931 (HPT_U64)Cdb[9]; 2932 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2933 break; 2934 2935 default: 2936 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2937 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2938 break; 2939 } 2940 2941 switch (Cdb[0]) 2942 { 2943 case READ_6: 2944 case READ_10: 2945 case 0x88: /* READ_16 */ 2946 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2947 pCmd->cf_data_in = 1; 2948 break; 2949 2950 case WRITE_6: 2951 case WRITE_10: 2952 case 0x8a: /* WRITE_16 */ 2953 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2954 pCmd->cf_data_out = 1; 2955 break; 2956 case 0x13: 2957 case 0x2f: 2958 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2959 break; 2960 } 2961 /*///////////////////////// */ 2962 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2963 int idx; 2964 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2965 2966 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2967 pCmd->cf_physical_sg = 1; 2968 2969 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2970 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2971 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len; 2972 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0; 2973 } 2974 2975 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2976 pVDev->pfnSendCommand(_VBUS_P pCmd); 2977 } 2978 else { 2979 int error; 2980 pCmd->cf_physical_sg = 1; 2981 error = bus_dmamap_load(pAdapter->io_dma_parent, 2982 pmap->dma_map, 2983 ccb->csio.data_ptr, ccb->csio.dxfer_len, 2984 hpt_io_dmamap_callback, pCmd, 2985 BUS_DMA_WAITOK 2986 ); 2987 KdPrint(("bus_dmamap_load return %d\n", error)); 2988 if (error && error!=EINPROGRESS) { 2989 hpt_printk(("bus_dmamap_load error %d\n", error)); 2990 FreeCommand(_VBUS_P pCmd); 2991 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2992 dmamap_put(pmap); 2993 pAdapter->outstandingCommands--; 2994 xpt_done(ccb); 2995 } 2996 } 2997 goto Command_Complished; 2998 } 2999 3000 default: 3001 ccb->ccb_h.status = CAM_REQ_INVALID; 3002 break; 3003 } 3004 ccb_done(ccb); 3005 Command_Complished: 3006 CheckPendingCall(_VBUS_P0); 3007 return; 3008 } 3009 3010 static void HPTLIBAPI 3011 fOsCommandDone(_VBUS_ARG PCommand pCmd) 3012 { 3013 union ccb *ccb = pCmd->pOrgCommand; 3014 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 3015 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 3016 3017 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 3018 3019 untimeout(hpt_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch); 3020 3021 switch(pCmd->Result) { 3022 case RETURN_SUCCESS: 3023 ccb->ccb_h.status = CAM_REQ_CMP; 3024 break; 3025 case RETURN_BAD_DEVICE: 3026 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 3027 break; 3028 case RETURN_DEVICE_BUSY: 3029 ccb->ccb_h.status = CAM_BUSY; 3030 break; 3031 case RETURN_INVALID_REQUEST: 3032 ccb->ccb_h.status = CAM_REQ_INVALID; 3033 break; 3034 case RETURN_SELECTION_TIMEOUT: 3035 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 3036 break; 3037 case RETURN_RETRY: 3038 ccb->ccb_h.status = CAM_BUSY; 3039 break; 3040 default: 3041 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 3042 break; 3043 } 3044 3045 if (pCmd->cf_data_in) { 3046 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 3047 } 3048 else if (pCmd->cf_data_in) { 3049 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 3050 } 3051 3052 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 3053 3054 FreeCommand(_VBUS_P pCmd); 3055 ccb_done(ccb); 3056 } 3057 3058 int 3059 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 3060 { 3061 int p; 3062 3063 p = (DpcQueue_Last + 1) % MAX_DPC; 3064 if (p==DpcQueue_First) { 3065 KdPrint(("DPC Queue full!\n")); 3066 return -1; 3067 } 3068 3069 DpcQueue[DpcQueue_Last].dpc = dpc; 3070 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 3071 DpcQueue[DpcQueue_Last].arg = arg; 3072 DpcQueue[DpcQueue_Last].flags = flags; 3073 DpcQueue_Last = p; 3074 3075 return 0; 3076 } 3077 3078 #ifdef _RAID5N_ 3079 /* 3080 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 3081 * How about the memory for 5081 request/response array and PRD table? 3082 */ 3083 void 3084 *os_alloc_page(_VBUS_ARG0) 3085 { 3086 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 3087 } 3088 3089 void 3090 *os_alloc_dma_page(_VBUS_ARG0) 3091 { 3092 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 3093 } 3094 3095 void 3096 os_free_page(_VBUS_ARG void *p) 3097 { 3098 contigfree(p, 0x1000, M_DEVBUF); 3099 } 3100 3101 void 3102 os_free_dma_page(_VBUS_ARG void *p) 3103 { 3104 contigfree(p, 0x1000, M_DEVBUF); 3105 } 3106 3107 void 3108 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 3109 { 3110 UINT i; 3111 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 3112 } 3113 3114 void 3115 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 3116 { 3117 UINT i; 3118 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 3119 } 3120 #endif 3121