1 /* 2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/malloc.h> 34 #include <sys/resource.h> 35 #include <sys/time.h> 36 #include <sys/callout.h> 37 #include <sys/signalvar.h> 38 #include <sys/eventhandler.h> 39 #include <sys/proc.h> 40 #include <sys/kthread.h> 41 42 #if (__FreeBSD_version >= 500000) 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #endif 46 47 #if (__FreeBSD_version >= 500000) 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #else 51 #include <pci/pcireg.h> 52 #include <pci/pcivar.h> 53 #include <sys/wait.h> 54 #include <sys/sysproto.h> 55 #endif 56 57 #ifndef __KERNEL__ 58 #define __KERNEL__ 59 #endif 60 61 #include <dev/hptmv/global.h> 62 #include <dev/hptmv/hptintf.h> 63 #include <dev/hptmv/osbsd.h> 64 #include <dev/hptmv/access601.h> 65 66 67 #ifdef DEBUG 68 #ifdef DEBUG_LEVEL 69 int hpt_dbg_level = DEBUG_LEVEL; 70 #else 71 int hpt_dbg_level = 0; 72 #endif 73 #endif 74 75 #define MV_ERROR printf 76 77 /* 78 * CAM SIM entry points 79 */ 80 static int hpt_probe (device_t dev); 81 static void launch_worker_thread(void); 82 static int hpt_attach(device_t dev); 83 static int hpt_detach(device_t dev); 84 static int hpt_shutdown(device_t dev); 85 static void hpt_poll(struct cam_sim *sim); 86 static void hpt_intr(void *arg); 87 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 88 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 89 90 static device_method_t driver_methods[] = { 91 /* Device interface */ 92 DEVMETHOD(device_probe, hpt_probe), 93 DEVMETHOD(device_attach, hpt_attach), 94 DEVMETHOD(device_detach, hpt_detach), 95 96 /* DEVMETHOD(device_shutdown, hpt_shutdown), */ 97 { 0, 0 } 98 }; 99 100 static driver_t hpt_pci_driver = { 101 __str(PROC_DIR_NAME), 102 driver_methods, 103 sizeof(IAL_ADAPTER_T) 104 }; 105 106 static devclass_t hpt_devclass; 107 108 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 109 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 110 111 #define ccb_ccb_ptr spriv_ptr0 112 #define ccb_adapter ccb_h.spriv_ptr1 113 114 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 115 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 116 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 117 static void ccb_done(union ccb *ccb); 118 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 119 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 120 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 121 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 122 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 123 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 124 static int fResetActiveCommands(PVBus _vbus_p); 125 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 126 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 127 static void hptmv_handle_event_disconnect(void *data); 128 static void hptmv_handle_event_connect(void *data); 129 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 130 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 131 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 132 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 133 int logical); 134 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 135 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 136 MV_U16 responseFlags, MV_U32 timeStamp, 137 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 138 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 139 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 140 141 #define ccb_ccb_ptr spriv_ptr0 142 #define ccb_adapter ccb_h.spriv_ptr1 143 144 IAL_ADAPTER_T *gIal_Adapter = 0; 145 IAL_ADAPTER_T *pCurAdapter = 0; 146 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 147 148 typedef struct st_HPT_DPC { 149 IAL_ADAPTER_T *pAdapter; 150 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 151 void *arg; 152 UCHAR flags; 153 } ST_HPT_DPC; 154 155 #define MAX_DPC 16 156 UCHAR DPC_Request_Nums = 0; 157 static ST_HPT_DPC DpcQueue[MAX_DPC]; 158 static int DpcQueue_First=0; 159 static int DpcQueue_Last = 0; 160 161 char DRIVER_VERSION[] = "v1.12"; 162 163 #if (__FreeBSD_version >= 500000) 164 static struct mtx driver_lock; 165 intrmask_t lock_driver() 166 { 167 168 intrmask_t spl = 0; 169 mtx_lock_spin(&driver_lock); 170 return spl; 171 } 172 void unlock_driver(intrmask_t spl) 173 { 174 mtx_unlock_spin(&driver_lock); 175 } 176 #else 177 static int driver_locked = 0; 178 intrmask_t lock_driver() 179 { 180 intrmask_t spl = splcam(); 181 loop: 182 while (driver_locked) 183 tsleep(&driver_locked, PRIBIO, "hptlck", hz); 184 atomic_add_int(&driver_locked, 1); 185 if (driver_locked>1) { 186 atomic_subtract_int(&driver_locked, 1); 187 goto loop; 188 } 189 return spl; 190 } 191 192 void unlock_driver(intrmask_t spl) 193 { 194 atomic_subtract_int(&driver_locked, 1); 195 if (driver_locked==0) { 196 wakeup(&driver_locked); 197 } 198 splx(spl); 199 } 200 #endif 201 202 /******************************************************************************* 203 * Name: hptmv_free_channel 204 * 205 * Description: free allocated queues for the given channel 206 * 207 * Parameters: pMvSataAdapter - pointer to the RR182x controler this 208 * channel connected to. 209 * channelNum - channel number. 210 * 211 ******************************************************************************/ 212 static void 213 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 214 { 215 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 216 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 217 } 218 219 static void failDevice(PVDevice pVDev) 220 { 221 PVBus _vbus_p = pVDev->pVBus; 222 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 223 224 pVDev->u.disk.df_on_line = 0; 225 pVDev->vf_online = 0; 226 if (pVDev->pfnDeviceFailed) 227 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 228 229 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 230 231 #ifndef FOR_DEMO 232 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 233 pAdapter->beeping = 1; 234 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 235 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 236 } 237 #endif 238 } 239 240 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 241 /*void fDeviceSendCommand(_VBUS_ARG PCommand pCmd); */ 242 243 static void 244 handleEdmaError(_VBUS_ARG PCommand pCmd) 245 { 246 PDevice pDevice = &pCmd->pVDevice->u.disk; 247 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 248 249 if (!pDevice->df_on_line) { 250 KdPrint(("Device is offline")); 251 pCmd->Result = RETURN_BAD_DEVICE; 252 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 253 return; 254 } 255 256 if (pCmd->RetryCount++>5) { 257 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 258 failed: 259 failDevice(pCmd->pVDevice); 260 pCmd->Result = RETURN_IDE_ERROR; 261 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 262 return; 263 } 264 265 /* reset the channel and retry the command */ 266 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 267 goto failed; 268 269 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 270 271 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 272 fDeviceSendCommand(_VBUS_P pCmd); 273 } 274 275 /**************************************************************** 276 * Name: hptmv_init_channel 277 * 278 * Description: allocate request and response queues for the EDMA of the 279 * given channel and sets other fields. 280 * 281 * Parameters: 282 * pAdapter - pointer to the emulated adapter data structure 283 * channelNum - channel number. 284 * Return: 0 on success, otherwise on failure 285 ****************************************************************/ 286 static int 287 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 288 { 289 MV_SATA_CHANNEL *pMvSataChannel; 290 dma_addr_t req_dma_addr; 291 dma_addr_t rsp_dma_addr; 292 293 if (channelNum >= MV_SATA_CHANNELS_NUM) 294 { 295 MV_ERROR("RR182x[%d]: Bad channelNum=%d", 296 pAdapter->mvSataAdapter.adapterId, channelNum); 297 return -1; 298 } 299 300 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 301 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 302 pMvSataChannel->channelNumber = channelNum; 303 pMvSataChannel->lba48Address = MV_FALSE; 304 pMvSataChannel->maxReadTransfer = MV_FALSE; 305 306 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 307 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 308 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 309 310 311 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 312 313 /* check the 1K alignment of the request queue*/ 314 if (req_dma_addr & 0x3ff) 315 { 316 MV_ERROR("RR182x[%d]: request queue allocated isn't 1 K aligned," 317 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 318 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 319 return -1; 320 } 321 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 322 pMvSataChannel->requestQueuePciHiAddress = 0; 323 KdPrint(("RR182x[%d,%d]: request queue allocated: 0x%p", 324 pAdapter->mvSataAdapter.adapterId, channelNum, 325 pMvSataChannel->requestQueue)); 326 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 327 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 328 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 329 330 /* check the 256 alignment of the response queue*/ 331 if (rsp_dma_addr & 0xff) 332 { 333 MV_ERROR("RR182x[%d,%d]: response queue allocated isn't 256 byte " 334 "aligned, dma_addr=%llx\n", 335 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 336 return -1; 337 } 338 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 339 pMvSataChannel->responseQueuePciHiAddress = 0; 340 KdPrint(("RR182x[%d,%d]: response queue allocated: 0x%p", 341 pAdapter->mvSataAdapter.adapterId, channelNum, 342 pMvSataChannel->responseQueue)); 343 344 pAdapter->mvChannel[channelNum].online = MV_TRUE; 345 return 0; 346 } 347 348 /****************************************************************************** 349 * Name: hptmv_parse_identify_results 350 * 351 * Description: this functions parses the identify command results, checks 352 * that the connected deives can be accesed by RR182x EDMA, 353 * and updates the channel stucture accordingly. 354 * 355 * Parameters: pMvSataChannel, pointer to the channel data structure. 356 * 357 * Returns: =0 ->success, < 0 ->failure. 358 * 359 ******************************************************************************/ 360 static int 361 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 362 { 363 MV_U16 *iden = pMvSataChannel->identifyDevice; 364 365 /*LBA addressing*/ 366 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 367 { 368 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 369 return -1; 370 } 371 else 372 { 373 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 374 } 375 /*DMA support*/ 376 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 377 { 378 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 379 return -1; 380 } 381 else 382 { 383 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 384 } 385 /* PIO */ 386 if ((iden[IDEN_VALID] & 2) == 0) 387 { 388 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 389 return -1; 390 } 391 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 392 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 393 394 /*UDMA*/ 395 if ((iden[IDEN_VALID] & 4) == 0) 396 { 397 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 398 return -1; 399 } 400 401 /* 48 bit address */ 402 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 403 { 404 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 405 pMvSataChannel->lba48Address = MV_TRUE; 406 } 407 else 408 { 409 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 410 pMvSataChannel->lba48Address = MV_FALSE; 411 } 412 return 0; 413 } 414 415 static void 416 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 417 { 418 PVDevice pVDev = &pAdapter->VDevices[channel]; 419 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 420 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 421 422 pMvSataChannel->outstandingCommands = 0; 423 424 pVDev->u.disk.mv = pMvSataChannel; 425 pVDev->u.disk.df_on_line = 1; 426 pVDev->u.disk.pVBus = &pAdapter->VBus; 427 pVDev->pVBus = &pAdapter->VBus; 428 429 #ifdef SUPPORT_48BIT_LBA 430 if (pMvSataChannel->lba48Address == MV_TRUE) 431 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 432 else 433 #endif 434 if(IdentifyData[53] & 1) { 435 pVDev->u.disk.dDeRealCapacity = 436 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 437 (IdentifyData[61]<<16 | IdentifyData[60]) : 438 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 439 } else 440 pVDev->u.disk.dDeRealCapacity = 441 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 442 443 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 444 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 445 446 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 447 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 448 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 449 } 450 } 451 452 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 453 { 454 PVDevice pVDev; 455 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 456 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 457 458 if (!pMvSataChannel) return; 459 460 if (plugged) 461 { 462 pVDev = &(pAdapter->VDevices[channelIndex]); 463 init_vdev_params(pAdapter, channelIndex); 464 465 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 466 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 467 468 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 469 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 470 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 471 pVDev->vf_online = 1; 472 473 #ifdef SUPPORT_ARRAY 474 if(pVDev->pParent) 475 { 476 int iMember; 477 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 478 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 479 pVDev->pParent->u.array.pMember[iMember] = NULL; 480 pVDev->pParent = NULL; 481 } 482 #endif 483 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 484 fCheckBootable(pVDev); 485 RegisterVDevice(pVDev); 486 487 #ifndef FOR_DEMO 488 if (pAdapter->beeping) { 489 pAdapter->beeping = 0; 490 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 491 } 492 #endif 493 494 } 495 else 496 { 497 pVDev = &(pAdapter->VDevices[channelIndex]); 498 failDevice(pVDev); 499 } 500 } 501 502 static int 503 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 504 { 505 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 506 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 507 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 508 MV_U32 udmaMode,pioMode; 509 510 KdPrint(("RR182x [%d]: start channel (%d)", pMvSataAdapter->adapterId, 511 channelNum)); 512 513 514 /* Software reset channel */ 515 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 516 { 517 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n", 518 pMvSataAdapter->adapterId, channelNum); 519 return -1; 520 } 521 522 /* Hardware reset channel */ 523 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 524 { 525 /* If failed, try again - this is when trying to hardreset a channel */ 526 /* when drive is just spinning up */ 527 StallExec(5000000); /* wait 5 sec before trying again */ 528 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 529 { 530 MV_ERROR("RR182x [%d,%d]: failed to perform Hard reset\n", 531 pMvSataAdapter->adapterId, channelNum); 532 return -1; 533 } 534 } 535 536 /* identify device*/ 537 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 538 { 539 MV_ERROR("RR182x [%d,%d]: failed to perform ATA Identify command\n" 540 , pMvSataAdapter->adapterId, channelNum); 541 return -1; 542 } 543 if (hptmv_parse_identify_results(pMvSataChannel)) 544 { 545 MV_ERROR("RR182x [%d,%d]: Error in parsing ATA Identify message\n" 546 , pMvSataAdapter->adapterId, channelNum); 547 return -1; 548 } 549 550 /* mvStorageDevATASetFeatures */ 551 /* Disable 8 bit PIO in case CFA enabled */ 552 if (pMvSataChannel->identifyDevice[86] & 4) 553 { 554 KdPrint(("RR182x [%d]: Disable 8 bit PIO (CFA enabled) \n", 555 pMvSataAdapter->adapterId)); 556 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 557 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 558 0, 0, 0) == MV_FALSE) 559 { 560 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures" 561 " failed\n", pMvSataAdapter->adapterId, channelNum); 562 return -1; 563 } 564 } 565 /* Write cache */ 566 #ifdef ENABLE_WRITE_CACHE 567 if (pMvSataChannel->identifyDevice[82] & 0x20) 568 { 569 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 570 { 571 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 572 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 573 0, 0, 0) == MV_FALSE) 574 { 575 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 576 pMvSataAdapter->adapterId, channelNum); 577 return -1; 578 } 579 } 580 KdPrint(("RR182x [%d]: channel %d, write cache enabled\n", 581 pMvSataAdapter->adapterId, channelNum)); 582 } 583 else 584 { 585 KdPrint(("RR182x [%d]: channel %d, write cache not supported\n", 586 pMvSataAdapter->adapterId, channelNum)); 587 } 588 #else /* disable write cache */ 589 { 590 if (pMvSataChannel->identifyDevice[85] & 0x20) 591 { 592 KdPrint(("RR182x [%d]: channel =%d, disable write cache\n", 593 pMvSataAdapter->adapterId, channelNum)); 594 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 595 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 596 0, 0, 0) == MV_FALSE) 597 { 598 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 599 pMvSataAdapter->adapterId, channelNum); 600 return -1; 601 } 602 } 603 KdPrint(("RR182x [%d]: channel=%d, write cache disabled\n", 604 pMvSataAdapter->adapterId, channelNum)); 605 } 606 #endif 607 608 /* Set transfer mode */ 609 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_SLOW\n", 610 pMvSataAdapter->adapterId)); 611 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 612 MV_ATA_SET_FEATURES_TRANSFER, 613 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 614 MV_FALSE) 615 { 616 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 617 pMvSataAdapter->adapterId, channelNum); 618 return -1; 619 } 620 621 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 622 { 623 pioMode = MV_ATA_TRANSFER_PIO_4; 624 } 625 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 626 { 627 pioMode = MV_ATA_TRANSFER_PIO_3; 628 } 629 else 630 { 631 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 632 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 633 } 634 635 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_4\n", 636 pMvSataAdapter->adapterId)); 637 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 638 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 639 MV_ATA_SET_FEATURES_TRANSFER, 640 pioMode, 0, 0, 0) == MV_FALSE) 641 { 642 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 643 pMvSataAdapter->adapterId, channelNum); 644 return -1; 645 } 646 647 udmaMode = MV_ATA_TRANSFER_UDMA_0; 648 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 649 { 650 udmaMode = MV_ATA_TRANSFER_UDMA_6; 651 } 652 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 653 { 654 udmaMode = MV_ATA_TRANSFER_UDMA_5; 655 } 656 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 657 { 658 udmaMode = MV_ATA_TRANSFER_UDMA_4; 659 } 660 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 661 { 662 udmaMode = MV_ATA_TRANSFER_UDMA_3; 663 } 664 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 665 { 666 udmaMode = MV_ATA_TRANSFER_UDMA_2; 667 } 668 669 KdPrint(("RR182x [%d] Set transfer mode XFER_UDMA_%d\n", 670 pMvSataAdapter->adapterId, udmaMode & 0xf)); 671 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 672 673 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 674 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 675 0, 0, 0) == MV_FALSE) 676 { 677 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 678 pMvSataAdapter->adapterId, channelNum); 679 return -1; 680 }*/ 681 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 682 return TRUE; 683 else 684 do 685 { 686 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 687 MV_ATA_SET_FEATURES_TRANSFER, 688 pChannelInfo->maxUltraDmaModeSupported, 689 0, 0, 0) == MV_FALSE) 690 { 691 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 692 { 693 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 694 { 695 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 696 pMvSataChannel->eDmaRegsOffset + 697 0x11c, /* command reg */ 698 MV_ATA_COMMAND_IDLE_IMMEDIATE); 699 mvMicroSecondsDelay(10000); 700 mvSataChannelHardReset(pMvSataAdapter, channelNum); 701 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 702 return FALSE; 703 } 704 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 705 return FALSE; 706 pChannelInfo->maxUltraDmaModeSupported--; 707 continue; 708 } 709 else return FALSE; 710 } 711 break; 712 }while (1); 713 714 /* Read look ahead */ 715 #ifdef ENABLE_READ_AHEAD 716 if (pMvSataChannel->identifyDevice[82] & 0x40) 717 { 718 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 719 { 720 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 721 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 722 0, 0) == MV_FALSE) 723 { 724 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 725 pMvSataAdapter->adapterId, channelNum); 726 return -1; 727 } 728 } 729 KdPrint(("RR182x [%d]: channel=%d, read look ahead enabled\n", 730 pMvSataAdapter->adapterId, channelNum)); 731 } 732 else 733 { 734 KdPrint(("RR182x [%d]: channel %d, Read Look Ahead not supported\n", 735 pMvSataAdapter->adapterId, channelNum)); 736 } 737 #else 738 { 739 if (pMvSataChannel->identifyDevice[86] & 0x20) 740 { 741 KdPrint(("RR182x [%d]:channel %d, disable read look ahead\n", 742 pMvSataAdapter->adapterId, channelNum)); 743 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 744 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 745 0, 0) == MV_FALSE) 746 { 747 MV_ERROR("RR182x [%d]:channel %d: ATA Set Features failed\n", 748 pMvSataAdapter->adapterId, channelNum); 749 return -1; 750 } 751 } 752 KdPrint(("RR182x [%d]:channel %d, read look ahead disabled\n", 753 pMvSataAdapter->adapterId, channelNum)); 754 } 755 #endif 756 757 758 { 759 KdPrint(("RR182x [%d]: channel %d config EDMA, Non Queued Mode\n", 760 pMvSataAdapter->adapterId, 761 channelNum)); 762 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 763 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 764 { 765 MV_ERROR("RR182x [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 766 pMvSataAdapter->adapterId, channelNum); 767 return -1; 768 } 769 } 770 /* Enable EDMA */ 771 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 772 { 773 MV_ERROR("RR182x [%d] Failed to enable DMA, channel=%d\n", 774 pMvSataAdapter->adapterId, channelNum); 775 return -1; 776 } 777 MV_ERROR("RR182x [%d,%d]: channel started successfully\n", 778 pMvSataAdapter->adapterId, channelNum); 779 780 #ifndef FOR_DEMO 781 set_fail_led(pMvSataAdapter, channelNum, 0); 782 #endif 783 return 0; 784 } 785 786 static void 787 hptmv_handle_event(void * data, int flag) 788 { 789 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 790 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 791 MV_U8 channelIndex; 792 793 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 794 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 795 { 796 switch(pAdapter->sataEvents[channelIndex]) 797 { 798 case SATA_EVENT_CHANNEL_CONNECTED: 799 /* Handle only connects */ 800 if (flag == 1) 801 break; 802 KdPrint(("RR182x [%d,%d]: new device connected\n", 803 pMvSataAdapter->adapterId, channelIndex)); 804 hptmv_init_channel(pAdapter, channelIndex); 805 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 806 { 807 MV_ERROR("RR182x [%d,%d] Failed to configure\n", 808 pMvSataAdapter->adapterId, channelIndex); 809 hptmv_free_channel(pAdapter, channelIndex); 810 } 811 else 812 { 813 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 814 if (start_channel( pAdapter, channelIndex)) 815 { 816 MV_ERROR("RR182x [%d,%d]Failed to start channel\n", 817 pMvSataAdapter->adapterId, channelIndex); 818 hptmv_free_channel(pAdapter, channelIndex); 819 } 820 else 821 { 822 device_change(pAdapter, channelIndex, TRUE); 823 } 824 } 825 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 826 break; 827 828 case SATA_EVENT_CHANNEL_DISCONNECTED: 829 /* Handle only disconnects */ 830 if (flag == 0) 831 break; 832 KdPrint(("RR182x [%d,%d]: device disconnected\n", 833 pMvSataAdapter->adapterId, channelIndex)); 834 /* Flush pending commands */ 835 if(pMvSataAdapter->sataChannel[channelIndex]) 836 { 837 _VBUS_INST(&pAdapter->VBus) 838 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 839 MV_FLUSH_TYPE_CALLBACK); 840 CheckPendingCall(_VBUS_P0); 841 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 842 hptmv_free_channel(pAdapter, channelIndex); 843 pMvSataAdapter->sataChannel[channelIndex] = NULL; 844 KdPrint(("RR182x [%d,%d]: channel removed\n", 845 pMvSataAdapter->adapterId, channelIndex)); 846 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 847 Check_Idle_Call(pAdapter); 848 } 849 else 850 { 851 KdPrint(("RR182x [%d,%d]: channel already removed!!\n", 852 pMvSataAdapter->adapterId, channelIndex)); 853 } 854 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 855 break; 856 857 case SATA_EVENT_NO_CHANGE: 858 break; 859 860 default: 861 break; 862 } 863 } 864 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 865 } 866 867 #define EVENT_CONNECT 1 868 #define EVENT_DISCONNECT 0 869 870 static void 871 hptmv_handle_event_connect(void *data) 872 { 873 hptmv_handle_event (data, 0); 874 } 875 876 static void 877 hptmv_handle_event_disconnect(void *data) 878 { 879 hptmv_handle_event (data, 1); 880 } 881 882 static MV_BOOLEAN 883 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 884 MV_U32 param1, MV_U32 param2) 885 { 886 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 887 888 switch (eventType) 889 { 890 case MV_EVENT_TYPE_SATA_CABLE: 891 { 892 MV_U8 channel = param2; 893 894 if (param1 == EVENT_CONNECT) 895 { 896 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 897 KdPrint(("RR182x [%d,%d]: device connected event received\n", 898 pMvSataAdapter->adapterId, channel)); 899 /* Delete previous timers (if multiple drives connected in the same time */ 900 pAdapter->event_timer_connect = timeout(hptmv_handle_event_connect, pAdapter, 10*hz); 901 } 902 else if (param1 == EVENT_DISCONNECT) 903 { 904 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 905 KdPrint(("RR182x [%d,%d]: device disconnected event received \n", 906 pMvSataAdapter->adapterId, channel)); 907 device_change(pAdapter, channel, FALSE); 908 /* Delete previous timers (if multiple drives disconnected in the same time */ 909 /*pAdapter->event_timer_disconnect = timeout(hptmv_handle_event_disconnect, pAdapter, 10*hz); */ 910 /*It is not necessary to wait, handle it directly*/ 911 hptmv_handle_event_disconnect(pAdapter); 912 } 913 else 914 { 915 916 MV_ERROR("RR182x: illigal value for param1(%d) at " 917 "connect/disconect event, host=%d\n", param1, 918 pMvSataAdapter->adapterId ); 919 920 } 921 } 922 break; 923 case MV_EVENT_TYPE_ADAPTER_ERROR: 924 KdPrint(("RR182x: DEVICE error event received, pci cause " 925 "reg=%x, don't how to handle this\n", param1)); 926 return MV_TRUE; 927 default: 928 MV_ERROR("RR182x[%d]: unknown event type (%d)\n", 929 pMvSataAdapter->adapterId, eventType); 930 return MV_FALSE; 931 } 932 return MV_TRUE; 933 } 934 935 static int 936 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 937 { 938 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 939 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 940 if (pAdapter->requestsArrayBaseAddr == NULL) 941 { 942 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA request" 943 " queues\n", pAdapter->mvSataAdapter.adapterId); 944 return -1; 945 } 946 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 947 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 948 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 949 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 950 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 951 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 952 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 953 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 954 955 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 956 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 957 { 958 MV_ERROR("RR182x[%d]: Error in Request Quueues Alignment\n", 959 pAdapter->mvSataAdapter.adapterId); 960 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 961 return -1; 962 } 963 /* response queues */ 964 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 965 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 966 if (pAdapter->responsesArrayBaseAddr == NULL) 967 { 968 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA response" 969 " queues\n", pAdapter->mvSataAdapter.adapterId); 970 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 971 return -1; 972 } 973 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 974 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 975 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 976 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 977 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 978 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 979 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 980 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 981 982 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 983 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 984 { 985 MV_ERROR("RR182x[%d]: Error in Response Quueues Alignment\n", 986 pAdapter->mvSataAdapter.adapterId); 987 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 988 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 989 return -1; 990 } 991 return 0; 992 } 993 994 static void 995 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 996 { 997 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 998 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 999 } 1000 1001 static PVOID 1002 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 1003 { 1004 PVOID ret; 1005 if (pAdapter->pFreePRDLink) { 1006 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 1007 ret = pAdapter->pFreePRDLink; 1008 pAdapter->pFreePRDLink = *(void**)ret; 1009 return ret; 1010 } 1011 return NULL; 1012 } 1013 1014 static void 1015 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 1016 { 1017 *(void**)PRDTable = pAdapter->pFreePRDLink; 1018 pAdapter->pFreePRDLink = PRDTable; 1019 } 1020 1021 extern PVDevice fGetFirstChild(PVDevice pLogical); 1022 extern void fResetBootMark(PVDevice pLogical); 1023 static void 1024 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 1025 { 1026 PVDevice pPhysical, pLogical; 1027 PVBus pVBus; 1028 int i,j; 1029 1030 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 1031 pPhysical = &(pAdapter->VDevices[i]); 1032 pLogical = pPhysical; 1033 while (pLogical->pParent) pLogical = pLogical->pParent; 1034 if (pLogical->vf_online==0) { 1035 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 1036 continue; 1037 } 1038 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1039 continue; 1040 1041 pVBus = &pAdapter->VBus; 1042 if(pVBus) 1043 { 1044 j=0; 1045 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1046 if(j<MAX_VDEVICE_PER_VBUS){ 1047 pVBus->pVDevice[j] = pLogical; 1048 pLogical->pVBus = pVBus; 1049 1050 if (j>0 && pLogical->vf_bootmark) { 1051 if (pVBus->pVDevice[0]->vf_bootmark) { 1052 fResetBootMark(pLogical); 1053 } 1054 else { 1055 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1056 pVBus->pVDevice[0] = pLogical; 1057 } 1058 } 1059 } 1060 } 1061 } 1062 } 1063 1064 PVDevice 1065 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1066 { 1067 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1068 ULONG capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1069 ULONG thiscap, maxcap = MAX_LBA_T; 1070 PVDevice pVDevice, pFind = NULL; 1071 int i; 1072 1073 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1074 { 1075 pVDevice = &pAdapter->VDevices[i]; 1076 if(!pVDevice) 1077 continue; 1078 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1079 /* find the smallest usable spare disk */ 1080 if (pVDevice->VDeviceType==VD_SPARE && 1081 pVDevice->u.disk.df_on_line && 1082 thiscap < maxcap && 1083 thiscap >= capacity) 1084 { 1085 maxcap = pVDevice->VDeviceCapacity; 1086 pFind = pVDevice; 1087 } 1088 } 1089 return pFind; 1090 } 1091 1092 /****************************************************************** 1093 * IO ATA Command 1094 *******************************************************************/ 1095 int HPTLIBAPI 1096 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1097 { 1098 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1099 } 1100 1101 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1102 { 1103 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1104 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1105 MV_U8 channelIndex = pSataChannel->channelNumber; 1106 UCHAR mvMode; 1107 /* 508x don't use MW-DMA? */ 1108 if (NewMode>4 && NewMode<8) NewMode = 4; 1109 pDev->bDeModeSetting = NewMode; 1110 if (NewMode<=4) 1111 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1112 else 1113 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1114 1115 /*To fix 88i8030 bug*/ 1116 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1117 mvMode = MV_ATA_TRANSFER_UDMA_0; 1118 1119 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1120 /* Flush pending commands */ 1121 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1122 1123 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1124 MV_ATA_SET_FEATURES_TRANSFER, 1125 mvMode, 0, 0, 0) == MV_FALSE) 1126 { 1127 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1128 } 1129 /* Enable EDMA */ 1130 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1131 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1132 } 1133 1134 #ifdef SUPPORT_ARRAY 1135 #define IdeRegisterVDevice fCheckArray 1136 #else 1137 void 1138 IdeRegisterVDevice(PDevice pDev) 1139 { 1140 PVDevice pVDev = Map2pVDevice(pDev); 1141 1142 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1143 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1144 pVDev->vf_online = 1; 1145 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1146 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1147 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1148 } 1149 #endif 1150 1151 static __inline PBUS_DMAMAP 1152 dmamap_get(struct IALAdapter * pAdapter) 1153 { 1154 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1155 if (p) 1156 pAdapter->pbus_dmamap_list = p-> next; 1157 return p; 1158 } 1159 1160 static __inline void 1161 dmamap_put(PBUS_DMAMAP p) 1162 { 1163 p->next = p->pAdapter->pbus_dmamap_list; 1164 p->pAdapter->pbus_dmamap_list = p; 1165 } 1166 1167 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/ 1168 #if __FreeBSD_version >= 500000 1169 static void hpt_init(void *dummy) 1170 { 1171 mtx_init(&driver_lock, "hptlock", NULL, MTX_SPIN); 1172 } 1173 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL); 1174 #endif 1175 1176 static int num_adapters = 0; 1177 static int 1178 init_adapter(IAL_ADAPTER_T *pAdapter) 1179 { 1180 PVBus _vbus_p = &pAdapter->VBus; 1181 MV_SATA_ADAPTER *pMvSataAdapter; 1182 int i, channel, rid; 1183 1184 PVDevice pVDev; 1185 1186 intrmask_t oldspl = lock_driver(); 1187 1188 pAdapter->next = 0; 1189 1190 if(gIal_Adapter == 0){ 1191 gIal_Adapter = pAdapter; 1192 pCurAdapter = gIal_Adapter; 1193 } 1194 else { 1195 pCurAdapter->next = pAdapter; 1196 pCurAdapter = pAdapter; 1197 } 1198 1199 pAdapter->outstandingCommands = 0; 1200 1201 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1202 _vbus_p->OsExt = (void *)pAdapter; 1203 pMvSataAdapter->IALData = pAdapter; 1204 1205 if (bus_dma_tag_create(NULL,/* parent */ 1206 4, /* alignment */ 1207 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1208 BUS_SPACE_MAXADDR, /* lowaddr */ 1209 BUS_SPACE_MAXADDR, /* highaddr */ 1210 NULL, NULL, /* filter, filterarg */ 1211 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1212 MAX_SG_DESCRIPTORS, /* nsegments */ 1213 0x10000, /* maxsegsize */ 1214 BUS_DMA_WAITOK, /* flags */ 1215 #if __FreeBSD_version>502000 1216 busdma_lock_mutex, /* lockfunc */ 1217 &driver_lock, /* lockfuncarg */ 1218 #endif 1219 &pAdapter->io_dma_parent /* tag */)) 1220 { 1221 return ENXIO;; 1222 } 1223 1224 1225 if (hptmv_allocate_edma_queues(pAdapter)) 1226 { 1227 MV_ERROR("RR182x: Failed to allocate memory for EDMA queues\n"); 1228 unlock_driver(oldspl); 1229 return ENOMEM; 1230 } 1231 1232 /* also map EPROM address */ 1233 rid = 0x10; 1234 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid, 1235 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE)) 1236 || 1237 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1238 { 1239 MV_ERROR("RR182x: Failed to remap memory space\n"); 1240 hptmv_free_edma_queues(pAdapter); 1241 unlock_driver(oldspl); 1242 return ENXIO; 1243 } 1244 else 1245 { 1246 KdPrint(("RR182x: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1247 } 1248 1249 pMvSataAdapter->adapterId = num_adapters++; 1250 /* get the revision ID */ 1251 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1252 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1253 1254 /* init RR182x */ 1255 pMvSataAdapter->intCoalThre[0]= 1; 1256 pMvSataAdapter->intCoalThre[1]= 1; 1257 pMvSataAdapter->intTimeThre[0] = 1; 1258 pMvSataAdapter->intTimeThre[1] = 1; 1259 pMvSataAdapter->pciCommand = 0x0107E371; 1260 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1261 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1262 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1263 1264 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1265 { 1266 MV_ERROR("RR182x[%d]: core failed to initialize the adapter\n", 1267 pMvSataAdapter->adapterId); 1268 unregister: 1269 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1270 hptmv_free_edma_queues(pAdapter); 1271 unlock_driver(oldspl); 1272 return ENXIO; 1273 } 1274 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1275 1276 #ifndef FOR_DEMO 1277 set_fail_leds(pMvSataAdapter, 0); 1278 #endif 1279 1280 /* setup command blocks */ 1281 KdPrint(("Allocate command blocks\n")); 1282 _vbus_(pFreeCommands) = 0; 1283 pAdapter->pCommandBlocks = 1284 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1285 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1286 if (!pAdapter->pCommandBlocks) { 1287 MV_ERROR("insufficient memory\n"); 1288 goto unregister; 1289 } 1290 1291 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1292 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1293 } 1294 1295 /*Set up the bus_dmamap*/ 1296 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1297 if(!pAdapter->pbus_dmamap) { 1298 MV_ERROR("insufficient memory\n"); 1299 free(pAdapter->pCommandBlocks, M_DEVBUF); 1300 goto unregister; 1301 } 1302 1303 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1304 pAdapter->pbus_dmamap_list = 0; 1305 for (i=0; i < MAX_QUEUE_COMM; i++) { 1306 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1307 pmap->pAdapter = pAdapter; 1308 dmamap_put(pmap); 1309 1310 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1311 MV_ERROR("Can not allocate dma map\n"); 1312 free(pAdapter->pCommandBlocks, M_DEVBUF); 1313 free(pAdapter->pbus_dmamap, M_DEVBUF); 1314 goto unregister; 1315 } 1316 } 1317 /* setup PRD Tables */ 1318 KdPrint(("Allocate PRD Tables\n")); 1319 pAdapter->pFreePRDLink = 0; 1320 1321 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1322 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1323 1324 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1325 if (!pAdapter->prdTableAddr) { 1326 MV_ERROR("insufficient PRD Tables\n"); 1327 goto unregister; 1328 } 1329 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1330 { 1331 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1332 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1333 { 1334 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1335 FreePRDTable(pAdapter, PRDTable); 1336 PRDTable += PRD_ENTRIES_SIZE; 1337 } 1338 } 1339 1340 /* enable the adapter interrupts */ 1341 1342 /* configure and start the connected channels*/ 1343 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1344 { 1345 pAdapter->mvChannel[channel].online = MV_FALSE; 1346 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1347 == MV_TRUE) 1348 { 1349 KdPrint(("RR182x[%d]: channel %d is connected\n", 1350 pMvSataAdapter->adapterId, channel)); 1351 1352 if (hptmv_init_channel(pAdapter, channel) == 0) 1353 { 1354 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1355 { 1356 MV_ERROR("RR182x[%d]: Failed to configure channel" 1357 " %d\n",pMvSataAdapter->adapterId, channel); 1358 hptmv_free_channel(pAdapter, channel); 1359 } 1360 else 1361 { 1362 if (start_channel(pAdapter, channel)) 1363 { 1364 MV_ERROR("RR182x[%d]: Failed to start channel," 1365 " channel=%d\n",pMvSataAdapter->adapterId, 1366 channel); 1367 hptmv_free_channel(pAdapter, channel); 1368 } 1369 pAdapter->mvChannel[channel].online = MV_TRUE; 1370 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1371 channel, 1372 MV_TRUE);*/ 1373 } 1374 } 1375 } 1376 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1377 pAdapter->mvChannel[channel].online, channel)); 1378 } 1379 1380 #ifdef SUPPORT_ARRAY 1381 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1382 pVDev = ArrayTables(i); 1383 mArFreeArrayTable(pVDev); 1384 } 1385 #endif 1386 1387 KdPrint(("Initialize Devices\n")); 1388 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1389 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1390 if (pMvSataChannel) { 1391 init_vdev_params(pAdapter, channel); 1392 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1393 } 1394 } 1395 #ifdef SUPPORT_ARRAY 1396 CheckArrayCritical(_VBUS_P0); 1397 #endif 1398 _vbus_p->nInstances = 1; 1399 fRegisterVdevice(pAdapter); 1400 1401 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1402 pVDev = _vbus_p->pVDevice[channel]; 1403 if (pVDev && pVDev->vf_online) 1404 fCheckBootable(pVDev); 1405 } 1406 1407 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1408 init_raid5_memory(_VBUS_P0); 1409 _vbus_(r5).enable_write_back = 1; 1410 printf("RR182x: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1411 #endif 1412 1413 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1414 unlock_driver(oldspl); 1415 return 0; 1416 } 1417 1418 int 1419 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1420 { 1421 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1422 1423 mvSataDisableChannelDma(pMvSataAdapter, channel); 1424 /* Flush pending commands */ 1425 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1426 1427 /* Software reset channel */ 1428 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1429 { 1430 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n", 1431 pMvSataAdapter->adapterId, channel); 1432 hptmv_free_channel(pAdapter, channel); 1433 return -1; 1434 } 1435 1436 /* Hardware reset channel */ 1437 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1438 { 1439 MV_ERROR("RR182x [%d,%d] Failed to Hard reser the SATA channel\n", 1440 pMvSataAdapter->adapterId, channel); 1441 hptmv_free_channel(pAdapter, channel); 1442 return -1; 1443 } 1444 1445 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1446 { 1447 MV_ERROR("RR182x [%d,%d] Failed to Connect Device\n", 1448 pMvSataAdapter->adapterId, channel); 1449 hptmv_free_channel(pAdapter, channel); 1450 return -1; 1451 }else 1452 { 1453 MV_ERROR("channel %d: perform recalibrate command", channel); 1454 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1455 MV_NON_UDMA_PROTOCOL_NON_DATA, 1456 MV_FALSE, 1457 NULL, /* pBuffer*/ 1458 0, /* count */ 1459 0, /*features*/ 1460 /* sectorCount */ 1461 0, 1462 0, /* lbaLow */ 1463 0, /* lbaMid */ 1464 /* lbaHigh */ 1465 0, 1466 0, /* device */ 1467 /* command */ 1468 0x10)) 1469 MV_ERROR("channel %d: recalibrate failed", channel); 1470 1471 /* Set transfer mode */ 1472 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1473 MV_ATA_SET_FEATURES_TRANSFER, 1474 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1475 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1476 MV_ATA_SET_FEATURES_TRANSFER, 1477 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1478 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1479 MV_ATA_SET_FEATURES_TRANSFER, 1480 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1481 { 1482 MV_ERROR("channel %d: Set Features failed", channel); 1483 hptmv_free_channel(pAdapter, channel); 1484 return -1; 1485 } 1486 /* Enable EDMA */ 1487 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1488 { 1489 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1490 hptmv_free_channel(pAdapter, channel); 1491 return -1; 1492 } 1493 } 1494 return 0; 1495 } 1496 1497 static int 1498 fResetActiveCommands(PVBus _vbus_p) 1499 { 1500 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1501 MV_U8 channel; 1502 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1503 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1504 MvSataResetChannel(pMvSataAdapter,channel); 1505 } 1506 return 0; 1507 } 1508 1509 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1510 { 1511 UINT cont; 1512 ULONG ticks = 0; 1513 MV_U8 channel; 1514 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1515 MV_SATA_CHANNEL *pMvSataChannel; 1516 1517 do { 1518 check_cmds: 1519 cont = 0; 1520 CheckPendingCall(_VBUS_P0); 1521 #ifdef _RAID5N_ 1522 dataxfer_poll(); 1523 xor_poll(); 1524 #endif 1525 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1526 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1527 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1528 { 1529 while (pMvSataChannel->outstandingCommands) { 1530 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1531 StallExec(1000); 1532 if (ticks++ > 3000) { 1533 MvSataResetChannel(pMvSataAdapter,channel); 1534 goto check_cmds; 1535 } 1536 } 1537 else 1538 ticks = 0; 1539 } 1540 cont = 1; 1541 } 1542 } 1543 } while (cont); 1544 } 1545 1546 void 1547 fResetVBus(_VBUS_ARG0) 1548 { 1549 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1550 1551 /* some commands may already finished. */ 1552 CheckPendingCall(_VBUS_P0); 1553 1554 fResetActiveCommands(_vbus_p); 1555 /* 1556 * the other pending commands may still be finished successfully. 1557 */ 1558 fCompleteAllCommandsSynchronously(_vbus_p); 1559 1560 /* Now there should be no pending commands. No more action needed. */ 1561 CheckIdleCall(_VBUS_P0); 1562 1563 KdPrint(("fMvResetBus() done")); 1564 } 1565 1566 /*No rescan function*/ 1567 void 1568 fRescanAllDevice(_VBUS_ARG0) 1569 { 1570 } 1571 1572 static MV_BOOLEAN 1573 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1574 MV_U8 channelNum, 1575 MV_COMPLETION_TYPE comp_type, 1576 MV_VOID_PTR commandId, 1577 MV_U16 responseFlags, 1578 MV_U32 timeStamp, 1579 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1580 { 1581 PCommand pCmd = (PCommand) commandId; 1582 _VBUS_INST(pCmd->pVDevice->pVBus) 1583 1584 if (pCmd->uScratch.sata_param.prdAddr) 1585 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1586 1587 switch (comp_type) 1588 { 1589 case MV_COMPLETION_TYPE_NORMAL: 1590 pCmd->Result = RETURN_SUCCESS; 1591 break; 1592 case MV_COMPLETION_TYPE_ABORT: 1593 pCmd->Result = RETURN_BUS_RESET; 1594 break; 1595 case MV_COMPLETION_TYPE_ERROR: 1596 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1597 pMvSataAdapter->adapterId, channelNum, responseFlags); 1598 1599 if (responseFlags & 4) { 1600 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1601 " LBA high %x, device %x, status %x\n", 1602 registerStruct->errorRegister, 1603 registerStruct->sectorCountRegister, 1604 registerStruct->lbaLowRegister, 1605 registerStruct->lbaMidRegister, 1606 registerStruct->lbaHighRegister, 1607 registerStruct->deviceRegister, 1608 registerStruct->statusRegister); 1609 } 1610 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1611 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1612 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1613 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1614 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1615 pCmd->pVDevice->u.disk.QueueLength--; 1616 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1617 return TRUE; 1618 1619 default: 1620 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1621 return MV_FALSE; 1622 } 1623 1624 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1625 pCmd->uScratch.sata_param.cmd_priv --; 1626 return TRUE; 1627 } 1628 pCmd->pVDevice->u.disk.QueueLength--; 1629 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1630 return TRUE; 1631 } 1632 1633 void 1634 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1635 { 1636 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1637 MV_SATA_ADAPTER *pMvSataAdapter; 1638 MV_SATA_CHANNEL *pMvSataChannel; 1639 PVDevice pVDevice = pCmd->pVDevice; 1640 PDevice pDevice = &pVDevice->u.disk; 1641 ULONG Lba = pCmd->uCmd.Ide.Lba; 1642 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1643 1644 MV_QUEUE_COMMAND_RESULT result; 1645 MV_QUEUE_COMMAND_INFO commandInfo; 1646 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1647 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1648 1649 MV_BOOLEAN is48bit = MV_FALSE; 1650 MV_U8 channel; 1651 int i=0; 1652 1653 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1654 1655 if (!pDevice->df_on_line) { 1656 MV_ERROR("Device is offline"); 1657 pCmd->Result = RETURN_BAD_DEVICE; 1658 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1659 return; 1660 } 1661 1662 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1663 pMvSataChannel = pDevice->mv; 1664 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1665 channel = pMvSataChannel->channelNumber; 1666 1667 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1668 Lba += pDevice->dDeHiddenLba; 1669 /* check LBA */ 1670 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1671 pCmd->Result = RETURN_INVALID_REQUEST; 1672 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1673 return; 1674 } 1675 1676 if(Lba & 0xF0000000){ 1677 is48bit = MV_TRUE; 1678 } 1679 1680 switch (pCmd->uCmd.Ide.Command) 1681 { 1682 case IDE_COMMAND_READ: 1683 case IDE_COMMAND_WRITE: 1684 if (pDevice->bDeModeSetting<8) goto pio; 1685 1686 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1687 pUdmaParams->isEXT = is48bit; 1688 pUdmaParams->numOfSectors = nSector; 1689 pUdmaParams->lowLBAAddress = Lba; 1690 pUdmaParams->highLBAAddress = 0; 1691 pUdmaParams->prdHighAddr = 0; 1692 pUdmaParams->callBack = CommandCompletionCB; 1693 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1694 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1695 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1696 else 1697 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1698 1699 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1700 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1701 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1702 } 1703 else { 1704 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1705 pio: 1706 mvSataDisableChannelDma(pMvSataAdapter, channel); 1707 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1708 1709 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1710 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1711 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1712 } 1713 else { 1714 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1715 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1716 goto finish_cmd; 1717 } 1718 } 1719 1720 do { 1721 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1722 ULONG_PTR addr = tmpSg->dSgAddress; 1723 if (size & 0x1ff) { 1724 pCmd->Result = RETURN_INVALID_REQUEST; 1725 goto finish_cmd; 1726 } 1727 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1728 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1729 is48bit, 1730 (MV_U16_PTR)addr, 1731 size >> 1, /* count */ 1732 0, /* features N/A */ 1733 (MV_U16)(size>>9), /*sector count*/ 1734 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1735 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1736 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1737 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1738 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1739 )==MV_FALSE) 1740 { 1741 pCmd->Result = RETURN_IDE_ERROR; 1742 goto finish_cmd; 1743 } 1744 Lba += size>>9; 1745 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1746 } 1747 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1748 pCmd->Result = RETURN_SUCCESS; 1749 finish_cmd: 1750 mvSataEnableChannelDma(pMvSataAdapter,channel); 1751 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1752 return; 1753 } 1754 } 1755 1756 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1757 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1758 if (!pPRDTable) { 1759 pCmd->Result = RETURN_DEVICE_BUSY; 1760 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1761 HPT_ASSERT(0); 1762 return; 1763 } 1764 1765 do{ 1766 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1767 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1768 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1769 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1770 pPRDTable[i].reserved = 0; 1771 i++; 1772 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1773 1774 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1775 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1776 pUdmaParams->numOfSectors = 0; 1777 } 1778 1779 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1780 1781 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1782 1783 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1784 { 1785 queue_failed: 1786 switch (result) 1787 { 1788 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1789 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1790 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1791 pCmd->Result = RETURN_IDE_ERROR; 1792 break; 1793 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1794 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1795 " disabled adapter %d channel %d\n", 1796 pMvSataAdapter->adapterId, channel); 1797 mvSataEnableChannelDma(pMvSataAdapter,channel); 1798 pCmd->Result = RETURN_IDE_ERROR; 1799 break; 1800 case MV_QUEUE_COMMAND_RESULT_FULL: 1801 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1802 " Full adapter %d channel %d\n", 1803 pMvSataAdapter->adapterId, channel); 1804 pCmd->Result = RETURN_DEVICE_BUSY; 1805 break; 1806 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1807 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1808 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1809 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1810 pCmd->Result = RETURN_IDE_ERROR; 1811 break; 1812 default: 1813 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1814 " command\n", result); 1815 pCmd->Result = RETURN_IDE_ERROR; 1816 } 1817 if(pPRDTable) 1818 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1819 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1820 } 1821 pDevice->QueueLength++; 1822 return; 1823 1824 case IDE_COMMAND_VERIFY: 1825 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1826 pNoUdmaParams->bufPtr = NULL; 1827 pNoUdmaParams->callBack = CommandCompletionCB; 1828 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1829 pNoUdmaParams->count = 0; 1830 pNoUdmaParams->features = 0; 1831 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1832 1833 pCmd->uScratch.sata_param.cmd_priv = 1; 1834 if (pMvSataChannel->lba48Address == MV_TRUE){ 1835 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1836 pNoUdmaParams->isEXT = MV_TRUE; 1837 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1838 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1839 pNoUdmaParams->lbaLow = 1840 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1841 pNoUdmaParams->sectorCount = nSector; 1842 pNoUdmaParams->device = 0x40; 1843 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1844 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1845 goto queue_failed; 1846 } 1847 return; 1848 } 1849 else{ 1850 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1851 pNoUdmaParams->isEXT = MV_FALSE; 1852 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1853 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1854 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1855 pNoUdmaParams->sectorCount = 0xff & nSector; 1856 pNoUdmaParams->device = (MV_U8)(0x40 | 1857 ((Lba & 0xf000000) >> 24)); 1858 pNoUdmaParams->callBack = CommandCompletionCB; 1859 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1860 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1861 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1862 goto queue_failed; 1863 } 1864 } 1865 break; 1866 default: 1867 pCmd->Result = RETURN_INVALID_REQUEST; 1868 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1869 break; 1870 } 1871 } 1872 1873 /********************************************************** 1874 * 1875 * Probe the hostadapter. 1876 * 1877 **********************************************************/ 1878 static int 1879 hpt_probe(device_t dev) 1880 { 1881 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1882 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1883 #ifdef FOR_DEMO 1884 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1885 #endif 1886 )) 1887 { 1888 KdPrintI((CONTROLLER_NAME " found\n")); 1889 device_set_desc(dev, CONTROLLER_NAME); 1890 return 0; 1891 } 1892 else 1893 return(ENXIO); 1894 } 1895 1896 /*********************************************************** 1897 * 1898 * Auto configuration: attach and init a host adapter. 1899 * 1900 ***********************************************************/ 1901 static int 1902 hpt_attach(device_t dev) 1903 { 1904 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1905 int rid; 1906 union ccb *ccb; 1907 struct cam_devq *devq; 1908 struct cam_sim *hpt_vsim; 1909 1910 printf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1911 1912 if (!pAdapter) 1913 { 1914 pAdapter = (IAL_ADAPTER_T *)malloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT); 1915 #if __FreeBSD_version > 410000 1916 device_set_softc(dev, (void *)pAdapter); 1917 #else 1918 device_set_driver(dev, (driver_t *)pAdapter); 1919 #endif 1920 } 1921 1922 if (!pAdapter) return (ENOMEM); 1923 bzero(pAdapter, sizeof(IAL_ADAPTER_T)); 1924 1925 pAdapter->hpt_dev = dev; 1926 1927 rid = init_adapter(pAdapter); 1928 if (rid) 1929 return rid; 1930 1931 rid = 0; 1932 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) 1933 { 1934 hpt_printk(("can't allocate interrupt\n")); 1935 return(ENXIO); 1936 } 1937 1938 if(bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 1939 { 1940 hpt_printk(("can't set up interrupt\n")); 1941 free(pAdapter, M_DEVBUF); 1942 return(ENXIO); 1943 } 1944 1945 1946 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL) 1947 { 1948 bzero(ccb, sizeof(*ccb)); 1949 ccb->ccb_h.pinfo.priority = 1; 1950 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 1951 } 1952 else 1953 { 1954 return ENOMEM; 1955 } 1956 /* 1957 * Create the device queue for our SIM(s). 1958 */ 1959 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 1960 { 1961 KdPrint(("ENXIO\n")); 1962 return ENOMEM; 1963 } 1964 1965 /* 1966 * Construct our SIM entry 1967 */ 1968 if ((hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 1969 pAdapter, device_get_unit(pAdapter->hpt_dev), /*untagged*/1, /*tagged*/8, devq)) == NULL) { 1970 cam_simq_free(devq); 1971 return ENOMEM; 1972 } 1973 1974 if(xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) 1975 { 1976 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 1977 hpt_vsim = NULL; 1978 return ENXIO; 1979 } 1980 1981 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 1982 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 1983 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 1984 { 1985 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 1986 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 1987 hpt_vsim = NULL; 1988 return ENXIO; 1989 } 1990 1991 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 1992 ccb->ccb_h.func_code = XPT_SASYNC_CB; 1993 ccb->csa.event_enable = AC_LOST_DEVICE; 1994 ccb->csa.callback = hpt_async; 1995 ccb->csa.callback_arg = hpt_vsim; 1996 xpt_action((union ccb *)ccb); 1997 free(ccb, M_DEVBUF); 1998 1999 /* Register shutdown handler, and start the work thread. */ 2000 if (device_get_unit(dev) == 0) { 2001 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_final, 2002 hpt_shutdown, dev, SHUTDOWN_PRI_DEFAULT); 2003 if (pAdapter->eh) 2004 launch_worker_thread(); 2005 else 2006 hpt_printk(("shutdown event registration failed\n")); 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int 2013 hpt_detach(device_t dev) 2014 { 2015 return (EBUSY); 2016 } 2017 2018 2019 /*************************************************************** 2020 * The poll function is used to simulate the interrupt when 2021 * the interrupt subsystem is not functioning. 2022 * 2023 ***************************************************************/ 2024 static void 2025 hpt_poll(struct cam_sim *sim) 2026 { 2027 hpt_intr((void *)cam_sim_softc(sim)); 2028 } 2029 2030 /**************************************************************** 2031 * Name: hpt_intr 2032 * Description: Interrupt handler. 2033 ****************************************************************/ 2034 static void 2035 hpt_intr(void *arg) 2036 { 2037 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg; 2038 intrmask_t oldspl = lock_driver(); 2039 2040 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2041 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2042 { 2043 _VBUS_INST(&pAdapter->VBus) 2044 CheckPendingCall(_VBUS_P0); 2045 } 2046 2047 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2048 unlock_driver(oldspl); 2049 } 2050 2051 /********************************************************** 2052 * Asynchronous Events 2053 *********************************************************/ 2054 #if (!defined(UNREFERENCED_PARAMETER)) 2055 #define UNREFERENCED_PARAMETER(x) (void)(x) 2056 #endif 2057 2058 static void 2059 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2060 void * arg) 2061 { 2062 /* debug XXXX */ 2063 panic("Here"); 2064 UNREFERENCED_PARAMETER(callback_arg); 2065 UNREFERENCED_PARAMETER(code); 2066 UNREFERENCED_PARAMETER(path); 2067 UNREFERENCED_PARAMETER(arg); 2068 2069 } 2070 2071 static void 2072 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2073 { 2074 int i; 2075 2076 hpt_printk(("flush all devices\n")); 2077 2078 /* flush all devices */ 2079 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2080 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2081 if(pVDev) fFlushVDev(pVDev); 2082 } 2083 } 2084 2085 static int 2086 hpt_shutdown(device_t dev) 2087 { 2088 IAL_ADAPTER_T *pAdapter; 2089 2090 pAdapter = device_get_softc(dev); 2091 if (pAdapter == NULL) 2092 return (EINVAL); 2093 2094 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2095 FlushAdapter(pAdapter); 2096 /* give the flush some time to happen, 2097 *otherwise "shutdown -p now" will make file system corrupted */ 2098 DELAY(1000 * 1000 * 5); 2099 return 0; 2100 } 2101 2102 void 2103 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2104 { 2105 _VBUS_INST(&pAdapter->VBus) 2106 2107 if (mWaitingForIdle(_VBUS_P0)) { 2108 CheckIdleCall(_VBUS_P0); 2109 #ifdef SUPPORT_ARRAY 2110 { 2111 int i; 2112 PVDevice pArray; 2113 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2114 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2115 continue; 2116 else if (pArray->u.array.rf_auto_rebuild) { 2117 KdPrint(("auto rebuild.\n")); 2118 pArray->u.array.rf_auto_rebuild = 0; 2119 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2120 } 2121 } 2122 } 2123 #endif 2124 } 2125 /* launch the awaiting commands blocked by mWaitingForIdle */ 2126 while(pAdapter->pending_Q!= NULL) 2127 { 2128 _VBUS_INST(&pAdapter->VBus) 2129 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2130 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2131 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2132 } 2133 } 2134 2135 static void 2136 ccb_done(union ccb *ccb) 2137 { 2138 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2139 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2140 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2141 2142 dmamap_put(pmap); 2143 xpt_done(ccb); 2144 2145 pAdapter->outstandingCommands--; 2146 2147 if (pAdapter->outstandingCommands == 0) 2148 { 2149 if(DPC_Request_Nums == 0) 2150 Check_Idle_Call(pAdapter); 2151 } 2152 } 2153 2154 /**************************************************************** 2155 * Name: hpt_action 2156 * Description: Process a queued command from the CAM layer. 2157 * Parameters: sim - Pointer to SIM object 2158 * ccb - Pointer to SCSI command structure. 2159 ****************************************************************/ 2160 2161 void 2162 hpt_action(struct cam_sim *sim, union ccb *ccb) 2163 { 2164 intrmask_t oldspl; 2165 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2166 PBUS_DMAMAP pmap; 2167 _VBUS_INST(&pAdapter->VBus) 2168 2169 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2170 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2171 2172 switch (ccb->ccb_h.func_code) 2173 { 2174 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2175 { 2176 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2177 2178 if (ccb->ccb_h.target_lun) { 2179 ccb->ccb_h.status = CAM_LUN_INVALID; 2180 xpt_done(ccb); 2181 return; 2182 } 2183 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2184 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2185 ccb->ccb_h.status = CAM_TID_INVALID; 2186 xpt_done(ccb); 2187 return; 2188 } 2189 2190 oldspl = lock_driver(); 2191 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2192 Check_Idle_Call(pAdapter); 2193 2194 pmap = dmamap_get(pAdapter); 2195 HPT_ASSERT(pmap); 2196 ccb->ccb_adapter = pmap; 2197 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2198 2199 if (mWaitingForIdle(_VBUS_P0)) 2200 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2201 else 2202 OsSendCommand(_VBUS_P ccb); 2203 unlock_driver(oldspl); 2204 2205 /* KdPrint(("leave scsiio\n")); */ 2206 break; 2207 } 2208 2209 case XPT_RESET_BUS: 2210 KdPrint(("reset bus\n")); 2211 oldspl = lock_driver(); 2212 fResetVBus(_VBUS_P0); 2213 unlock_driver(oldspl); 2214 xpt_done(ccb); 2215 break; 2216 2217 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2218 case XPT_EN_LUN: /* Enable LUN as a target */ 2219 case XPT_TARGET_IO: /* Execute target I/O request */ 2220 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2221 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2222 case XPT_ABORT: /* Abort the specified CCB */ 2223 case XPT_TERM_IO: /* Terminate the I/O process */ 2224 /* XXX Implement */ 2225 ccb->ccb_h.status = CAM_REQ_INVALID; 2226 xpt_done(ccb); 2227 break; 2228 2229 case XPT_GET_TRAN_SETTINGS: 2230 case XPT_SET_TRAN_SETTINGS: 2231 /* XXX Implement */ 2232 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2233 xpt_done(ccb); 2234 break; 2235 2236 case XPT_CALC_GEOMETRY: 2237 { 2238 struct ccb_calc_geometry *ccg; 2239 u_int32_t size_mb; 2240 u_int32_t secs_per_cylinder; 2241 2242 ccg = &ccb->ccg; 2243 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size); 2244 2245 if (size_mb > 1024 ) { 2246 ccg->heads = 255; 2247 ccg->secs_per_track = 63; 2248 } else { 2249 ccg->heads = 64; 2250 ccg->secs_per_track = 32; 2251 } 2252 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2253 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2254 ccb->ccb_h.status = CAM_REQ_CMP; 2255 xpt_done(ccb); 2256 break; 2257 } 2258 2259 case XPT_PATH_INQ: /* Path routing inquiry */ 2260 { 2261 struct ccb_pathinq *cpi = &ccb->cpi; 2262 2263 cpi->version_num = 1; /* XXX??? */ 2264 cpi->hba_inquiry = PI_SDTR_ABLE; 2265 cpi->target_sprt = 0; 2266 /* Not necessary to reset bus */ 2267 cpi->hba_misc = PIM_NOBUSRESET; 2268 cpi->hba_eng_cnt = 0; 2269 2270 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2271 cpi->max_lun = 0; 2272 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2273 2274 cpi->bus_id = cam_sim_bus(sim); 2275 cpi->base_transfer_speed = 3300; 2276 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2277 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2278 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2279 cpi->unit_number = cam_sim_unit(sim); 2280 cpi->ccb_h.status = CAM_REQ_CMP; 2281 xpt_done(ccb); 2282 break; 2283 } 2284 2285 default: 2286 KdPrint(("invalid cmd\n")); 2287 ccb->ccb_h.status = CAM_REQ_INVALID; 2288 xpt_done(ccb); 2289 break; 2290 } 2291 /* KdPrint(("leave hpt_action..............\n")); */ 2292 } 2293 2294 /* shall be called at lock_driver() */ 2295 static void 2296 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2297 { 2298 if(*ccb_Q == NULL) 2299 ccb->ccb_h.ccb_ccb_ptr = ccb; 2300 else { 2301 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2302 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2303 } 2304 2305 *ccb_Q = ccb; 2306 } 2307 2308 /* shall be called at lock_driver() */ 2309 static void 2310 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2311 { 2312 union ccb *TempCCB; 2313 2314 TempCCB = *ccb_Q; 2315 2316 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2317 *ccb_Q = NULL; 2318 else { 2319 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2320 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2321 2322 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2323 2324 if(*ccb_Q == ccb) 2325 *ccb_Q = TempCCB; 2326 } 2327 } 2328 2329 #ifdef SUPPORT_ARRAY 2330 /*************************************************************************** 2331 * Function: hpt_worker_thread 2332 * Description: Do background rebuilding. Execute in kernel thread context. 2333 * Returns: None 2334 ***************************************************************************/ 2335 static void hpt_worker_thread(void) 2336 { 2337 intrmask_t oldspl; 2338 2339 for(;;) { 2340 while (DpcQueue_First!=DpcQueue_Last) { 2341 ST_HPT_DPC p; 2342 oldspl = lock_driver(); 2343 p = DpcQueue[DpcQueue_First]; 2344 DpcQueue_First++; 2345 DpcQueue_First %= MAX_DPC; 2346 DPC_Request_Nums++; 2347 unlock_driver(oldspl); 2348 p.dpc(p.pAdapter, p.arg, p.flags); 2349 2350 oldspl = lock_driver(); 2351 DPC_Request_Nums--; 2352 /* since we may have prevented Check_Idle_Call, do it here */ 2353 if (DPC_Request_Nums==0) { 2354 if (p.pAdapter->outstandingCommands == 0) { 2355 _VBUS_INST(&p.pAdapter->VBus); 2356 Check_Idle_Call(p.pAdapter); 2357 CheckPendingCall(_VBUS_P0); 2358 } 2359 } 2360 unlock_driver(oldspl); 2361 2362 /*Schedule out*/ 2363 #if (__FreeBSD_version < 500000) 2364 YIELD_THREAD; 2365 #else 2366 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "sched", 1); 2367 #endif 2368 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2369 /* abort rebuilding process. */ 2370 IAL_ADAPTER_T *pAdapter; 2371 PVDevice pArray; 2372 PVBus _vbus_p; 2373 int i; 2374 pAdapter = gIal_Adapter; 2375 2376 while(pAdapter != 0){ 2377 2378 _vbus_p = &pAdapter->VBus; 2379 2380 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2381 { 2382 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2383 continue; 2384 else if (pArray->u.array.rf_rebuilding || 2385 pArray->u.array.rf_verifying || 2386 pArray->u.array.rf_initializing) 2387 { 2388 pArray->u.array.rf_abort_rebuild = 1; 2389 } 2390 } 2391 pAdapter = pAdapter->next; 2392 } 2393 } 2394 } 2395 2396 /*Remove this debug option*/ 2397 /* 2398 #ifdef DEBUG 2399 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2400 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); 2401 #endif 2402 */ 2403 #if (__FreeBSD_version >= 500043) 2404 kthread_suspend_check(curproc); 2405 #else 2406 kproc_suspend_loop(curproc); 2407 #endif 2408 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); /* wait for something to do */ 2409 } 2410 } 2411 2412 static struct proc *hptdaemonproc; 2413 static struct kproc_desc hpt_kp = { 2414 "hpt_wt", 2415 hpt_worker_thread, 2416 &hptdaemonproc 2417 }; 2418 2419 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2420 static void 2421 launch_worker_thread(void) 2422 { 2423 IAL_ADAPTER_T *pAdapTemp; 2424 2425 kproc_start(&hpt_kp); 2426 2427 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2428 2429 _VBUS_INST(&pAdapTemp->VBus) 2430 int i; 2431 PVDevice pVDev; 2432 2433 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2434 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2435 continue; 2436 else{ 2437 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2438 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2439 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2440 } 2441 } 2442 2443 /* 2444 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2445 */ 2446 #if (__FreeBSD_version < 500043) 2447 EVENTHANDLER_REGISTER(shutdown_post_sync, shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2448 #else 2449 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2450 #endif 2451 } 2452 /* 2453 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2454 */ 2455 2456 #endif 2457 2458 /********************************************************************************/ 2459 2460 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2461 { 2462 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2463 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2464 int idx; 2465 2466 if(logical) { 2467 if (ccb->ccb_h.flags & CAM_DATA_PHYS) 2468 panic("physical address unsupported"); 2469 2470 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2471 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2472 panic("physical address unsupported"); 2473 2474 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2475 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2476 pSg[idx].wSgSize = sgList[idx].ds_len; 2477 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0; 2478 } 2479 } 2480 else { 2481 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2482 pSg->wSgSize = ccb->csio.dxfer_len; 2483 pSg->wSgFlag = SG_FLAG_EOT; 2484 } 2485 return TRUE; 2486 } 2487 2488 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2489 HPT_ASSERT(0); 2490 return FALSE; 2491 } 2492 2493 /*******************************************************************************/ 2494 ULONG HPTLIBAPI 2495 GetStamp(void) 2496 { 2497 /* 2498 * the system variable, ticks, can't be used since it hasn't yet been active 2499 * when our driver starts (ticks==0, it's a invalid stamp value) 2500 */ 2501 ULONG stamp; 2502 do { stamp = random(); } while (stamp==0); 2503 return stamp; 2504 } 2505 2506 2507 static void 2508 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2509 { 2510 int i; 2511 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2512 2513 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2514 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2515 #ifndef SERIAL_CMDS 2516 inquiryData->CommandQueue = 1; 2517 #endif 2518 2519 switch(pVDev->VDeviceType) { 2520 case VD_SINGLE_DISK: 2521 case VD_ATAPI: 2522 case VD_REMOVABLE: 2523 /* Set the removable bit, if applicable. */ 2524 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2525 inquiryData->RemovableMedia = 1; 2526 2527 /* Fill in vendor identification fields. */ 2528 for (i = 0; i < 20; i += 2) { 2529 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2530 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2531 2532 } 2533 2534 /* Initialize unused portion of product id. */ 2535 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2536 2537 /* firmware revision */ 2538 for (i = 0; i < 4; i += 2) 2539 { 2540 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2541 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2542 } 2543 break; 2544 default: 2545 memcpy(&inquiryData->VendorId, "RR182x ", 8); 2546 #ifdef SUPPORT_ARRAY 2547 switch(pVDev->VDeviceType){ 2548 case VD_RAID_0: 2549 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2550 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2551 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2552 else 2553 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2554 break; 2555 case VD_RAID_1: 2556 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2557 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2558 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2559 else 2560 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2561 break; 2562 case VD_RAID_5: 2563 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2564 break; 2565 case VD_JBOD: 2566 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2567 break; 2568 } 2569 #endif 2570 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2571 break; 2572 } 2573 } 2574 2575 static void 2576 hpt_timeout(void *arg) 2577 { 2578 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus) 2579 intrmask_t oldspl = lock_driver(); 2580 fResetVBus(_VBUS_P0); 2581 unlock_driver(oldspl); 2582 } 2583 2584 static void 2585 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2586 { 2587 PCommand pCmd = (PCommand)arg; 2588 union ccb *ccb = pCmd->pOrgCommand; 2589 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2590 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2591 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2592 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2593 FPSCAT_GATH psg = pCmd->pSgTable; 2594 int idx; 2595 _VBUS_INST(pVDev->pVBus) 2596 2597 HPT_ASSERT(pCmd->cf_physical_sg); 2598 2599 if (error || nsegs == 0) 2600 panic("busdma error"); 2601 2602 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2603 2604 for (idx = 0; idx < nsegs; idx++, psg++) { 2605 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2606 psg->wSgSize = segs[idx].ds_len; 2607 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2608 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2609 } 2610 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2611 2612 if (pCmd->cf_data_in) { 2613 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD); 2614 } 2615 else if (pCmd->cf_data_out) { 2616 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE); 2617 } 2618 2619 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2620 pVDev->pfnSendCommand(_VBUS_P pCmd); 2621 CheckPendingCall(_VBUS_P0); 2622 } 2623 2624 2625 2626 static void HPTLIBAPI 2627 OsSendCommand(_VBUS_ARG union ccb *ccb) 2628 { 2629 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2630 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2631 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2632 struct ccb_scsiio *csio = &ccb->csio; 2633 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2634 2635 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2636 ccb, 2637 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2638 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2639 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2640 )); 2641 2642 pAdapter->outstandingCommands++; 2643 2644 if (pVDev == NULL || pVDev->vf_online == 0) { 2645 ccb->ccb_h.status = CAM_REQ_INVALID; 2646 ccb_done(ccb); 2647 goto Command_Complished; 2648 } 2649 2650 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2651 { 2652 case TEST_UNIT_READY: 2653 case START_STOP_UNIT: 2654 case SYNCHRONIZE_CACHE: 2655 /* FALLTHROUGH */ 2656 ccb->ccb_h.status = CAM_REQ_CMP; 2657 break; 2658 2659 case INQUIRY: 2660 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2661 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2662 ccb_h->status = CAM_REQ_CMP; 2663 break; 2664 2665 case READ_CAPACITY: 2666 { 2667 UCHAR swip[4]; 2668 /* Claim 512 byte blocks (big-endian). */ 2669 ((PREAD_CAPACITY_DATA)csio->data_ptr)->BytesPerBlock = 0x20000; 2670 *(ULONG*)swip = pVDev->VDeviceCapacity - 1; 2671 ((PREAD_CAPACITY_DATA)csio->data_ptr)->LogicalBlockAddress = 2672 (swip[0] << 24) | (swip[1] << 16) | (swip[2] << 8) | swip[3]; 2673 ccb_h->status = CAM_REQ_CMP; 2674 break; 2675 } 2676 2677 case READ_6: 2678 case WRITE_6: 2679 case READ_10: 2680 case WRITE_10: 2681 case 0x13: 2682 case 0x2f: 2683 { 2684 UCHAR Cdb[16]; 2685 UCHAR CdbLength; 2686 _VBUS_INST(pVDev->pVBus) 2687 PCommand pCmd = AllocateCommand(_VBUS_P0); 2688 HPT_ASSERT(pCmd); 2689 2690 CdbLength = csio->cdb_len; 2691 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2692 { 2693 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2694 { 2695 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2696 } 2697 else 2698 { 2699 KdPrintE(("ERROR!!!\n")); 2700 ccb->ccb_h.status = CAM_REQ_INVALID; 2701 break; 2702 } 2703 } 2704 else 2705 { 2706 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2707 } 2708 2709 pCmd->pOrgCommand = ccb; 2710 pCmd->pVDevice = pVDev; 2711 pCmd->pfnCompletion = fOsCommandDone; 2712 pCmd->pfnBuildSgl = fOsBuildSgl; 2713 pCmd->pSgTable = pmap->psg; 2714 2715 switch (Cdb[0]) 2716 { 2717 case READ_6: 2718 case WRITE_6: 2719 case 0x13: 2720 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2721 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2722 break; 2723 2724 default: 2725 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2726 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2727 break; 2728 } 2729 2730 switch (Cdb[0]) 2731 { 2732 case READ_6: 2733 case READ_10: 2734 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2735 pCmd->cf_data_in = 1; 2736 break; 2737 2738 case WRITE_6: 2739 case WRITE_10: 2740 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2741 pCmd->cf_data_out = 1; 2742 break; 2743 case 0x13: 2744 case 0x2f: 2745 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2746 break; 2747 } 2748 /*///////////////////////// */ 2749 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2750 int idx; 2751 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2752 2753 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2754 pCmd->cf_physical_sg = 1; 2755 2756 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2757 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2758 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len; 2759 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0; 2760 } 2761 2762 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2763 pVDev->pfnSendCommand(_VBUS_P pCmd); 2764 } 2765 else { 2766 int error; 2767 pCmd->cf_physical_sg = 1; 2768 error = bus_dmamap_load(pAdapter->io_dma_parent, 2769 pmap->dma_map, 2770 ccb->csio.data_ptr, ccb->csio.dxfer_len, 2771 hpt_io_dmamap_callback, pCmd, 2772 BUS_DMA_WAITOK 2773 ); 2774 KdPrint(("bus_dmamap_load return %d\n", error)); 2775 if (error && error!=EINPROGRESS) { 2776 hpt_printk(("bus_dmamap_load error %d\n", error)); 2777 FreeCommand(_VBUS_P pCmd); 2778 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2779 dmamap_put(pmap); 2780 pAdapter->outstandingCommands--; 2781 xpt_done(ccb); 2782 } 2783 } 2784 goto Command_Complished; 2785 } 2786 2787 default: 2788 ccb->ccb_h.status = CAM_REQ_INVALID; 2789 break; 2790 } 2791 ccb_done(ccb); 2792 Command_Complished: 2793 CheckPendingCall(_VBUS_P0); 2794 return; 2795 } 2796 2797 static void HPTLIBAPI 2798 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2799 { 2800 union ccb *ccb = pCmd->pOrgCommand; 2801 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2802 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2803 2804 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2805 2806 untimeout(hpt_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch); 2807 2808 switch(pCmd->Result) { 2809 case RETURN_SUCCESS: 2810 ccb->ccb_h.status = CAM_REQ_CMP; 2811 break; 2812 case RETURN_BAD_DEVICE: 2813 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2814 break; 2815 case RETURN_DEVICE_BUSY: 2816 ccb->ccb_h.status = CAM_BUSY; 2817 break; 2818 case RETURN_INVALID_REQUEST: 2819 ccb->ccb_h.status = CAM_REQ_INVALID; 2820 break; 2821 case RETURN_SELECTION_TIMEOUT: 2822 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2823 break; 2824 case RETURN_RETRY: 2825 ccb->ccb_h.status = CAM_BUSY; 2826 break; 2827 default: 2828 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2829 break; 2830 } 2831 2832 if (pCmd->cf_data_in) { 2833 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2834 } 2835 else if (pCmd->cf_data_in) { 2836 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2837 } 2838 2839 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2840 2841 FreeCommand(_VBUS_P pCmd); 2842 ccb_done(ccb); 2843 } 2844 2845 int 2846 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2847 { 2848 int p; 2849 2850 p = (DpcQueue_Last + 1) % MAX_DPC; 2851 if (p==DpcQueue_First) { 2852 KdPrint(("DPC Queue full!\n")); 2853 return -1; 2854 } 2855 2856 DpcQueue[DpcQueue_Last].dpc = dpc; 2857 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2858 DpcQueue[DpcQueue_Last].arg = arg; 2859 DpcQueue[DpcQueue_Last].flags = flags; 2860 DpcQueue_Last = p; 2861 2862 return 0; 2863 } 2864 2865 #ifdef _RAID5N_ 2866 /* 2867 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2868 * How about the memory for 5081 request/response array and PRD table? 2869 */ 2870 void 2871 *os_alloc_page(_VBUS_ARG0) 2872 { 2873 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2874 } 2875 2876 void 2877 *os_alloc_dma_page(_VBUS_ARG0) 2878 { 2879 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2880 } 2881 2882 void 2883 os_free_page(_VBUS_ARG void *p) 2884 { 2885 contigfree(p, 0x1000, M_DEVBUF); 2886 } 2887 2888 void 2889 os_free_dma_page(_VBUS_ARG void *p) 2890 { 2891 contigfree(p, 0x1000, M_DEVBUF); 2892 } 2893 2894 void 2895 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2896 { 2897 UINT i; 2898 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 2899 } 2900 2901 void 2902 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 2903 { 2904 UINT i; 2905 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 2906 } 2907 #endif 2908