1 /* 2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/malloc.h> 34 #include <sys/resource.h> 35 #include <sys/time.h> 36 #include <sys/callout.h> 37 #include <sys/signalvar.h> 38 #include <sys/eventhandler.h> 39 #include <sys/proc.h> 40 #include <sys/kthread.h> 41 42 #if (__FreeBSD_version >= 500000) 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #endif 46 47 #if (__FreeBSD_version >= 500000) 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #else 51 #include <pci/pcireg.h> 52 #include <pci/pcivar.h> 53 #include <sys/wait.h> 54 #include <sys/sysproto.h> 55 #endif 56 57 #ifndef __KERNEL__ 58 #define __KERNEL__ 59 #endif 60 61 #include <dev/hptmv/global.h> 62 #include <dev/hptmv/hptintf.h> 63 #include <dev/hptmv/osbsd.h> 64 #include <dev/hptmv/access601.h> 65 66 67 #ifdef DEBUG 68 #ifdef DEBUG_LEVEL 69 int hpt_dbg_level = DEBUG_LEVEL; 70 #else 71 int hpt_dbg_level = 0; 72 #endif 73 #endif 74 75 #define MV_ERROR printf 76 77 /* 78 * CAM SIM entry points 79 */ 80 static int hpt_probe (device_t dev); 81 static void launch_worker_thread(void); 82 static int hpt_attach(device_t dev); 83 static int hpt_detach(device_t dev); 84 static int hpt_shutdown(device_t dev); 85 static void hpt_poll(struct cam_sim *sim); 86 static void hpt_intr(void *arg); 87 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 88 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 89 90 static device_method_t driver_methods[] = { 91 /* Device interface */ 92 DEVMETHOD(device_probe, hpt_probe), 93 DEVMETHOD(device_attach, hpt_attach), 94 DEVMETHOD(device_detach, hpt_detach), 95 96 /* DEVMETHOD(device_shutdown, hpt_shutdown), */ 97 { 0, 0 } 98 }; 99 100 static driver_t hpt_pci_driver = { 101 __str(PROC_DIR_NAME), 102 driver_methods, 103 sizeof(IAL_ADAPTER_T) 104 }; 105 106 static devclass_t hpt_devclass; 107 108 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 109 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 110 111 #define ccb_ccb_ptr spriv_ptr0 112 #define ccb_adapter ccb_h.spriv_ptr1 113 114 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 115 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 116 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 117 static void ccb_done(union ccb *ccb); 118 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 119 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 120 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 121 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 122 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 123 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 124 static int fResetActiveCommands(PVBus _vbus_p); 125 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 126 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 127 static void hptmv_handle_event_disconnect(void *data); 128 static void hptmv_handle_event_connect(void *data); 129 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 130 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 131 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 132 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 133 int logical); 134 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 135 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 136 MV_U16 responseFlags, MV_U32 timeStamp, 137 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 138 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 139 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 140 141 #define ccb_ccb_ptr spriv_ptr0 142 #define ccb_adapter ccb_h.spriv_ptr1 143 144 IAL_ADAPTER_T *gIal_Adapter = 0; 145 IAL_ADAPTER_T *pCurAdapter = 0; 146 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 147 148 typedef struct st_HPT_DPC { 149 IAL_ADAPTER_T *pAdapter; 150 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 151 void *arg; 152 UCHAR flags; 153 } ST_HPT_DPC; 154 155 #define MAX_DPC 16 156 UCHAR DPC_Request_Nums = 0; 157 static ST_HPT_DPC DpcQueue[MAX_DPC]; 158 static int DpcQueue_First=0; 159 static int DpcQueue_Last = 0; 160 161 char DRIVER_VERSION[] = "v1.12"; 162 163 #if (__FreeBSD_version >= 500000) 164 static struct mtx driver_lock; 165 intrmask_t lock_driver() 166 { 167 168 intrmask_t spl = 0; 169 mtx_lock(&driver_lock); 170 return spl; 171 } 172 void unlock_driver(intrmask_t spl) 173 { 174 mtx_unlock(&driver_lock); 175 } 176 #else 177 static int driver_locked = 0; 178 intrmask_t lock_driver() 179 { 180 intrmask_t spl = splcam(); 181 loop: 182 while (driver_locked) 183 tsleep(&driver_locked, PRIBIO, "hptlck", hz); 184 atomic_add_int(&driver_locked, 1); 185 if (driver_locked>1) { 186 atomic_subtract_int(&driver_locked, 1); 187 goto loop; 188 } 189 return spl; 190 } 191 192 void unlock_driver(intrmask_t spl) 193 { 194 atomic_subtract_int(&driver_locked, 1); 195 if (driver_locked==0) { 196 wakeup(&driver_locked); 197 } 198 splx(spl); 199 } 200 #endif 201 202 /******************************************************************************* 203 * Name: hptmv_free_channel 204 * 205 * Description: free allocated queues for the given channel 206 * 207 * Parameters: pMvSataAdapter - pointer to the RR182x controler this 208 * channel connected to. 209 * channelNum - channel number. 210 * 211 ******************************************************************************/ 212 static void 213 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 214 { 215 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 216 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 217 } 218 219 static void failDevice(PVDevice pVDev) 220 { 221 PVBus _vbus_p = pVDev->pVBus; 222 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 223 224 pVDev->u.disk.df_on_line = 0; 225 pVDev->vf_online = 0; 226 if (pVDev->pfnDeviceFailed) 227 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 228 229 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 230 231 #ifndef FOR_DEMO 232 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 233 pAdapter->beeping = 1; 234 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 235 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 236 } 237 #endif 238 } 239 240 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 241 /*void fDeviceSendCommand(_VBUS_ARG PCommand pCmd); */ 242 243 static void 244 handleEdmaError(_VBUS_ARG PCommand pCmd) 245 { 246 PDevice pDevice = &pCmd->pVDevice->u.disk; 247 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 248 249 if (!pDevice->df_on_line) { 250 KdPrint(("Device is offline")); 251 pCmd->Result = RETURN_BAD_DEVICE; 252 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 253 return; 254 } 255 256 if (pCmd->RetryCount++>5) { 257 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 258 failed: 259 failDevice(pCmd->pVDevice); 260 pCmd->Result = RETURN_IDE_ERROR; 261 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 262 return; 263 } 264 265 /* reset the channel and retry the command */ 266 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 267 goto failed; 268 269 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 270 271 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 272 fDeviceSendCommand(_VBUS_P pCmd); 273 } 274 275 /**************************************************************** 276 * Name: hptmv_init_channel 277 * 278 * Description: allocate request and response queues for the EDMA of the 279 * given channel and sets other fields. 280 * 281 * Parameters: 282 * pAdapter - pointer to the emulated adapter data structure 283 * channelNum - channel number. 284 * Return: 0 on success, otherwise on failure 285 ****************************************************************/ 286 static int 287 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 288 { 289 MV_SATA_CHANNEL *pMvSataChannel; 290 dma_addr_t req_dma_addr; 291 dma_addr_t rsp_dma_addr; 292 293 if (channelNum >= MV_SATA_CHANNELS_NUM) 294 { 295 MV_ERROR("RR182x[%d]: Bad channelNum=%d", 296 pAdapter->mvSataAdapter.adapterId, channelNum); 297 return -1; 298 } 299 300 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 301 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 302 pMvSataChannel->channelNumber = channelNum; 303 pMvSataChannel->lba48Address = MV_FALSE; 304 pMvSataChannel->maxReadTransfer = MV_FALSE; 305 306 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 307 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 308 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 309 310 311 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 312 313 /* check the 1K alignment of the request queue*/ 314 if (req_dma_addr & 0x3ff) 315 { 316 MV_ERROR("RR182x[%d]: request queue allocated isn't 1 K aligned," 317 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 318 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 319 return -1; 320 } 321 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 322 pMvSataChannel->requestQueuePciHiAddress = 0; 323 KdPrint(("RR182x[%d,%d]: request queue allocated: 0x%p", 324 pAdapter->mvSataAdapter.adapterId, channelNum, 325 pMvSataChannel->requestQueue)); 326 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 327 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 328 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 329 330 /* check the 256 alignment of the response queue*/ 331 if (rsp_dma_addr & 0xff) 332 { 333 MV_ERROR("RR182x[%d,%d]: response queue allocated isn't 256 byte " 334 "aligned, dma_addr=%llx\n", 335 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 336 return -1; 337 } 338 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 339 pMvSataChannel->responseQueuePciHiAddress = 0; 340 KdPrint(("RR182x[%d,%d]: response queue allocated: 0x%p", 341 pAdapter->mvSataAdapter.adapterId, channelNum, 342 pMvSataChannel->responseQueue)); 343 344 pAdapter->mvChannel[channelNum].online = MV_TRUE; 345 return 0; 346 } 347 348 /****************************************************************************** 349 * Name: hptmv_parse_identify_results 350 * 351 * Description: this functions parses the identify command results, checks 352 * that the connected deives can be accesed by RR182x EDMA, 353 * and updates the channel stucture accordingly. 354 * 355 * Parameters: pMvSataChannel, pointer to the channel data structure. 356 * 357 * Returns: =0 ->success, < 0 ->failure. 358 * 359 ******************************************************************************/ 360 static int 361 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 362 { 363 MV_U16 *iden = pMvSataChannel->identifyDevice; 364 365 /*LBA addressing*/ 366 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 367 { 368 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 369 return -1; 370 } 371 else 372 { 373 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 374 } 375 /*DMA support*/ 376 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 377 { 378 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 379 return -1; 380 } 381 else 382 { 383 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 384 } 385 /* PIO */ 386 if ((iden[IDEN_VALID] & 2) == 0) 387 { 388 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 389 return -1; 390 } 391 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 392 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 393 394 /*UDMA*/ 395 if ((iden[IDEN_VALID] & 4) == 0) 396 { 397 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 398 return -1; 399 } 400 401 /* 48 bit address */ 402 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 403 { 404 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 405 pMvSataChannel->lba48Address = MV_TRUE; 406 } 407 else 408 { 409 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 410 pMvSataChannel->lba48Address = MV_FALSE; 411 } 412 return 0; 413 } 414 415 static void 416 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 417 { 418 PVDevice pVDev = &pAdapter->VDevices[channel]; 419 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 420 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 421 422 pMvSataChannel->outstandingCommands = 0; 423 424 pVDev->u.disk.mv = pMvSataChannel; 425 pVDev->u.disk.df_on_line = 1; 426 pVDev->u.disk.pVBus = &pAdapter->VBus; 427 pVDev->pVBus = &pAdapter->VBus; 428 429 #ifdef SUPPORT_48BIT_LBA 430 if (pMvSataChannel->lba48Address == MV_TRUE) 431 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 432 else 433 #endif 434 if(IdentifyData[53] & 1) { 435 pVDev->u.disk.dDeRealCapacity = 436 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 437 (IdentifyData[61]<<16 | IdentifyData[60]) : 438 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 439 } else 440 pVDev->u.disk.dDeRealCapacity = 441 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 442 443 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 444 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 445 446 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 447 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 448 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 449 } 450 } 451 452 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 453 { 454 PVDevice pVDev; 455 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 456 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 457 458 if (!pMvSataChannel) return; 459 460 if (plugged) 461 { 462 pVDev = &(pAdapter->VDevices[channelIndex]); 463 init_vdev_params(pAdapter, channelIndex); 464 465 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 466 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 467 468 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 469 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 470 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 471 pVDev->vf_online = 1; 472 473 #ifdef SUPPORT_ARRAY 474 if(pVDev->pParent) 475 { 476 int iMember; 477 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 478 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 479 pVDev->pParent->u.array.pMember[iMember] = NULL; 480 pVDev->pParent = NULL; 481 } 482 #endif 483 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 484 fCheckBootable(pVDev); 485 RegisterVDevice(pVDev); 486 487 #ifndef FOR_DEMO 488 if (pAdapter->beeping) { 489 pAdapter->beeping = 0; 490 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 491 } 492 #endif 493 494 } 495 else 496 { 497 pVDev = &(pAdapter->VDevices[channelIndex]); 498 failDevice(pVDev); 499 } 500 } 501 502 static int 503 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 504 { 505 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 506 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 507 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 508 MV_U32 udmaMode,pioMode; 509 510 KdPrint(("RR182x [%d]: start channel (%d)", pMvSataAdapter->adapterId, 511 channelNum)); 512 513 514 /* Software reset channel */ 515 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 516 { 517 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n", 518 pMvSataAdapter->adapterId, channelNum); 519 return -1; 520 } 521 522 /* Hardware reset channel */ 523 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 524 { 525 /* If failed, try again - this is when trying to hardreset a channel */ 526 /* when drive is just spinning up */ 527 StallExec(5000000); /* wait 5 sec before trying again */ 528 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 529 { 530 MV_ERROR("RR182x [%d,%d]: failed to perform Hard reset\n", 531 pMvSataAdapter->adapterId, channelNum); 532 return -1; 533 } 534 } 535 536 /* identify device*/ 537 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 538 { 539 MV_ERROR("RR182x [%d,%d]: failed to perform ATA Identify command\n" 540 , pMvSataAdapter->adapterId, channelNum); 541 return -1; 542 } 543 if (hptmv_parse_identify_results(pMvSataChannel)) 544 { 545 MV_ERROR("RR182x [%d,%d]: Error in parsing ATA Identify message\n" 546 , pMvSataAdapter->adapterId, channelNum); 547 return -1; 548 } 549 550 /* mvStorageDevATASetFeatures */ 551 /* Disable 8 bit PIO in case CFA enabled */ 552 if (pMvSataChannel->identifyDevice[86] & 4) 553 { 554 KdPrint(("RR182x [%d]: Disable 8 bit PIO (CFA enabled) \n", 555 pMvSataAdapter->adapterId)); 556 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 557 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 558 0, 0, 0) == MV_FALSE) 559 { 560 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures" 561 " failed\n", pMvSataAdapter->adapterId, channelNum); 562 return -1; 563 } 564 } 565 /* Write cache */ 566 #ifdef ENABLE_WRITE_CACHE 567 if (pMvSataChannel->identifyDevice[82] & 0x20) 568 { 569 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 570 { 571 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 572 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 573 0, 0, 0) == MV_FALSE) 574 { 575 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 576 pMvSataAdapter->adapterId, channelNum); 577 return -1; 578 } 579 } 580 KdPrint(("RR182x [%d]: channel %d, write cache enabled\n", 581 pMvSataAdapter->adapterId, channelNum)); 582 } 583 else 584 { 585 KdPrint(("RR182x [%d]: channel %d, write cache not supported\n", 586 pMvSataAdapter->adapterId, channelNum)); 587 } 588 #else /* disable write cache */ 589 { 590 if (pMvSataChannel->identifyDevice[85] & 0x20) 591 { 592 KdPrint(("RR182x [%d]: channel =%d, disable write cache\n", 593 pMvSataAdapter->adapterId, channelNum)); 594 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 595 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 596 0, 0, 0) == MV_FALSE) 597 { 598 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 599 pMvSataAdapter->adapterId, channelNum); 600 return -1; 601 } 602 } 603 KdPrint(("RR182x [%d]: channel=%d, write cache disabled\n", 604 pMvSataAdapter->adapterId, channelNum)); 605 } 606 #endif 607 608 /* Set transfer mode */ 609 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_SLOW\n", 610 pMvSataAdapter->adapterId)); 611 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 612 MV_ATA_SET_FEATURES_TRANSFER, 613 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 614 MV_FALSE) 615 { 616 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 617 pMvSataAdapter->adapterId, channelNum); 618 return -1; 619 } 620 621 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 622 { 623 pioMode = MV_ATA_TRANSFER_PIO_4; 624 } 625 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 626 { 627 pioMode = MV_ATA_TRANSFER_PIO_3; 628 } 629 else 630 { 631 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 632 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 633 } 634 635 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_4\n", 636 pMvSataAdapter->adapterId)); 637 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 638 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 639 MV_ATA_SET_FEATURES_TRANSFER, 640 pioMode, 0, 0, 0) == MV_FALSE) 641 { 642 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 643 pMvSataAdapter->adapterId, channelNum); 644 return -1; 645 } 646 647 udmaMode = MV_ATA_TRANSFER_UDMA_0; 648 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 649 { 650 udmaMode = MV_ATA_TRANSFER_UDMA_6; 651 } 652 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 653 { 654 udmaMode = MV_ATA_TRANSFER_UDMA_5; 655 } 656 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 657 { 658 udmaMode = MV_ATA_TRANSFER_UDMA_4; 659 } 660 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 661 { 662 udmaMode = MV_ATA_TRANSFER_UDMA_3; 663 } 664 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 665 { 666 udmaMode = MV_ATA_TRANSFER_UDMA_2; 667 } 668 669 KdPrint(("RR182x [%d] Set transfer mode XFER_UDMA_%d\n", 670 pMvSataAdapter->adapterId, udmaMode & 0xf)); 671 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 672 673 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 674 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 675 0, 0, 0) == MV_FALSE) 676 { 677 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 678 pMvSataAdapter->adapterId, channelNum); 679 return -1; 680 }*/ 681 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 682 return TRUE; 683 else 684 do 685 { 686 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 687 MV_ATA_SET_FEATURES_TRANSFER, 688 pChannelInfo->maxUltraDmaModeSupported, 689 0, 0, 0) == MV_FALSE) 690 { 691 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 692 { 693 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 694 { 695 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 696 pMvSataChannel->eDmaRegsOffset + 697 0x11c, /* command reg */ 698 MV_ATA_COMMAND_IDLE_IMMEDIATE); 699 mvMicroSecondsDelay(10000); 700 mvSataChannelHardReset(pMvSataAdapter, channelNum); 701 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 702 return FALSE; 703 } 704 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 705 return FALSE; 706 pChannelInfo->maxUltraDmaModeSupported--; 707 continue; 708 } 709 else return FALSE; 710 } 711 break; 712 }while (1); 713 714 /* Read look ahead */ 715 #ifdef ENABLE_READ_AHEAD 716 if (pMvSataChannel->identifyDevice[82] & 0x40) 717 { 718 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 719 { 720 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 721 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 722 0, 0) == MV_FALSE) 723 { 724 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 725 pMvSataAdapter->adapterId, channelNum); 726 return -1; 727 } 728 } 729 KdPrint(("RR182x [%d]: channel=%d, read look ahead enabled\n", 730 pMvSataAdapter->adapterId, channelNum)); 731 } 732 else 733 { 734 KdPrint(("RR182x [%d]: channel %d, Read Look Ahead not supported\n", 735 pMvSataAdapter->adapterId, channelNum)); 736 } 737 #else 738 { 739 if (pMvSataChannel->identifyDevice[86] & 0x20) 740 { 741 KdPrint(("RR182x [%d]:channel %d, disable read look ahead\n", 742 pMvSataAdapter->adapterId, channelNum)); 743 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 744 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 745 0, 0) == MV_FALSE) 746 { 747 MV_ERROR("RR182x [%d]:channel %d: ATA Set Features failed\n", 748 pMvSataAdapter->adapterId, channelNum); 749 return -1; 750 } 751 } 752 KdPrint(("RR182x [%d]:channel %d, read look ahead disabled\n", 753 pMvSataAdapter->adapterId, channelNum)); 754 } 755 #endif 756 757 758 { 759 KdPrint(("RR182x [%d]: channel %d config EDMA, Non Queued Mode\n", 760 pMvSataAdapter->adapterId, 761 channelNum)); 762 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 763 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 764 { 765 MV_ERROR("RR182x [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 766 pMvSataAdapter->adapterId, channelNum); 767 return -1; 768 } 769 } 770 /* Enable EDMA */ 771 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 772 { 773 MV_ERROR("RR182x [%d] Failed to enable DMA, channel=%d\n", 774 pMvSataAdapter->adapterId, channelNum); 775 return -1; 776 } 777 MV_ERROR("RR182x [%d,%d]: channel started successfully\n", 778 pMvSataAdapter->adapterId, channelNum); 779 780 #ifndef FOR_DEMO 781 set_fail_led(pMvSataAdapter, channelNum, 0); 782 #endif 783 return 0; 784 } 785 786 static void 787 hptmv_handle_event(void * data, int flag) 788 { 789 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 790 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 791 MV_U8 channelIndex; 792 793 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 794 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 795 { 796 switch(pAdapter->sataEvents[channelIndex]) 797 { 798 case SATA_EVENT_CHANNEL_CONNECTED: 799 /* Handle only connects */ 800 if (flag == 1) 801 break; 802 KdPrint(("RR182x [%d,%d]: new device connected\n", 803 pMvSataAdapter->adapterId, channelIndex)); 804 hptmv_init_channel(pAdapter, channelIndex); 805 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 806 { 807 MV_ERROR("RR182x [%d,%d] Failed to configure\n", 808 pMvSataAdapter->adapterId, channelIndex); 809 hptmv_free_channel(pAdapter, channelIndex); 810 } 811 else 812 { 813 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 814 if (start_channel( pAdapter, channelIndex)) 815 { 816 MV_ERROR("RR182x [%d,%d]Failed to start channel\n", 817 pMvSataAdapter->adapterId, channelIndex); 818 hptmv_free_channel(pAdapter, channelIndex); 819 } 820 else 821 { 822 device_change(pAdapter, channelIndex, TRUE); 823 } 824 } 825 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 826 break; 827 828 case SATA_EVENT_CHANNEL_DISCONNECTED: 829 /* Handle only disconnects */ 830 if (flag == 0) 831 break; 832 KdPrint(("RR182x [%d,%d]: device disconnected\n", 833 pMvSataAdapter->adapterId, channelIndex)); 834 /* Flush pending commands */ 835 if(pMvSataAdapter->sataChannel[channelIndex]) 836 { 837 _VBUS_INST(&pAdapter->VBus) 838 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 839 MV_FLUSH_TYPE_CALLBACK); 840 CheckPendingCall(_VBUS_P0); 841 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 842 hptmv_free_channel(pAdapter, channelIndex); 843 pMvSataAdapter->sataChannel[channelIndex] = NULL; 844 KdPrint(("RR182x [%d,%d]: channel removed\n", 845 pMvSataAdapter->adapterId, channelIndex)); 846 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 847 Check_Idle_Call(pAdapter); 848 } 849 else 850 { 851 KdPrint(("RR182x [%d,%d]: channel already removed!!\n", 852 pMvSataAdapter->adapterId, channelIndex)); 853 } 854 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 855 break; 856 857 case SATA_EVENT_NO_CHANGE: 858 break; 859 860 default: 861 break; 862 } 863 } 864 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 865 } 866 867 #define EVENT_CONNECT 1 868 #define EVENT_DISCONNECT 0 869 870 static void 871 hptmv_handle_event_connect(void *data) 872 { 873 hptmv_handle_event (data, 0); 874 } 875 876 static void 877 hptmv_handle_event_disconnect(void *data) 878 { 879 hptmv_handle_event (data, 1); 880 } 881 882 static MV_BOOLEAN 883 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 884 MV_U32 param1, MV_U32 param2) 885 { 886 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 887 888 switch (eventType) 889 { 890 case MV_EVENT_TYPE_SATA_CABLE: 891 { 892 MV_U8 channel = param2; 893 894 if (param1 == EVENT_CONNECT) 895 { 896 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 897 KdPrint(("RR182x [%d,%d]: device connected event received\n", 898 pMvSataAdapter->adapterId, channel)); 899 /* Delete previous timers (if multiple drives connected in the same time */ 900 pAdapter->event_timer_connect = timeout(hptmv_handle_event_connect, pAdapter, 10*hz); 901 } 902 else if (param1 == EVENT_DISCONNECT) 903 { 904 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 905 KdPrint(("RR182x [%d,%d]: device disconnected event received \n", 906 pMvSataAdapter->adapterId, channel)); 907 device_change(pAdapter, channel, FALSE); 908 /* Delete previous timers (if multiple drives disconnected in the same time */ 909 /*pAdapter->event_timer_disconnect = timeout(hptmv_handle_event_disconnect, pAdapter, 10*hz); */ 910 /*It is not necessary to wait, handle it directly*/ 911 hptmv_handle_event_disconnect(pAdapter); 912 } 913 else 914 { 915 916 MV_ERROR("RR182x: illigal value for param1(%d) at " 917 "connect/disconect event, host=%d\n", param1, 918 pMvSataAdapter->adapterId ); 919 920 } 921 } 922 break; 923 case MV_EVENT_TYPE_ADAPTER_ERROR: 924 KdPrint(("RR182x: DEVICE error event received, pci cause " 925 "reg=%x, don't how to handle this\n", param1)); 926 return MV_TRUE; 927 default: 928 MV_ERROR("RR182x[%d]: unknown event type (%d)\n", 929 pMvSataAdapter->adapterId, eventType); 930 return MV_FALSE; 931 } 932 return MV_TRUE; 933 } 934 935 static int 936 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 937 { 938 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 939 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 940 if (pAdapter->requestsArrayBaseAddr == NULL) 941 { 942 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA request" 943 " queues\n", pAdapter->mvSataAdapter.adapterId); 944 return -1; 945 } 946 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 947 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 948 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 949 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 950 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 951 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 952 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 953 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 954 955 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 956 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 957 { 958 MV_ERROR("RR182x[%d]: Error in Request Quueues Alignment\n", 959 pAdapter->mvSataAdapter.adapterId); 960 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 961 return -1; 962 } 963 /* response queues */ 964 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 965 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 966 if (pAdapter->responsesArrayBaseAddr == NULL) 967 { 968 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA response" 969 " queues\n", pAdapter->mvSataAdapter.adapterId); 970 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 971 return -1; 972 } 973 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 974 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 975 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 976 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 977 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 978 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 979 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 980 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 981 982 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 983 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 984 { 985 MV_ERROR("RR182x[%d]: Error in Response Quueues Alignment\n", 986 pAdapter->mvSataAdapter.adapterId); 987 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 988 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 989 return -1; 990 } 991 return 0; 992 } 993 994 static void 995 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 996 { 997 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 998 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 999 } 1000 1001 static PVOID 1002 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 1003 { 1004 PVOID ret; 1005 if (pAdapter->pFreePRDLink) { 1006 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 1007 ret = pAdapter->pFreePRDLink; 1008 pAdapter->pFreePRDLink = *(void**)ret; 1009 return ret; 1010 } 1011 return NULL; 1012 } 1013 1014 static void 1015 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 1016 { 1017 *(void**)PRDTable = pAdapter->pFreePRDLink; 1018 pAdapter->pFreePRDLink = PRDTable; 1019 } 1020 1021 extern PVDevice fGetFirstChild(PVDevice pLogical); 1022 extern void fResetBootMark(PVDevice pLogical); 1023 static void 1024 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 1025 { 1026 PVDevice pPhysical, pLogical; 1027 PVBus pVBus; 1028 int i,j; 1029 1030 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 1031 pPhysical = &(pAdapter->VDevices[i]); 1032 pLogical = pPhysical; 1033 while (pLogical->pParent) pLogical = pLogical->pParent; 1034 if (pLogical->vf_online==0) { 1035 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 1036 continue; 1037 } 1038 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1039 continue; 1040 1041 pVBus = &pAdapter->VBus; 1042 if(pVBus) 1043 { 1044 j=0; 1045 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1046 if(j<MAX_VDEVICE_PER_VBUS){ 1047 pVBus->pVDevice[j] = pLogical; 1048 pLogical->pVBus = pVBus; 1049 1050 if (j>0 && pLogical->vf_bootmark) { 1051 if (pVBus->pVDevice[0]->vf_bootmark) { 1052 fResetBootMark(pLogical); 1053 } 1054 else { 1055 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1056 pVBus->pVDevice[0] = pLogical; 1057 } 1058 } 1059 } 1060 } 1061 } 1062 } 1063 1064 PVDevice 1065 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1066 { 1067 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1068 ULONG capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1069 ULONG thiscap, maxcap = MAX_LBA_T; 1070 PVDevice pVDevice, pFind = NULL; 1071 int i; 1072 1073 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1074 { 1075 pVDevice = &pAdapter->VDevices[i]; 1076 if(!pVDevice) 1077 continue; 1078 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1079 /* find the smallest usable spare disk */ 1080 if (pVDevice->VDeviceType==VD_SPARE && 1081 pVDevice->u.disk.df_on_line && 1082 thiscap < maxcap && 1083 thiscap >= capacity) 1084 { 1085 maxcap = pVDevice->VDeviceCapacity; 1086 pFind = pVDevice; 1087 } 1088 } 1089 return pFind; 1090 } 1091 1092 /****************************************************************** 1093 * IO ATA Command 1094 *******************************************************************/ 1095 int HPTLIBAPI 1096 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1097 { 1098 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1099 } 1100 1101 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1102 { 1103 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1104 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1105 MV_U8 channelIndex = pSataChannel->channelNumber; 1106 UCHAR mvMode; 1107 /* 508x don't use MW-DMA? */ 1108 if (NewMode>4 && NewMode<8) NewMode = 4; 1109 pDev->bDeModeSetting = NewMode; 1110 if (NewMode<=4) 1111 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1112 else 1113 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1114 1115 /*To fix 88i8030 bug*/ 1116 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1117 mvMode = MV_ATA_TRANSFER_UDMA_0; 1118 1119 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1120 /* Flush pending commands */ 1121 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1122 1123 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1124 MV_ATA_SET_FEATURES_TRANSFER, 1125 mvMode, 0, 0, 0) == MV_FALSE) 1126 { 1127 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1128 } 1129 /* Enable EDMA */ 1130 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1131 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1132 } 1133 1134 #ifdef SUPPORT_ARRAY 1135 #define IdeRegisterVDevice fCheckArray 1136 #else 1137 void 1138 IdeRegisterVDevice(PDevice pDev) 1139 { 1140 PVDevice pVDev = Map2pVDevice(pDev); 1141 1142 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1143 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1144 pVDev->vf_online = 1; 1145 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1146 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1147 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1148 } 1149 #endif 1150 1151 static __inline PBUS_DMAMAP 1152 dmamap_get(struct IALAdapter * pAdapter) 1153 { 1154 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1155 if (p) 1156 pAdapter->pbus_dmamap_list = p-> next; 1157 return p; 1158 } 1159 1160 static __inline void 1161 dmamap_put(PBUS_DMAMAP p) 1162 { 1163 p->next = p->pAdapter->pbus_dmamap_list; 1164 p->pAdapter->pbus_dmamap_list = p; 1165 } 1166 1167 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/ 1168 #if __FreeBSD_version >= 500000 1169 static void hpt_init(void *dummy) 1170 { 1171 mtx_init(&driver_lock, "hptlock", NULL, MTX_DEF); 1172 } 1173 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL); 1174 #endif 1175 1176 static int num_adapters = 0; 1177 static int 1178 init_adapter(IAL_ADAPTER_T *pAdapter) 1179 { 1180 PVBus _vbus_p = &pAdapter->VBus; 1181 MV_SATA_ADAPTER *pMvSataAdapter; 1182 int i, channel, rid; 1183 1184 PVDevice pVDev; 1185 1186 pAdapter->next = 0; 1187 1188 if(gIal_Adapter == 0){ 1189 gIal_Adapter = pAdapter; 1190 pCurAdapter = gIal_Adapter; 1191 } 1192 else { 1193 pCurAdapter->next = pAdapter; 1194 pCurAdapter = pAdapter; 1195 } 1196 1197 pAdapter->outstandingCommands = 0; 1198 1199 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1200 _vbus_p->OsExt = (void *)pAdapter; 1201 pMvSataAdapter->IALData = pAdapter; 1202 1203 if (bus_dma_tag_create(NULL,/* parent */ 1204 4, /* alignment */ 1205 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1206 BUS_SPACE_MAXADDR, /* lowaddr */ 1207 BUS_SPACE_MAXADDR, /* highaddr */ 1208 NULL, NULL, /* filter, filterarg */ 1209 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1210 MAX_SG_DESCRIPTORS, /* nsegments */ 1211 0x10000, /* maxsegsize */ 1212 BUS_DMA_WAITOK, /* flags */ 1213 #if __FreeBSD_version>502000 1214 busdma_lock_mutex, /* lockfunc */ 1215 &driver_lock, /* lockfuncarg */ 1216 #endif 1217 &pAdapter->io_dma_parent /* tag */)) 1218 { 1219 return ENXIO;; 1220 } 1221 1222 1223 if (hptmv_allocate_edma_queues(pAdapter)) 1224 { 1225 MV_ERROR("RR182x: Failed to allocate memory for EDMA queues\n"); 1226 return ENOMEM; 1227 } 1228 1229 /* also map EPROM address */ 1230 rid = 0x10; 1231 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid, 1232 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE)) 1233 || 1234 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1235 { 1236 MV_ERROR("RR182x: Failed to remap memory space\n"); 1237 hptmv_free_edma_queues(pAdapter); 1238 return ENXIO; 1239 } 1240 else 1241 { 1242 KdPrint(("RR182x: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1243 } 1244 1245 pMvSataAdapter->adapterId = num_adapters++; 1246 /* get the revision ID */ 1247 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1248 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1249 1250 /* init RR182x */ 1251 pMvSataAdapter->intCoalThre[0]= 1; 1252 pMvSataAdapter->intCoalThre[1]= 1; 1253 pMvSataAdapter->intTimeThre[0] = 1; 1254 pMvSataAdapter->intTimeThre[1] = 1; 1255 pMvSataAdapter->pciCommand = 0x0107E371; 1256 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1257 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1258 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1259 1260 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1261 { 1262 MV_ERROR("RR182x[%d]: core failed to initialize the adapter\n", 1263 pMvSataAdapter->adapterId); 1264 unregister: 1265 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1266 hptmv_free_edma_queues(pAdapter); 1267 return ENXIO; 1268 } 1269 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1270 1271 #ifndef FOR_DEMO 1272 set_fail_leds(pMvSataAdapter, 0); 1273 #endif 1274 1275 /* setup command blocks */ 1276 KdPrint(("Allocate command blocks\n")); 1277 _vbus_(pFreeCommands) = 0; 1278 pAdapter->pCommandBlocks = 1279 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1280 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1281 if (!pAdapter->pCommandBlocks) { 1282 MV_ERROR("insufficient memory\n"); 1283 goto unregister; 1284 } 1285 1286 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1287 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1288 } 1289 1290 /*Set up the bus_dmamap*/ 1291 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1292 if(!pAdapter->pbus_dmamap) { 1293 MV_ERROR("insufficient memory\n"); 1294 free(pAdapter->pCommandBlocks, M_DEVBUF); 1295 goto unregister; 1296 } 1297 1298 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1299 pAdapter->pbus_dmamap_list = 0; 1300 for (i=0; i < MAX_QUEUE_COMM; i++) { 1301 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1302 pmap->pAdapter = pAdapter; 1303 dmamap_put(pmap); 1304 1305 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1306 MV_ERROR("Can not allocate dma map\n"); 1307 free(pAdapter->pCommandBlocks, M_DEVBUF); 1308 free(pAdapter->pbus_dmamap, M_DEVBUF); 1309 goto unregister; 1310 } 1311 } 1312 /* setup PRD Tables */ 1313 KdPrint(("Allocate PRD Tables\n")); 1314 pAdapter->pFreePRDLink = 0; 1315 1316 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1317 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1318 1319 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1320 if (!pAdapter->prdTableAddr) { 1321 MV_ERROR("insufficient PRD Tables\n"); 1322 goto unregister; 1323 } 1324 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1325 { 1326 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1327 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1328 { 1329 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1330 FreePRDTable(pAdapter, PRDTable); 1331 PRDTable += PRD_ENTRIES_SIZE; 1332 } 1333 } 1334 1335 /* enable the adapter interrupts */ 1336 1337 /* configure and start the connected channels*/ 1338 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1339 { 1340 pAdapter->mvChannel[channel].online = MV_FALSE; 1341 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1342 == MV_TRUE) 1343 { 1344 KdPrint(("RR182x[%d]: channel %d is connected\n", 1345 pMvSataAdapter->adapterId, channel)); 1346 1347 if (hptmv_init_channel(pAdapter, channel) == 0) 1348 { 1349 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1350 { 1351 MV_ERROR("RR182x[%d]: Failed to configure channel" 1352 " %d\n",pMvSataAdapter->adapterId, channel); 1353 hptmv_free_channel(pAdapter, channel); 1354 } 1355 else 1356 { 1357 if (start_channel(pAdapter, channel)) 1358 { 1359 MV_ERROR("RR182x[%d]: Failed to start channel," 1360 " channel=%d\n",pMvSataAdapter->adapterId, 1361 channel); 1362 hptmv_free_channel(pAdapter, channel); 1363 } 1364 pAdapter->mvChannel[channel].online = MV_TRUE; 1365 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1366 channel, 1367 MV_TRUE);*/ 1368 } 1369 } 1370 } 1371 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1372 pAdapter->mvChannel[channel].online, channel)); 1373 } 1374 1375 #ifdef SUPPORT_ARRAY 1376 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1377 pVDev = ArrayTables(i); 1378 mArFreeArrayTable(pVDev); 1379 } 1380 #endif 1381 1382 KdPrint(("Initialize Devices\n")); 1383 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1384 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1385 if (pMvSataChannel) { 1386 init_vdev_params(pAdapter, channel); 1387 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1388 } 1389 } 1390 #ifdef SUPPORT_ARRAY 1391 CheckArrayCritical(_VBUS_P0); 1392 #endif 1393 _vbus_p->nInstances = 1; 1394 fRegisterVdevice(pAdapter); 1395 1396 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1397 pVDev = _vbus_p->pVDevice[channel]; 1398 if (pVDev && pVDev->vf_online) 1399 fCheckBootable(pVDev); 1400 } 1401 1402 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1403 init_raid5_memory(_VBUS_P0); 1404 _vbus_(r5).enable_write_back = 1; 1405 printf("RR182x: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1406 #endif 1407 1408 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1409 return 0; 1410 } 1411 1412 int 1413 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1414 { 1415 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1416 1417 mvSataDisableChannelDma(pMvSataAdapter, channel); 1418 /* Flush pending commands */ 1419 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1420 1421 /* Software reset channel */ 1422 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1423 { 1424 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n", 1425 pMvSataAdapter->adapterId, channel); 1426 hptmv_free_channel(pAdapter, channel); 1427 return -1; 1428 } 1429 1430 /* Hardware reset channel */ 1431 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1432 { 1433 MV_ERROR("RR182x [%d,%d] Failed to Hard reser the SATA channel\n", 1434 pMvSataAdapter->adapterId, channel); 1435 hptmv_free_channel(pAdapter, channel); 1436 return -1; 1437 } 1438 1439 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1440 { 1441 MV_ERROR("RR182x [%d,%d] Failed to Connect Device\n", 1442 pMvSataAdapter->adapterId, channel); 1443 hptmv_free_channel(pAdapter, channel); 1444 return -1; 1445 }else 1446 { 1447 MV_ERROR("channel %d: perform recalibrate command", channel); 1448 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1449 MV_NON_UDMA_PROTOCOL_NON_DATA, 1450 MV_FALSE, 1451 NULL, /* pBuffer*/ 1452 0, /* count */ 1453 0, /*features*/ 1454 /* sectorCount */ 1455 0, 1456 0, /* lbaLow */ 1457 0, /* lbaMid */ 1458 /* lbaHigh */ 1459 0, 1460 0, /* device */ 1461 /* command */ 1462 0x10)) 1463 MV_ERROR("channel %d: recalibrate failed", channel); 1464 1465 /* Set transfer mode */ 1466 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1467 MV_ATA_SET_FEATURES_TRANSFER, 1468 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1469 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1470 MV_ATA_SET_FEATURES_TRANSFER, 1471 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1472 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1473 MV_ATA_SET_FEATURES_TRANSFER, 1474 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1475 { 1476 MV_ERROR("channel %d: Set Features failed", channel); 1477 hptmv_free_channel(pAdapter, channel); 1478 return -1; 1479 } 1480 /* Enable EDMA */ 1481 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1482 { 1483 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1484 hptmv_free_channel(pAdapter, channel); 1485 return -1; 1486 } 1487 } 1488 return 0; 1489 } 1490 1491 static int 1492 fResetActiveCommands(PVBus _vbus_p) 1493 { 1494 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1495 MV_U8 channel; 1496 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1497 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1498 MvSataResetChannel(pMvSataAdapter,channel); 1499 } 1500 return 0; 1501 } 1502 1503 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1504 { 1505 UINT cont; 1506 ULONG ticks = 0; 1507 MV_U8 channel; 1508 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1509 MV_SATA_CHANNEL *pMvSataChannel; 1510 1511 do { 1512 check_cmds: 1513 cont = 0; 1514 CheckPendingCall(_VBUS_P0); 1515 #ifdef _RAID5N_ 1516 dataxfer_poll(); 1517 xor_poll(); 1518 #endif 1519 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1520 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1521 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1522 { 1523 while (pMvSataChannel->outstandingCommands) { 1524 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1525 StallExec(1000); 1526 if (ticks++ > 3000) { 1527 MvSataResetChannel(pMvSataAdapter,channel); 1528 goto check_cmds; 1529 } 1530 } 1531 else 1532 ticks = 0; 1533 } 1534 cont = 1; 1535 } 1536 } 1537 } while (cont); 1538 } 1539 1540 void 1541 fResetVBus(_VBUS_ARG0) 1542 { 1543 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1544 1545 /* some commands may already finished. */ 1546 CheckPendingCall(_VBUS_P0); 1547 1548 fResetActiveCommands(_vbus_p); 1549 /* 1550 * the other pending commands may still be finished successfully. 1551 */ 1552 fCompleteAllCommandsSynchronously(_vbus_p); 1553 1554 /* Now there should be no pending commands. No more action needed. */ 1555 CheckIdleCall(_VBUS_P0); 1556 1557 KdPrint(("fMvResetBus() done")); 1558 } 1559 1560 /*No rescan function*/ 1561 void 1562 fRescanAllDevice(_VBUS_ARG0) 1563 { 1564 } 1565 1566 static MV_BOOLEAN 1567 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1568 MV_U8 channelNum, 1569 MV_COMPLETION_TYPE comp_type, 1570 MV_VOID_PTR commandId, 1571 MV_U16 responseFlags, 1572 MV_U32 timeStamp, 1573 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1574 { 1575 PCommand pCmd = (PCommand) commandId; 1576 _VBUS_INST(pCmd->pVDevice->pVBus) 1577 1578 if (pCmd->uScratch.sata_param.prdAddr) 1579 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1580 1581 switch (comp_type) 1582 { 1583 case MV_COMPLETION_TYPE_NORMAL: 1584 pCmd->Result = RETURN_SUCCESS; 1585 break; 1586 case MV_COMPLETION_TYPE_ABORT: 1587 pCmd->Result = RETURN_BUS_RESET; 1588 break; 1589 case MV_COMPLETION_TYPE_ERROR: 1590 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1591 pMvSataAdapter->adapterId, channelNum, responseFlags); 1592 1593 if (responseFlags & 4) { 1594 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1595 " LBA high %x, device %x, status %x\n", 1596 registerStruct->errorRegister, 1597 registerStruct->sectorCountRegister, 1598 registerStruct->lbaLowRegister, 1599 registerStruct->lbaMidRegister, 1600 registerStruct->lbaHighRegister, 1601 registerStruct->deviceRegister, 1602 registerStruct->statusRegister); 1603 } 1604 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1605 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1606 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1607 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1608 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1609 pCmd->pVDevice->u.disk.QueueLength--; 1610 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1611 return TRUE; 1612 1613 default: 1614 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1615 return MV_FALSE; 1616 } 1617 1618 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1619 pCmd->uScratch.sata_param.cmd_priv --; 1620 return TRUE; 1621 } 1622 pCmd->pVDevice->u.disk.QueueLength--; 1623 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1624 return TRUE; 1625 } 1626 1627 void 1628 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1629 { 1630 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1631 MV_SATA_ADAPTER *pMvSataAdapter; 1632 MV_SATA_CHANNEL *pMvSataChannel; 1633 PVDevice pVDevice = pCmd->pVDevice; 1634 PDevice pDevice = &pVDevice->u.disk; 1635 ULONG Lba = pCmd->uCmd.Ide.Lba; 1636 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1637 1638 MV_QUEUE_COMMAND_RESULT result; 1639 MV_QUEUE_COMMAND_INFO commandInfo; 1640 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1641 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1642 1643 MV_BOOLEAN is48bit = MV_FALSE; 1644 MV_U8 channel; 1645 int i=0; 1646 1647 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1648 1649 if (!pDevice->df_on_line) { 1650 MV_ERROR("Device is offline"); 1651 pCmd->Result = RETURN_BAD_DEVICE; 1652 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1653 return; 1654 } 1655 1656 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1657 pMvSataChannel = pDevice->mv; 1658 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1659 channel = pMvSataChannel->channelNumber; 1660 1661 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1662 Lba += pDevice->dDeHiddenLba; 1663 /* check LBA */ 1664 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1665 pCmd->Result = RETURN_INVALID_REQUEST; 1666 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1667 return; 1668 } 1669 1670 if(Lba & 0xF0000000){ 1671 is48bit = MV_TRUE; 1672 } 1673 1674 switch (pCmd->uCmd.Ide.Command) 1675 { 1676 case IDE_COMMAND_READ: 1677 case IDE_COMMAND_WRITE: 1678 if (pDevice->bDeModeSetting<8) goto pio; 1679 1680 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1681 pUdmaParams->isEXT = is48bit; 1682 pUdmaParams->numOfSectors = nSector; 1683 pUdmaParams->lowLBAAddress = Lba; 1684 pUdmaParams->highLBAAddress = 0; 1685 pUdmaParams->prdHighAddr = 0; 1686 pUdmaParams->callBack = CommandCompletionCB; 1687 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1688 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1689 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1690 else 1691 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1692 1693 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1694 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1695 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1696 } 1697 else { 1698 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1699 pio: 1700 mvSataDisableChannelDma(pMvSataAdapter, channel); 1701 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1702 1703 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1704 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1705 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1706 } 1707 else { 1708 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1709 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1710 goto finish_cmd; 1711 } 1712 } 1713 1714 do { 1715 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1716 ULONG_PTR addr = tmpSg->dSgAddress; 1717 if (size & 0x1ff) { 1718 pCmd->Result = RETURN_INVALID_REQUEST; 1719 goto finish_cmd; 1720 } 1721 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1722 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1723 is48bit, 1724 (MV_U16_PTR)addr, 1725 size >> 1, /* count */ 1726 0, /* features N/A */ 1727 (MV_U16)(size>>9), /*sector count*/ 1728 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1729 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1730 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1731 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1732 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1733 )==MV_FALSE) 1734 { 1735 pCmd->Result = RETURN_IDE_ERROR; 1736 goto finish_cmd; 1737 } 1738 Lba += size>>9; 1739 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1740 } 1741 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1742 pCmd->Result = RETURN_SUCCESS; 1743 finish_cmd: 1744 mvSataEnableChannelDma(pMvSataAdapter,channel); 1745 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1746 return; 1747 } 1748 } 1749 1750 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1751 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1752 if (!pPRDTable) { 1753 pCmd->Result = RETURN_DEVICE_BUSY; 1754 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1755 HPT_ASSERT(0); 1756 return; 1757 } 1758 1759 do{ 1760 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1761 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1762 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1763 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1764 pPRDTable[i].reserved = 0; 1765 i++; 1766 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1767 1768 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1769 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1770 pUdmaParams->numOfSectors = 0; 1771 } 1772 1773 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1774 1775 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1776 1777 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1778 { 1779 queue_failed: 1780 switch (result) 1781 { 1782 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1783 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1784 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1785 pCmd->Result = RETURN_IDE_ERROR; 1786 break; 1787 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1788 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1789 " disabled adapter %d channel %d\n", 1790 pMvSataAdapter->adapterId, channel); 1791 mvSataEnableChannelDma(pMvSataAdapter,channel); 1792 pCmd->Result = RETURN_IDE_ERROR; 1793 break; 1794 case MV_QUEUE_COMMAND_RESULT_FULL: 1795 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1796 " Full adapter %d channel %d\n", 1797 pMvSataAdapter->adapterId, channel); 1798 pCmd->Result = RETURN_DEVICE_BUSY; 1799 break; 1800 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1801 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1802 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1803 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1804 pCmd->Result = RETURN_IDE_ERROR; 1805 break; 1806 default: 1807 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1808 " command\n", result); 1809 pCmd->Result = RETURN_IDE_ERROR; 1810 } 1811 if(pPRDTable) 1812 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1813 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1814 } 1815 pDevice->QueueLength++; 1816 return; 1817 1818 case IDE_COMMAND_VERIFY: 1819 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1820 pNoUdmaParams->bufPtr = NULL; 1821 pNoUdmaParams->callBack = CommandCompletionCB; 1822 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1823 pNoUdmaParams->count = 0; 1824 pNoUdmaParams->features = 0; 1825 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1826 1827 pCmd->uScratch.sata_param.cmd_priv = 1; 1828 if (pMvSataChannel->lba48Address == MV_TRUE){ 1829 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1830 pNoUdmaParams->isEXT = MV_TRUE; 1831 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1832 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1833 pNoUdmaParams->lbaLow = 1834 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1835 pNoUdmaParams->sectorCount = nSector; 1836 pNoUdmaParams->device = 0x40; 1837 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1838 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1839 goto queue_failed; 1840 } 1841 return; 1842 } 1843 else{ 1844 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1845 pNoUdmaParams->isEXT = MV_FALSE; 1846 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1847 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1848 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1849 pNoUdmaParams->sectorCount = 0xff & nSector; 1850 pNoUdmaParams->device = (MV_U8)(0x40 | 1851 ((Lba & 0xf000000) >> 24)); 1852 pNoUdmaParams->callBack = CommandCompletionCB; 1853 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1854 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1855 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1856 goto queue_failed; 1857 } 1858 } 1859 break; 1860 default: 1861 pCmd->Result = RETURN_INVALID_REQUEST; 1862 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1863 break; 1864 } 1865 } 1866 1867 /********************************************************** 1868 * 1869 * Probe the hostadapter. 1870 * 1871 **********************************************************/ 1872 static int 1873 hpt_probe(device_t dev) 1874 { 1875 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1876 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1877 #ifdef FOR_DEMO 1878 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1879 #endif 1880 )) 1881 { 1882 KdPrintI((CONTROLLER_NAME " found\n")); 1883 device_set_desc(dev, CONTROLLER_NAME); 1884 return 0; 1885 } 1886 else 1887 return(ENXIO); 1888 } 1889 1890 /*********************************************************** 1891 * 1892 * Auto configuration: attach and init a host adapter. 1893 * 1894 ***********************************************************/ 1895 static int 1896 hpt_attach(device_t dev) 1897 { 1898 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1899 int rid; 1900 union ccb *ccb; 1901 struct cam_devq *devq; 1902 struct cam_sim *hpt_vsim; 1903 1904 printf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1905 1906 if (!pAdapter) 1907 { 1908 pAdapter = (IAL_ADAPTER_T *)malloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT); 1909 #if __FreeBSD_version > 410000 1910 device_set_softc(dev, (void *)pAdapter); 1911 #else 1912 device_set_driver(dev, (driver_t *)pAdapter); 1913 #endif 1914 } 1915 1916 if (!pAdapter) return (ENOMEM); 1917 bzero(pAdapter, sizeof(IAL_ADAPTER_T)); 1918 1919 pAdapter->hpt_dev = dev; 1920 1921 rid = init_adapter(pAdapter); 1922 if (rid) 1923 return rid; 1924 1925 rid = 0; 1926 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) 1927 { 1928 hpt_printk(("can't allocate interrupt\n")); 1929 return(ENXIO); 1930 } 1931 1932 if(bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 1933 { 1934 hpt_printk(("can't set up interrupt\n")); 1935 free(pAdapter, M_DEVBUF); 1936 return(ENXIO); 1937 } 1938 1939 1940 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL) 1941 { 1942 bzero(ccb, sizeof(*ccb)); 1943 ccb->ccb_h.pinfo.priority = 1; 1944 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 1945 } 1946 else 1947 { 1948 return ENOMEM; 1949 } 1950 /* 1951 * Create the device queue for our SIM(s). 1952 */ 1953 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 1954 { 1955 KdPrint(("ENXIO\n")); 1956 return ENOMEM; 1957 } 1958 1959 /* 1960 * Construct our SIM entry 1961 */ 1962 if ((hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 1963 pAdapter, device_get_unit(pAdapter->hpt_dev), /*untagged*/1, /*tagged*/8, devq)) == NULL) { 1964 cam_simq_free(devq); 1965 return ENOMEM; 1966 } 1967 1968 if(xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) 1969 { 1970 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 1971 hpt_vsim = NULL; 1972 return ENXIO; 1973 } 1974 1975 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 1976 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 1977 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 1978 { 1979 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 1980 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 1981 hpt_vsim = NULL; 1982 return ENXIO; 1983 } 1984 1985 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 1986 ccb->ccb_h.func_code = XPT_SASYNC_CB; 1987 ccb->csa.event_enable = AC_LOST_DEVICE; 1988 ccb->csa.callback = hpt_async; 1989 ccb->csa.callback_arg = hpt_vsim; 1990 xpt_action((union ccb *)ccb); 1991 free(ccb, M_DEVBUF); 1992 1993 /* Register shutdown handler, and start the work thread. */ 1994 if (device_get_unit(dev) == 0) { 1995 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_final, 1996 hpt_shutdown, dev, SHUTDOWN_PRI_DEFAULT); 1997 if (pAdapter->eh) 1998 launch_worker_thread(); 1999 else 2000 hpt_printk(("shutdown event registration failed\n")); 2001 } 2002 2003 return 0; 2004 } 2005 2006 static int 2007 hpt_detach(device_t dev) 2008 { 2009 return (EBUSY); 2010 } 2011 2012 2013 /*************************************************************** 2014 * The poll function is used to simulate the interrupt when 2015 * the interrupt subsystem is not functioning. 2016 * 2017 ***************************************************************/ 2018 static void 2019 hpt_poll(struct cam_sim *sim) 2020 { 2021 hpt_intr((void *)cam_sim_softc(sim)); 2022 } 2023 2024 /**************************************************************** 2025 * Name: hpt_intr 2026 * Description: Interrupt handler. 2027 ****************************************************************/ 2028 static void 2029 hpt_intr(void *arg) 2030 { 2031 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg; 2032 intrmask_t oldspl = lock_driver(); 2033 2034 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2035 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2036 { 2037 _VBUS_INST(&pAdapter->VBus) 2038 CheckPendingCall(_VBUS_P0); 2039 } 2040 2041 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2042 unlock_driver(oldspl); 2043 } 2044 2045 /********************************************************** 2046 * Asynchronous Events 2047 *********************************************************/ 2048 #if (!defined(UNREFERENCED_PARAMETER)) 2049 #define UNREFERENCED_PARAMETER(x) (void)(x) 2050 #endif 2051 2052 static void 2053 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2054 void * arg) 2055 { 2056 /* debug XXXX */ 2057 panic("Here"); 2058 UNREFERENCED_PARAMETER(callback_arg); 2059 UNREFERENCED_PARAMETER(code); 2060 UNREFERENCED_PARAMETER(path); 2061 UNREFERENCED_PARAMETER(arg); 2062 2063 } 2064 2065 static void 2066 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2067 { 2068 int i; 2069 2070 hpt_printk(("flush all devices\n")); 2071 2072 /* flush all devices */ 2073 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2074 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2075 if(pVDev) fFlushVDev(pVDev); 2076 } 2077 } 2078 2079 static int 2080 hpt_shutdown(device_t dev) 2081 { 2082 IAL_ADAPTER_T *pAdapter; 2083 2084 pAdapter = device_get_softc(dev); 2085 if (pAdapter == NULL) 2086 return (EINVAL); 2087 2088 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2089 FlushAdapter(pAdapter); 2090 /* give the flush some time to happen, 2091 *otherwise "shutdown -p now" will make file system corrupted */ 2092 DELAY(1000 * 1000 * 5); 2093 return 0; 2094 } 2095 2096 void 2097 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2098 { 2099 _VBUS_INST(&pAdapter->VBus) 2100 2101 if (mWaitingForIdle(_VBUS_P0)) { 2102 CheckIdleCall(_VBUS_P0); 2103 #ifdef SUPPORT_ARRAY 2104 { 2105 int i; 2106 PVDevice pArray; 2107 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2108 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2109 continue; 2110 else if (pArray->u.array.rf_auto_rebuild) { 2111 KdPrint(("auto rebuild.\n")); 2112 pArray->u.array.rf_auto_rebuild = 0; 2113 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2114 } 2115 } 2116 } 2117 #endif 2118 } 2119 /* launch the awaiting commands blocked by mWaitingForIdle */ 2120 while(pAdapter->pending_Q!= NULL) 2121 { 2122 _VBUS_INST(&pAdapter->VBus) 2123 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2124 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2125 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2126 } 2127 } 2128 2129 static void 2130 ccb_done(union ccb *ccb) 2131 { 2132 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2133 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2134 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2135 2136 dmamap_put(pmap); 2137 xpt_done(ccb); 2138 2139 pAdapter->outstandingCommands--; 2140 2141 if (pAdapter->outstandingCommands == 0) 2142 { 2143 if(DPC_Request_Nums == 0) 2144 Check_Idle_Call(pAdapter); 2145 } 2146 } 2147 2148 /**************************************************************** 2149 * Name: hpt_action 2150 * Description: Process a queued command from the CAM layer. 2151 * Parameters: sim - Pointer to SIM object 2152 * ccb - Pointer to SCSI command structure. 2153 ****************************************************************/ 2154 2155 void 2156 hpt_action(struct cam_sim *sim, union ccb *ccb) 2157 { 2158 intrmask_t oldspl; 2159 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2160 PBUS_DMAMAP pmap; 2161 _VBUS_INST(&pAdapter->VBus) 2162 2163 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2164 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2165 2166 switch (ccb->ccb_h.func_code) 2167 { 2168 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2169 { 2170 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2171 2172 if (ccb->ccb_h.target_lun) { 2173 ccb->ccb_h.status = CAM_LUN_INVALID; 2174 xpt_done(ccb); 2175 return; 2176 } 2177 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2178 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2179 ccb->ccb_h.status = CAM_TID_INVALID; 2180 xpt_done(ccb); 2181 return; 2182 } 2183 2184 oldspl = lock_driver(); 2185 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2186 Check_Idle_Call(pAdapter); 2187 2188 pmap = dmamap_get(pAdapter); 2189 HPT_ASSERT(pmap); 2190 ccb->ccb_adapter = pmap; 2191 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2192 2193 if (mWaitingForIdle(_VBUS_P0)) 2194 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2195 else 2196 OsSendCommand(_VBUS_P ccb); 2197 unlock_driver(oldspl); 2198 2199 /* KdPrint(("leave scsiio\n")); */ 2200 break; 2201 } 2202 2203 case XPT_RESET_BUS: 2204 KdPrint(("reset bus\n")); 2205 oldspl = lock_driver(); 2206 fResetVBus(_VBUS_P0); 2207 unlock_driver(oldspl); 2208 xpt_done(ccb); 2209 break; 2210 2211 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2212 case XPT_EN_LUN: /* Enable LUN as a target */ 2213 case XPT_TARGET_IO: /* Execute target I/O request */ 2214 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2215 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2216 case XPT_ABORT: /* Abort the specified CCB */ 2217 case XPT_TERM_IO: /* Terminate the I/O process */ 2218 /* XXX Implement */ 2219 ccb->ccb_h.status = CAM_REQ_INVALID; 2220 xpt_done(ccb); 2221 break; 2222 2223 case XPT_GET_TRAN_SETTINGS: 2224 case XPT_SET_TRAN_SETTINGS: 2225 /* XXX Implement */ 2226 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2227 xpt_done(ccb); 2228 break; 2229 2230 case XPT_CALC_GEOMETRY: 2231 { 2232 struct ccb_calc_geometry *ccg; 2233 u_int32_t size_mb; 2234 u_int32_t secs_per_cylinder; 2235 2236 ccg = &ccb->ccg; 2237 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size); 2238 2239 if (size_mb > 1024 ) { 2240 ccg->heads = 255; 2241 ccg->secs_per_track = 63; 2242 } else { 2243 ccg->heads = 64; 2244 ccg->secs_per_track = 32; 2245 } 2246 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2247 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2248 ccb->ccb_h.status = CAM_REQ_CMP; 2249 xpt_done(ccb); 2250 break; 2251 } 2252 2253 case XPT_PATH_INQ: /* Path routing inquiry */ 2254 { 2255 struct ccb_pathinq *cpi = &ccb->cpi; 2256 2257 cpi->version_num = 1; /* XXX??? */ 2258 cpi->hba_inquiry = PI_SDTR_ABLE; 2259 cpi->target_sprt = 0; 2260 /* Not necessary to reset bus */ 2261 cpi->hba_misc = PIM_NOBUSRESET; 2262 cpi->hba_eng_cnt = 0; 2263 2264 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2265 cpi->max_lun = 0; 2266 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2267 2268 cpi->bus_id = cam_sim_bus(sim); 2269 cpi->base_transfer_speed = 3300; 2270 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2271 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2272 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2273 cpi->unit_number = cam_sim_unit(sim); 2274 cpi->ccb_h.status = CAM_REQ_CMP; 2275 xpt_done(ccb); 2276 break; 2277 } 2278 2279 default: 2280 KdPrint(("invalid cmd\n")); 2281 ccb->ccb_h.status = CAM_REQ_INVALID; 2282 xpt_done(ccb); 2283 break; 2284 } 2285 /* KdPrint(("leave hpt_action..............\n")); */ 2286 } 2287 2288 /* shall be called at lock_driver() */ 2289 static void 2290 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2291 { 2292 if(*ccb_Q == NULL) 2293 ccb->ccb_h.ccb_ccb_ptr = ccb; 2294 else { 2295 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2296 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2297 } 2298 2299 *ccb_Q = ccb; 2300 } 2301 2302 /* shall be called at lock_driver() */ 2303 static void 2304 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2305 { 2306 union ccb *TempCCB; 2307 2308 TempCCB = *ccb_Q; 2309 2310 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2311 *ccb_Q = NULL; 2312 else { 2313 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2314 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2315 2316 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2317 2318 if(*ccb_Q == ccb) 2319 *ccb_Q = TempCCB; 2320 } 2321 } 2322 2323 #ifdef SUPPORT_ARRAY 2324 /*************************************************************************** 2325 * Function: hpt_worker_thread 2326 * Description: Do background rebuilding. Execute in kernel thread context. 2327 * Returns: None 2328 ***************************************************************************/ 2329 static void hpt_worker_thread(void) 2330 { 2331 intrmask_t oldspl; 2332 2333 for(;;) { 2334 while (DpcQueue_First!=DpcQueue_Last) { 2335 ST_HPT_DPC p; 2336 oldspl = lock_driver(); 2337 p = DpcQueue[DpcQueue_First]; 2338 DpcQueue_First++; 2339 DpcQueue_First %= MAX_DPC; 2340 DPC_Request_Nums++; 2341 unlock_driver(oldspl); 2342 p.dpc(p.pAdapter, p.arg, p.flags); 2343 2344 oldspl = lock_driver(); 2345 DPC_Request_Nums--; 2346 /* since we may have prevented Check_Idle_Call, do it here */ 2347 if (DPC_Request_Nums==0) { 2348 if (p.pAdapter->outstandingCommands == 0) { 2349 _VBUS_INST(&p.pAdapter->VBus); 2350 Check_Idle_Call(p.pAdapter); 2351 CheckPendingCall(_VBUS_P0); 2352 } 2353 } 2354 unlock_driver(oldspl); 2355 2356 /*Schedule out*/ 2357 #if (__FreeBSD_version < 500000) 2358 YIELD_THREAD; 2359 #else 2360 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "sched", 1); 2361 #endif 2362 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2363 /* abort rebuilding process. */ 2364 IAL_ADAPTER_T *pAdapter; 2365 PVDevice pArray; 2366 PVBus _vbus_p; 2367 int i; 2368 pAdapter = gIal_Adapter; 2369 2370 while(pAdapter != 0){ 2371 2372 _vbus_p = &pAdapter->VBus; 2373 2374 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2375 { 2376 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2377 continue; 2378 else if (pArray->u.array.rf_rebuilding || 2379 pArray->u.array.rf_verifying || 2380 pArray->u.array.rf_initializing) 2381 { 2382 pArray->u.array.rf_abort_rebuild = 1; 2383 } 2384 } 2385 pAdapter = pAdapter->next; 2386 } 2387 } 2388 } 2389 2390 /*Remove this debug option*/ 2391 /* 2392 #ifdef DEBUG 2393 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2394 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); 2395 #endif 2396 */ 2397 #if (__FreeBSD_version >= 500043) 2398 kthread_suspend_check(curproc); 2399 #else 2400 kproc_suspend_loop(curproc); 2401 #endif 2402 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); /* wait for something to do */ 2403 } 2404 } 2405 2406 static struct proc *hptdaemonproc; 2407 static struct kproc_desc hpt_kp = { 2408 "hpt_wt", 2409 hpt_worker_thread, 2410 &hptdaemonproc 2411 }; 2412 2413 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2414 static void 2415 launch_worker_thread(void) 2416 { 2417 IAL_ADAPTER_T *pAdapTemp; 2418 2419 kproc_start(&hpt_kp); 2420 2421 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2422 2423 _VBUS_INST(&pAdapTemp->VBus) 2424 int i; 2425 PVDevice pVDev; 2426 2427 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2428 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2429 continue; 2430 else{ 2431 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2432 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2433 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2434 } 2435 } 2436 2437 /* 2438 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2439 */ 2440 #if (__FreeBSD_version < 500043) 2441 EVENTHANDLER_REGISTER(shutdown_post_sync, shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2442 #else 2443 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2444 #endif 2445 } 2446 /* 2447 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2448 */ 2449 2450 #endif 2451 2452 /********************************************************************************/ 2453 2454 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2455 { 2456 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2457 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2458 int idx; 2459 2460 if(logical) { 2461 if (ccb->ccb_h.flags & CAM_DATA_PHYS) 2462 panic("physical address unsupported"); 2463 2464 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2465 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2466 panic("physical address unsupported"); 2467 2468 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2469 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2470 pSg[idx].wSgSize = sgList[idx].ds_len; 2471 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0; 2472 } 2473 } 2474 else { 2475 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2476 pSg->wSgSize = ccb->csio.dxfer_len; 2477 pSg->wSgFlag = SG_FLAG_EOT; 2478 } 2479 return TRUE; 2480 } 2481 2482 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2483 HPT_ASSERT(0); 2484 return FALSE; 2485 } 2486 2487 /*******************************************************************************/ 2488 ULONG HPTLIBAPI 2489 GetStamp(void) 2490 { 2491 /* 2492 * the system variable, ticks, can't be used since it hasn't yet been active 2493 * when our driver starts (ticks==0, it's a invalid stamp value) 2494 */ 2495 ULONG stamp; 2496 do { stamp = random(); } while (stamp==0); 2497 return stamp; 2498 } 2499 2500 2501 static void 2502 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2503 { 2504 int i; 2505 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2506 2507 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2508 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2509 #ifndef SERIAL_CMDS 2510 inquiryData->CommandQueue = 1; 2511 #endif 2512 2513 switch(pVDev->VDeviceType) { 2514 case VD_SINGLE_DISK: 2515 case VD_ATAPI: 2516 case VD_REMOVABLE: 2517 /* Set the removable bit, if applicable. */ 2518 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2519 inquiryData->RemovableMedia = 1; 2520 2521 /* Fill in vendor identification fields. */ 2522 for (i = 0; i < 20; i += 2) { 2523 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2524 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2525 2526 } 2527 2528 /* Initialize unused portion of product id. */ 2529 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2530 2531 /* firmware revision */ 2532 for (i = 0; i < 4; i += 2) 2533 { 2534 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2535 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2536 } 2537 break; 2538 default: 2539 memcpy(&inquiryData->VendorId, "RR182x ", 8); 2540 #ifdef SUPPORT_ARRAY 2541 switch(pVDev->VDeviceType){ 2542 case VD_RAID_0: 2543 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2544 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2545 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2546 else 2547 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2548 break; 2549 case VD_RAID_1: 2550 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2551 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2552 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2553 else 2554 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2555 break; 2556 case VD_RAID_5: 2557 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2558 break; 2559 case VD_JBOD: 2560 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2561 break; 2562 } 2563 #endif 2564 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2565 break; 2566 } 2567 } 2568 2569 static void 2570 hpt_timeout(void *arg) 2571 { 2572 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus) 2573 intrmask_t oldspl = lock_driver(); 2574 fResetVBus(_VBUS_P0); 2575 unlock_driver(oldspl); 2576 } 2577 2578 static void 2579 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2580 { 2581 PCommand pCmd = (PCommand)arg; 2582 union ccb *ccb = pCmd->pOrgCommand; 2583 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2584 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2585 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2586 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2587 FPSCAT_GATH psg = pCmd->pSgTable; 2588 int idx; 2589 _VBUS_INST(pVDev->pVBus) 2590 2591 HPT_ASSERT(pCmd->cf_physical_sg); 2592 2593 if (error || nsegs == 0) 2594 panic("busdma error"); 2595 2596 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2597 2598 for (idx = 0; idx < nsegs; idx++, psg++) { 2599 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2600 psg->wSgSize = segs[idx].ds_len; 2601 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2602 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2603 } 2604 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2605 2606 if (pCmd->cf_data_in) { 2607 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD); 2608 } 2609 else if (pCmd->cf_data_out) { 2610 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE); 2611 } 2612 2613 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2614 pVDev->pfnSendCommand(_VBUS_P pCmd); 2615 CheckPendingCall(_VBUS_P0); 2616 } 2617 2618 2619 2620 static void HPTLIBAPI 2621 OsSendCommand(_VBUS_ARG union ccb *ccb) 2622 { 2623 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2624 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2625 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2626 struct ccb_scsiio *csio = &ccb->csio; 2627 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2628 2629 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2630 ccb, 2631 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2632 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2633 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2634 )); 2635 2636 pAdapter->outstandingCommands++; 2637 2638 if (pVDev == NULL || pVDev->vf_online == 0) { 2639 ccb->ccb_h.status = CAM_REQ_INVALID; 2640 ccb_done(ccb); 2641 goto Command_Complished; 2642 } 2643 2644 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2645 { 2646 case TEST_UNIT_READY: 2647 case START_STOP_UNIT: 2648 case SYNCHRONIZE_CACHE: 2649 /* FALLTHROUGH */ 2650 ccb->ccb_h.status = CAM_REQ_CMP; 2651 break; 2652 2653 case INQUIRY: 2654 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2655 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2656 ccb_h->status = CAM_REQ_CMP; 2657 break; 2658 2659 case READ_CAPACITY: 2660 { 2661 UCHAR swip[4]; 2662 /* Claim 512 byte blocks (big-endian). */ 2663 ((PREAD_CAPACITY_DATA)csio->data_ptr)->BytesPerBlock = 0x20000; 2664 *(ULONG*)swip = pVDev->VDeviceCapacity - 1; 2665 ((PREAD_CAPACITY_DATA)csio->data_ptr)->LogicalBlockAddress = 2666 (swip[0] << 24) | (swip[1] << 16) | (swip[2] << 8) | swip[3]; 2667 ccb_h->status = CAM_REQ_CMP; 2668 break; 2669 } 2670 2671 case READ_6: 2672 case WRITE_6: 2673 case READ_10: 2674 case WRITE_10: 2675 case 0x13: 2676 case 0x2f: 2677 { 2678 UCHAR Cdb[16]; 2679 UCHAR CdbLength; 2680 _VBUS_INST(pVDev->pVBus) 2681 PCommand pCmd = AllocateCommand(_VBUS_P0); 2682 HPT_ASSERT(pCmd); 2683 2684 CdbLength = csio->cdb_len; 2685 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2686 { 2687 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2688 { 2689 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2690 } 2691 else 2692 { 2693 KdPrintE(("ERROR!!!\n")); 2694 ccb->ccb_h.status = CAM_REQ_INVALID; 2695 break; 2696 } 2697 } 2698 else 2699 { 2700 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2701 } 2702 2703 pCmd->pOrgCommand = ccb; 2704 pCmd->pVDevice = pVDev; 2705 pCmd->pfnCompletion = fOsCommandDone; 2706 pCmd->pfnBuildSgl = fOsBuildSgl; 2707 pCmd->pSgTable = pmap->psg; 2708 2709 switch (Cdb[0]) 2710 { 2711 case READ_6: 2712 case WRITE_6: 2713 case 0x13: 2714 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2715 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2716 break; 2717 2718 default: 2719 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2720 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2721 break; 2722 } 2723 2724 switch (Cdb[0]) 2725 { 2726 case READ_6: 2727 case READ_10: 2728 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2729 pCmd->cf_data_in = 1; 2730 break; 2731 2732 case WRITE_6: 2733 case WRITE_10: 2734 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2735 pCmd->cf_data_out = 1; 2736 break; 2737 case 0x13: 2738 case 0x2f: 2739 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2740 break; 2741 } 2742 /*///////////////////////// */ 2743 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2744 int idx; 2745 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2746 2747 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2748 pCmd->cf_physical_sg = 1; 2749 2750 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2751 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2752 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len; 2753 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0; 2754 } 2755 2756 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2757 pVDev->pfnSendCommand(_VBUS_P pCmd); 2758 } 2759 else { 2760 int error; 2761 pCmd->cf_physical_sg = 1; 2762 error = bus_dmamap_load(pAdapter->io_dma_parent, 2763 pmap->dma_map, 2764 ccb->csio.data_ptr, ccb->csio.dxfer_len, 2765 hpt_io_dmamap_callback, pCmd, 2766 BUS_DMA_WAITOK 2767 ); 2768 KdPrint(("bus_dmamap_load return %d\n", error)); 2769 if (error && error!=EINPROGRESS) { 2770 hpt_printk(("bus_dmamap_load error %d\n", error)); 2771 FreeCommand(_VBUS_P pCmd); 2772 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2773 dmamap_put(pmap); 2774 pAdapter->outstandingCommands--; 2775 xpt_done(ccb); 2776 } 2777 } 2778 goto Command_Complished; 2779 } 2780 2781 default: 2782 ccb->ccb_h.status = CAM_REQ_INVALID; 2783 break; 2784 } 2785 ccb_done(ccb); 2786 Command_Complished: 2787 CheckPendingCall(_VBUS_P0); 2788 return; 2789 } 2790 2791 static void HPTLIBAPI 2792 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2793 { 2794 union ccb *ccb = pCmd->pOrgCommand; 2795 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2796 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2797 2798 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2799 2800 untimeout(hpt_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch); 2801 2802 switch(pCmd->Result) { 2803 case RETURN_SUCCESS: 2804 ccb->ccb_h.status = CAM_REQ_CMP; 2805 break; 2806 case RETURN_BAD_DEVICE: 2807 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2808 break; 2809 case RETURN_DEVICE_BUSY: 2810 ccb->ccb_h.status = CAM_BUSY; 2811 break; 2812 case RETURN_INVALID_REQUEST: 2813 ccb->ccb_h.status = CAM_REQ_INVALID; 2814 break; 2815 case RETURN_SELECTION_TIMEOUT: 2816 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2817 break; 2818 case RETURN_RETRY: 2819 ccb->ccb_h.status = CAM_BUSY; 2820 break; 2821 default: 2822 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2823 break; 2824 } 2825 2826 if (pCmd->cf_data_in) { 2827 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2828 } 2829 else if (pCmd->cf_data_in) { 2830 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2831 } 2832 2833 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2834 2835 FreeCommand(_VBUS_P pCmd); 2836 ccb_done(ccb); 2837 } 2838 2839 int 2840 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2841 { 2842 int p; 2843 2844 p = (DpcQueue_Last + 1) % MAX_DPC; 2845 if (p==DpcQueue_First) { 2846 KdPrint(("DPC Queue full!\n")); 2847 return -1; 2848 } 2849 2850 DpcQueue[DpcQueue_Last].dpc = dpc; 2851 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2852 DpcQueue[DpcQueue_Last].arg = arg; 2853 DpcQueue[DpcQueue_Last].flags = flags; 2854 DpcQueue_Last = p; 2855 2856 return 0; 2857 } 2858 2859 #ifdef _RAID5N_ 2860 /* 2861 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2862 * How about the memory for 5081 request/response array and PRD table? 2863 */ 2864 void 2865 *os_alloc_page(_VBUS_ARG0) 2866 { 2867 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2868 } 2869 2870 void 2871 *os_alloc_dma_page(_VBUS_ARG0) 2872 { 2873 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2874 } 2875 2876 void 2877 os_free_page(_VBUS_ARG void *p) 2878 { 2879 contigfree(p, 0x1000, M_DEVBUF); 2880 } 2881 2882 void 2883 os_free_dma_page(_VBUS_ARG void *p) 2884 { 2885 contigfree(p, 0x1000, M_DEVBUF); 2886 } 2887 2888 void 2889 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2890 { 2891 UINT i; 2892 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 2893 } 2894 2895 void 2896 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 2897 { 2898 UINT i; 2899 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 2900 } 2901 #endif 2902