1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/malloc.h> 34 #include <sys/resource.h> 35 #include <sys/time.h> 36 #include <sys/callout.h> 37 #include <sys/signalvar.h> 38 #include <sys/eventhandler.h> 39 #include <sys/proc.h> 40 #include <sys/kthread.h> 41 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/sx.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #ifndef __KERNEL__ 50 #define __KERNEL__ 51 #endif 52 53 #include <dev/hptmv/global.h> 54 #include <dev/hptmv/hptintf.h> 55 #include <dev/hptmv/osbsd.h> 56 #include <dev/hptmv/access601.h> 57 58 59 #ifdef DEBUG 60 #ifdef DEBUG_LEVEL 61 int hpt_dbg_level = DEBUG_LEVEL; 62 #else 63 int hpt_dbg_level = 0; 64 #endif 65 #endif 66 67 #define MV_ERROR printf 68 69 /* 70 * CAM SIM entry points 71 */ 72 static int hpt_probe (device_t dev); 73 static void launch_worker_thread(void); 74 static int hpt_attach(device_t dev); 75 static int hpt_detach(device_t dev); 76 static int hpt_shutdown(device_t dev); 77 static void hpt_poll(struct cam_sim *sim); 78 static void hpt_intr(void *arg); 79 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 80 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 81 82 static device_method_t driver_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_probe, hpt_probe), 85 DEVMETHOD(device_attach, hpt_attach), 86 DEVMETHOD(device_detach, hpt_detach), 87 88 DEVMETHOD(device_shutdown, hpt_shutdown), 89 DEVMETHOD_END 90 }; 91 92 static driver_t hpt_pci_driver = { 93 __str(PROC_DIR_NAME), 94 driver_methods, 95 sizeof(IAL_ADAPTER_T) 96 }; 97 98 #define __DRIVER_MODULE(p1, p2, p3, p4, p5) DRIVER_MODULE(p1, p2, p3, p4, p5) 99 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, 0, 0); 100 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1); 101 102 #define ccb_ccb_ptr spriv_ptr0 103 #define ccb_adapter ccb_h.spriv_ptr1 104 105 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 106 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 107 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 108 static void ccb_done(union ccb *ccb); 109 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 110 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 111 static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter); 112 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 113 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 114 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 115 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 116 static int fResetActiveCommands(PVBus _vbus_p); 117 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 118 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 119 static void hptmv_handle_event_disconnect(void *data); 120 static void hptmv_handle_event_connect(void *data); 121 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 122 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 123 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 124 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 125 int logical); 126 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 127 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 128 MV_U16 responseFlags, MV_U32 timeStamp, 129 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 130 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 131 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 132 133 #define ccb_ccb_ptr spriv_ptr0 134 #define ccb_adapter ccb_h.spriv_ptr1 135 136 static struct sx hptmv_list_lock; 137 SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list"); 138 IAL_ADAPTER_T *gIal_Adapter = NULL; 139 IAL_ADAPTER_T *pCurAdapter = NULL; 140 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 141 142 typedef struct st_HPT_DPC { 143 IAL_ADAPTER_T *pAdapter; 144 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 145 void *arg; 146 UCHAR flags; 147 } ST_HPT_DPC; 148 149 #define MAX_DPC 16 150 UCHAR DPC_Request_Nums = 0; 151 static ST_HPT_DPC DpcQueue[MAX_DPC]; 152 static int DpcQueue_First=0; 153 static int DpcQueue_Last = 0; 154 static struct mtx DpcQueue_Lock; 155 MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF); 156 157 char DRIVER_VERSION[] = "v1.16"; 158 159 /******************************************************************************* 160 * Name: hptmv_free_channel 161 * 162 * Description: free allocated queues for the given channel 163 * 164 * Parameters: pMvSataAdapter - pointer to the RR18xx controller this 165 * channel connected to. 166 * channelNum - channel number. 167 * 168 ******************************************************************************/ 169 static void 170 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 171 { 172 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 173 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 174 } 175 176 static void failDevice(PVDevice pVDev) 177 { 178 PVBus _vbus_p = pVDev->pVBus; 179 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 180 181 pVDev->u.disk.df_on_line = 0; 182 pVDev->vf_online = 0; 183 if (pVDev->pfnDeviceFailed) 184 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 185 186 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 187 188 #ifndef FOR_DEMO 189 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 190 pAdapter->beeping = 1; 191 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 192 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 193 } 194 #endif 195 } 196 197 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 198 199 static void 200 handleEdmaError(_VBUS_ARG PCommand pCmd) 201 { 202 PDevice pDevice = &pCmd->pVDevice->u.disk; 203 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 204 205 if (!pDevice->df_on_line) { 206 KdPrint(("Device is offline")); 207 pCmd->Result = RETURN_BAD_DEVICE; 208 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 209 return; 210 } 211 212 if (pCmd->RetryCount++>5) { 213 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 214 failed: 215 failDevice(pCmd->pVDevice); 216 pCmd->Result = RETURN_IDE_ERROR; 217 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 218 return; 219 } 220 221 /* reset the channel and retry the command */ 222 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 223 goto failed; 224 225 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 226 227 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 228 fDeviceSendCommand(_VBUS_P pCmd); 229 } 230 231 /**************************************************************** 232 * Name: hptmv_init_channel 233 * 234 * Description: allocate request and response queues for the EDMA of the 235 * given channel and sets other fields. 236 * 237 * Parameters: 238 * pAdapter - pointer to the emulated adapter data structure 239 * channelNum - channel number. 240 * Return: 0 on success, otherwise on failure 241 ****************************************************************/ 242 static int 243 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 244 { 245 MV_SATA_CHANNEL *pMvSataChannel; 246 dma_addr_t req_dma_addr; 247 dma_addr_t rsp_dma_addr; 248 249 if (channelNum >= MV_SATA_CHANNELS_NUM) 250 { 251 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 252 pAdapter->mvSataAdapter.adapterId, channelNum); 253 return -1; 254 } 255 256 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 257 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 258 pMvSataChannel->channelNumber = channelNum; 259 pMvSataChannel->lba48Address = MV_FALSE; 260 pMvSataChannel->maxReadTransfer = MV_FALSE; 261 262 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 263 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 264 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 265 266 267 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 268 269 /* check the 1K alignment of the request queue*/ 270 if (req_dma_addr & 0x3ff) 271 { 272 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 273 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 274 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 275 return -1; 276 } 277 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 278 pMvSataChannel->requestQueuePciHiAddress = 0; 279 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 280 pAdapter->mvSataAdapter.adapterId, channelNum, 281 pMvSataChannel->requestQueue)); 282 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 283 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 284 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 285 286 /* check the 256 alignment of the response queue*/ 287 if (rsp_dma_addr & 0xff) 288 { 289 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 290 "aligned, dma_addr=%llx\n", 291 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 292 return -1; 293 } 294 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 295 pMvSataChannel->responseQueuePciHiAddress = 0; 296 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 297 pAdapter->mvSataAdapter.adapterId, channelNum, 298 pMvSataChannel->responseQueue)); 299 300 pAdapter->mvChannel[channelNum].online = MV_TRUE; 301 return 0; 302 } 303 304 /****************************************************************************** 305 * Name: hptmv_parse_identify_results 306 * 307 * Description: this functions parses the identify command results, checks 308 * that the connected deives can be accesed by RR18xx EDMA, 309 * and updates the channel structure accordingly. 310 * 311 * Parameters: pMvSataChannel, pointer to the channel data structure. 312 * 313 * Returns: =0 ->success, < 0 ->failure. 314 * 315 ******************************************************************************/ 316 static int 317 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 318 { 319 MV_U16 *iden = pMvSataChannel->identifyDevice; 320 321 /*LBA addressing*/ 322 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 323 { 324 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 325 return -1; 326 } 327 else 328 { 329 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 330 } 331 /*DMA support*/ 332 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 333 { 334 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 335 return -1; 336 } 337 else 338 { 339 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 340 } 341 /* PIO */ 342 if ((iden[IDEN_VALID] & 2) == 0) 343 { 344 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 345 return -1; 346 } 347 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 348 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 349 350 /*UDMA*/ 351 if ((iden[IDEN_VALID] & 4) == 0) 352 { 353 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 354 return -1; 355 } 356 357 /* 48 bit address */ 358 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 359 { 360 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 361 pMvSataChannel->lba48Address = MV_TRUE; 362 } 363 else 364 { 365 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 366 pMvSataChannel->lba48Address = MV_FALSE; 367 } 368 return 0; 369 } 370 371 static void 372 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 373 { 374 PVDevice pVDev = &pAdapter->VDevices[channel]; 375 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 376 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 377 378 pMvSataChannel->outstandingCommands = 0; 379 380 pVDev->u.disk.mv = pMvSataChannel; 381 pVDev->u.disk.df_on_line = 1; 382 pVDev->u.disk.pVBus = &pAdapter->VBus; 383 pVDev->pVBus = &pAdapter->VBus; 384 385 #ifdef SUPPORT_48BIT_LBA 386 if (pMvSataChannel->lba48Address == MV_TRUE) 387 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 388 else 389 #endif 390 if(IdentifyData[53] & 1) { 391 pVDev->u.disk.dDeRealCapacity = 392 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 393 (IdentifyData[61]<<16 | IdentifyData[60]) : 394 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 395 } else 396 pVDev->u.disk.dDeRealCapacity = 397 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 398 399 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 400 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 401 402 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 403 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 404 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 405 } 406 } 407 408 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 409 { 410 PVDevice pVDev; 411 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 412 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 413 414 if (!pMvSataChannel) return; 415 416 if (plugged) 417 { 418 pVDev = &(pAdapter->VDevices[channelIndex]); 419 init_vdev_params(pAdapter, channelIndex); 420 421 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 422 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 423 424 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 425 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 426 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 427 pVDev->vf_online = 1; 428 429 #ifdef SUPPORT_ARRAY 430 if(pVDev->pParent) 431 { 432 int iMember; 433 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 434 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 435 pVDev->pParent->u.array.pMember[iMember] = NULL; 436 pVDev->pParent = NULL; 437 } 438 #endif 439 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 440 fCheckBootable(pVDev); 441 RegisterVDevice(pVDev); 442 443 #ifndef FOR_DEMO 444 if (pAdapter->beeping) { 445 pAdapter->beeping = 0; 446 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 447 } 448 #endif 449 450 } 451 else 452 { 453 pVDev = &(pAdapter->VDevices[channelIndex]); 454 failDevice(pVDev); 455 } 456 } 457 458 static int 459 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 460 { 461 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 462 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 463 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 464 MV_U32 udmaMode,pioMode; 465 466 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 467 channelNum)); 468 469 470 /* Software reset channel */ 471 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 472 { 473 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 474 pMvSataAdapter->adapterId, channelNum); 475 return -1; 476 } 477 478 /* Hardware reset channel */ 479 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 480 { 481 /* If failed, try again - this is when trying to hardreset a channel */ 482 /* when drive is just spinning up */ 483 StallExec(5000000); /* wait 5 sec before trying again */ 484 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 485 { 486 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 487 pMvSataAdapter->adapterId, channelNum); 488 return -1; 489 } 490 } 491 492 /* identify device*/ 493 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 494 { 495 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 496 , pMvSataAdapter->adapterId, channelNum); 497 return -1; 498 } 499 if (hptmv_parse_identify_results(pMvSataChannel)) 500 { 501 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 502 , pMvSataAdapter->adapterId, channelNum); 503 return -1; 504 } 505 506 /* mvStorageDevATASetFeatures */ 507 /* Disable 8 bit PIO in case CFA enabled */ 508 if (pMvSataChannel->identifyDevice[86] & 4) 509 { 510 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 511 pMvSataAdapter->adapterId)); 512 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 513 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 514 0, 0, 0) == MV_FALSE) 515 { 516 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 517 " failed\n", pMvSataAdapter->adapterId, channelNum); 518 return -1; 519 } 520 } 521 /* Write cache */ 522 #ifdef ENABLE_WRITE_CACHE 523 if (pMvSataChannel->identifyDevice[82] & 0x20) 524 { 525 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 526 { 527 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 528 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 529 0, 0, 0) == MV_FALSE) 530 { 531 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 532 pMvSataAdapter->adapterId, channelNum); 533 return -1; 534 } 535 } 536 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 537 pMvSataAdapter->adapterId, channelNum)); 538 } 539 else 540 { 541 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 542 pMvSataAdapter->adapterId, channelNum)); 543 } 544 #else /* disable write cache */ 545 { 546 if (pMvSataChannel->identifyDevice[85] & 0x20) 547 { 548 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 549 pMvSataAdapter->adapterId, channelNum)); 550 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 551 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 552 0, 0, 0) == MV_FALSE) 553 { 554 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 555 pMvSataAdapter->adapterId, channelNum); 556 return -1; 557 } 558 } 559 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 560 pMvSataAdapter->adapterId, channelNum)); 561 } 562 #endif 563 564 /* Set transfer mode */ 565 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 566 pMvSataAdapter->adapterId)); 567 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 568 MV_ATA_SET_FEATURES_TRANSFER, 569 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 570 MV_FALSE) 571 { 572 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 573 pMvSataAdapter->adapterId, channelNum); 574 return -1; 575 } 576 577 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 578 { 579 pioMode = MV_ATA_TRANSFER_PIO_4; 580 } 581 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 582 { 583 pioMode = MV_ATA_TRANSFER_PIO_3; 584 } 585 else 586 { 587 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 588 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 589 } 590 591 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 592 pMvSataAdapter->adapterId)); 593 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 594 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 595 MV_ATA_SET_FEATURES_TRANSFER, 596 pioMode, 0, 0, 0) == MV_FALSE) 597 { 598 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 599 pMvSataAdapter->adapterId, channelNum); 600 return -1; 601 } 602 603 udmaMode = MV_ATA_TRANSFER_UDMA_0; 604 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 605 { 606 udmaMode = MV_ATA_TRANSFER_UDMA_6; 607 } 608 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 609 { 610 udmaMode = MV_ATA_TRANSFER_UDMA_5; 611 } 612 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 613 { 614 udmaMode = MV_ATA_TRANSFER_UDMA_4; 615 } 616 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 617 { 618 udmaMode = MV_ATA_TRANSFER_UDMA_3; 619 } 620 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 621 { 622 udmaMode = MV_ATA_TRANSFER_UDMA_2; 623 } 624 625 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 626 pMvSataAdapter->adapterId, udmaMode & 0xf)); 627 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 628 629 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 630 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 631 0, 0, 0) == MV_FALSE) 632 { 633 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 634 pMvSataAdapter->adapterId, channelNum); 635 return -1; 636 }*/ 637 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 638 return TRUE; 639 else 640 do 641 { 642 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 643 MV_ATA_SET_FEATURES_TRANSFER, 644 pChannelInfo->maxUltraDmaModeSupported, 645 0, 0, 0) == MV_FALSE) 646 { 647 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 648 { 649 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 650 { 651 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 652 pMvSataChannel->eDmaRegsOffset + 653 0x11c, /* command reg */ 654 MV_ATA_COMMAND_IDLE_IMMEDIATE); 655 mvMicroSecondsDelay(10000); 656 mvSataChannelHardReset(pMvSataAdapter, channelNum); 657 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 658 return FALSE; 659 } 660 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 661 return FALSE; 662 pChannelInfo->maxUltraDmaModeSupported--; 663 continue; 664 } 665 else return FALSE; 666 } 667 break; 668 }while (1); 669 670 /* Read look ahead */ 671 #ifdef ENABLE_READ_AHEAD 672 if (pMvSataChannel->identifyDevice[82] & 0x40) 673 { 674 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 675 { 676 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 677 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 678 0, 0) == MV_FALSE) 679 { 680 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 681 pMvSataAdapter->adapterId, channelNum); 682 return -1; 683 } 684 } 685 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 686 pMvSataAdapter->adapterId, channelNum)); 687 } 688 else 689 { 690 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 691 pMvSataAdapter->adapterId, channelNum)); 692 } 693 #else 694 { 695 if (pMvSataChannel->identifyDevice[86] & 0x20) 696 { 697 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 698 pMvSataAdapter->adapterId, channelNum)); 699 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 700 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 701 0, 0) == MV_FALSE) 702 { 703 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 704 pMvSataAdapter->adapterId, channelNum); 705 return -1; 706 } 707 } 708 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 709 pMvSataAdapter->adapterId, channelNum)); 710 } 711 #endif 712 713 714 { 715 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 716 pMvSataAdapter->adapterId, 717 channelNum)); 718 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 719 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 720 { 721 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 722 pMvSataAdapter->adapterId, channelNum); 723 return -1; 724 } 725 } 726 /* Enable EDMA */ 727 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 728 { 729 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 730 pMvSataAdapter->adapterId, channelNum); 731 return -1; 732 } 733 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 734 pMvSataAdapter->adapterId, channelNum); 735 736 #ifndef FOR_DEMO 737 set_fail_led(pMvSataAdapter, channelNum, 0); 738 #endif 739 return 0; 740 } 741 742 static void 743 hptmv_handle_event(void * data, int flag) 744 { 745 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 746 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 747 MV_U8 channelIndex; 748 749 mtx_assert(&pAdapter->lock, MA_OWNED); 750 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 751 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 752 { 753 switch(pAdapter->sataEvents[channelIndex]) 754 { 755 case SATA_EVENT_CHANNEL_CONNECTED: 756 /* Handle only connects */ 757 if (flag == 1) 758 break; 759 KdPrint(("RR18xx [%d,%d]: new device connected\n", 760 pMvSataAdapter->adapterId, channelIndex)); 761 hptmv_init_channel(pAdapter, channelIndex); 762 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 763 { 764 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 765 pMvSataAdapter->adapterId, channelIndex); 766 hptmv_free_channel(pAdapter, channelIndex); 767 } 768 else 769 { 770 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 771 if (start_channel( pAdapter, channelIndex)) 772 { 773 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 774 pMvSataAdapter->adapterId, channelIndex); 775 hptmv_free_channel(pAdapter, channelIndex); 776 } 777 else 778 { 779 device_change(pAdapter, channelIndex, TRUE); 780 } 781 } 782 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 783 break; 784 785 case SATA_EVENT_CHANNEL_DISCONNECTED: 786 /* Handle only disconnects */ 787 if (flag == 0) 788 break; 789 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 790 pMvSataAdapter->adapterId, channelIndex)); 791 /* Flush pending commands */ 792 if(pMvSataAdapter->sataChannel[channelIndex]) 793 { 794 _VBUS_INST(&pAdapter->VBus) 795 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 796 MV_FLUSH_TYPE_CALLBACK); 797 CheckPendingCall(_VBUS_P0); 798 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 799 hptmv_free_channel(pAdapter, channelIndex); 800 pMvSataAdapter->sataChannel[channelIndex] = NULL; 801 KdPrint(("RR18xx [%d,%d]: channel removed\n", 802 pMvSataAdapter->adapterId, channelIndex)); 803 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 804 Check_Idle_Call(pAdapter); 805 } 806 else 807 { 808 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 809 pMvSataAdapter->adapterId, channelIndex)); 810 } 811 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 812 break; 813 814 case SATA_EVENT_NO_CHANGE: 815 break; 816 817 default: 818 break; 819 } 820 } 821 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 822 } 823 824 #define EVENT_CONNECT 1 825 #define EVENT_DISCONNECT 0 826 827 static void 828 hptmv_handle_event_connect(void *data) 829 { 830 hptmv_handle_event (data, 0); 831 } 832 833 static void 834 hptmv_handle_event_disconnect(void *data) 835 { 836 hptmv_handle_event (data, 1); 837 } 838 839 static MV_BOOLEAN 840 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 841 MV_U32 param1, MV_U32 param2) 842 { 843 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 844 845 switch (eventType) 846 { 847 case MV_EVENT_TYPE_SATA_CABLE: 848 { 849 MV_U8 channel = param2; 850 851 if (param1 == EVENT_CONNECT) 852 { 853 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 854 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 855 pMvSataAdapter->adapterId, channel)); 856 /* Delete previous timers (if multiple drives connected in the same time */ 857 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter); 858 } 859 else if (param1 == EVENT_DISCONNECT) 860 { 861 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 862 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 863 pMvSataAdapter->adapterId, channel)); 864 device_change(pAdapter, channel, FALSE); 865 /* Delete previous timers (if multiple drives disconnected in the same time */ 866 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */ 867 /*It is not necessary to wait, handle it directly*/ 868 hptmv_handle_event_disconnect(pAdapter); 869 } 870 else 871 { 872 873 MV_ERROR("RR18xx: illegal value for param1(%d) at " 874 "connect/disconnect event, host=%d\n", param1, 875 pMvSataAdapter->adapterId ); 876 877 } 878 } 879 break; 880 case MV_EVENT_TYPE_ADAPTER_ERROR: 881 KdPrint(("RR18xx: DEVICE error event received, pci cause " 882 "reg=%x, don't how to handle this\n", param1)); 883 return MV_TRUE; 884 default: 885 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 886 pMvSataAdapter->adapterId, eventType); 887 return MV_FALSE; 888 } 889 return MV_TRUE; 890 } 891 892 static int 893 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 894 { 895 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 896 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 897 if (pAdapter->requestsArrayBaseAddr == NULL) 898 { 899 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 900 " queues\n", pAdapter->mvSataAdapter.adapterId); 901 return -1; 902 } 903 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 904 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 905 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 906 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 907 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 908 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 909 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 910 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 911 912 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 913 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 914 { 915 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 916 pAdapter->mvSataAdapter.adapterId); 917 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 918 return -1; 919 } 920 /* response queues */ 921 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 922 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 923 if (pAdapter->responsesArrayBaseAddr == NULL) 924 { 925 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 926 " queues\n", pAdapter->mvSataAdapter.adapterId); 927 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 928 return -1; 929 } 930 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 931 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 932 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 933 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 934 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 935 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 936 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 937 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 938 939 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 940 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 941 { 942 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n", 943 pAdapter->mvSataAdapter.adapterId); 944 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 945 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 946 return -1; 947 } 948 return 0; 949 } 950 951 static void 952 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 953 { 954 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 955 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 956 } 957 958 static PVOID 959 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 960 { 961 PVOID ret; 962 if (pAdapter->pFreePRDLink) { 963 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 964 ret = pAdapter->pFreePRDLink; 965 pAdapter->pFreePRDLink = *(void**)ret; 966 return ret; 967 } 968 return NULL; 969 } 970 971 static void 972 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 973 { 974 *(void**)PRDTable = pAdapter->pFreePRDLink; 975 pAdapter->pFreePRDLink = PRDTable; 976 } 977 978 extern PVDevice fGetFirstChild(PVDevice pLogical); 979 extern void fResetBootMark(PVDevice pLogical); 980 static void 981 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 982 { 983 PVDevice pPhysical, pLogical; 984 PVBus pVBus; 985 int i,j; 986 987 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 988 pPhysical = &(pAdapter->VDevices[i]); 989 pLogical = pPhysical; 990 while (pLogical->pParent) pLogical = pLogical->pParent; 991 if (pLogical->vf_online==0) { 992 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 993 continue; 994 } 995 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 996 continue; 997 998 pVBus = &pAdapter->VBus; 999 if(pVBus) 1000 { 1001 j=0; 1002 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1003 if(j<MAX_VDEVICE_PER_VBUS){ 1004 pVBus->pVDevice[j] = pLogical; 1005 pLogical->pVBus = pVBus; 1006 1007 if (j>0 && pLogical->vf_bootmark) { 1008 if (pVBus->pVDevice[0]->vf_bootmark) { 1009 fResetBootMark(pLogical); 1010 } 1011 else { 1012 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1013 pVBus->pVDevice[0] = pLogical; 1014 } 1015 } 1016 } 1017 } 1018 } 1019 } 1020 1021 PVDevice 1022 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1023 { 1024 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1025 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1026 LBA_T thiscap, maxcap = MAX_LBA_T; 1027 PVDevice pVDevice, pFind = NULL; 1028 int i; 1029 1030 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1031 { 1032 pVDevice = &pAdapter->VDevices[i]; 1033 if(!pVDevice) 1034 continue; 1035 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1036 /* find the smallest usable spare disk */ 1037 if (pVDevice->VDeviceType==VD_SPARE && 1038 pVDevice->u.disk.df_on_line && 1039 thiscap < maxcap && 1040 thiscap >= capacity) 1041 { 1042 maxcap = pVDevice->VDeviceCapacity; 1043 pFind = pVDevice; 1044 } 1045 } 1046 return pFind; 1047 } 1048 1049 /****************************************************************** 1050 * IO ATA Command 1051 *******************************************************************/ 1052 int HPTLIBAPI 1053 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1054 { 1055 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1056 } 1057 1058 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1059 { 1060 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1061 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1062 MV_U8 channelIndex = pSataChannel->channelNumber; 1063 UCHAR mvMode; 1064 /* 508x don't use MW-DMA? */ 1065 if (NewMode>4 && NewMode<8) NewMode = 4; 1066 pDev->bDeModeSetting = NewMode; 1067 if (NewMode<=4) 1068 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1069 else 1070 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1071 1072 /*To fix 88i8030 bug*/ 1073 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1074 mvMode = MV_ATA_TRANSFER_UDMA_0; 1075 1076 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1077 /* Flush pending commands */ 1078 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1079 1080 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1081 MV_ATA_SET_FEATURES_TRANSFER, 1082 mvMode, 0, 0, 0) == MV_FALSE) 1083 { 1084 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1085 } 1086 /* Enable EDMA */ 1087 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1088 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1089 } 1090 1091 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1092 { 1093 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1094 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1095 MV_U8 channelIndex = pSataChannel->channelNumber; 1096 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1097 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1098 int dmaActive = pSataChannel->queueCommandsEnabled; 1099 int ret = 0; 1100 1101 if (dmaActive) { 1102 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1103 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1104 } 1105 1106 if (enable) { 1107 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1108 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1109 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1110 channelInfo->queueDepth = (depth==32)? 31 : depth; 1111 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1112 ret = 1; 1113 } 1114 } 1115 else 1116 { 1117 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1118 channelInfo->queueDepth = 2; 1119 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1120 ret = 1; 1121 } 1122 } 1123 1124 if (dmaActive) 1125 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1126 return ret; 1127 } 1128 1129 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1130 { 1131 return 0; 1132 } 1133 1134 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1135 { 1136 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1137 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1138 MV_U8 channelIndex = pSataChannel->channelNumber; 1139 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1140 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1141 int dmaActive = pSataChannel->queueCommandsEnabled; 1142 int ret = 0; 1143 1144 if (dmaActive) { 1145 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1146 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1147 } 1148 1149 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1150 if (enable) { 1151 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1152 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1153 { 1154 channelInfo->writeCacheEnabled = MV_TRUE; 1155 ret = 1; 1156 } 1157 } 1158 else { 1159 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1160 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1161 { 1162 channelInfo->writeCacheEnabled = MV_FALSE; 1163 ret = 1; 1164 } 1165 } 1166 } 1167 1168 if (dmaActive) 1169 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1170 return ret; 1171 } 1172 1173 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1174 { 1175 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1176 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1177 MV_U8 channelIndex = pSataChannel->channelNumber; 1178 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1179 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1180 int dmaActive = pSataChannel->queueCommandsEnabled; 1181 int ret = 0; 1182 1183 if (dmaActive) { 1184 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1185 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1186 } 1187 1188 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1189 if (enable) { 1190 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1191 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1192 { 1193 channelInfo->readAheadEnabled = MV_TRUE; 1194 ret = 1; 1195 } 1196 } 1197 else { 1198 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1199 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1200 { 1201 channelInfo->readAheadEnabled = MV_FALSE; 1202 ret = 1; 1203 } 1204 } 1205 } 1206 1207 if (dmaActive) 1208 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1209 return ret; 1210 } 1211 1212 #ifdef SUPPORT_ARRAY 1213 #define IdeRegisterVDevice fCheckArray 1214 #else 1215 void 1216 IdeRegisterVDevice(PDevice pDev) 1217 { 1218 PVDevice pVDev = Map2pVDevice(pDev); 1219 1220 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1221 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1222 pVDev->vf_online = 1; 1223 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1224 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1225 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1226 } 1227 #endif 1228 1229 static __inline PBUS_DMAMAP 1230 dmamap_get(struct IALAdapter * pAdapter) 1231 { 1232 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1233 if (p) 1234 pAdapter->pbus_dmamap_list = p-> next; 1235 return p; 1236 } 1237 1238 static __inline void 1239 dmamap_put(PBUS_DMAMAP p) 1240 { 1241 p->next = p->pAdapter->pbus_dmamap_list; 1242 p->pAdapter->pbus_dmamap_list = p; 1243 } 1244 1245 static int num_adapters = 0; 1246 static int 1247 init_adapter(IAL_ADAPTER_T *pAdapter) 1248 { 1249 PVBus _vbus_p = &pAdapter->VBus; 1250 MV_SATA_ADAPTER *pMvSataAdapter; 1251 int i, channel, rid; 1252 1253 PVDevice pVDev; 1254 1255 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF); 1256 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0); 1257 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0); 1258 1259 sx_xlock(&hptmv_list_lock); 1260 pAdapter->next = 0; 1261 1262 if(gIal_Adapter == NULL){ 1263 gIal_Adapter = pAdapter; 1264 pCurAdapter = gIal_Adapter; 1265 } 1266 else { 1267 pCurAdapter->next = pAdapter; 1268 pCurAdapter = pAdapter; 1269 } 1270 sx_xunlock(&hptmv_list_lock); 1271 1272 pAdapter->outstandingCommands = 0; 1273 1274 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1275 _vbus_p->OsExt = (void *)pAdapter; 1276 pMvSataAdapter->IALData = pAdapter; 1277 1278 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */ 1279 4, /* alignment */ 1280 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1281 BUS_SPACE_MAXADDR, /* lowaddr */ 1282 BUS_SPACE_MAXADDR, /* highaddr */ 1283 NULL, NULL, /* filter, filterarg */ 1284 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1285 MAX_SG_DESCRIPTORS, /* nsegments */ 1286 0x10000, /* maxsegsize */ 1287 BUS_DMA_WAITOK, /* flags */ 1288 busdma_lock_mutex, /* lockfunc */ 1289 &pAdapter->lock, /* lockfuncarg */ 1290 &pAdapter->io_dma_parent /* tag */)) 1291 { 1292 return ENXIO; 1293 } 1294 1295 1296 if (hptmv_allocate_edma_queues(pAdapter)) 1297 { 1298 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1299 return ENOMEM; 1300 } 1301 1302 /* also map EPROM address */ 1303 rid = 0x10; 1304 if (!(pAdapter->mem_res = bus_alloc_resource_any(pAdapter->hpt_dev, 1305 SYS_RES_MEMORY, &rid, RF_ACTIVE)) 1306 || 1307 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1308 { 1309 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1310 hptmv_free_edma_queues(pAdapter); 1311 return ENXIO; 1312 } 1313 else 1314 { 1315 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1316 } 1317 1318 pMvSataAdapter->adapterId = num_adapters++; 1319 /* get the revision ID */ 1320 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1321 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1322 1323 /* init RR18xx */ 1324 pMvSataAdapter->intCoalThre[0]= 1; 1325 pMvSataAdapter->intCoalThre[1]= 1; 1326 pMvSataAdapter->intTimeThre[0] = 1; 1327 pMvSataAdapter->intTimeThre[1] = 1; 1328 pMvSataAdapter->pciCommand = 0x0107E371; 1329 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1330 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1331 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1332 1333 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1334 { 1335 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1336 pMvSataAdapter->adapterId); 1337 unregister: 1338 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1339 hptmv_free_edma_queues(pAdapter); 1340 return ENXIO; 1341 } 1342 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1343 1344 #ifndef FOR_DEMO 1345 set_fail_leds(pMvSataAdapter, 0); 1346 #endif 1347 1348 /* setup command blocks */ 1349 KdPrint(("Allocate command blocks\n")); 1350 _vbus_(pFreeCommands) = 0; 1351 pAdapter->pCommandBlocks = 1352 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1353 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1354 if (!pAdapter->pCommandBlocks) { 1355 MV_ERROR("insufficient memory\n"); 1356 goto unregister; 1357 } 1358 1359 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1360 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1361 } 1362 1363 /*Set up the bus_dmamap*/ 1364 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1365 if(!pAdapter->pbus_dmamap) { 1366 MV_ERROR("insufficient memory\n"); 1367 free(pAdapter->pCommandBlocks, M_DEVBUF); 1368 goto unregister; 1369 } 1370 1371 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1372 pAdapter->pbus_dmamap_list = 0; 1373 for (i=0; i < MAX_QUEUE_COMM; i++) { 1374 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1375 pmap->pAdapter = pAdapter; 1376 dmamap_put(pmap); 1377 1378 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1379 MV_ERROR("Can not allocate dma map\n"); 1380 free(pAdapter->pCommandBlocks, M_DEVBUF); 1381 free(pAdapter->pbus_dmamap, M_DEVBUF); 1382 goto unregister; 1383 } 1384 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0); 1385 } 1386 /* setup PRD Tables */ 1387 KdPrint(("Allocate PRD Tables\n")); 1388 pAdapter->pFreePRDLink = 0; 1389 1390 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1391 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1392 1393 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1394 if (!pAdapter->prdTableAddr) { 1395 MV_ERROR("insufficient PRD Tables\n"); 1396 goto unregister; 1397 } 1398 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1399 { 1400 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1401 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1402 { 1403 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1404 FreePRDTable(pAdapter, PRDTable); 1405 PRDTable += PRD_ENTRIES_SIZE; 1406 } 1407 } 1408 1409 /* enable the adapter interrupts */ 1410 1411 /* configure and start the connected channels*/ 1412 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1413 { 1414 pAdapter->mvChannel[channel].online = MV_FALSE; 1415 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1416 == MV_TRUE) 1417 { 1418 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1419 pMvSataAdapter->adapterId, channel)); 1420 1421 if (hptmv_init_channel(pAdapter, channel) == 0) 1422 { 1423 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1424 { 1425 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1426 " %d\n",pMvSataAdapter->adapterId, channel); 1427 hptmv_free_channel(pAdapter, channel); 1428 } 1429 else 1430 { 1431 if (start_channel(pAdapter, channel)) 1432 { 1433 MV_ERROR("RR18xx[%d]: Failed to start channel," 1434 " channel=%d\n",pMvSataAdapter->adapterId, 1435 channel); 1436 hptmv_free_channel(pAdapter, channel); 1437 } 1438 pAdapter->mvChannel[channel].online = MV_TRUE; 1439 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1440 channel, 1441 MV_TRUE);*/ 1442 } 1443 } 1444 } 1445 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1446 pAdapter->mvChannel[channel].online, channel)); 1447 } 1448 1449 #ifdef SUPPORT_ARRAY 1450 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1451 pVDev = ArrayTables(i); 1452 mArFreeArrayTable(pVDev); 1453 } 1454 #endif 1455 1456 KdPrint(("Initialize Devices\n")); 1457 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1458 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1459 if (pMvSataChannel) { 1460 init_vdev_params(pAdapter, channel); 1461 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1462 } 1463 } 1464 #ifdef SUPPORT_ARRAY 1465 CheckArrayCritical(_VBUS_P0); 1466 #endif 1467 _vbus_p->nInstances = 1; 1468 fRegisterVdevice(pAdapter); 1469 1470 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1471 pVDev = _vbus_p->pVDevice[channel]; 1472 if (pVDev && pVDev->vf_online) 1473 fCheckBootable(pVDev); 1474 } 1475 1476 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1477 init_raid5_memory(_VBUS_P0); 1478 _vbus_(r5).enable_write_back = 1; 1479 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1480 #endif 1481 1482 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1483 return 0; 1484 } 1485 1486 int 1487 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1488 { 1489 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1490 1491 mvSataDisableChannelDma(pMvSataAdapter, channel); 1492 /* Flush pending commands */ 1493 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1494 1495 /* Software reset channel */ 1496 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1497 { 1498 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1499 pMvSataAdapter->adapterId, channel); 1500 hptmv_free_channel(pAdapter, channel); 1501 return -1; 1502 } 1503 1504 /* Hardware reset channel */ 1505 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1506 { 1507 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1508 pMvSataAdapter->adapterId, channel); 1509 hptmv_free_channel(pAdapter, channel); 1510 return -1; 1511 } 1512 1513 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1514 { 1515 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1516 pMvSataAdapter->adapterId, channel); 1517 hptmv_free_channel(pAdapter, channel); 1518 return -1; 1519 }else 1520 { 1521 MV_ERROR("channel %d: perform recalibrate command", channel); 1522 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1523 MV_NON_UDMA_PROTOCOL_NON_DATA, 1524 MV_FALSE, 1525 NULL, /* pBuffer*/ 1526 0, /* count */ 1527 0, /*features*/ 1528 /* sectorCount */ 1529 0, 1530 0, /* lbaLow */ 1531 0, /* lbaMid */ 1532 /* lbaHigh */ 1533 0, 1534 0, /* device */ 1535 /* command */ 1536 0x10)) 1537 MV_ERROR("channel %d: recalibrate failed", channel); 1538 1539 /* Set transfer mode */ 1540 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1541 MV_ATA_SET_FEATURES_TRANSFER, 1542 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1543 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1544 MV_ATA_SET_FEATURES_TRANSFER, 1545 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1546 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1547 MV_ATA_SET_FEATURES_TRANSFER, 1548 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1549 { 1550 MV_ERROR("channel %d: Set Features failed", channel); 1551 hptmv_free_channel(pAdapter, channel); 1552 return -1; 1553 } 1554 /* Enable EDMA */ 1555 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1556 { 1557 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1558 hptmv_free_channel(pAdapter, channel); 1559 return -1; 1560 } 1561 } 1562 return 0; 1563 } 1564 1565 static int 1566 fResetActiveCommands(PVBus _vbus_p) 1567 { 1568 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1569 MV_U8 channel; 1570 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1571 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1572 MvSataResetChannel(pMvSataAdapter,channel); 1573 } 1574 return 0; 1575 } 1576 1577 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1578 { 1579 UINT cont; 1580 ULONG ticks = 0; 1581 MV_U8 channel; 1582 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1583 MV_SATA_CHANNEL *pMvSataChannel; 1584 1585 do { 1586 check_cmds: 1587 cont = 0; 1588 CheckPendingCall(_VBUS_P0); 1589 #ifdef _RAID5N_ 1590 dataxfer_poll(); 1591 xor_poll(); 1592 #endif 1593 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1594 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1595 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1596 { 1597 while (pMvSataChannel->outstandingCommands) { 1598 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1599 StallExec(1000); 1600 if (ticks++ > 3000) { 1601 MvSataResetChannel(pMvSataAdapter,channel); 1602 goto check_cmds; 1603 } 1604 } 1605 else 1606 ticks = 0; 1607 } 1608 cont = 1; 1609 } 1610 } 1611 } while (cont); 1612 } 1613 1614 void 1615 fResetVBus(_VBUS_ARG0) 1616 { 1617 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1618 1619 /* some commands may already finished. */ 1620 CheckPendingCall(_VBUS_P0); 1621 1622 fResetActiveCommands(_vbus_p); 1623 /* 1624 * the other pending commands may still be finished successfully. 1625 */ 1626 fCompleteAllCommandsSynchronously(_vbus_p); 1627 1628 /* Now there should be no pending commands. No more action needed. */ 1629 CheckIdleCall(_VBUS_P0); 1630 1631 KdPrint(("fMvResetBus() done")); 1632 } 1633 1634 /*No rescan function*/ 1635 void 1636 fRescanAllDevice(_VBUS_ARG0) 1637 { 1638 } 1639 1640 static MV_BOOLEAN 1641 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1642 MV_U8 channelNum, 1643 MV_COMPLETION_TYPE comp_type, 1644 MV_VOID_PTR commandId, 1645 MV_U16 responseFlags, 1646 MV_U32 timeStamp, 1647 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1648 { 1649 PCommand pCmd = (PCommand) commandId; 1650 _VBUS_INST(pCmd->pVDevice->pVBus) 1651 1652 if (pCmd->uScratch.sata_param.prdAddr) 1653 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1654 1655 switch (comp_type) 1656 { 1657 case MV_COMPLETION_TYPE_NORMAL: 1658 pCmd->Result = RETURN_SUCCESS; 1659 break; 1660 case MV_COMPLETION_TYPE_ABORT: 1661 pCmd->Result = RETURN_BUS_RESET; 1662 break; 1663 case MV_COMPLETION_TYPE_ERROR: 1664 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1665 pMvSataAdapter->adapterId, channelNum, responseFlags); 1666 1667 if (responseFlags & 4) { 1668 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1669 " LBA high %x, device %x, status %x\n", 1670 registerStruct->errorRegister, 1671 registerStruct->sectorCountRegister, 1672 registerStruct->lbaLowRegister, 1673 registerStruct->lbaMidRegister, 1674 registerStruct->lbaHighRegister, 1675 registerStruct->deviceRegister, 1676 registerStruct->statusRegister); 1677 } 1678 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1679 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1680 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1681 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1682 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1683 pCmd->pVDevice->u.disk.QueueLength--; 1684 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1685 return TRUE; 1686 1687 default: 1688 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1689 return MV_FALSE; 1690 } 1691 1692 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1693 pCmd->uScratch.sata_param.cmd_priv --; 1694 return TRUE; 1695 } 1696 pCmd->pVDevice->u.disk.QueueLength--; 1697 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1698 return TRUE; 1699 } 1700 1701 void 1702 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1703 { 1704 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1705 MV_SATA_ADAPTER *pMvSataAdapter; 1706 MV_SATA_CHANNEL *pMvSataChannel; 1707 PVDevice pVDevice = pCmd->pVDevice; 1708 PDevice pDevice = &pVDevice->u.disk; 1709 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1710 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1711 1712 MV_QUEUE_COMMAND_RESULT result; 1713 MV_QUEUE_COMMAND_INFO commandInfo; 1714 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1715 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1716 1717 MV_BOOLEAN is48bit; 1718 MV_U8 channel; 1719 int i=0; 1720 1721 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1722 1723 if (!pDevice->df_on_line) { 1724 MV_ERROR("Device is offline"); 1725 pCmd->Result = RETURN_BAD_DEVICE; 1726 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1727 return; 1728 } 1729 1730 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1731 pMvSataChannel = pDevice->mv; 1732 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1733 channel = pMvSataChannel->channelNumber; 1734 1735 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1736 Lba += pDevice->dDeHiddenLba; 1737 /* check LBA */ 1738 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1739 pCmd->Result = RETURN_INVALID_REQUEST; 1740 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1741 return; 1742 } 1743 1744 /* 1745 * always use 48bit LBA if drive supports it. 1746 * Some Seagate drives report error if you use a 28-bit command 1747 * to access sector 0xfffffff. 1748 */ 1749 is48bit = pMvSataChannel->lba48Address; 1750 1751 switch (pCmd->uCmd.Ide.Command) 1752 { 1753 case IDE_COMMAND_READ: 1754 case IDE_COMMAND_WRITE: 1755 if (pDevice->bDeModeSetting<8) goto pio; 1756 1757 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1758 pUdmaParams->isEXT = is48bit; 1759 pUdmaParams->numOfSectors = nSector; 1760 pUdmaParams->lowLBAAddress = Lba; 1761 pUdmaParams->highLBAAddress = 0; 1762 pUdmaParams->prdHighAddr = 0; 1763 pUdmaParams->callBack = CommandCompletionCB; 1764 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1765 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1766 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1767 else 1768 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1769 1770 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1771 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1772 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1773 } 1774 else { 1775 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1776 pio: 1777 mvSataDisableChannelDma(pMvSataAdapter, channel); 1778 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1779 1780 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1781 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1782 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1783 } 1784 else { 1785 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1786 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1787 goto finish_cmd; 1788 } 1789 } 1790 1791 do { 1792 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1793 ULONG_PTR addr = tmpSg->dSgAddress; 1794 if (size & 0x1ff) { 1795 pCmd->Result = RETURN_INVALID_REQUEST; 1796 goto finish_cmd; 1797 } 1798 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1799 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1800 is48bit, 1801 (MV_U16_PTR)addr, 1802 size >> 1, /* count */ 1803 0, /* features N/A */ 1804 (MV_U16)(size>>9), /*sector count*/ 1805 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1806 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1807 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1808 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1809 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1810 )==MV_FALSE) 1811 { 1812 pCmd->Result = RETURN_IDE_ERROR; 1813 goto finish_cmd; 1814 } 1815 Lba += size>>9; 1816 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1817 } 1818 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1819 pCmd->Result = RETURN_SUCCESS; 1820 finish_cmd: 1821 mvSataEnableChannelDma(pMvSataAdapter,channel); 1822 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1823 return; 1824 } 1825 } 1826 1827 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1828 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1829 if (!pPRDTable) { 1830 pCmd->Result = RETURN_DEVICE_BUSY; 1831 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1832 HPT_ASSERT(0); 1833 return; 1834 } 1835 1836 do{ 1837 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1838 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1839 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1840 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1841 pPRDTable[i].reserved = 0; 1842 i++; 1843 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1844 1845 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1846 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1847 pUdmaParams->numOfSectors = 0; 1848 } 1849 1850 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1851 1852 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1853 1854 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1855 { 1856 queue_failed: 1857 switch (result) 1858 { 1859 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1860 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1861 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1862 pCmd->Result = RETURN_IDE_ERROR; 1863 break; 1864 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1865 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1866 " disabled adapter %d channel %d\n", 1867 pMvSataAdapter->adapterId, channel); 1868 mvSataEnableChannelDma(pMvSataAdapter,channel); 1869 pCmd->Result = RETURN_IDE_ERROR; 1870 break; 1871 case MV_QUEUE_COMMAND_RESULT_FULL: 1872 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1873 " Full adapter %d channel %d\n", 1874 pMvSataAdapter->adapterId, channel); 1875 pCmd->Result = RETURN_DEVICE_BUSY; 1876 break; 1877 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1878 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1879 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1880 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1881 pCmd->Result = RETURN_IDE_ERROR; 1882 break; 1883 default: 1884 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1885 " command\n", result); 1886 pCmd->Result = RETURN_IDE_ERROR; 1887 } 1888 if(pPRDTable) 1889 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1890 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1891 } 1892 pDevice->QueueLength++; 1893 return; 1894 1895 case IDE_COMMAND_VERIFY: 1896 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1897 pNoUdmaParams->bufPtr = NULL; 1898 pNoUdmaParams->callBack = CommandCompletionCB; 1899 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1900 pNoUdmaParams->count = 0; 1901 pNoUdmaParams->features = 0; 1902 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1903 1904 pCmd->uScratch.sata_param.cmd_priv = 1; 1905 if (pMvSataChannel->lba48Address == MV_TRUE){ 1906 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1907 pNoUdmaParams->isEXT = MV_TRUE; 1908 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1909 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1910 pNoUdmaParams->lbaLow = 1911 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1912 pNoUdmaParams->sectorCount = nSector; 1913 pNoUdmaParams->device = 0x40; 1914 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1915 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1916 goto queue_failed; 1917 } 1918 return; 1919 } 1920 else{ 1921 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1922 pNoUdmaParams->isEXT = MV_FALSE; 1923 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1924 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1925 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1926 pNoUdmaParams->sectorCount = 0xff & nSector; 1927 pNoUdmaParams->device = (MV_U8)(0x40 | 1928 ((Lba & 0xf000000) >> 24)); 1929 pNoUdmaParams->callBack = CommandCompletionCB; 1930 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1931 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1932 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1933 goto queue_failed; 1934 } 1935 } 1936 break; 1937 default: 1938 pCmd->Result = RETURN_INVALID_REQUEST; 1939 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1940 break; 1941 } 1942 } 1943 1944 /********************************************************** 1945 * 1946 * Probe the hostadapter. 1947 * 1948 **********************************************************/ 1949 static int 1950 hpt_probe(device_t dev) 1951 { 1952 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1953 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1954 #ifdef FOR_DEMO 1955 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1956 #endif 1957 )) 1958 { 1959 KdPrintI((CONTROLLER_NAME " found\n")); 1960 device_set_desc(dev, CONTROLLER_NAME); 1961 return (BUS_PROBE_DEFAULT); 1962 } 1963 else 1964 return(ENXIO); 1965 } 1966 1967 /*********************************************************** 1968 * 1969 * Auto configuration: attach and init a host adapter. 1970 * 1971 ***********************************************************/ 1972 static int 1973 hpt_attach(device_t dev) 1974 { 1975 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1976 int rid; 1977 union ccb *ccb; 1978 struct cam_devq *devq; 1979 struct cam_sim *hpt_vsim; 1980 1981 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1982 1983 pAdapter->hpt_dev = dev; 1984 1985 rid = init_adapter(pAdapter); 1986 if (rid) 1987 return rid; 1988 1989 rid = 0; 1990 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) 1991 { 1992 hpt_printk(("can't allocate interrupt\n")); 1993 return(ENXIO); 1994 } 1995 1996 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 1997 INTR_TYPE_CAM | INTR_MPSAFE, 1998 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 1999 { 2000 hpt_printk(("can't set up interrupt\n")); 2001 free(pAdapter, M_DEVBUF); 2002 return(ENXIO); 2003 } 2004 2005 2006 ccb = xpt_alloc_ccb(); 2007 ccb->ccb_h.pinfo.priority = 1; 2008 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2009 2010 /* 2011 * Create the device queue for our SIM(s). 2012 */ 2013 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2014 { 2015 KdPrint(("ENXIO\n")); 2016 return ENOMEM; 2017 } 2018 2019 /* 2020 * Construct our SIM entry 2021 */ 2022 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2023 pAdapter, device_get_unit(pAdapter->hpt_dev), 2024 &pAdapter->lock, 1, 8, devq); 2025 if (hpt_vsim == NULL) { 2026 cam_simq_free(devq); 2027 return ENOMEM; 2028 } 2029 2030 mtx_lock(&pAdapter->lock); 2031 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS) 2032 { 2033 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 2034 mtx_unlock(&pAdapter->lock); 2035 hpt_vsim = NULL; 2036 return ENXIO; 2037 } 2038 2039 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2040 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2041 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2042 { 2043 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2044 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 2045 mtx_unlock(&pAdapter->lock); 2046 hpt_vsim = NULL; 2047 return ENXIO; 2048 } 2049 mtx_unlock(&pAdapter->lock); 2050 2051 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2052 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2053 ccb->csa.event_enable = AC_LOST_DEVICE; 2054 ccb->csa.callback = hpt_async; 2055 ccb->csa.callback_arg = hpt_vsim; 2056 xpt_action((union ccb *)ccb); 2057 xpt_free_ccb(ccb); 2058 2059 if (device_get_unit(dev) == 0) { 2060 /* Start the work thread. XXX */ 2061 launch_worker_thread(); 2062 } 2063 2064 return 0; 2065 } 2066 2067 static int 2068 hpt_detach(device_t dev) 2069 { 2070 return (EBUSY); 2071 } 2072 2073 2074 /*************************************************************** 2075 * The poll function is used to simulate the interrupt when 2076 * the interrupt subsystem is not functioning. 2077 * 2078 ***************************************************************/ 2079 static void 2080 hpt_poll(struct cam_sim *sim) 2081 { 2082 2083 hpt_intr_locked((void *)cam_sim_softc(sim)); 2084 } 2085 2086 /**************************************************************** 2087 * Name: hpt_intr 2088 * Description: Interrupt handler. 2089 ****************************************************************/ 2090 static void 2091 hpt_intr(void *arg) 2092 { 2093 IAL_ADAPTER_T *pAdapter; 2094 2095 pAdapter = arg; 2096 mtx_lock(&pAdapter->lock); 2097 hpt_intr_locked(pAdapter); 2098 mtx_unlock(&pAdapter->lock); 2099 } 2100 2101 static void 2102 hpt_intr_locked(IAL_ADAPTER_T *pAdapter) 2103 { 2104 2105 mtx_assert(&pAdapter->lock, MA_OWNED); 2106 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2107 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2108 { 2109 _VBUS_INST(&pAdapter->VBus) 2110 CheckPendingCall(_VBUS_P0); 2111 } 2112 2113 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2114 } 2115 2116 /********************************************************** 2117 * Asynchronous Events 2118 *********************************************************/ 2119 #if (!defined(UNREFERENCED_PARAMETER)) 2120 #define UNREFERENCED_PARAMETER(x) (void)(x) 2121 #endif 2122 2123 static void 2124 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2125 void * arg) 2126 { 2127 /* debug XXXX */ 2128 panic("Here"); 2129 UNREFERENCED_PARAMETER(callback_arg); 2130 UNREFERENCED_PARAMETER(code); 2131 UNREFERENCED_PARAMETER(path); 2132 UNREFERENCED_PARAMETER(arg); 2133 2134 } 2135 2136 static void 2137 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2138 { 2139 int i; 2140 2141 hpt_printk(("flush all devices\n")); 2142 2143 /* flush all devices */ 2144 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2145 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2146 if(pVDev) fFlushVDev(pVDev); 2147 } 2148 } 2149 2150 static int 2151 hpt_shutdown(device_t dev) 2152 { 2153 IAL_ADAPTER_T *pAdapter; 2154 2155 pAdapter = device_get_softc(dev); 2156 2157 mtx_lock(&pAdapter->lock); 2158 FlushAdapter(pAdapter); 2159 mtx_unlock(&pAdapter->lock); 2160 /* give the flush some time to happen, 2161 *otherwise "shutdown -p now" will make file system corrupted */ 2162 DELAY(1000 * 1000 * 5); 2163 return 0; 2164 } 2165 2166 void 2167 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2168 { 2169 _VBUS_INST(&pAdapter->VBus) 2170 2171 if (mWaitingForIdle(_VBUS_P0)) { 2172 CheckIdleCall(_VBUS_P0); 2173 #ifdef SUPPORT_ARRAY 2174 { 2175 int i; 2176 PVDevice pArray; 2177 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2178 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2179 continue; 2180 else if (pArray->u.array.rf_auto_rebuild) { 2181 KdPrint(("auto rebuild.\n")); 2182 pArray->u.array.rf_auto_rebuild = 0; 2183 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2184 } 2185 } 2186 } 2187 #endif 2188 } 2189 /* launch the awaiting commands blocked by mWaitingForIdle */ 2190 while(pAdapter->pending_Q!= NULL) 2191 { 2192 _VBUS_INST(&pAdapter->VBus) 2193 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2194 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2195 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2196 } 2197 } 2198 2199 static void 2200 ccb_done(union ccb *ccb) 2201 { 2202 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2203 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2204 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2205 2206 dmamap_put(pmap); 2207 xpt_done(ccb); 2208 2209 pAdapter->outstandingCommands--; 2210 2211 if (pAdapter->outstandingCommands == 0) 2212 { 2213 if(DPC_Request_Nums == 0) 2214 Check_Idle_Call(pAdapter); 2215 wakeup(pAdapter); 2216 } 2217 } 2218 2219 /**************************************************************** 2220 * Name: hpt_action 2221 * Description: Process a queued command from the CAM layer. 2222 * Parameters: sim - Pointer to SIM object 2223 * ccb - Pointer to SCSI command structure. 2224 ****************************************************************/ 2225 2226 void 2227 hpt_action(struct cam_sim *sim, union ccb *ccb) 2228 { 2229 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2230 PBUS_DMAMAP pmap; 2231 _VBUS_INST(&pAdapter->VBus) 2232 2233 mtx_assert(&pAdapter->lock, MA_OWNED); 2234 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2235 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2236 2237 switch (ccb->ccb_h.func_code) 2238 { 2239 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2240 { 2241 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2242 2243 if (ccb->ccb_h.target_lun) { 2244 ccb->ccb_h.status = CAM_LUN_INVALID; 2245 xpt_done(ccb); 2246 return; 2247 } 2248 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2249 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2250 ccb->ccb_h.status = CAM_TID_INVALID; 2251 xpt_done(ccb); 2252 return; 2253 } 2254 2255 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2256 Check_Idle_Call(pAdapter); 2257 2258 pmap = dmamap_get(pAdapter); 2259 HPT_ASSERT(pmap); 2260 ccb->ccb_adapter = pmap; 2261 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2262 2263 if (mWaitingForIdle(_VBUS_P0)) 2264 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2265 else 2266 OsSendCommand(_VBUS_P ccb); 2267 2268 /* KdPrint(("leave scsiio\n")); */ 2269 break; 2270 } 2271 2272 case XPT_RESET_BUS: 2273 KdPrint(("reset bus\n")); 2274 fResetVBus(_VBUS_P0); 2275 xpt_done(ccb); 2276 break; 2277 2278 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2279 case XPT_ABORT: /* Abort the specified CCB */ 2280 case XPT_TERM_IO: /* Terminate the I/O process */ 2281 /* XXX Implement */ 2282 ccb->ccb_h.status = CAM_REQ_INVALID; 2283 xpt_done(ccb); 2284 break; 2285 2286 case XPT_GET_TRAN_SETTINGS: 2287 case XPT_SET_TRAN_SETTINGS: 2288 /* XXX Implement */ 2289 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2290 xpt_done(ccb); 2291 break; 2292 2293 case XPT_CALC_GEOMETRY: 2294 cam_calc_geometry(&ccb->ccg, 1); 2295 xpt_done(ccb); 2296 break; 2297 2298 case XPT_PATH_INQ: /* Path routing inquiry */ 2299 { 2300 struct ccb_pathinq *cpi = &ccb->cpi; 2301 2302 cpi->version_num = 1; /* XXX??? */ 2303 cpi->hba_inquiry = PI_SDTR_ABLE; 2304 cpi->target_sprt = 0; 2305 /* Not necessary to reset bus */ 2306 cpi->hba_misc = PIM_NOBUSRESET; 2307 cpi->hba_eng_cnt = 0; 2308 2309 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2310 cpi->max_lun = 0; 2311 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2312 2313 cpi->bus_id = cam_sim_bus(sim); 2314 cpi->base_transfer_speed = 3300; 2315 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2316 strlcpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2317 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2318 cpi->unit_number = cam_sim_unit(sim); 2319 cpi->transport = XPORT_SPI; 2320 cpi->transport_version = 2; 2321 cpi->protocol = PROTO_SCSI; 2322 cpi->protocol_version = SCSI_REV_2; 2323 cpi->ccb_h.status = CAM_REQ_CMP; 2324 xpt_done(ccb); 2325 break; 2326 } 2327 2328 default: 2329 KdPrint(("invalid cmd\n")); 2330 ccb->ccb_h.status = CAM_REQ_INVALID; 2331 xpt_done(ccb); 2332 break; 2333 } 2334 /* KdPrint(("leave hpt_action..............\n")); */ 2335 } 2336 2337 /* shall be called at lock_driver() */ 2338 static void 2339 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2340 { 2341 if(*ccb_Q == NULL) 2342 ccb->ccb_h.ccb_ccb_ptr = ccb; 2343 else { 2344 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2345 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2346 } 2347 2348 *ccb_Q = ccb; 2349 } 2350 2351 /* shall be called at lock_driver() */ 2352 static void 2353 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2354 { 2355 union ccb *TempCCB; 2356 2357 TempCCB = *ccb_Q; 2358 2359 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2360 *ccb_Q = NULL; 2361 else { 2362 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2363 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2364 2365 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2366 2367 if(*ccb_Q == ccb) 2368 *ccb_Q = TempCCB; 2369 } 2370 } 2371 2372 #ifdef SUPPORT_ARRAY 2373 /*************************************************************************** 2374 * Function: hpt_worker_thread 2375 * Description: Do background rebuilding. Execute in kernel thread context. 2376 * Returns: None 2377 ***************************************************************************/ 2378 static void hpt_worker_thread(void) 2379 { 2380 2381 for(;;) { 2382 mtx_lock(&DpcQueue_Lock); 2383 while (DpcQueue_First!=DpcQueue_Last) { 2384 ST_HPT_DPC p; 2385 p = DpcQueue[DpcQueue_First]; 2386 DpcQueue_First++; 2387 DpcQueue_First %= MAX_DPC; 2388 DPC_Request_Nums++; 2389 mtx_unlock(&DpcQueue_Lock); 2390 p.dpc(p.pAdapter, p.arg, p.flags); 2391 2392 mtx_lock(&p.pAdapter->lock); 2393 mtx_lock(&DpcQueue_Lock); 2394 DPC_Request_Nums--; 2395 /* since we may have prevented Check_Idle_Call, do it here */ 2396 if (DPC_Request_Nums==0) { 2397 if (p.pAdapter->outstandingCommands == 0) { 2398 _VBUS_INST(&p.pAdapter->VBus); 2399 Check_Idle_Call(p.pAdapter); 2400 CheckPendingCall(_VBUS_P0); 2401 } 2402 } 2403 mtx_unlock(&p.pAdapter->lock); 2404 mtx_unlock(&DpcQueue_Lock); 2405 2406 /*Schedule out*/ 2407 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2408 /* abort rebuilding process. */ 2409 IAL_ADAPTER_T *pAdapter; 2410 PVDevice pArray; 2411 PVBus _vbus_p; 2412 int i; 2413 2414 sx_slock(&hptmv_list_lock); 2415 pAdapter = gIal_Adapter; 2416 2417 while(pAdapter != NULL){ 2418 mtx_lock(&pAdapter->lock); 2419 _vbus_p = &pAdapter->VBus; 2420 2421 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2422 { 2423 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2424 continue; 2425 else if (pArray->u.array.rf_rebuilding || 2426 pArray->u.array.rf_verifying || 2427 pArray->u.array.rf_initializing) 2428 { 2429 pArray->u.array.rf_abort_rebuild = 1; 2430 } 2431 } 2432 mtx_unlock(&pAdapter->lock); 2433 pAdapter = pAdapter->next; 2434 } 2435 sx_sunlock(&hptmv_list_lock); 2436 } 2437 mtx_lock(&DpcQueue_Lock); 2438 } 2439 mtx_unlock(&DpcQueue_Lock); 2440 2441 /*Remove this debug option*/ 2442 /* 2443 #ifdef DEBUG 2444 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2445 pause("hptrdy", 2*hz); 2446 #endif 2447 */ 2448 kproc_suspend_check(curproc); 2449 pause("-", 2*hz); /* wait for something to do */ 2450 } 2451 } 2452 2453 static struct proc *hptdaemonproc; 2454 static struct kproc_desc hpt_kp = { 2455 "hpt_wt", 2456 hpt_worker_thread, 2457 &hptdaemonproc 2458 }; 2459 2460 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2461 static void 2462 launch_worker_thread(void) 2463 { 2464 IAL_ADAPTER_T *pAdapTemp; 2465 2466 kproc_start(&hpt_kp); 2467 2468 sx_slock(&hptmv_list_lock); 2469 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2470 2471 _VBUS_INST(&pAdapTemp->VBus) 2472 int i; 2473 PVDevice pVDev; 2474 2475 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2476 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2477 continue; 2478 else{ 2479 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2480 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2481 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2482 } 2483 } 2484 sx_sunlock(&hptmv_list_lock); 2485 2486 /* 2487 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2488 */ 2489 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, 2490 SHUTDOWN_PRI_LAST); 2491 } 2492 /* 2493 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2494 */ 2495 2496 #endif 2497 2498 /********************************************************************************/ 2499 2500 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2501 { 2502 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2503 2504 if (logical) { 2505 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2506 pSg->wSgSize = ccb->csio.dxfer_len; 2507 pSg->wSgFlag = SG_FLAG_EOT; 2508 return TRUE; 2509 } 2510 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2511 HPT_ASSERT(0); 2512 return FALSE; 2513 } 2514 2515 /*******************************************************************************/ 2516 ULONG HPTLIBAPI 2517 GetStamp(void) 2518 { 2519 /* 2520 * the system variable, ticks, can't be used since it hasn't yet been active 2521 * when our driver starts (ticks==0, it's a invalid stamp value) 2522 */ 2523 ULONG stamp; 2524 do { stamp = random(); } while (stamp==0); 2525 return stamp; 2526 } 2527 2528 2529 static void 2530 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2531 { 2532 int i; 2533 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2534 2535 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2536 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2537 #ifndef SERIAL_CMDS 2538 inquiryData->CommandQueue = 1; 2539 #endif 2540 2541 switch(pVDev->VDeviceType) { 2542 case VD_SINGLE_DISK: 2543 case VD_ATAPI: 2544 case VD_REMOVABLE: 2545 /* Set the removable bit, if applicable. */ 2546 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2547 inquiryData->RemovableMedia = 1; 2548 2549 /* Fill in vendor identification fields. */ 2550 for (i = 0; i < 20; i += 2) { 2551 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2552 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2553 2554 } 2555 2556 /* Initialize unused portion of product id. */ 2557 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2558 2559 /* firmware revision */ 2560 for (i = 0; i < 4; i += 2) 2561 { 2562 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2563 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2564 } 2565 break; 2566 default: 2567 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2568 #ifdef SUPPORT_ARRAY 2569 switch(pVDev->VDeviceType){ 2570 case VD_RAID_0: 2571 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2572 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2573 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2574 else 2575 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2576 break; 2577 case VD_RAID_1: 2578 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2579 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2580 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2581 else 2582 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2583 break; 2584 case VD_RAID_5: 2585 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2586 break; 2587 case VD_JBOD: 2588 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2589 break; 2590 } 2591 #endif 2592 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2593 break; 2594 } 2595 } 2596 2597 static void 2598 hpt_timeout(void *arg) 2599 { 2600 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter; 2601 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2602 _VBUS_INST(&pAdapter->VBus) 2603 2604 mtx_assert(&pAdapter->lock, MA_OWNED); 2605 fResetVBus(_VBUS_P0); 2606 } 2607 2608 static void 2609 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2610 { 2611 PCommand pCmd = (PCommand)arg; 2612 union ccb *ccb = pCmd->pOrgCommand; 2613 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2614 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2615 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2616 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2617 FPSCAT_GATH psg = pCmd->pSgTable; 2618 int idx; 2619 _VBUS_INST(pVDev->pVBus) 2620 2621 HPT_ASSERT(pCmd->cf_physical_sg); 2622 2623 if (error) 2624 panic("busdma error"); 2625 2626 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2627 2628 if (nsegs != 0) { 2629 for (idx = 0; idx < nsegs; idx++, psg++) { 2630 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2631 psg->wSgSize = segs[idx].ds_len; 2632 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2633 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2634 } 2635 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2636 2637 if (pCmd->cf_data_in) { 2638 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2639 BUS_DMASYNC_PREREAD); 2640 } 2641 else if (pCmd->cf_data_out) { 2642 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2643 BUS_DMASYNC_PREWRITE); 2644 } 2645 } 2646 2647 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb); 2648 pVDev->pfnSendCommand(_VBUS_P pCmd); 2649 CheckPendingCall(_VBUS_P0); 2650 } 2651 2652 2653 2654 static void HPTLIBAPI 2655 OsSendCommand(_VBUS_ARG union ccb *ccb) 2656 { 2657 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2658 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2659 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2660 struct ccb_scsiio *csio = &ccb->csio; 2661 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2662 2663 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2664 ccb, 2665 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2666 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2667 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2668 )); 2669 2670 pAdapter->outstandingCommands++; 2671 2672 if (pVDev == NULL || pVDev->vf_online == 0) { 2673 ccb->ccb_h.status = CAM_REQ_INVALID; 2674 ccb_done(ccb); 2675 goto Command_Complished; 2676 } 2677 2678 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2679 { 2680 case TEST_UNIT_READY: 2681 case START_STOP_UNIT: 2682 case SYNCHRONIZE_CACHE: 2683 /* FALLTHROUGH */ 2684 ccb->ccb_h.status = CAM_REQ_CMP; 2685 break; 2686 2687 case INQUIRY: 2688 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2689 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2690 ccb_h->status = CAM_REQ_CMP; 2691 break; 2692 2693 case READ_CAPACITY: 2694 { 2695 UCHAR *rbuf=csio->data_ptr; 2696 unsigned int cap; 2697 2698 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2699 cap = 0xfffffffful; 2700 } else { 2701 cap = pVDev->VDeviceCapacity - 1; 2702 } 2703 2704 rbuf[0] = (UCHAR)(cap>>24); 2705 rbuf[1] = (UCHAR)(cap>>16); 2706 rbuf[2] = (UCHAR)(cap>>8); 2707 rbuf[3] = (UCHAR)cap; 2708 /* Claim 512 byte blocks (big-endian). */ 2709 rbuf[4] = 0; 2710 rbuf[5] = 0; 2711 rbuf[6] = 2; 2712 rbuf[7] = 0; 2713 2714 ccb_h->status = CAM_REQ_CMP; 2715 break; 2716 } 2717 2718 case 0x9e: /*SERVICE_ACTION_IN*/ 2719 { 2720 UCHAR *rbuf = csio->data_ptr; 2721 LBA_T cap = pVDev->VDeviceCapacity - 1; 2722 2723 rbuf[0] = (UCHAR)(cap>>56); 2724 rbuf[1] = (UCHAR)(cap>>48); 2725 rbuf[2] = (UCHAR)(cap>>40); 2726 rbuf[3] = (UCHAR)(cap>>32); 2727 rbuf[4] = (UCHAR)(cap>>24); 2728 rbuf[5] = (UCHAR)(cap>>16); 2729 rbuf[6] = (UCHAR)(cap>>8); 2730 rbuf[7] = (UCHAR)cap; 2731 rbuf[8] = 0; 2732 rbuf[9] = 0; 2733 rbuf[10] = 2; 2734 rbuf[11] = 0; 2735 2736 ccb_h->status = CAM_REQ_CMP; 2737 break; 2738 } 2739 2740 case READ_6: 2741 case WRITE_6: 2742 case READ_10: 2743 case WRITE_10: 2744 case 0x88: /* READ_16 */ 2745 case 0x8a: /* WRITE_16 */ 2746 case 0x13: 2747 case 0x2f: 2748 { 2749 UCHAR Cdb[16]; 2750 UCHAR CdbLength; 2751 _VBUS_INST(pVDev->pVBus) 2752 PCommand pCmd = AllocateCommand(_VBUS_P0); 2753 int error; 2754 HPT_ASSERT(pCmd); 2755 2756 CdbLength = csio->cdb_len; 2757 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2758 { 2759 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2760 { 2761 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2762 } 2763 else 2764 { 2765 KdPrintE(("ERROR!!!\n")); 2766 ccb->ccb_h.status = CAM_REQ_INVALID; 2767 break; 2768 } 2769 } 2770 else 2771 { 2772 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2773 } 2774 2775 pCmd->pOrgCommand = ccb; 2776 pCmd->pVDevice = pVDev; 2777 pCmd->pfnCompletion = fOsCommandDone; 2778 pCmd->pfnBuildSgl = fOsBuildSgl; 2779 pCmd->pSgTable = pmap->psg; 2780 2781 switch (Cdb[0]) 2782 { 2783 case READ_6: 2784 case WRITE_6: 2785 case 0x13: 2786 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2787 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2788 break; 2789 2790 case 0x88: /* READ_16 */ 2791 case 0x8a: /* WRITE_16 */ 2792 pCmd->uCmd.Ide.Lba = 2793 (HPT_U64)Cdb[2] << 56 | 2794 (HPT_U64)Cdb[3] << 48 | 2795 (HPT_U64)Cdb[4] << 40 | 2796 (HPT_U64)Cdb[5] << 32 | 2797 (HPT_U64)Cdb[6] << 24 | 2798 (HPT_U64)Cdb[7] << 16 | 2799 (HPT_U64)Cdb[8] << 8 | 2800 (HPT_U64)Cdb[9]; 2801 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2802 break; 2803 2804 default: 2805 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2806 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2807 break; 2808 } 2809 2810 switch (Cdb[0]) 2811 { 2812 case READ_6: 2813 case READ_10: 2814 case 0x88: /* READ_16 */ 2815 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2816 pCmd->cf_data_in = 1; 2817 break; 2818 2819 case WRITE_6: 2820 case WRITE_10: 2821 case 0x8a: /* WRITE_16 */ 2822 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2823 pCmd->cf_data_out = 1; 2824 break; 2825 case 0x13: 2826 case 0x2f: 2827 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2828 break; 2829 } 2830 /*///////////////////////// */ 2831 pCmd->cf_physical_sg = 1; 2832 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent, 2833 pmap->dma_map, 2834 ccb, 2835 hpt_io_dmamap_callback, 2836 pCmd, BUS_DMA_WAITOK 2837 ); 2838 KdPrint(("bus_dmamap_load return %d\n", error)); 2839 if (error && error!=EINPROGRESS) { 2840 hpt_printk(("bus_dmamap_load error %d\n", error)); 2841 FreeCommand(_VBUS_P pCmd); 2842 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2843 dmamap_put(pmap); 2844 pAdapter->outstandingCommands--; 2845 if (pAdapter->outstandingCommands == 0) 2846 wakeup(pAdapter); 2847 xpt_done(ccb); 2848 } 2849 goto Command_Complished; 2850 } 2851 2852 default: 2853 ccb->ccb_h.status = CAM_REQ_INVALID; 2854 break; 2855 } 2856 ccb_done(ccb); 2857 Command_Complished: 2858 CheckPendingCall(_VBUS_P0); 2859 return; 2860 } 2861 2862 static void HPTLIBAPI 2863 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2864 { 2865 union ccb *ccb = pCmd->pOrgCommand; 2866 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2867 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2868 2869 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2870 2871 callout_stop(&pmap->timeout); 2872 2873 switch(pCmd->Result) { 2874 case RETURN_SUCCESS: 2875 ccb->ccb_h.status = CAM_REQ_CMP; 2876 break; 2877 case RETURN_BAD_DEVICE: 2878 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2879 break; 2880 case RETURN_DEVICE_BUSY: 2881 ccb->ccb_h.status = CAM_BUSY; 2882 break; 2883 case RETURN_INVALID_REQUEST: 2884 ccb->ccb_h.status = CAM_REQ_INVALID; 2885 break; 2886 case RETURN_SELECTION_TIMEOUT: 2887 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2888 break; 2889 case RETURN_RETRY: 2890 ccb->ccb_h.status = CAM_BUSY; 2891 break; 2892 default: 2893 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2894 break; 2895 } 2896 2897 if (pCmd->cf_data_in) { 2898 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2899 } 2900 else if (pCmd->cf_data_out) { 2901 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2902 } 2903 2904 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2905 2906 FreeCommand(_VBUS_P pCmd); 2907 ccb_done(ccb); 2908 } 2909 2910 int 2911 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2912 { 2913 int p; 2914 2915 mtx_lock(&DpcQueue_Lock); 2916 p = (DpcQueue_Last + 1) % MAX_DPC; 2917 if (p==DpcQueue_First) { 2918 KdPrint(("DPC Queue full!\n")); 2919 mtx_unlock(&DpcQueue_Lock); 2920 return -1; 2921 } 2922 2923 DpcQueue[DpcQueue_Last].dpc = dpc; 2924 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2925 DpcQueue[DpcQueue_Last].arg = arg; 2926 DpcQueue[DpcQueue_Last].flags = flags; 2927 DpcQueue_Last = p; 2928 mtx_unlock(&DpcQueue_Lock); 2929 2930 return 0; 2931 } 2932 2933 #ifdef _RAID5N_ 2934 /* 2935 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2936 * How about the memory for 5081 request/response array and PRD table? 2937 */ 2938 void 2939 *os_alloc_page(_VBUS_ARG0) 2940 { 2941 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2942 } 2943 2944 void 2945 *os_alloc_dma_page(_VBUS_ARG0) 2946 { 2947 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2948 } 2949 2950 void 2951 os_free_page(_VBUS_ARG void *p) 2952 { 2953 contigfree(p, 0x1000, M_DEVBUF); 2954 } 2955 2956 void 2957 os_free_dma_page(_VBUS_ARG void *p) 2958 { 2959 contigfree(p, 0x1000, M_DEVBUF); 2960 } 2961 2962 void 2963 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2964 { 2965 UINT i; 2966 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 2967 } 2968 2969 void 2970 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 2971 { 2972 UINT i; 2973 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 2974 } 2975 #endif 2976