1 /* 2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/malloc.h> 34 #include <sys/resource.h> 35 #include <sys/time.h> 36 #include <sys/callout.h> 37 #include <sys/signalvar.h> 38 #include <sys/eventhandler.h> 39 #include <sys/proc.h> 40 #include <sys/kthread.h> 41 42 #if (__FreeBSD_version >= 500000) 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #endif 46 47 #if (__FreeBSD_version >= 500000) 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #else 51 #include <pci/pcireg.h> 52 #include <pci/pcivar.h> 53 #include <machine/clock.h> 54 #include <sys/wait.h> 55 #include <sys/sysproto.h> 56 #endif 57 58 #ifndef __KERNEL__ 59 #define __KERNEL__ 60 #endif 61 62 #include <dev/hptmv/global.h> 63 #include <dev/hptmv/hptintf.h> 64 #include <dev/hptmv/osbsd.h> 65 #include <dev/hptmv/access601.h> 66 67 68 #ifdef DEBUG 69 #ifdef DEBUG_LEVEL 70 int hpt_dbg_level = DEBUG_LEVEL; 71 #else 72 int hpt_dbg_level = 0; 73 #endif 74 #endif 75 76 #define MV_ERROR printf 77 78 /* 79 * CAM SIM entry points 80 */ 81 static int hpt_probe (device_t dev); 82 static void launch_worker_thread(void); 83 static int hpt_attach(device_t dev); 84 static int hpt_detach(device_t dev); 85 static int hpt_shutdown(device_t dev); 86 static void hpt_poll(struct cam_sim *sim); 87 static void hpt_intr(void *arg); 88 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 89 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 90 91 static device_method_t driver_methods[] = { 92 /* Device interface */ 93 DEVMETHOD(device_probe, hpt_probe), 94 DEVMETHOD(device_attach, hpt_attach), 95 DEVMETHOD(device_detach, hpt_detach), 96 97 /* DEVMETHOD(device_shutdown, hpt_shutdown), */ 98 { 0, 0 } 99 }; 100 101 static driver_t hpt_pci_driver = { 102 __str(PROC_DIR_NAME), 103 driver_methods, 104 sizeof(IAL_ADAPTER_T) 105 }; 106 107 static devclass_t hpt_devclass; 108 109 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 110 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 111 112 #define ccb_ccb_ptr spriv_ptr0 113 #define ccb_adapter ccb_h.spriv_ptr1 114 115 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 116 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 117 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 118 static void ccb_done(union ccb *ccb); 119 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 120 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 121 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 122 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 123 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 124 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 125 static int fResetActiveCommands(PVBus _vbus_p); 126 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 127 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 128 static void hptmv_handle_event_disconnect(void *data); 129 static void hptmv_handle_event_connect(void *data); 130 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 131 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 132 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 133 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 134 int logical); 135 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 136 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 137 MV_U16 responseFlags, MV_U32 timeStamp, 138 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 139 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 140 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 141 142 #define ccb_ccb_ptr spriv_ptr0 143 #define ccb_adapter ccb_h.spriv_ptr1 144 145 IAL_ADAPTER_T *gIal_Adapter = 0; 146 IAL_ADAPTER_T *pCurAdapter = 0; 147 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 148 149 typedef struct st_HPT_DPC { 150 IAL_ADAPTER_T *pAdapter; 151 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 152 void *arg; 153 UCHAR flags; 154 } ST_HPT_DPC; 155 156 #define MAX_DPC 16 157 UCHAR DPC_Request_Nums = 0; 158 static ST_HPT_DPC DpcQueue[MAX_DPC]; 159 static int DpcQueue_First=0; 160 static int DpcQueue_Last = 0; 161 162 char DRIVER_VERSION[] = "v1.12"; 163 164 #if (__FreeBSD_version >= 500000) 165 static struct mtx driver_lock; 166 intrmask_t lock_driver() 167 { 168 169 intrmask_t spl = 0; 170 mtx_lock_spin(&driver_lock); 171 return spl; 172 } 173 void unlock_driver(intrmask_t spl) 174 { 175 mtx_unlock_spin(&driver_lock); 176 } 177 #else 178 static int driver_locked = 0; 179 intrmask_t lock_driver() 180 { 181 intrmask_t spl = splcam(); 182 loop: 183 while (driver_locked) 184 tsleep(&driver_locked, PRIBIO, "hptlck", hz); 185 atomic_add_int(&driver_locked, 1); 186 if (driver_locked>1) { 187 atomic_subtract_int(&driver_locked, 1); 188 goto loop; 189 } 190 return spl; 191 } 192 193 void unlock_driver(intrmask_t spl) 194 { 195 atomic_subtract_int(&driver_locked, 1); 196 if (driver_locked==0) { 197 wakeup(&driver_locked); 198 } 199 splx(spl); 200 } 201 #endif 202 203 /******************************************************************************* 204 * Name: hptmv_free_channel 205 * 206 * Description: free allocated queues for the given channel 207 * 208 * Parameters: pMvSataAdapter - pointer to the RR182x controler this 209 * channel connected to. 210 * channelNum - channel number. 211 * 212 ******************************************************************************/ 213 static void 214 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 215 { 216 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 217 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 218 } 219 220 static void failDevice(PVDevice pVDev) 221 { 222 PVBus _vbus_p = pVDev->pVBus; 223 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 224 225 pVDev->u.disk.df_on_line = 0; 226 pVDev->vf_online = 0; 227 if (pVDev->pfnDeviceFailed) 228 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 229 230 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 231 232 #ifndef FOR_DEMO 233 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 234 pAdapter->beeping = 1; 235 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 236 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 237 } 238 #endif 239 } 240 241 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 242 /*void fDeviceSendCommand(_VBUS_ARG PCommand pCmd); */ 243 244 static void 245 handleEdmaError(_VBUS_ARG PCommand pCmd) 246 { 247 PDevice pDevice = &pCmd->pVDevice->u.disk; 248 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 249 250 if (!pDevice->df_on_line) { 251 KdPrint(("Device is offline")); 252 pCmd->Result = RETURN_BAD_DEVICE; 253 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 254 return; 255 } 256 257 if (pCmd->RetryCount++>5) { 258 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 259 failed: 260 failDevice(pCmd->pVDevice); 261 pCmd->Result = RETURN_IDE_ERROR; 262 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 263 return; 264 } 265 266 /* reset the channel and retry the command */ 267 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 268 goto failed; 269 270 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 271 272 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 273 fDeviceSendCommand(_VBUS_P pCmd); 274 } 275 276 /**************************************************************** 277 * Name: hptmv_init_channel 278 * 279 * Description: allocate request and response queues for the EDMA of the 280 * given channel and sets other fields. 281 * 282 * Parameters: 283 * pAdapter - pointer to the emulated adapter data structure 284 * channelNum - channel number. 285 * Return: 0 on success, otherwise on failure 286 ****************************************************************/ 287 static int 288 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 289 { 290 MV_SATA_CHANNEL *pMvSataChannel; 291 dma_addr_t req_dma_addr; 292 dma_addr_t rsp_dma_addr; 293 294 if (channelNum >= MV_SATA_CHANNELS_NUM) 295 { 296 MV_ERROR("RR182x[%d]: Bad channelNum=%d", 297 pAdapter->mvSataAdapter.adapterId, channelNum); 298 return -1; 299 } 300 301 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 302 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 303 pMvSataChannel->channelNumber = channelNum; 304 pMvSataChannel->lba48Address = MV_FALSE; 305 pMvSataChannel->maxReadTransfer = MV_FALSE; 306 307 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 308 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 309 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 310 311 312 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 313 314 /* check the 1K alignment of the request queue*/ 315 if (req_dma_addr & 0x3ff) 316 { 317 MV_ERROR("RR182x[%d]: request queue allocated isn't 1 K aligned," 318 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 319 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 320 return -1; 321 } 322 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 323 pMvSataChannel->requestQueuePciHiAddress = 0; 324 KdPrint(("RR182x[%d,%d]: request queue allocated: 0x%p", 325 pAdapter->mvSataAdapter.adapterId, channelNum, 326 pMvSataChannel->requestQueue)); 327 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 328 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 329 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 330 331 /* check the 256 alignment of the response queue*/ 332 if (rsp_dma_addr & 0xff) 333 { 334 MV_ERROR("RR182x[%d,%d]: response queue allocated isn't 256 byte " 335 "aligned, dma_addr=%llx\n", 336 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 337 return -1; 338 } 339 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 340 pMvSataChannel->responseQueuePciHiAddress = 0; 341 KdPrint(("RR182x[%d,%d]: response queue allocated: 0x%p", 342 pAdapter->mvSataAdapter.adapterId, channelNum, 343 pMvSataChannel->responseQueue)); 344 345 pAdapter->mvChannel[channelNum].online = MV_TRUE; 346 return 0; 347 } 348 349 /****************************************************************************** 350 * Name: hptmv_parse_identify_results 351 * 352 * Description: this functions parses the identify command results, checks 353 * that the connected deives can be accesed by RR182x EDMA, 354 * and updates the channel stucture accordingly. 355 * 356 * Parameters: pMvSataChannel, pointer to the channel data structure. 357 * 358 * Returns: =0 ->success, < 0 ->failure. 359 * 360 ******************************************************************************/ 361 static int 362 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 363 { 364 MV_U16 *iden = pMvSataChannel->identifyDevice; 365 366 /*LBA addressing*/ 367 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 368 { 369 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 370 return -1; 371 } 372 else 373 { 374 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 375 } 376 /*DMA support*/ 377 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 378 { 379 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 380 return -1; 381 } 382 else 383 { 384 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 385 } 386 /* PIO */ 387 if ((iden[IDEN_VALID] & 2) == 0) 388 { 389 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 390 return -1; 391 } 392 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 393 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 394 395 /*UDMA*/ 396 if ((iden[IDEN_VALID] & 4) == 0) 397 { 398 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 399 return -1; 400 } 401 402 /* 48 bit address */ 403 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 404 { 405 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 406 pMvSataChannel->lba48Address = MV_TRUE; 407 } 408 else 409 { 410 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 411 pMvSataChannel->lba48Address = MV_FALSE; 412 } 413 return 0; 414 } 415 416 static void 417 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 418 { 419 PVDevice pVDev = &pAdapter->VDevices[channel]; 420 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 421 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 422 423 pMvSataChannel->outstandingCommands = 0; 424 425 pVDev->u.disk.mv = pMvSataChannel; 426 pVDev->u.disk.df_on_line = 1; 427 pVDev->u.disk.pVBus = &pAdapter->VBus; 428 pVDev->pVBus = &pAdapter->VBus; 429 430 #ifdef SUPPORT_48BIT_LBA 431 if (pMvSataChannel->lba48Address == MV_TRUE) 432 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 433 else 434 #endif 435 if(IdentifyData[53] & 1) { 436 pVDev->u.disk.dDeRealCapacity = 437 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 438 (IdentifyData[61]<<16 | IdentifyData[60]) : 439 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 440 } else 441 pVDev->u.disk.dDeRealCapacity = 442 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 443 444 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 445 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 446 447 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 448 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 449 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 450 } 451 } 452 453 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 454 { 455 PVDevice pVDev; 456 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 457 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 458 459 if (!pMvSataChannel) return; 460 461 if (plugged) 462 { 463 pVDev = &(pAdapter->VDevices[channelIndex]); 464 init_vdev_params(pAdapter, channelIndex); 465 466 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 467 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 468 469 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 470 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 471 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 472 pVDev->vf_online = 1; 473 474 #ifdef SUPPORT_ARRAY 475 if(pVDev->pParent) 476 { 477 int iMember; 478 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 479 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 480 pVDev->pParent->u.array.pMember[iMember] = NULL; 481 pVDev->pParent = NULL; 482 } 483 #endif 484 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 485 fCheckBootable(pVDev); 486 RegisterVDevice(pVDev); 487 488 #ifndef FOR_DEMO 489 if (pAdapter->beeping) { 490 pAdapter->beeping = 0; 491 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 492 } 493 #endif 494 495 } 496 else 497 { 498 pVDev = &(pAdapter->VDevices[channelIndex]); 499 failDevice(pVDev); 500 } 501 } 502 503 static int 504 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 505 { 506 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 507 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 508 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 509 MV_U32 udmaMode,pioMode; 510 511 KdPrint(("RR182x [%d]: start channel (%d)", pMvSataAdapter->adapterId, 512 channelNum)); 513 514 515 /* Software reset channel */ 516 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 517 { 518 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n", 519 pMvSataAdapter->adapterId, channelNum); 520 return -1; 521 } 522 523 /* Hardware reset channel */ 524 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 525 { 526 /* If failed, try again - this is when trying to hardreset a channel */ 527 /* when drive is just spinning up */ 528 StallExec(5000000); /* wait 5 sec before trying again */ 529 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 530 { 531 MV_ERROR("RR182x [%d,%d]: failed to perform Hard reset\n", 532 pMvSataAdapter->adapterId, channelNum); 533 return -1; 534 } 535 } 536 537 /* identify device*/ 538 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 539 { 540 MV_ERROR("RR182x [%d,%d]: failed to perform ATA Identify command\n" 541 , pMvSataAdapter->adapterId, channelNum); 542 return -1; 543 } 544 if (hptmv_parse_identify_results(pMvSataChannel)) 545 { 546 MV_ERROR("RR182x [%d,%d]: Error in parsing ATA Identify message\n" 547 , pMvSataAdapter->adapterId, channelNum); 548 return -1; 549 } 550 551 /* mvStorageDevATASetFeatures */ 552 /* Disable 8 bit PIO in case CFA enabled */ 553 if (pMvSataChannel->identifyDevice[86] & 4) 554 { 555 KdPrint(("RR182x [%d]: Disable 8 bit PIO (CFA enabled) \n", 556 pMvSataAdapter->adapterId)); 557 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 558 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 559 0, 0, 0) == MV_FALSE) 560 { 561 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures" 562 " failed\n", pMvSataAdapter->adapterId, channelNum); 563 return -1; 564 } 565 } 566 /* Write cache */ 567 #ifdef ENABLE_WRITE_CACHE 568 if (pMvSataChannel->identifyDevice[82] & 0x20) 569 { 570 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 571 { 572 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 573 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 574 0, 0, 0) == MV_FALSE) 575 { 576 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 577 pMvSataAdapter->adapterId, channelNum); 578 return -1; 579 } 580 } 581 KdPrint(("RR182x [%d]: channel %d, write cache enabled\n", 582 pMvSataAdapter->adapterId, channelNum)); 583 } 584 else 585 { 586 KdPrint(("RR182x [%d]: channel %d, write cache not supported\n", 587 pMvSataAdapter->adapterId, channelNum)); 588 } 589 #else /* disable write cache */ 590 { 591 if (pMvSataChannel->identifyDevice[85] & 0x20) 592 { 593 KdPrint(("RR182x [%d]: channel =%d, disable write cache\n", 594 pMvSataAdapter->adapterId, channelNum)); 595 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 596 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 597 0, 0, 0) == MV_FALSE) 598 { 599 MV_ERROR("RR182x [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 600 pMvSataAdapter->adapterId, channelNum); 601 return -1; 602 } 603 } 604 KdPrint(("RR182x [%d]: channel=%d, write cache disabled\n", 605 pMvSataAdapter->adapterId, channelNum)); 606 } 607 #endif 608 609 /* Set transfer mode */ 610 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_SLOW\n", 611 pMvSataAdapter->adapterId)); 612 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 613 MV_ATA_SET_FEATURES_TRANSFER, 614 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 615 MV_FALSE) 616 { 617 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 618 pMvSataAdapter->adapterId, channelNum); 619 return -1; 620 } 621 622 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 623 { 624 pioMode = MV_ATA_TRANSFER_PIO_4; 625 } 626 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 627 { 628 pioMode = MV_ATA_TRANSFER_PIO_3; 629 } 630 else 631 { 632 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 633 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 634 } 635 636 KdPrint(("RR182x [%d] Set transfer mode XFER_PIO_4\n", 637 pMvSataAdapter->adapterId)); 638 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 639 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 640 MV_ATA_SET_FEATURES_TRANSFER, 641 pioMode, 0, 0, 0) == MV_FALSE) 642 { 643 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 644 pMvSataAdapter->adapterId, channelNum); 645 return -1; 646 } 647 648 udmaMode = MV_ATA_TRANSFER_UDMA_0; 649 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 650 { 651 udmaMode = MV_ATA_TRANSFER_UDMA_6; 652 } 653 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 654 { 655 udmaMode = MV_ATA_TRANSFER_UDMA_5; 656 } 657 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 658 { 659 udmaMode = MV_ATA_TRANSFER_UDMA_4; 660 } 661 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 662 { 663 udmaMode = MV_ATA_TRANSFER_UDMA_3; 664 } 665 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 666 { 667 udmaMode = MV_ATA_TRANSFER_UDMA_2; 668 } 669 670 KdPrint(("RR182x [%d] Set transfer mode XFER_UDMA_%d\n", 671 pMvSataAdapter->adapterId, udmaMode & 0xf)); 672 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 673 674 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 675 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 676 0, 0, 0) == MV_FALSE) 677 { 678 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 679 pMvSataAdapter->adapterId, channelNum); 680 return -1; 681 }*/ 682 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 683 return TRUE; 684 else 685 do 686 { 687 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 688 MV_ATA_SET_FEATURES_TRANSFER, 689 pChannelInfo->maxUltraDmaModeSupported, 690 0, 0, 0) == MV_FALSE) 691 { 692 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 693 { 694 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 695 { 696 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 697 pMvSataChannel->eDmaRegsOffset + 698 0x11c, /* command reg */ 699 MV_ATA_COMMAND_IDLE_IMMEDIATE); 700 mvMicroSecondsDelay(10000); 701 mvSataChannelHardReset(pMvSataAdapter, channelNum); 702 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 703 return FALSE; 704 } 705 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 706 return FALSE; 707 pChannelInfo->maxUltraDmaModeSupported--; 708 continue; 709 } 710 else return FALSE; 711 } 712 break; 713 }while (1); 714 715 /* Read look ahead */ 716 #ifdef ENABLE_READ_AHEAD 717 if (pMvSataChannel->identifyDevice[82] & 0x40) 718 { 719 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 720 { 721 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 722 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 723 0, 0) == MV_FALSE) 724 { 725 MV_ERROR("RR182x [%d] channel %d: Set Features failed\n", 726 pMvSataAdapter->adapterId, channelNum); 727 return -1; 728 } 729 } 730 KdPrint(("RR182x [%d]: channel=%d, read look ahead enabled\n", 731 pMvSataAdapter->adapterId, channelNum)); 732 } 733 else 734 { 735 KdPrint(("RR182x [%d]: channel %d, Read Look Ahead not supported\n", 736 pMvSataAdapter->adapterId, channelNum)); 737 } 738 #else 739 { 740 if (pMvSataChannel->identifyDevice[86] & 0x20) 741 { 742 KdPrint(("RR182x [%d]:channel %d, disable read look ahead\n", 743 pMvSataAdapter->adapterId, channelNum)); 744 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 745 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 746 0, 0) == MV_FALSE) 747 { 748 MV_ERROR("RR182x [%d]:channel %d: ATA Set Features failed\n", 749 pMvSataAdapter->adapterId, channelNum); 750 return -1; 751 } 752 } 753 KdPrint(("RR182x [%d]:channel %d, read look ahead disabled\n", 754 pMvSataAdapter->adapterId, channelNum)); 755 } 756 #endif 757 758 759 { 760 KdPrint(("RR182x [%d]: channel %d config EDMA, Non Queued Mode\n", 761 pMvSataAdapter->adapterId, 762 channelNum)); 763 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 764 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 765 { 766 MV_ERROR("RR182x [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 767 pMvSataAdapter->adapterId, channelNum); 768 return -1; 769 } 770 } 771 /* Enable EDMA */ 772 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 773 { 774 MV_ERROR("RR182x [%d] Failed to enable DMA, channel=%d\n", 775 pMvSataAdapter->adapterId, channelNum); 776 return -1; 777 } 778 MV_ERROR("RR182x [%d,%d]: channel started successfully\n", 779 pMvSataAdapter->adapterId, channelNum); 780 781 #ifndef FOR_DEMO 782 set_fail_led(pMvSataAdapter, channelNum, 0); 783 #endif 784 return 0; 785 } 786 787 static void 788 hptmv_handle_event(void * data, int flag) 789 { 790 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 791 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 792 MV_U8 channelIndex; 793 794 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 795 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 796 { 797 switch(pAdapter->sataEvents[channelIndex]) 798 { 799 case SATA_EVENT_CHANNEL_CONNECTED: 800 /* Handle only connects */ 801 if (flag == 1) 802 break; 803 KdPrint(("RR182x [%d,%d]: new device connected\n", 804 pMvSataAdapter->adapterId, channelIndex)); 805 hptmv_init_channel(pAdapter, channelIndex); 806 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 807 { 808 MV_ERROR("RR182x [%d,%d] Failed to configure\n", 809 pMvSataAdapter->adapterId, channelIndex); 810 hptmv_free_channel(pAdapter, channelIndex); 811 } 812 else 813 { 814 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 815 if (start_channel( pAdapter, channelIndex)) 816 { 817 MV_ERROR("RR182x [%d,%d]Failed to start channel\n", 818 pMvSataAdapter->adapterId, channelIndex); 819 hptmv_free_channel(pAdapter, channelIndex); 820 } 821 else 822 { 823 device_change(pAdapter, channelIndex, TRUE); 824 } 825 } 826 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 827 break; 828 829 case SATA_EVENT_CHANNEL_DISCONNECTED: 830 /* Handle only disconnects */ 831 if (flag == 0) 832 break; 833 KdPrint(("RR182x [%d,%d]: device disconnected\n", 834 pMvSataAdapter->adapterId, channelIndex)); 835 /* Flush pending commands */ 836 if(pMvSataAdapter->sataChannel[channelIndex]) 837 { 838 _VBUS_INST(&pAdapter->VBus) 839 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 840 MV_FLUSH_TYPE_CALLBACK); 841 CheckPendingCall(_VBUS_P0); 842 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 843 hptmv_free_channel(pAdapter, channelIndex); 844 pMvSataAdapter->sataChannel[channelIndex] = NULL; 845 KdPrint(("RR182x [%d,%d]: channel removed\n", 846 pMvSataAdapter->adapterId, channelIndex)); 847 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 848 Check_Idle_Call(pAdapter); 849 } 850 else 851 { 852 KdPrint(("RR182x [%d,%d]: channel already removed!!\n", 853 pMvSataAdapter->adapterId, channelIndex)); 854 } 855 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 856 break; 857 858 case SATA_EVENT_NO_CHANGE: 859 break; 860 861 default: 862 break; 863 } 864 } 865 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 866 } 867 868 #define EVENT_CONNECT 1 869 #define EVENT_DISCONNECT 0 870 871 static void 872 hptmv_handle_event_connect(void *data) 873 { 874 hptmv_handle_event (data, 0); 875 } 876 877 static void 878 hptmv_handle_event_disconnect(void *data) 879 { 880 hptmv_handle_event (data, 1); 881 } 882 883 static MV_BOOLEAN 884 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 885 MV_U32 param1, MV_U32 param2) 886 { 887 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 888 889 switch (eventType) 890 { 891 case MV_EVENT_TYPE_SATA_CABLE: 892 { 893 MV_U8 channel = param2; 894 895 if (param1 == EVENT_CONNECT) 896 { 897 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 898 KdPrint(("RR182x [%d,%d]: device connected event received\n", 899 pMvSataAdapter->adapterId, channel)); 900 /* Delete previous timers (if multiple drives connected in the same time */ 901 pAdapter->event_timer_connect = timeout(hptmv_handle_event_connect, pAdapter, 10*hz); 902 } 903 else if (param1 == EVENT_DISCONNECT) 904 { 905 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 906 KdPrint(("RR182x [%d,%d]: device disconnected event received \n", 907 pMvSataAdapter->adapterId, channel)); 908 device_change(pAdapter, channel, FALSE); 909 /* Delete previous timers (if multiple drives disconnected in the same time */ 910 /*pAdapter->event_timer_disconnect = timeout(hptmv_handle_event_disconnect, pAdapter, 10*hz); */ 911 /*It is not necessary to wait, handle it directly*/ 912 hptmv_handle_event_disconnect(pAdapter); 913 } 914 else 915 { 916 917 MV_ERROR("RR182x: illigal value for param1(%d) at " 918 "connect/disconect event, host=%d\n", param1, 919 pMvSataAdapter->adapterId ); 920 921 } 922 } 923 break; 924 case MV_EVENT_TYPE_ADAPTER_ERROR: 925 KdPrint(("RR182x: DEVICE error event received, pci cause " 926 "reg=%x, don't how to handle this\n", param1)); 927 return MV_TRUE; 928 default: 929 MV_ERROR("RR182x[%d]: unknown event type (%d)\n", 930 pMvSataAdapter->adapterId, eventType); 931 return MV_FALSE; 932 } 933 return MV_TRUE; 934 } 935 936 static int 937 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 938 { 939 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 940 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 941 if (pAdapter->requestsArrayBaseAddr == NULL) 942 { 943 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA request" 944 " queues\n", pAdapter->mvSataAdapter.adapterId); 945 return -1; 946 } 947 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 948 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 949 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 950 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 951 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 952 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 953 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 954 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 955 956 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 957 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 958 { 959 MV_ERROR("RR182x[%d]: Error in Request Quueues Alignment\n", 960 pAdapter->mvSataAdapter.adapterId); 961 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 962 return -1; 963 } 964 /* response queues */ 965 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 966 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 967 if (pAdapter->responsesArrayBaseAddr == NULL) 968 { 969 MV_ERROR("RR182x[%d]: Failed to allocate memory for EDMA response" 970 " queues\n", pAdapter->mvSataAdapter.adapterId); 971 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 972 return -1; 973 } 974 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 975 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 976 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 977 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 978 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 979 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 980 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 981 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 982 983 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 984 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 985 { 986 MV_ERROR("RR182x[%d]: Error in Response Quueues Alignment\n", 987 pAdapter->mvSataAdapter.adapterId); 988 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 989 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 990 return -1; 991 } 992 return 0; 993 } 994 995 static void 996 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 997 { 998 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 999 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 1000 } 1001 1002 static PVOID 1003 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 1004 { 1005 PVOID ret; 1006 if (pAdapter->pFreePRDLink) { 1007 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 1008 ret = pAdapter->pFreePRDLink; 1009 pAdapter->pFreePRDLink = *(void**)ret; 1010 return ret; 1011 } 1012 return NULL; 1013 } 1014 1015 static void 1016 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 1017 { 1018 *(void**)PRDTable = pAdapter->pFreePRDLink; 1019 pAdapter->pFreePRDLink = PRDTable; 1020 } 1021 1022 extern PVDevice fGetFirstChild(PVDevice pLogical); 1023 extern void fResetBootMark(PVDevice pLogical); 1024 static void 1025 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 1026 { 1027 PVDevice pPhysical, pLogical; 1028 PVBus pVBus; 1029 int i,j; 1030 1031 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 1032 pPhysical = &(pAdapter->VDevices[i]); 1033 pLogical = pPhysical; 1034 while (pLogical->pParent) pLogical = pLogical->pParent; 1035 if (pLogical->vf_online==0) { 1036 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 1037 continue; 1038 } 1039 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1040 continue; 1041 1042 pVBus = &pAdapter->VBus; 1043 if(pVBus) 1044 { 1045 j=0; 1046 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1047 if(j<MAX_VDEVICE_PER_VBUS){ 1048 pVBus->pVDevice[j] = pLogical; 1049 pLogical->pVBus = pVBus; 1050 1051 if (j>0 && pLogical->vf_bootmark) { 1052 if (pVBus->pVDevice[0]->vf_bootmark) { 1053 fResetBootMark(pLogical); 1054 } 1055 else { 1056 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1057 pVBus->pVDevice[0] = pLogical; 1058 } 1059 } 1060 } 1061 } 1062 } 1063 } 1064 1065 PVDevice 1066 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1067 { 1068 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1069 ULONG capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1070 ULONG thiscap, maxcap = MAX_LBA_T; 1071 PVDevice pVDevice, pFind = NULL; 1072 int i; 1073 1074 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1075 { 1076 pVDevice = &pAdapter->VDevices[i]; 1077 if(!pVDevice) 1078 continue; 1079 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1080 /* find the smallest usable spare disk */ 1081 if (pVDevice->VDeviceType==VD_SPARE && 1082 pVDevice->u.disk.df_on_line && 1083 thiscap < maxcap && 1084 thiscap >= capacity) 1085 { 1086 maxcap = pVDevice->VDeviceCapacity; 1087 pFind = pVDevice; 1088 } 1089 } 1090 return pFind; 1091 } 1092 1093 /****************************************************************** 1094 * IO ATA Command 1095 *******************************************************************/ 1096 int HPTLIBAPI 1097 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1098 { 1099 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1100 } 1101 1102 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1103 { 1104 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1105 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1106 MV_U8 channelIndex = pSataChannel->channelNumber; 1107 UCHAR mvMode; 1108 /* 508x don't use MW-DMA? */ 1109 if (NewMode>4 && NewMode<8) NewMode = 4; 1110 pDev->bDeModeSetting = NewMode; 1111 if (NewMode<=4) 1112 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1113 else 1114 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1115 1116 /*To fix 88i8030 bug*/ 1117 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1118 mvMode = MV_ATA_TRANSFER_UDMA_0; 1119 1120 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1121 /* Flush pending commands */ 1122 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1123 1124 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1125 MV_ATA_SET_FEATURES_TRANSFER, 1126 mvMode, 0, 0, 0) == MV_FALSE) 1127 { 1128 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1129 } 1130 /* Enable EDMA */ 1131 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1132 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1133 } 1134 1135 #ifdef SUPPORT_ARRAY 1136 #define IdeRegisterVDevice fCheckArray 1137 #else 1138 void 1139 IdeRegisterVDevice(PDevice pDev) 1140 { 1141 PVDevice pVDev = Map2pVDevice(pDev); 1142 1143 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1144 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1145 pVDev->vf_online = 1; 1146 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1147 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1148 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1149 } 1150 #endif 1151 1152 static __inline PBUS_DMAMAP 1153 dmamap_get(struct IALAdapter * pAdapter) 1154 { 1155 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1156 if (p) 1157 pAdapter->pbus_dmamap_list = p-> next; 1158 return p; 1159 } 1160 1161 static __inline void 1162 dmamap_put(PBUS_DMAMAP p) 1163 { 1164 p->next = p->pAdapter->pbus_dmamap_list; 1165 p->pAdapter->pbus_dmamap_list = p; 1166 } 1167 1168 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/ 1169 #if __FreeBSD_version >= 500000 1170 static void hpt_init(void *dummy) 1171 { 1172 mtx_init(&driver_lock, "hptlock", NULL, MTX_SPIN); 1173 } 1174 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL); 1175 #endif 1176 1177 static int num_adapters = 0; 1178 static int 1179 init_adapter(IAL_ADAPTER_T *pAdapter) 1180 { 1181 PVBus _vbus_p = &pAdapter->VBus; 1182 MV_SATA_ADAPTER *pMvSataAdapter; 1183 int i, channel, rid; 1184 1185 PVDevice pVDev; 1186 1187 intrmask_t oldspl = lock_driver(); 1188 1189 pAdapter->next = 0; 1190 1191 if(gIal_Adapter == 0){ 1192 gIal_Adapter = pAdapter; 1193 pCurAdapter = gIal_Adapter; 1194 } 1195 else { 1196 pCurAdapter->next = pAdapter; 1197 pCurAdapter = pAdapter; 1198 } 1199 1200 pAdapter->outstandingCommands = 0; 1201 1202 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1203 _vbus_p->OsExt = (void *)pAdapter; 1204 pMvSataAdapter->IALData = pAdapter; 1205 1206 if (bus_dma_tag_create(NULL,/* parent */ 1207 4, /* alignment */ 1208 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1209 BUS_SPACE_MAXADDR, /* lowaddr */ 1210 BUS_SPACE_MAXADDR, /* highaddr */ 1211 NULL, NULL, /* filter, filterarg */ 1212 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1213 MAX_SG_DESCRIPTORS, /* nsegments */ 1214 0x10000, /* maxsegsize */ 1215 BUS_DMA_WAITOK, /* flags */ 1216 #if __FreeBSD_version>502000 1217 busdma_lock_mutex, /* lockfunc */ 1218 &driver_lock, /* lockfuncarg */ 1219 #endif 1220 &pAdapter->io_dma_parent /* tag */)) 1221 { 1222 return ENXIO;; 1223 } 1224 1225 1226 if (hptmv_allocate_edma_queues(pAdapter)) 1227 { 1228 MV_ERROR("RR182x: Failed to allocate memory for EDMA queues\n"); 1229 unlock_driver(oldspl); 1230 return ENOMEM; 1231 } 1232 1233 /* also map EPROM address */ 1234 rid = 0x10; 1235 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid, 1236 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE)) 1237 || 1238 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1239 { 1240 MV_ERROR("RR182x: Failed to remap memory space\n"); 1241 hptmv_free_edma_queues(pAdapter); 1242 unlock_driver(oldspl); 1243 return ENXIO; 1244 } 1245 else 1246 { 1247 KdPrint(("RR182x: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1248 } 1249 1250 pMvSataAdapter->adapterId = num_adapters++; 1251 /* get the revision ID */ 1252 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1253 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1254 1255 /* init RR182x */ 1256 pMvSataAdapter->intCoalThre[0]= 1; 1257 pMvSataAdapter->intCoalThre[1]= 1; 1258 pMvSataAdapter->intTimeThre[0] = 1; 1259 pMvSataAdapter->intTimeThre[1] = 1; 1260 pMvSataAdapter->pciCommand = 0x0107E371; 1261 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1262 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1263 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1264 1265 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1266 { 1267 MV_ERROR("RR182x[%d]: core failed to initialize the adapter\n", 1268 pMvSataAdapter->adapterId); 1269 unregister: 1270 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1271 hptmv_free_edma_queues(pAdapter); 1272 unlock_driver(oldspl); 1273 return ENXIO; 1274 } 1275 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1276 1277 #ifndef FOR_DEMO 1278 set_fail_leds(pMvSataAdapter, 0); 1279 #endif 1280 1281 /* setup command blocks */ 1282 KdPrint(("Allocate command blocks\n")); 1283 _vbus_(pFreeCommands) = 0; 1284 pAdapter->pCommandBlocks = 1285 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1286 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1287 if (!pAdapter->pCommandBlocks) { 1288 MV_ERROR("insufficient memory\n"); 1289 goto unregister; 1290 } 1291 1292 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1293 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1294 } 1295 1296 /*Set up the bus_dmamap*/ 1297 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1298 if(!pAdapter->pbus_dmamap) { 1299 MV_ERROR("insufficient memory\n"); 1300 free(pAdapter->pCommandBlocks, M_DEVBUF); 1301 goto unregister; 1302 } 1303 1304 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1305 pAdapter->pbus_dmamap_list = 0; 1306 for (i=0; i < MAX_QUEUE_COMM; i++) { 1307 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1308 pmap->pAdapter = pAdapter; 1309 dmamap_put(pmap); 1310 1311 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1312 MV_ERROR("Can not allocate dma map\n"); 1313 free(pAdapter->pCommandBlocks, M_DEVBUF); 1314 free(pAdapter->pbus_dmamap, M_DEVBUF); 1315 goto unregister; 1316 } 1317 } 1318 /* setup PRD Tables */ 1319 KdPrint(("Allocate PRD Tables\n")); 1320 pAdapter->pFreePRDLink = 0; 1321 1322 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1323 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1324 1325 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1326 if (!pAdapter->prdTableAddr) { 1327 MV_ERROR("insufficient PRD Tables\n"); 1328 goto unregister; 1329 } 1330 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1331 { 1332 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1333 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1334 { 1335 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1336 FreePRDTable(pAdapter, PRDTable); 1337 PRDTable += PRD_ENTRIES_SIZE; 1338 } 1339 } 1340 1341 /* enable the adapter interrupts */ 1342 1343 /* configure and start the connected channels*/ 1344 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1345 { 1346 pAdapter->mvChannel[channel].online = MV_FALSE; 1347 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1348 == MV_TRUE) 1349 { 1350 KdPrint(("RR182x[%d]: channel %d is connected\n", 1351 pMvSataAdapter->adapterId, channel)); 1352 1353 if (hptmv_init_channel(pAdapter, channel) == 0) 1354 { 1355 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1356 { 1357 MV_ERROR("RR182x[%d]: Failed to configure channel" 1358 " %d\n",pMvSataAdapter->adapterId, channel); 1359 hptmv_free_channel(pAdapter, channel); 1360 } 1361 else 1362 { 1363 if (start_channel(pAdapter, channel)) 1364 { 1365 MV_ERROR("RR182x[%d]: Failed to start channel," 1366 " channel=%d\n",pMvSataAdapter->adapterId, 1367 channel); 1368 hptmv_free_channel(pAdapter, channel); 1369 } 1370 pAdapter->mvChannel[channel].online = MV_TRUE; 1371 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1372 channel, 1373 MV_TRUE);*/ 1374 } 1375 } 1376 } 1377 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1378 pAdapter->mvChannel[channel].online, channel)); 1379 } 1380 1381 #ifdef SUPPORT_ARRAY 1382 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1383 pVDev = ArrayTables(i); 1384 mArFreeArrayTable(pVDev); 1385 } 1386 #endif 1387 1388 KdPrint(("Initialize Devices\n")); 1389 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1390 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1391 if (pMvSataChannel) { 1392 init_vdev_params(pAdapter, channel); 1393 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1394 } 1395 } 1396 #ifdef SUPPORT_ARRAY 1397 CheckArrayCritical(_VBUS_P0); 1398 #endif 1399 _vbus_p->nInstances = 1; 1400 fRegisterVdevice(pAdapter); 1401 1402 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1403 pVDev = _vbus_p->pVDevice[channel]; 1404 if (pVDev && pVDev->vf_online) 1405 fCheckBootable(pVDev); 1406 } 1407 1408 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1409 init_raid5_memory(_VBUS_P0); 1410 _vbus_(r5).enable_write_back = 1; 1411 printf("RR182x: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1412 #endif 1413 1414 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1415 unlock_driver(oldspl); 1416 return 0; 1417 } 1418 1419 int 1420 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1421 { 1422 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1423 1424 mvSataDisableChannelDma(pMvSataAdapter, channel); 1425 /* Flush pending commands */ 1426 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1427 1428 /* Software reset channel */ 1429 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1430 { 1431 MV_ERROR("RR182x [%d,%d]: failed to perform Software reset\n", 1432 pMvSataAdapter->adapterId, channel); 1433 hptmv_free_channel(pAdapter, channel); 1434 return -1; 1435 } 1436 1437 /* Hardware reset channel */ 1438 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1439 { 1440 MV_ERROR("RR182x [%d,%d] Failed to Hard reser the SATA channel\n", 1441 pMvSataAdapter->adapterId, channel); 1442 hptmv_free_channel(pAdapter, channel); 1443 return -1; 1444 } 1445 1446 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1447 { 1448 MV_ERROR("RR182x [%d,%d] Failed to Connect Device\n", 1449 pMvSataAdapter->adapterId, channel); 1450 hptmv_free_channel(pAdapter, channel); 1451 return -1; 1452 }else 1453 { 1454 MV_ERROR("channel %d: perform recalibrate command", channel); 1455 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1456 MV_NON_UDMA_PROTOCOL_NON_DATA, 1457 MV_FALSE, 1458 NULL, /* pBuffer*/ 1459 0, /* count */ 1460 0, /*features*/ 1461 /* sectorCount */ 1462 0, 1463 0, /* lbaLow */ 1464 0, /* lbaMid */ 1465 /* lbaHigh */ 1466 0, 1467 0, /* device */ 1468 /* command */ 1469 0x10)) 1470 MV_ERROR("channel %d: recalibrate failed", channel); 1471 1472 /* Set transfer mode */ 1473 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1474 MV_ATA_SET_FEATURES_TRANSFER, 1475 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1476 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1477 MV_ATA_SET_FEATURES_TRANSFER, 1478 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1479 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1480 MV_ATA_SET_FEATURES_TRANSFER, 1481 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1482 { 1483 MV_ERROR("channel %d: Set Features failed", channel); 1484 hptmv_free_channel(pAdapter, channel); 1485 return -1; 1486 } 1487 /* Enable EDMA */ 1488 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1489 { 1490 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1491 hptmv_free_channel(pAdapter, channel); 1492 return -1; 1493 } 1494 } 1495 return 0; 1496 } 1497 1498 static int 1499 fResetActiveCommands(PVBus _vbus_p) 1500 { 1501 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1502 MV_U8 channel; 1503 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1504 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1505 MvSataResetChannel(pMvSataAdapter,channel); 1506 } 1507 return 0; 1508 } 1509 1510 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1511 { 1512 UINT cont; 1513 ULONG ticks = 0; 1514 MV_U8 channel; 1515 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1516 MV_SATA_CHANNEL *pMvSataChannel; 1517 1518 do { 1519 check_cmds: 1520 cont = 0; 1521 CheckPendingCall(_VBUS_P0); 1522 #ifdef _RAID5N_ 1523 dataxfer_poll(); 1524 xor_poll(); 1525 #endif 1526 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1527 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1528 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1529 { 1530 while (pMvSataChannel->outstandingCommands) { 1531 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1532 StallExec(1000); 1533 if (ticks++ > 3000) { 1534 MvSataResetChannel(pMvSataAdapter,channel); 1535 goto check_cmds; 1536 } 1537 } 1538 else 1539 ticks = 0; 1540 } 1541 cont = 1; 1542 } 1543 } 1544 } while (cont); 1545 } 1546 1547 void 1548 fResetVBus(_VBUS_ARG0) 1549 { 1550 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1551 1552 /* some commands may already finished. */ 1553 CheckPendingCall(_VBUS_P0); 1554 1555 fResetActiveCommands(_vbus_p); 1556 /* 1557 * the other pending commands may still be finished successfully. 1558 */ 1559 fCompleteAllCommandsSynchronously(_vbus_p); 1560 1561 /* Now there should be no pending commands. No more action needed. */ 1562 CheckIdleCall(_VBUS_P0); 1563 1564 KdPrint(("fMvResetBus() done")); 1565 } 1566 1567 /*No rescan function*/ 1568 void 1569 fRescanAllDevice(_VBUS_ARG0) 1570 { 1571 } 1572 1573 static MV_BOOLEAN 1574 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1575 MV_U8 channelNum, 1576 MV_COMPLETION_TYPE comp_type, 1577 MV_VOID_PTR commandId, 1578 MV_U16 responseFlags, 1579 MV_U32 timeStamp, 1580 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1581 { 1582 PCommand pCmd = (PCommand) commandId; 1583 _VBUS_INST(pCmd->pVDevice->pVBus) 1584 1585 if (pCmd->uScratch.sata_param.prdAddr) 1586 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1587 1588 switch (comp_type) 1589 { 1590 case MV_COMPLETION_TYPE_NORMAL: 1591 pCmd->Result = RETURN_SUCCESS; 1592 break; 1593 case MV_COMPLETION_TYPE_ABORT: 1594 pCmd->Result = RETURN_BUS_RESET; 1595 break; 1596 case MV_COMPLETION_TYPE_ERROR: 1597 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1598 pMvSataAdapter->adapterId, channelNum, responseFlags); 1599 1600 if (responseFlags & 4) { 1601 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1602 " LBA high %x, device %x, status %x\n", 1603 registerStruct->errorRegister, 1604 registerStruct->sectorCountRegister, 1605 registerStruct->lbaLowRegister, 1606 registerStruct->lbaMidRegister, 1607 registerStruct->lbaHighRegister, 1608 registerStruct->deviceRegister, 1609 registerStruct->statusRegister); 1610 } 1611 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1612 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1613 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1614 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1615 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1616 pCmd->pVDevice->u.disk.QueueLength--; 1617 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1618 return TRUE; 1619 1620 default: 1621 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1622 return MV_FALSE; 1623 } 1624 1625 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1626 pCmd->uScratch.sata_param.cmd_priv --; 1627 return TRUE; 1628 } 1629 pCmd->pVDevice->u.disk.QueueLength--; 1630 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1631 return TRUE; 1632 } 1633 1634 void 1635 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1636 { 1637 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1638 MV_SATA_ADAPTER *pMvSataAdapter; 1639 MV_SATA_CHANNEL *pMvSataChannel; 1640 PVDevice pVDevice = pCmd->pVDevice; 1641 PDevice pDevice = &pVDevice->u.disk; 1642 ULONG Lba = pCmd->uCmd.Ide.Lba; 1643 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1644 1645 MV_QUEUE_COMMAND_RESULT result; 1646 MV_QUEUE_COMMAND_INFO commandInfo; 1647 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1648 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1649 1650 MV_BOOLEAN is48bit = MV_FALSE; 1651 MV_U8 channel; 1652 int i=0; 1653 1654 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1655 1656 if (!pDevice->df_on_line) { 1657 MV_ERROR("Device is offline"); 1658 pCmd->Result = RETURN_BAD_DEVICE; 1659 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1660 return; 1661 } 1662 1663 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1664 pMvSataChannel = pDevice->mv; 1665 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1666 channel = pMvSataChannel->channelNumber; 1667 1668 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1669 Lba += pDevice->dDeHiddenLba; 1670 /* check LBA */ 1671 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1672 pCmd->Result = RETURN_INVALID_REQUEST; 1673 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1674 return; 1675 } 1676 1677 if(Lba & 0xF0000000){ 1678 is48bit = MV_TRUE; 1679 } 1680 1681 switch (pCmd->uCmd.Ide.Command) 1682 { 1683 case IDE_COMMAND_READ: 1684 case IDE_COMMAND_WRITE: 1685 if (pDevice->bDeModeSetting<8) goto pio; 1686 1687 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1688 pUdmaParams->isEXT = is48bit; 1689 pUdmaParams->numOfSectors = nSector; 1690 pUdmaParams->lowLBAAddress = Lba; 1691 pUdmaParams->highLBAAddress = 0; 1692 pUdmaParams->prdHighAddr = 0; 1693 pUdmaParams->callBack = CommandCompletionCB; 1694 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1695 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1696 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1697 else 1698 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1699 1700 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1701 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1702 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1703 } 1704 else { 1705 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1706 pio: 1707 mvSataDisableChannelDma(pMvSataAdapter, channel); 1708 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1709 1710 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1711 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1712 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1713 } 1714 else { 1715 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1716 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1717 goto finish_cmd; 1718 } 1719 } 1720 1721 do { 1722 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1723 ULONG_PTR addr = tmpSg->dSgAddress; 1724 if (size & 0x1ff) { 1725 pCmd->Result = RETURN_INVALID_REQUEST; 1726 goto finish_cmd; 1727 } 1728 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1729 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1730 is48bit, 1731 (MV_U16_PTR)addr, 1732 size >> 1, /* count */ 1733 0, /* features N/A */ 1734 (MV_U16)(size>>9), /*sector count*/ 1735 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1736 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1737 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1738 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1739 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1740 )==MV_FALSE) 1741 { 1742 pCmd->Result = RETURN_IDE_ERROR; 1743 goto finish_cmd; 1744 } 1745 Lba += size>>9; 1746 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1747 } 1748 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1749 pCmd->Result = RETURN_SUCCESS; 1750 finish_cmd: 1751 mvSataEnableChannelDma(pMvSataAdapter,channel); 1752 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1753 return; 1754 } 1755 } 1756 1757 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1758 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1759 if (!pPRDTable) { 1760 pCmd->Result = RETURN_DEVICE_BUSY; 1761 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1762 HPT_ASSERT(0); 1763 return; 1764 } 1765 1766 do{ 1767 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1768 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1769 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1770 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1771 pPRDTable[i].reserved = 0; 1772 i++; 1773 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1774 1775 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1776 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1777 pUdmaParams->numOfSectors = 0; 1778 } 1779 1780 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1781 1782 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1783 1784 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1785 { 1786 queue_failed: 1787 switch (result) 1788 { 1789 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1790 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1791 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1792 pCmd->Result = RETURN_IDE_ERROR; 1793 break; 1794 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1795 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1796 " disabled adapter %d channel %d\n", 1797 pMvSataAdapter->adapterId, channel); 1798 mvSataEnableChannelDma(pMvSataAdapter,channel); 1799 pCmd->Result = RETURN_IDE_ERROR; 1800 break; 1801 case MV_QUEUE_COMMAND_RESULT_FULL: 1802 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1803 " Full adapter %d channel %d\n", 1804 pMvSataAdapter->adapterId, channel); 1805 pCmd->Result = RETURN_DEVICE_BUSY; 1806 break; 1807 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1808 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1809 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1810 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1811 pCmd->Result = RETURN_IDE_ERROR; 1812 break; 1813 default: 1814 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1815 " command\n", result); 1816 pCmd->Result = RETURN_IDE_ERROR; 1817 } 1818 if(pPRDTable) 1819 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1820 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1821 } 1822 pDevice->QueueLength++; 1823 return; 1824 1825 case IDE_COMMAND_VERIFY: 1826 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1827 pNoUdmaParams->bufPtr = NULL; 1828 pNoUdmaParams->callBack = CommandCompletionCB; 1829 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1830 pNoUdmaParams->count = 0; 1831 pNoUdmaParams->features = 0; 1832 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1833 1834 pCmd->uScratch.sata_param.cmd_priv = 1; 1835 if (pMvSataChannel->lba48Address == MV_TRUE){ 1836 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1837 pNoUdmaParams->isEXT = MV_TRUE; 1838 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1839 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1840 pNoUdmaParams->lbaLow = 1841 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1842 pNoUdmaParams->sectorCount = nSector; 1843 pNoUdmaParams->device = 0x40; 1844 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1845 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1846 goto queue_failed; 1847 } 1848 return; 1849 } 1850 else{ 1851 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1852 pNoUdmaParams->isEXT = MV_FALSE; 1853 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1854 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1855 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1856 pNoUdmaParams->sectorCount = 0xff & nSector; 1857 pNoUdmaParams->device = (MV_U8)(0x40 | 1858 ((Lba & 0xf000000) >> 24)); 1859 pNoUdmaParams->callBack = CommandCompletionCB; 1860 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1861 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1862 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1863 goto queue_failed; 1864 } 1865 } 1866 break; 1867 default: 1868 pCmd->Result = RETURN_INVALID_REQUEST; 1869 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1870 break; 1871 } 1872 } 1873 1874 /********************************************************** 1875 * 1876 * Probe the hostadapter. 1877 * 1878 **********************************************************/ 1879 static int 1880 hpt_probe(device_t dev) 1881 { 1882 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1883 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1884 #ifdef FOR_DEMO 1885 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1886 #endif 1887 )) 1888 { 1889 KdPrintI((CONTROLLER_NAME " found\n")); 1890 device_set_desc(dev, CONTROLLER_NAME); 1891 return 0; 1892 } 1893 else 1894 return(ENXIO); 1895 } 1896 1897 /*********************************************************** 1898 * 1899 * Auto configuration: attach and init a host adapter. 1900 * 1901 ***********************************************************/ 1902 static int 1903 hpt_attach(device_t dev) 1904 { 1905 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1906 int rid; 1907 union ccb *ccb; 1908 struct cam_devq *devq; 1909 struct cam_sim *hpt_vsim; 1910 1911 printf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1912 1913 if (!pAdapter) 1914 { 1915 pAdapter = (IAL_ADAPTER_T *)malloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT); 1916 #if __FreeBSD_version > 410000 1917 device_set_softc(dev, (void *)pAdapter); 1918 #else 1919 device_set_driver(dev, (driver_t *)pAdapter); 1920 #endif 1921 } 1922 1923 if (!pAdapter) return (ENOMEM); 1924 bzero(pAdapter, sizeof(IAL_ADAPTER_T)); 1925 1926 pAdapter->hpt_dev = dev; 1927 1928 rid = init_adapter(pAdapter); 1929 if (rid) 1930 return rid; 1931 1932 rid = 0; 1933 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) 1934 { 1935 hpt_printk(("can't allocate interrupt\n")); 1936 return(ENXIO); 1937 } 1938 1939 if(bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 1940 { 1941 hpt_printk(("can't set up interrupt\n")); 1942 free(pAdapter, M_DEVBUF); 1943 return(ENXIO); 1944 } 1945 1946 1947 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL) 1948 { 1949 bzero(ccb, sizeof(*ccb)); 1950 ccb->ccb_h.pinfo.priority = 1; 1951 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 1952 } 1953 else 1954 { 1955 return ENOMEM; 1956 } 1957 /* 1958 * Create the device queue for our SIM(s). 1959 */ 1960 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 1961 { 1962 KdPrint(("ENXIO\n")); 1963 return ENOMEM; 1964 } 1965 1966 /* 1967 * Construct our SIM entry 1968 */ 1969 if ((hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 1970 pAdapter, device_get_unit(pAdapter->hpt_dev), /*untagged*/1, /*tagged*/8, devq)) == NULL) { 1971 cam_simq_free(devq); 1972 return ENOMEM; 1973 } 1974 1975 if(xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) 1976 { 1977 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 1978 hpt_vsim = NULL; 1979 return ENXIO; 1980 } 1981 1982 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 1983 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 1984 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 1985 { 1986 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 1987 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 1988 hpt_vsim = NULL; 1989 return ENXIO; 1990 } 1991 1992 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 1993 ccb->ccb_h.func_code = XPT_SASYNC_CB; 1994 ccb->csa.event_enable = AC_LOST_DEVICE; 1995 ccb->csa.callback = hpt_async; 1996 ccb->csa.callback_arg = hpt_vsim; 1997 xpt_action((union ccb *)ccb); 1998 free(ccb, M_DEVBUF); 1999 2000 /* Register shutdown handler, and start the work thread. */ 2001 if (device_get_unit(dev) == 0) { 2002 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_final, 2003 hpt_shutdown, dev, SHUTDOWN_PRI_DEFAULT); 2004 if (pAdapter->eh) 2005 launch_worker_thread(); 2006 else 2007 hpt_printk(("shutdown event registration failed\n")); 2008 } 2009 2010 return 0; 2011 } 2012 2013 static int 2014 hpt_detach(device_t dev) 2015 { 2016 return (EBUSY); 2017 } 2018 2019 2020 /*************************************************************** 2021 * The poll function is used to simulate the interrupt when 2022 * the interrupt subsystem is not functioning. 2023 * 2024 ***************************************************************/ 2025 static void 2026 hpt_poll(struct cam_sim *sim) 2027 { 2028 hpt_intr((void *)cam_sim_softc(sim)); 2029 } 2030 2031 /**************************************************************** 2032 * Name: hpt_intr 2033 * Description: Interrupt handler. 2034 ****************************************************************/ 2035 static void 2036 hpt_intr(void *arg) 2037 { 2038 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg; 2039 intrmask_t oldspl = lock_driver(); 2040 2041 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2042 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2043 { 2044 _VBUS_INST(&pAdapter->VBus) 2045 CheckPendingCall(_VBUS_P0); 2046 } 2047 2048 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2049 unlock_driver(oldspl); 2050 } 2051 2052 /********************************************************** 2053 * Asynchronous Events 2054 *********************************************************/ 2055 #if (!defined(UNREFERENCED_PARAMETER)) 2056 #define UNREFERENCED_PARAMETER(x) (void)(x) 2057 #endif 2058 2059 static void 2060 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2061 void * arg) 2062 { 2063 /* debug XXXX */ 2064 panic("Here"); 2065 UNREFERENCED_PARAMETER(callback_arg); 2066 UNREFERENCED_PARAMETER(code); 2067 UNREFERENCED_PARAMETER(path); 2068 UNREFERENCED_PARAMETER(arg); 2069 2070 } 2071 2072 static void 2073 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2074 { 2075 int i; 2076 2077 hpt_printk(("flush all devices\n")); 2078 2079 /* flush all devices */ 2080 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2081 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2082 if(pVDev) fFlushVDev(pVDev); 2083 } 2084 } 2085 2086 static int 2087 hpt_shutdown(device_t dev) 2088 { 2089 IAL_ADAPTER_T *pAdapter; 2090 2091 pAdapter = device_get_softc(dev); 2092 if (pAdapter == NULL) 2093 return (EINVAL); 2094 2095 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2096 FlushAdapter(pAdapter); 2097 /* give the flush some time to happen, 2098 *otherwise "shutdown -p now" will make file system corrupted */ 2099 DELAY(1000 * 1000 * 5); 2100 return 0; 2101 } 2102 2103 void 2104 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2105 { 2106 _VBUS_INST(&pAdapter->VBus) 2107 2108 if (mWaitingForIdle(_VBUS_P0)) { 2109 CheckIdleCall(_VBUS_P0); 2110 #ifdef SUPPORT_ARRAY 2111 { 2112 int i; 2113 PVDevice pArray; 2114 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2115 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2116 continue; 2117 else if (pArray->u.array.rf_auto_rebuild) { 2118 KdPrint(("auto rebuild.\n")); 2119 pArray->u.array.rf_auto_rebuild = 0; 2120 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2121 } 2122 } 2123 } 2124 #endif 2125 } 2126 /* launch the awaiting commands blocked by mWaitingForIdle */ 2127 while(pAdapter->pending_Q!= NULL) 2128 { 2129 _VBUS_INST(&pAdapter->VBus) 2130 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2131 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2132 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2133 } 2134 } 2135 2136 static void 2137 ccb_done(union ccb *ccb) 2138 { 2139 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2140 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2141 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2142 2143 dmamap_put(pmap); 2144 xpt_done(ccb); 2145 2146 pAdapter->outstandingCommands--; 2147 2148 if (pAdapter->outstandingCommands == 0) 2149 { 2150 if(DPC_Request_Nums == 0) 2151 Check_Idle_Call(pAdapter); 2152 } 2153 } 2154 2155 /**************************************************************** 2156 * Name: hpt_action 2157 * Description: Process a queued command from the CAM layer. 2158 * Parameters: sim - Pointer to SIM object 2159 * ccb - Pointer to SCSI command structure. 2160 ****************************************************************/ 2161 2162 void 2163 hpt_action(struct cam_sim *sim, union ccb *ccb) 2164 { 2165 intrmask_t oldspl; 2166 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2167 PBUS_DMAMAP pmap; 2168 _VBUS_INST(&pAdapter->VBus) 2169 2170 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2171 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2172 2173 switch (ccb->ccb_h.func_code) 2174 { 2175 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2176 { 2177 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2178 2179 if (ccb->ccb_h.target_lun) { 2180 ccb->ccb_h.status = CAM_LUN_INVALID; 2181 xpt_done(ccb); 2182 return; 2183 } 2184 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2185 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2186 ccb->ccb_h.status = CAM_TID_INVALID; 2187 xpt_done(ccb); 2188 return; 2189 } 2190 2191 oldspl = lock_driver(); 2192 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2193 Check_Idle_Call(pAdapter); 2194 2195 pmap = dmamap_get(pAdapter); 2196 HPT_ASSERT(pmap); 2197 ccb->ccb_adapter = pmap; 2198 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2199 2200 if (mWaitingForIdle(_VBUS_P0)) 2201 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2202 else 2203 OsSendCommand(_VBUS_P ccb); 2204 unlock_driver(oldspl); 2205 2206 /* KdPrint(("leave scsiio\n")); */ 2207 break; 2208 } 2209 2210 case XPT_RESET_BUS: 2211 KdPrint(("reset bus\n")); 2212 oldspl = lock_driver(); 2213 fResetVBus(_VBUS_P0); 2214 unlock_driver(oldspl); 2215 xpt_done(ccb); 2216 break; 2217 2218 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2219 case XPT_EN_LUN: /* Enable LUN as a target */ 2220 case XPT_TARGET_IO: /* Execute target I/O request */ 2221 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2222 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2223 case XPT_ABORT: /* Abort the specified CCB */ 2224 case XPT_TERM_IO: /* Terminate the I/O process */ 2225 /* XXX Implement */ 2226 ccb->ccb_h.status = CAM_REQ_INVALID; 2227 xpt_done(ccb); 2228 break; 2229 2230 case XPT_GET_TRAN_SETTINGS: 2231 case XPT_SET_TRAN_SETTINGS: 2232 /* XXX Implement */ 2233 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2234 xpt_done(ccb); 2235 break; 2236 2237 case XPT_CALC_GEOMETRY: 2238 { 2239 struct ccb_calc_geometry *ccg; 2240 u_int32_t size_mb; 2241 u_int32_t secs_per_cylinder; 2242 2243 ccg = &ccb->ccg; 2244 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size); 2245 2246 if (size_mb > 1024 ) { 2247 ccg->heads = 255; 2248 ccg->secs_per_track = 63; 2249 } else { 2250 ccg->heads = 64; 2251 ccg->secs_per_track = 32; 2252 } 2253 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2254 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2255 ccb->ccb_h.status = CAM_REQ_CMP; 2256 xpt_done(ccb); 2257 break; 2258 } 2259 2260 case XPT_PATH_INQ: /* Path routing inquiry */ 2261 { 2262 struct ccb_pathinq *cpi = &ccb->cpi; 2263 2264 cpi->version_num = 1; /* XXX??? */ 2265 cpi->hba_inquiry = PI_SDTR_ABLE; 2266 cpi->target_sprt = 0; 2267 /* Not necessary to reset bus */ 2268 cpi->hba_misc = PIM_NOBUSRESET; 2269 cpi->hba_eng_cnt = 0; 2270 2271 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2272 cpi->max_lun = 0; 2273 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2274 2275 cpi->bus_id = cam_sim_bus(sim); 2276 cpi->base_transfer_speed = 3300; 2277 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2278 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2279 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2280 cpi->unit_number = cam_sim_unit(sim); 2281 cpi->ccb_h.status = CAM_REQ_CMP; 2282 xpt_done(ccb); 2283 break; 2284 } 2285 2286 default: 2287 KdPrint(("invalid cmd\n")); 2288 ccb->ccb_h.status = CAM_REQ_INVALID; 2289 xpt_done(ccb); 2290 break; 2291 } 2292 /* KdPrint(("leave hpt_action..............\n")); */ 2293 } 2294 2295 /* shall be called at lock_driver() */ 2296 static void 2297 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2298 { 2299 if(*ccb_Q == NULL) 2300 ccb->ccb_h.ccb_ccb_ptr = ccb; 2301 else { 2302 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2303 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2304 } 2305 2306 *ccb_Q = ccb; 2307 } 2308 2309 /* shall be called at lock_driver() */ 2310 static void 2311 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2312 { 2313 union ccb *TempCCB; 2314 2315 TempCCB = *ccb_Q; 2316 2317 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2318 *ccb_Q = NULL; 2319 else { 2320 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2321 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2322 2323 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2324 2325 if(*ccb_Q == ccb) 2326 *ccb_Q = TempCCB; 2327 } 2328 } 2329 2330 #ifdef SUPPORT_ARRAY 2331 /*************************************************************************** 2332 * Function: hpt_worker_thread 2333 * Description: Do background rebuilding. Execute in kernel thread context. 2334 * Returns: None 2335 ***************************************************************************/ 2336 static void hpt_worker_thread(void) 2337 { 2338 intrmask_t oldspl; 2339 2340 for(;;) { 2341 while (DpcQueue_First!=DpcQueue_Last) { 2342 ST_HPT_DPC p; 2343 oldspl = lock_driver(); 2344 p = DpcQueue[DpcQueue_First]; 2345 DpcQueue_First++; 2346 DpcQueue_First %= MAX_DPC; 2347 DPC_Request_Nums++; 2348 unlock_driver(oldspl); 2349 p.dpc(p.pAdapter, p.arg, p.flags); 2350 2351 oldspl = lock_driver(); 2352 DPC_Request_Nums--; 2353 /* since we may have prevented Check_Idle_Call, do it here */ 2354 if (DPC_Request_Nums==0) { 2355 if (p.pAdapter->outstandingCommands == 0) { 2356 _VBUS_INST(&p.pAdapter->VBus); 2357 Check_Idle_Call(p.pAdapter); 2358 CheckPendingCall(_VBUS_P0); 2359 } 2360 } 2361 unlock_driver(oldspl); 2362 2363 /*Schedule out*/ 2364 #if (__FreeBSD_version < 500000) 2365 YIELD_THREAD; 2366 #else 2367 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "sched", 1); 2368 #endif 2369 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2370 /* abort rebuilding process. */ 2371 IAL_ADAPTER_T *pAdapter; 2372 PVDevice pArray; 2373 PVBus _vbus_p; 2374 int i; 2375 pAdapter = gIal_Adapter; 2376 2377 while(pAdapter != 0){ 2378 2379 _vbus_p = &pAdapter->VBus; 2380 2381 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2382 { 2383 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2384 continue; 2385 else if (pArray->u.array.rf_rebuilding || 2386 pArray->u.array.rf_verifying || 2387 pArray->u.array.rf_initializing) 2388 { 2389 pArray->u.array.rf_abort_rebuild = 1; 2390 } 2391 } 2392 pAdapter = pAdapter->next; 2393 } 2394 } 2395 } 2396 2397 /*Remove this debug option*/ 2398 /* 2399 #ifdef DEBUG 2400 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2401 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); 2402 #endif 2403 */ 2404 #if (__FreeBSD_version >= 500043) 2405 kthread_suspend_check(curproc); 2406 #else 2407 kproc_suspend_loop(curproc); 2408 #endif 2409 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); /* wait for something to do */ 2410 } 2411 } 2412 2413 static struct proc *hptdaemonproc; 2414 static struct kproc_desc hpt_kp = { 2415 "hpt_wt", 2416 hpt_worker_thread, 2417 &hptdaemonproc 2418 }; 2419 2420 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2421 static void 2422 launch_worker_thread(void) 2423 { 2424 IAL_ADAPTER_T *pAdapTemp; 2425 2426 kproc_start(&hpt_kp); 2427 2428 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2429 2430 _VBUS_INST(&pAdapTemp->VBus) 2431 int i; 2432 PVDevice pVDev; 2433 2434 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2435 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2436 continue; 2437 else{ 2438 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2439 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2440 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2441 } 2442 } 2443 2444 /* 2445 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2446 */ 2447 #if (__FreeBSD_version < 500043) 2448 EVENTHANDLER_REGISTER(shutdown_post_sync, shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2449 #else 2450 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2451 #endif 2452 } 2453 /* 2454 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2455 */ 2456 2457 #endif 2458 2459 /********************************************************************************/ 2460 2461 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2462 { 2463 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2464 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2465 int idx; 2466 2467 if(logical) { 2468 if (ccb->ccb_h.flags & CAM_DATA_PHYS) 2469 panic("physical address unsupported"); 2470 2471 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2472 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2473 panic("physical address unsupported"); 2474 2475 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2476 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2477 pSg[idx].wSgSize = sgList[idx].ds_len; 2478 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0; 2479 } 2480 } 2481 else { 2482 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2483 pSg->wSgSize = ccb->csio.dxfer_len; 2484 pSg->wSgFlag = SG_FLAG_EOT; 2485 } 2486 return TRUE; 2487 } 2488 2489 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2490 HPT_ASSERT(0); 2491 return FALSE; 2492 } 2493 2494 /*******************************************************************************/ 2495 ULONG HPTLIBAPI 2496 GetStamp(void) 2497 { 2498 /* 2499 * the system variable, ticks, can't be used since it hasn't yet been active 2500 * when our driver starts (ticks==0, it's a invalid stamp value) 2501 */ 2502 ULONG stamp; 2503 do { stamp = random(); } while (stamp==0); 2504 return stamp; 2505 } 2506 2507 2508 static void 2509 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2510 { 2511 int i; 2512 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2513 2514 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2515 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2516 #ifndef SERIAL_CMDS 2517 inquiryData->CommandQueue = 1; 2518 #endif 2519 2520 switch(pVDev->VDeviceType) { 2521 case VD_SINGLE_DISK: 2522 case VD_ATAPI: 2523 case VD_REMOVABLE: 2524 /* Set the removable bit, if applicable. */ 2525 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2526 inquiryData->RemovableMedia = 1; 2527 2528 /* Fill in vendor identification fields. */ 2529 for (i = 0; i < 20; i += 2) { 2530 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2531 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2532 2533 } 2534 2535 /* Initialize unused portion of product id. */ 2536 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2537 2538 /* firmware revision */ 2539 for (i = 0; i < 4; i += 2) 2540 { 2541 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2542 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2543 } 2544 break; 2545 default: 2546 memcpy(&inquiryData->VendorId, "RR182x ", 8); 2547 #ifdef SUPPORT_ARRAY 2548 switch(pVDev->VDeviceType){ 2549 case VD_RAID_0: 2550 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2551 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2552 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2553 else 2554 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2555 break; 2556 case VD_RAID_1: 2557 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2558 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2559 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2560 else 2561 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2562 break; 2563 case VD_RAID_5: 2564 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2565 break; 2566 case VD_JBOD: 2567 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2568 break; 2569 } 2570 #endif 2571 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2572 break; 2573 } 2574 } 2575 2576 static void 2577 hpt_timeout(void *arg) 2578 { 2579 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus) 2580 intrmask_t oldspl = lock_driver(); 2581 fResetVBus(_VBUS_P0); 2582 unlock_driver(oldspl); 2583 } 2584 2585 static void 2586 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2587 { 2588 PCommand pCmd = (PCommand)arg; 2589 union ccb *ccb = pCmd->pOrgCommand; 2590 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2591 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2592 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2593 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2594 FPSCAT_GATH psg = pCmd->pSgTable; 2595 int idx; 2596 _VBUS_INST(pVDev->pVBus) 2597 2598 HPT_ASSERT(pCmd->cf_physical_sg); 2599 2600 if (error || nsegs == 0) 2601 panic("busdma error"); 2602 2603 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2604 2605 for (idx = 0; idx < nsegs; idx++, psg++) { 2606 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2607 psg->wSgSize = segs[idx].ds_len; 2608 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2609 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2610 } 2611 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2612 2613 if (pCmd->cf_data_in) { 2614 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD); 2615 } 2616 else if (pCmd->cf_data_out) { 2617 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE); 2618 } 2619 2620 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2621 pVDev->pfnSendCommand(_VBUS_P pCmd); 2622 CheckPendingCall(_VBUS_P0); 2623 } 2624 2625 2626 2627 static void HPTLIBAPI 2628 OsSendCommand(_VBUS_ARG union ccb *ccb) 2629 { 2630 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2631 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2632 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2633 struct ccb_scsiio *csio = &ccb->csio; 2634 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2635 2636 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2637 ccb, 2638 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2639 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2640 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2641 )); 2642 2643 pAdapter->outstandingCommands++; 2644 2645 if (pVDev == NULL || pVDev->vf_online == 0) { 2646 ccb->ccb_h.status = CAM_REQ_INVALID; 2647 ccb_done(ccb); 2648 goto Command_Complished; 2649 } 2650 2651 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2652 { 2653 case TEST_UNIT_READY: 2654 case START_STOP_UNIT: 2655 case SYNCHRONIZE_CACHE: 2656 /* FALLTHROUGH */ 2657 ccb->ccb_h.status = CAM_REQ_CMP; 2658 break; 2659 2660 case INQUIRY: 2661 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2662 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2663 ccb_h->status = CAM_REQ_CMP; 2664 break; 2665 2666 case READ_CAPACITY: 2667 { 2668 UCHAR swip[4]; 2669 /* Claim 512 byte blocks (big-endian). */ 2670 ((PREAD_CAPACITY_DATA)csio->data_ptr)->BytesPerBlock = 0x20000; 2671 *(ULONG*)swip = pVDev->VDeviceCapacity - 1; 2672 ((PREAD_CAPACITY_DATA)csio->data_ptr)->LogicalBlockAddress = 2673 (swip[0] << 24) | (swip[1] << 16) | (swip[2] << 8) | swip[3]; 2674 ccb_h->status = CAM_REQ_CMP; 2675 break; 2676 } 2677 2678 case READ_6: 2679 case WRITE_6: 2680 case READ_10: 2681 case WRITE_10: 2682 case 0x13: 2683 case 0x2f: 2684 { 2685 UCHAR Cdb[16]; 2686 UCHAR CdbLength; 2687 _VBUS_INST(pVDev->pVBus) 2688 PCommand pCmd = AllocateCommand(_VBUS_P0); 2689 HPT_ASSERT(pCmd); 2690 2691 CdbLength = csio->cdb_len; 2692 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2693 { 2694 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2695 { 2696 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2697 } 2698 else 2699 { 2700 KdPrintE(("ERROR!!!\n")); 2701 ccb->ccb_h.status = CAM_REQ_INVALID; 2702 break; 2703 } 2704 } 2705 else 2706 { 2707 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2708 } 2709 2710 pCmd->pOrgCommand = ccb; 2711 pCmd->pVDevice = pVDev; 2712 pCmd->pfnCompletion = fOsCommandDone; 2713 pCmd->pfnBuildSgl = fOsBuildSgl; 2714 pCmd->pSgTable = pmap->psg; 2715 2716 switch (Cdb[0]) 2717 { 2718 case READ_6: 2719 case WRITE_6: 2720 case 0x13: 2721 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2722 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2723 break; 2724 2725 default: 2726 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2727 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2728 break; 2729 } 2730 2731 switch (Cdb[0]) 2732 { 2733 case READ_6: 2734 case READ_10: 2735 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2736 pCmd->cf_data_in = 1; 2737 break; 2738 2739 case WRITE_6: 2740 case WRITE_10: 2741 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2742 pCmd->cf_data_out = 1; 2743 break; 2744 case 0x13: 2745 case 0x2f: 2746 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2747 break; 2748 } 2749 /*///////////////////////// */ 2750 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2751 int idx; 2752 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2753 2754 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2755 pCmd->cf_physical_sg = 1; 2756 2757 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2758 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2759 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len; 2760 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0; 2761 } 2762 2763 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2764 pVDev->pfnSendCommand(_VBUS_P pCmd); 2765 } 2766 else { 2767 int error; 2768 pCmd->cf_physical_sg = 1; 2769 error = bus_dmamap_load(pAdapter->io_dma_parent, 2770 pmap->dma_map, 2771 ccb->csio.data_ptr, ccb->csio.dxfer_len, 2772 hpt_io_dmamap_callback, pCmd, 2773 BUS_DMA_WAITOK 2774 ); 2775 KdPrint(("bus_dmamap_load return %d\n", error)); 2776 if (error && error!=EINPROGRESS) { 2777 hpt_printk(("bus_dmamap_load error %d\n", error)); 2778 FreeCommand(_VBUS_P pCmd); 2779 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2780 dmamap_put(pmap); 2781 pAdapter->outstandingCommands--; 2782 xpt_done(ccb); 2783 } 2784 } 2785 goto Command_Complished; 2786 } 2787 2788 default: 2789 ccb->ccb_h.status = CAM_REQ_INVALID; 2790 break; 2791 } 2792 ccb_done(ccb); 2793 Command_Complished: 2794 CheckPendingCall(_VBUS_P0); 2795 return; 2796 } 2797 2798 static void HPTLIBAPI 2799 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2800 { 2801 union ccb *ccb = pCmd->pOrgCommand; 2802 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2803 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2804 2805 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2806 2807 untimeout(hpt_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch); 2808 2809 switch(pCmd->Result) { 2810 case RETURN_SUCCESS: 2811 ccb->ccb_h.status = CAM_REQ_CMP; 2812 break; 2813 case RETURN_BAD_DEVICE: 2814 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2815 break; 2816 case RETURN_DEVICE_BUSY: 2817 ccb->ccb_h.status = CAM_BUSY; 2818 break; 2819 case RETURN_INVALID_REQUEST: 2820 ccb->ccb_h.status = CAM_REQ_INVALID; 2821 break; 2822 case RETURN_SELECTION_TIMEOUT: 2823 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2824 break; 2825 case RETURN_RETRY: 2826 ccb->ccb_h.status = CAM_BUSY; 2827 break; 2828 default: 2829 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2830 break; 2831 } 2832 2833 if (pCmd->cf_data_in) { 2834 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2835 } 2836 else if (pCmd->cf_data_in) { 2837 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2838 } 2839 2840 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2841 2842 FreeCommand(_VBUS_P pCmd); 2843 ccb_done(ccb); 2844 } 2845 2846 int 2847 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2848 { 2849 int p; 2850 2851 p = (DpcQueue_Last + 1) % MAX_DPC; 2852 if (p==DpcQueue_First) { 2853 KdPrint(("DPC Queue full!\n")); 2854 return -1; 2855 } 2856 2857 DpcQueue[DpcQueue_Last].dpc = dpc; 2858 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2859 DpcQueue[DpcQueue_Last].arg = arg; 2860 DpcQueue[DpcQueue_Last].flags = flags; 2861 DpcQueue_Last = p; 2862 2863 return 0; 2864 } 2865 2866 #ifdef _RAID5N_ 2867 /* 2868 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2869 * How about the memory for 5081 request/response array and PRD table? 2870 */ 2871 void 2872 *os_alloc_page(_VBUS_ARG0) 2873 { 2874 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2875 } 2876 2877 void 2878 *os_alloc_dma_page(_VBUS_ARG0) 2879 { 2880 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2881 } 2882 2883 void 2884 os_free_page(_VBUS_ARG void *p) 2885 { 2886 contigfree(p, 0x1000, M_DEVBUF); 2887 } 2888 2889 void 2890 os_free_dma_page(_VBUS_ARG void *p) 2891 { 2892 contigfree(p, 0x1000, M_DEVBUF); 2893 } 2894 2895 void 2896 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2897 { 2898 UINT i; 2899 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 2900 } 2901 2902 void 2903 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 2904 { 2905 UINT i; 2906 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 2907 } 2908 #endif 2909