1 /* 2 * Copyright (c) 2003-2004 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _ATAPI_H_ 30 #define _ATAPI_H_ 31 32 #pragma pack(1) 33 34 /*************************************************************************** 35 * IDE IO Register File 36 ***************************************************************************/ 37 38 /* 39 * IDE IO Port definition 40 */ 41 typedef struct _IDE_REGISTERS_1 { 42 USHORT Data; /* RW: Data port feature register */ 43 UCHAR BlockCount; /* RW: Sector count */ 44 UCHAR BlockNumber; /* RW: Sector number & LBA 0-7 */ 45 UCHAR CylinderLow; /* RW: Cylinder low & LBA 8-15 */ 46 UCHAR CylinderHigh; /* RW: Cylinder hign & LBA 16-23 */ 47 UCHAR DriveSelect; /* RW: Drive/head & LBA 24-27 */ 48 UCHAR Command; /* RO: Status WR:Command */ 49 } IDE_REGISTERS_1, *PIDE_REGISTERS_1; 50 51 52 /* 53 * IDE status definitions 54 */ 55 #define IDE_STATUS_ERROR 0x01 /* Error Occurred in Execution */ 56 #define IDE_STATUS_INDEX 0x02 /* is vendor specific */ 57 #define IDE_STATUS_CORRECTED_ERROR 0x04 /* Corrected Data */ 58 #define IDE_STATUS_DRQ 0x08 /* Ready to transfer data */ 59 #define IDE_STATUS_DSC 0x10 /* not defined in ATA-2 */ 60 #define IDE_STATUS_DWF 0x20 /* Device Fault has been detected */ 61 #define IDE_STATUS_DRDY 0x40 /* Device Ready to accept command */ 62 #define IDE_STATUS_IDLE 0x50 /* Device is OK */ 63 #define IDE_STATUS_BUSY 0x80 /* Device Busy, must wait */ 64 65 66 #define IDE_ERROR_BAD_BLOCK 0x80 /* Reserved now */ 67 #define IDE_ERROR_DATA_ERROR 0x40 /* Uncorreectable Data Error */ 68 #define IDE_ERROR_MEDIA_CHANGE 0x20 /* Media Changed */ 69 #define IDE_ERROR_ID_NOT_FOUND 0x10 /* ID Not Found */ 70 #define IDE_ERROR_MEDIA_CHANGE_REQ 0x08 /* Media Change Requested */ 71 #define IDE_ERROR_COMMAND_ABORTED 0x04 /* Aborted Command */ 72 #define IDE_ERROR_TRACK0_NOT_FOUND 0x02 /* Track 0 Not Found */ 73 #define IDE_ERROR_ADDRESS_NOT_FOUND 0x01 /* Address Mark Not Found */ 74 75 76 #define LBA_MODE 0x40 77 78 /* 79 * IDE command definitions 80 */ 81 82 #define IDE_COMMAND_RECALIBRATE 0x10 /* Recalibrate */ 83 #define IDE_COMMAND_READ 0x20 /* Read Sectors with retry */ 84 #define IDE_COMMAND_WRITE 0x30 /* Write Sectors with retry */ 85 #define IDE_COMMAND_VERIFY 0x40 /* Read Verify Sectors with Retry */ 86 #define IDE_COMMAND_SEEK 0x70 /* Seek */ 87 #define IDE_COMMAND_SET_DRIVE_PARAMETER 0x91 /* Initialize Device Parmeters */ 88 #define IDE_COMMAND_GET_MEDIA_STATUS 0xDA 89 #define IDE_COMMAND_DOOR_LOCK 0xDE /* Door Lock */ 90 #define IDE_COMMAND_DOOR_UNLOCK 0xDF /* Door Unlock */ 91 #define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF /* Set Features */ 92 #define IDE_COMMAND_IDENTIFY 0xEC /* Identify Device */ 93 #define IDE_COMMAND_MEDIA_EJECT 0xED 94 #define IDE_COMMAND_SET_FEATURES 0xEF /* IDE set features command */ 95 96 #define IDE_COMMAND_FLUSH_CACHE 0xE7 97 #define IDE_COMMAND_STANDBY_IMMEDIATE 0xE0 98 99 #ifndef NOT_SUPPORT_MULTIPLE 100 #define IDE_COMMAND_READ_MULTIPLE 0xC4 /* Read Multiple */ 101 #define IDE_COMMAND_WRITE_MULTIPLE 0xC5 /* Write Multiple */ 102 #define IDE_COMMAND_SET_MULTIPLE 0xC6 /* Set Multiple Mode */ 103 #endif 104 105 #ifndef NOT_SUPPORT_DMA 106 #define IDE_COMMAND_DMA_READ 0xc8 /* IDE DMA read command */ 107 #define IDE_COMMAND_DMA_WRITE 0xca /* IDE DMA write command */ 108 #endif 109 110 #define IDE_COMMAND_READ_DMA_QUEUE 0xc7 /* IDE read DMA queue command */ 111 #define IDE_COMMAND_WRITE_DMA_QUEUE 0xcc /* IDE write DMA queue command */ 112 #define IDE_COMMAND_SERVICE 0xA2 /* IDE service command command */ 113 #define IDE_COMMAND_NOP 0x00 /* IDE NOP command */ 114 #define IDE_STATUS_SRV 0x10 115 #define IDE_RELEASE_BUS 4 116 117 /*#define IDE_COMMAND_FLUSH_CACHE_EXT */ 118 #define IDE_COMMAND_READ_DMA_EXT 0x25 119 #define IDE_COMMAND_READ_QUEUE_EXT 0x26 120 #define IDE_COMMAND_READ_MULTIPLE_EXT 0x29 121 #define IDE_COMMAND_READ_MAX_ADDR 0x27 122 #define IDE_COMMAND_READ_EXT 0x24 123 #define IDE_COMMAND_VERIFY_EXT 0x42 124 #define IDE_COMMAND_SET_MULTIPLE_EXT 0x37 125 #define IDE_COMMAND_WRITE_DMA_EXT 0x35 126 #define IDE_COMMAND_WRITE_QUEUE_EXT 0x36 127 #define IDE_COMMAND_WRITE_EXT 0x34 128 #define IDE_COMMAND_WRITE_MULTIPLE_EXT 0x39 129 130 /* 131 * IDE_COMMAND_SET_FEATURES 132 */ 133 #define FT_USE_ULTRA 0x40 /* Set feature for Ultra DMA */ 134 #define FT_USE_MWDMA 0x20 /* Set feature for MW DMA */ 135 #define FT_USE_SWDMA 0x10 /* Set feature for SW DMA */ 136 #define FT_USE_PIO 0x8 /* Set feature for PIO */ 137 #define FT_DISABLE_IORDY 0x10 /* Set feature for disabling IORDY */ 138 139 /* 140 * S.M.A.R.T. commands 141 */ 142 #define IDE_COMMAND_SMART 0xB0 143 #define SMART_READ_VALUES 0xd0 144 #define SMART_READ_THRESHOLDS 0xd1 145 #define SMART_AUTOSAVE 0xd2 146 #define SMART_SAVE 0xd3 147 #define SMART_IMMEDIATE_OFFLINE 0xd4 148 #define SMART_READ_LOG_SECTOR 0xd5 149 #define SMART_WRITE_LOG_SECTOR 0xd6 150 #define SMART_ENABLE 0xd8 151 #define SMART_DISABLE 0xd9 152 #define SMART_STATUS 0xda 153 #define SMART_AUTO_OFFLINE 0xdb 154 155 /*************************************************************************** 156 * IDE Control Register File 157 ***************************************************************************/ 158 159 typedef struct _IDE_REGISTERS_2 { 160 UCHAR AlternateStatus; /* RW: device control port */ 161 } IDE_REGISTERS_2, *PIDE_REGISTERS_2; 162 163 164 /* 165 * IDE drive control definitions 166 */ 167 #define IDE_DC_DISABLE_INTERRUPTS 0x02 168 #define IDE_DC_RESET_CONTROLLER 0x04 169 #define IDE_DC_REENABLE_CONTROLLER 0x00 170 171 /*************************************************************************** 172 * MSNS: Removable device 173 ***************************************************************************/ 174 /* 175 * Media syatus 176 */ 177 #define MSNS_NO_MEDIA 2 178 #define MSNS_MEDIA_CHANGE_REQUEST 8 179 #define MSNS_MIDIA_CHANGE 0x20 180 #define MSNS_WRITE_PROTECT 0x40 181 #define MSNS_READ_PROTECT 0x80 182 183 /*************************************************************************** 184 * ATAPI IO Register File 185 ***************************************************************************/ 186 187 /* 188 * ATAPI register definition 189 */ 190 191 typedef struct _ATAPI_REGISTERS_1 { 192 USHORT Data; 193 UCHAR InterruptReason; /* Atapi Phase Port */ 194 UCHAR Unused1; 195 UCHAR ByteCountLow; /* Byte Count LSB */ 196 UCHAR ByteCountHigh; /* Byte Count MSB */ 197 UCHAR DriveSelect; 198 UCHAR Command; 199 } ATAPI_REGISTERS_1, *PATAPI_REGISTERS_1; 200 201 /* 202 * Atapi Error Status 203 */ 204 #define IDE_ERROR_END_OF_MEDIA IDE_ERROR_TRACK0_NOT_FOUND 205 #define IDE_ERROR_ILLEGAL_LENGTH IDE_ERROR_ADDRESS_NOT_FOUND 206 207 /* 208 * ATAPI interrupt reasons 209 */ 210 #define ATAPI_IR_COD 0x01 211 #define ATAPI_IR_IO 0x02 212 213 /* sense key */ 214 #define ATAPI_SENSE_NO_SENSE 0x00 215 #define ATAPI_SENSE_RECOVERED_ERROR 0x01 216 #define ATAPI_SENSE_NOT_READY 0x02 217 #define ATAPI_SENSE_MEDIUM_ERROR 0x03 218 #define ATAPI_SENSE_HARDWARE_ERROR 0x04 219 #define ATAPI_SENSE_ILLEGAL_REQUEST 0x05 220 #define ATAPI_SENSE_UNIT_ATTENTION 0x06 221 #define ATAPI_SENSE_DATA_PROTECT 0x07 222 #define ATAPI_SENSE_BLANK_CHECK 0x08 223 #define ATAPI_SENSE_UNIQUE 0x09 224 #define ATAPI_SENSE_COPY_ABORTED 0x0A 225 #define ATAPI_SENSE_ABORTED_COMMAND 0x0B 226 #define ATAPI_SENSE_EQUAL 0x0C 227 #define ATAPI_SENSE_VOL_OVERFLOW 0x0D 228 #define ATAPI_SENSE_MISCOMPARE 0x0E 229 #define ATAPI_SENSE_RESERVED 0x0F 230 231 /* Additional Sense codes */ 232 #define ATAPI_ASC_NO_SENSE 0x00 233 #define ATAPI_ASC_LUN_NOT_READY 0x04 234 #define ATAPI_ASC_TRACK_ERROR 0x14 235 #define ATAPI_ASC_SEEK_ERROR 0x15 236 #define ATAPI_ASC_REC_DATA_NOECC 0x17 237 #define ATAPI_ASC_REC_DATA_ECC 0x18 238 #define ATAPI_ASC_ILLEGAL_COMMAND 0x20 239 #define ATAPI_ASC_ILLEGAL_BLOCK 0x21 240 #define ATAPI_ASC_INVALID_CDB 0x24 241 #define ATAPI_ASC_INVALID_LUN 0x25 242 #define ATAPI_ASC_PROTECT 0x27 243 #define ATAPI_ASC_MEDIUM_CHANGED 0x28 244 #define ATAPI_ASC_BUS_RESET 0x29 245 #define ATAPI_ASC_NO_MEDIA_IN_DEVICE 0x3a 246 #define ATAPI_ASC_MUSIC_AREA 0xA0 247 #define ATAPI_ASC_DATA_AREA 0xA1 248 #define ATAPI_ASC_VOLUME_OVERFLOW 0xA7 249 250 /* 251 * IDE command definitions ( for ATAPI ) 252 */ 253 254 #define IDE_COMMAND_ATAPI_RESET 0x08 /* Atapi Software Reset command */ 255 #define IDE_COMMAND_ATAPI_PACKET 0xA0 /* Atapi Identify command */ 256 #define IDE_COMMAND_ATAPI_IDENTIFY 0xA1 /* Atapi Packet Command */ 257 258 259 /* 260 * ATAPI command definitions 261 */ 262 263 #define ATAPI_TEST_UNIT_READY 0x00 264 #define ATAPI_REZERO_UNIT 0x01 265 #define ATAPI_REQUEST_SENSE 0x03 266 #define ATAPI_FORMAT_UNIT6 0x04 267 #define ATAPI_FORMAT_UNIT 0x24 268 #define ATAPI_INQUIRY 0x12 269 #define ATAPI_MODE_SELECT 0x15 270 #define ATAPI_MODE_SENSE 0x1A 271 #define ATAPI_START_STOP_UNIT 0x1B 272 #define ATAPI_LOAD_UNLOAD 0x1B 273 #define ATAPI_MEDIUM_REMOVAL 0x1E 274 #define ATAPI_READ_CAPACITY 0x25 275 #define ATAPI_READ 0x28 276 #define ATAPI_WRITE 0x2A 277 #define ATAPI_SEEK 0x2B 278 #define ATAPI_VERIFY 0x2F 279 #define ATAPI_READ_DATA_BUFF 0x3C 280 #define ATAPI_READ_SUB_CHANNEL 0x42 281 #define ATAPI_READ_TOC 0x43 282 #define ATAPI_READ_HEADER 0x44 283 #define ATAPI_GET_CONFIGURATION 0x46 284 #define ATAPI_PLAY_AUDIO_MSF 0x47 285 #define ATAPI_GET_EVENT_STATUS_NOTIFICATION 0x4A 286 #define ATAPI_PAUSE_RESUME 0x4B 287 #define ATAPI_STOP_PLAY_SCAN 0x4E 288 #define ATAPI_READ_DISK_INFORMATION 0x51 289 #define ATAPI_READ_TRACK_INFORMATION 0x52 290 #define ATAPI_MODE_SELECT10 0x55 291 #define ATAPI_MODE_SENSE10 0x5A 292 #define ATAPI_CLOSE_TRACK_SESSION 0x5B 293 #define ATAPI_READ_BUFFER_CAPACITY 0x5C 294 #define ATAPI_BLANK_COMMAND 0xA1 /*Provide the ability to erase any part of a CD-RW disc.*/ 295 #define ATAPI_REPORT_KEY 0xA4 296 #define ATAPI_PLAY_AUDIO 0xA5 297 #define ATAPI_READ12 0xA8 298 #define ATAPI_READ_DVD_STRUCTURE 0xAD 299 #define ATAPI_READ_CD_MSF 0xB9 300 #define ATAPI_SET_CD_SPEED 0xBB 301 #define ATAPI_MECHANISM_STATUS 0xBD 302 #define ATAPI_READ_CD 0xBE 303 #define ATAPI_SET_CDRW_SPEED 0xDA /*WindowsXP need*/ 304 305 #define MODE_DSP_WRITE_PROTECT 0x80 306 307 308 /*************************************************************************** 309 * ATAPI IO Register File 310 ***************************************************************************/ 311 312 313 typedef struct _ATAPI_REGISTERS_2 { 314 UCHAR AlternateStatus; 315 } ATAPI_REGISTERS_2, *PATAPI_REGISTERS_2; 316 317 318 /*************************************************************************** 319 * ATAPI packets 320 ***************************************************************************/ 321 typedef struct _ATAPI_SENSE_DATA { 322 #ifdef __BIG_ENDIAN_BITFIELD 323 UCHAR Valid:1; 324 UCHAR ErrorCode:7; 325 UCHAR SegmentNumber; 326 UCHAR FileMark:1; 327 UCHAR EndOfMedia:1; 328 UCHAR IncorrectLength:1; 329 UCHAR Reserved:1; 330 UCHAR SenseKey:4; 331 #else 332 UCHAR ErrorCode:7; 333 UCHAR Valid:1; 334 UCHAR SegmentNumber; 335 UCHAR SenseKey:4; 336 UCHAR Reserved:1; 337 UCHAR IncorrectLength:1; 338 UCHAR EndOfMedia:1; 339 UCHAR FileMark:1; 340 #endif 341 UCHAR Information[4]; 342 UCHAR AdditionalSenseLength; 343 UCHAR CommandSpecificInformation[4]; 344 UCHAR AdditionalSenseCode; 345 UCHAR AdditionalSenseCodeQualifier; 346 UCHAR FieldReplaceableUnitCode; 347 UCHAR SenseKeySpecific[3]; 348 } ATAPI_SENSE_DATA, *PATAPI_SENSE_DATA; 349 350 /* 351 * IDENTIFY data 352 */ 353 typedef struct _IDENTIFY_DATA { 354 USHORT GeneralConfiguration; /* 00 00 */ 355 USHORT NumberOfCylinders; /* 02 1 */ 356 USHORT Reserved1; /* 04 2 */ 357 USHORT NumberOfHeads; /* 06 3 */ 358 USHORT UnformattedBytesPerTrack; /* 08 4 */ 359 USHORT UnformattedBytesPerSector; /* 0A 5 */ 360 USHORT SectorsPerTrack; /* 0C 6 */ 361 USHORT VendorUnique1[3]; /* 0E 7-9 */ 362 USHORT SerialNumber[10]; /* 14 10-19 */ 363 USHORT BufferType; /* 28 20 */ 364 USHORT BufferSectorSize; /* 2A 21 */ 365 USHORT NumberOfEccBytes; /* 2C 22 */ 366 USHORT FirmwareRevision[4]; /* 2E 23-26 */ 367 USHORT ModelNumber[20]; /* 36 27-46 */ 368 UCHAR MaximumBlockTransfer; /* 5E 47 */ 369 UCHAR VendorUnique2; /* 5F */ 370 USHORT DoubleWordIo; /* 60 48 */ 371 USHORT Capabilities; /* 62 49 */ 372 USHORT Reserved2; /* 64 50 */ 373 UCHAR VendorUnique3; /* 66 51 */ 374 UCHAR PioCycleTimingMode; /* 67 */ 375 UCHAR VendorUnique4; /* 68 52 */ 376 UCHAR DmaCycleTimingMode; /* 69 */ 377 USHORT TranslationFieldsValid; /* 6A 53 */ 378 USHORT NumberOfCurrentCylinders; /* 6C 54 */ 379 USHORT NumberOfCurrentHeads; /* 6E 55 */ 380 USHORT CurrentSectorsPerTrack; /* 70 56 */ 381 ULONG CurrentSectorCapacity; /* 72 57-58 */ 382 USHORT CurrentMultiSectorSetting; /* 76 59 */ 383 ULONG UserAddressableSectors; /* 78 60-61 */ 384 UCHAR SingleWordDMASupport; /* 7C 62 */ 385 UCHAR SingleWordDMAActive; /* 7D */ 386 UCHAR MultiWordDMASupport; /* 7E 63 */ 387 UCHAR MultiWordDMAActive; /* 7F */ 388 UCHAR AdvancedPIOModes; /* 80 64 */ 389 UCHAR Reserved4; /* 81 */ 390 USHORT MinimumMWXferCycleTime; /* 82 65 */ 391 USHORT RecommendedMWXferCycleTime; /* 84 66 */ 392 USHORT MinimumPIOCycleTime; /* 86 67 */ 393 USHORT MinimumPIOCycleTimeIORDY; /* 88 68 */ 394 USHORT Reserved5[2]; /* 8A 69-70 */ 395 USHORT ReleaseTimeOverlapped; /* 8E 71 */ 396 USHORT ReleaseTimeServiceCommand; /* 90 72 */ 397 USHORT MajorRevision; /* 92 73 */ 398 USHORT MinorRevision; /* 94 74 */ 399 USHORT MaxQueueDepth; /* 96 75 */ 400 USHORT SataCapability; /* 76 */ 401 USHORT Reserved6[9]; /* 98 77-85 */ 402 USHORT CommandSupport; /* 86 */ 403 USHORT CommandEnable; /* 87 */ 404 USHORT UtralDmaMode; /* 88 */ 405 USHORT Reserved7[11]; /* 89-99 */ 406 ULONG Lba48BitLow; /* 101-100 */ 407 ULONG Lba48BitHigh; /* 103-102 */ 408 USHORT Reserved8[23]; /* 104-126 */ 409 USHORT SpecialFunctionsEnabled; /* 127 */ 410 USHORT Reserved9[128]; /* 128-255 */ 411 412 } IDENTIFY_DATA, *PIDENTIFY_DATA; 413 414 typedef struct _CONFIGURATION_IDENTIFY_DATA { 415 USHORT Revision; 416 USHORT MWDMAModeSupported; 417 USHORT UDMAModeSupported; 418 ULONG MaximumLbaLow; 419 ULONG MaximumLbaHigh; 420 USHORT CommandSupport; 421 USHORT Reserved[247]; 422 UCHAR Signature; /* 0xA5 */ 423 UCHAR CheckSum; 424 } 425 CONFIGURATION_IDENTIFY_DATA, *PCONFIGURATION_IDENTIFY_DATA; 426 427 /* */ 428 /* Identify data without the Reserved4. */ 429 /* */ 430 typedef struct _IDENTIFY_DATA2 { 431 USHORT GeneralConfiguration; /* 00 00 */ 432 USHORT NumberOfCylinders; /* 02 1 */ 433 USHORT Reserved1; /* 04 2 */ 434 USHORT NumberOfHeads; /* 06 3 */ 435 USHORT UnformattedBytesPerTrack; /* 08 4 */ 436 USHORT UnformattedBytesPerSector; /* 0A 5 */ 437 USHORT SectorsPerTrack; /* 0C 6 */ 438 USHORT VendorUnique1[3]; /* 0E 7-9 */ 439 USHORT SerialNumber[10]; /* 14 10-19 */ 440 USHORT BufferType; /* 28 20 */ 441 USHORT BufferSectorSize; /* 2A 21 */ 442 USHORT NumberOfEccBytes; /* 2C 22 */ 443 USHORT FirmwareRevision[4]; /* 2E 23-26 */ 444 USHORT ModelNumber[20]; /* 36 27-46 */ 445 UCHAR MaximumBlockTransfer; /* 5E 47 */ 446 UCHAR VendorUnique2; /* 5F */ 447 USHORT DoubleWordIo; /* 60 48 */ 448 USHORT Capabilities; /* 62 49 */ 449 USHORT Reserved2; /* 64 50 */ 450 UCHAR VendorUnique3; /* 66 51 */ 451 UCHAR PioCycleTimingMode; /* 67 */ 452 UCHAR VendorUnique4; /* 68 52 */ 453 UCHAR DmaCycleTimingMode; /* 69 */ 454 USHORT TranslationFieldsValid; /* 6A 53 */ 455 USHORT NumberOfCurrentCylinders; /* 6C 54 */ 456 USHORT NumberOfCurrentHeads; /* 6E 55 */ 457 USHORT CurrentSectorsPerTrack; /* 70 56 */ 458 ULONG CurrentSectorCapacity; /* 72 57-58 */ 459 USHORT CurrentMultiSectorSetting; /* 59 */ 460 ULONG UserAddressableSectors; /* 60-61 */ 461 UCHAR SingleWordDMASupport; /* 62 */ 462 UCHAR SingleWordDMAActive; 463 UCHAR MultiWordDMASupport; /* 63 */ 464 UCHAR MultiWordDMAActive; 465 UCHAR AdvancedPIOModes; /* 64 */ 466 UCHAR Reserved4; 467 USHORT MinimumMWXferCycleTime; /* 65 */ 468 USHORT RecommendedMWXferCycleTime; /* 66 */ 469 USHORT MinimumPIOCycleTime; /* 67 */ 470 USHORT MinimumPIOCycleTimeIORDY; /* 68 */ 471 USHORT Reserved5[2]; /* 69-70 */ 472 USHORT ReleaseTimeOverlapped; /* 71 */ 473 USHORT ReleaseTimeServiceCommand; /* 72 */ 474 USHORT MajorRevision; /* 73 */ 475 USHORT MinorRevision; /* 74 */ 476 /* USHORT Reserved6[14]; // 75-88 */ 477 } IDENTIFY_DATA2, *PIDENTIFY_DATA2; 478 479 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA2) 480 481 /* */ 482 /* IDENTIFY DMA timing cycle modes. */ 483 /* */ 484 485 #define IDENTIFY_DMA_CYCLES_MODE_0 0x00 486 #define IDENTIFY_DMA_CYCLES_MODE_1 0x01 487 #define IDENTIFY_DMA_CYCLES_MODE_2 0x02 488 489 /* 490 * Mode definitions 491 */ 492 typedef enum _DISK_MODE 493 { 494 IDE_PIO_0 = 0, 495 IDE_PIO_1, 496 IDE_PIO_2, 497 IDE_PIO_3, 498 IDE_PIO_4, 499 IDE_MWDMA_0, 500 IDE_MWDMA_1, 501 IDE_MWDMA_2, 502 IDE_UDMA_0, 503 IDE_UDMA_1, 504 IDE_UDMA_2, 505 IDE_UDMA_3, 506 IDE_UDMA_4, 507 IDE_UDMA_5, 508 IDE_UDMA_6, 509 IDE_UDMA_7, 510 } DISK_MODE; 511 512 /*************************************************************************** 513 * IDE Macro 514 ***************************************************************************/ 515 #ifndef MAX_LBA_T 516 #define MAX_LBA_T ((LBA_T)-1) 517 #endif 518 519 #define SECTOR_TO_BYTE_SHIFT 9 520 #define SECTOR_TO_BYTE(x) ((ULONG)(x) << SECTOR_TO_BYTE_SHIFT) 521 522 #define mGetStatus(IOPort2) (UCHAR)InPort(&IOPort2->AlternateStatus) 523 #define mUnitControl(IOPort2, Value) OutPort(&IOPort2->AlternateStatus,(UCHAR)(Value)) 524 525 #define mGetErrorCode(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->Data+1) 526 #define mSetFeaturePort(IOPort,x) OutPort((PUCHAR)&IOPort->Data+1, x) 527 #define mSetBlockCount(IOPort,x) OutPort(&IOPort->BlockCount, x) 528 #define mGetBlockCount(IOPort) (UCHAR)InPort(&IOPort->BlockCount) 529 #define mGetInterruptReason(IOPort) (UCHAR)InPort(&IOPort->BlockCount) 530 #define mSetBlockNumber(IOPort,x) OutPort(&IOPort->BlockNumber, x) 531 #define mGetBlockNumber(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->BlockNumber) 532 #define mGetByteLow(IOPort) (UCHAR)InPort(&IOPort->CylinderLow) 533 #define mSetCylinderLow(IOPort,x) OutPort(&IOPort->CylinderLow, x) 534 #define mGetByteHigh(IOPort) (UCHAR)InPort(&IOPort->CylinderHigh) 535 #define mSetCylinderHigh(IOPort,x) OutPort(&IOPort->CylinderHigh, x) 536 #define mGetBaseStatus(IOPort) (UCHAR)InPort(&IOPort->Command) 537 #ifdef SUPPORT_HPT601 538 #define mSelectUnit(IOPort,UnitId) do {\ 539 OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\ 540 OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\ 541 } while (0) 542 #else 543 #define mSelectUnit(IOPort,UnitId) OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId)) 544 #endif 545 #define mGetUnitNumber(IOPort) InPort(&IOPort->DriveSelect) 546 #define mIssueCommand(IOPort,Cmd) OutPort(&IOPort->Command, (UCHAR)(Cmd)) 547 548 /* 549 * WDC old disk, don't care right now 550 */ 551 #define WDC_MW1_FIX_FLAG_OFFSET 129 552 #define WDC_MW1_FIX_FLAG_VALUE 0x00005555 553 554 #pragma pack() 555 #endif 556 557 558 559