1 /* 2 * Copyright (c) 2003-2004 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _ATAPI_H_ 28 #define _ATAPI_H_ 29 30 #pragma pack(1) 31 32 /*************************************************************************** 33 * IDE IO Register File 34 ***************************************************************************/ 35 36 /* 37 * IDE IO Port definition 38 */ 39 typedef struct _IDE_REGISTERS_1 { 40 USHORT Data; /* RW: Data port feature register */ 41 UCHAR BlockCount; /* RW: Sector count */ 42 UCHAR BlockNumber; /* RW: Sector number & LBA 0-7 */ 43 UCHAR CylinderLow; /* RW: Cylinder low & LBA 8-15 */ 44 UCHAR CylinderHigh; /* RW: Cylinder hign & LBA 16-23 */ 45 UCHAR DriveSelect; /* RW: Drive/head & LBA 24-27 */ 46 UCHAR Command; /* RO: Status WR:Command */ 47 } IDE_REGISTERS_1, *PIDE_REGISTERS_1; 48 49 50 /* 51 * IDE status definitions 52 */ 53 #define IDE_STATUS_ERROR 0x01 /* Error Occurred in Execution */ 54 #define IDE_STATUS_INDEX 0x02 /* is vendor specific */ 55 #define IDE_STATUS_CORRECTED_ERROR 0x04 /* Corrected Data */ 56 #define IDE_STATUS_DRQ 0x08 /* Ready to transfer data */ 57 #define IDE_STATUS_DSC 0x10 /* not defined in ATA-2 */ 58 #define IDE_STATUS_DWF 0x20 /* Device Fault has been detected */ 59 #define IDE_STATUS_DRDY 0x40 /* Device Ready to accept command */ 60 #define IDE_STATUS_IDLE 0x50 /* Device is OK */ 61 #define IDE_STATUS_BUSY 0x80 /* Device Busy, must wait */ 62 63 64 #define IDE_ERROR_BAD_BLOCK 0x80 /* Reserved now */ 65 #define IDE_ERROR_DATA_ERROR 0x40 /* Uncorreectable Data Error */ 66 #define IDE_ERROR_MEDIA_CHANGE 0x20 /* Media Changed */ 67 #define IDE_ERROR_ID_NOT_FOUND 0x10 /* ID Not Found */ 68 #define IDE_ERROR_MEDIA_CHANGE_REQ 0x08 /* Media Change Requested */ 69 #define IDE_ERROR_COMMAND_ABORTED 0x04 /* Aborted Command */ 70 #define IDE_ERROR_TRACK0_NOT_FOUND 0x02 /* Track 0 Not Found */ 71 #define IDE_ERROR_ADDRESS_NOT_FOUND 0x01 /* Address Mark Not Found */ 72 73 74 #define LBA_MODE 0x40 75 76 /* 77 * IDE command definitions 78 */ 79 80 #define IDE_COMMAND_RECALIBRATE 0x10 /* Recalibrate */ 81 #define IDE_COMMAND_READ 0x20 /* Read Sectors with retry */ 82 #define IDE_COMMAND_WRITE 0x30 /* Write Sectors with retry */ 83 #define IDE_COMMAND_VERIFY 0x40 /* Read Verify Sectors with Retry */ 84 #define IDE_COMMAND_SEEK 0x70 /* Seek */ 85 #define IDE_COMMAND_SET_DRIVE_PARAMETER 0x91 /* Initialize Device Parmeters */ 86 #define IDE_COMMAND_GET_MEDIA_STATUS 0xDA 87 #define IDE_COMMAND_DOOR_LOCK 0xDE /* Door Lock */ 88 #define IDE_COMMAND_DOOR_UNLOCK 0xDF /* Door Unlock */ 89 #define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF /* Set Features */ 90 #define IDE_COMMAND_IDENTIFY 0xEC /* Identify Device */ 91 #define IDE_COMMAND_MEDIA_EJECT 0xED 92 #define IDE_COMMAND_SET_FEATURES 0xEF /* IDE set features command */ 93 94 #define IDE_COMMAND_FLUSH_CACHE 0xE7 95 #define IDE_COMMAND_STANDBY_IMMEDIATE 0xE0 96 97 #ifndef NOT_SUPPORT_MULTIPLE 98 #define IDE_COMMAND_READ_MULTIPLE 0xC4 /* Read Multiple */ 99 #define IDE_COMMAND_WRITE_MULTIPLE 0xC5 /* Write Multiple */ 100 #define IDE_COMMAND_SET_MULTIPLE 0xC6 /* Set Multiple Mode */ 101 #endif 102 103 #ifndef NOT_SUPPORT_DMA 104 #define IDE_COMMAND_DMA_READ 0xc8 /* IDE DMA read command */ 105 #define IDE_COMMAND_DMA_WRITE 0xca /* IDE DMA write command */ 106 #endif 107 108 #define IDE_COMMAND_READ_DMA_QUEUE 0xc7 /* IDE read DMA queue command */ 109 #define IDE_COMMAND_WRITE_DMA_QUEUE 0xcc /* IDE write DMA queue command */ 110 #define IDE_COMMAND_SERVICE 0xA2 /* IDE service command command */ 111 #define IDE_COMMAND_NOP 0x00 /* IDE NOP command */ 112 #define IDE_STATUS_SRV 0x10 113 #define IDE_RELEASE_BUS 4 114 115 /*#define IDE_COMMAND_FLUSH_CACHE_EXT */ 116 #define IDE_COMMAND_READ_DMA_EXT 0x25 117 #define IDE_COMMAND_READ_QUEUE_EXT 0x26 118 #define IDE_COMMAND_READ_MULTIPLE_EXT 0x29 119 #define IDE_COMMAND_READ_MAX_ADDR 0x27 120 #define IDE_COMMAND_READ_EXT 0x24 121 #define IDE_COMMAND_VERIFY_EXT 0x42 122 #define IDE_COMMAND_SET_MULTIPLE_EXT 0x37 123 #define IDE_COMMAND_WRITE_DMA_EXT 0x35 124 #define IDE_COMMAND_WRITE_QUEUE_EXT 0x36 125 #define IDE_COMMAND_WRITE_EXT 0x34 126 #define IDE_COMMAND_WRITE_MULTIPLE_EXT 0x39 127 128 /* 129 * IDE_COMMAND_SET_FEATURES 130 */ 131 #define FT_USE_ULTRA 0x40 /* Set feature for Ultra DMA */ 132 #define FT_USE_MWDMA 0x20 /* Set feature for MW DMA */ 133 #define FT_USE_SWDMA 0x10 /* Set feature for SW DMA */ 134 #define FT_USE_PIO 0x8 /* Set feature for PIO */ 135 #define FT_DISABLE_IORDY 0x10 /* Set feature for disabling IORDY */ 136 137 /* 138 * S.M.A.R.T. commands 139 */ 140 #define IDE_COMMAND_SMART 0xB0 141 #define SMART_READ_VALUES 0xd0 142 #define SMART_READ_THRESHOLDS 0xd1 143 #define SMART_AUTOSAVE 0xd2 144 #define SMART_SAVE 0xd3 145 #define SMART_IMMEDIATE_OFFLINE 0xd4 146 #define SMART_READ_LOG_SECTOR 0xd5 147 #define SMART_WRITE_LOG_SECTOR 0xd6 148 #define SMART_ENABLE 0xd8 149 #define SMART_DISABLE 0xd9 150 #define SMART_STATUS 0xda 151 #define SMART_AUTO_OFFLINE 0xdb 152 153 /*************************************************************************** 154 * IDE Control Register File 155 ***************************************************************************/ 156 157 typedef struct _IDE_REGISTERS_2 { 158 UCHAR AlternateStatus; /* RW: device control port */ 159 } IDE_REGISTERS_2, *PIDE_REGISTERS_2; 160 161 162 /* 163 * IDE drive control definitions 164 */ 165 #define IDE_DC_DISABLE_INTERRUPTS 0x02 166 #define IDE_DC_RESET_CONTROLLER 0x04 167 #define IDE_DC_REENABLE_CONTROLLER 0x00 168 169 /*************************************************************************** 170 * MSNS: Removable device 171 ***************************************************************************/ 172 /* 173 * Media syatus 174 */ 175 #define MSNS_NO_MEDIA 2 176 #define MSNS_MEDIA_CHANGE_REQUEST 8 177 #define MSNS_MIDIA_CHANGE 0x20 178 #define MSNS_WRITE_PROTECT 0x40 179 #define MSNS_READ_PROTECT 0x80 180 181 /*************************************************************************** 182 * ATAPI IO Register File 183 ***************************************************************************/ 184 185 /* 186 * ATAPI register definition 187 */ 188 189 typedef struct _ATAPI_REGISTERS_1 { 190 USHORT Data; 191 UCHAR InterruptReason; /* Atapi Phase Port */ 192 UCHAR Unused1; 193 UCHAR ByteCountLow; /* Byte Count LSB */ 194 UCHAR ByteCountHigh; /* Byte Count MSB */ 195 UCHAR DriveSelect; 196 UCHAR Command; 197 } ATAPI_REGISTERS_1, *PATAPI_REGISTERS_1; 198 199 /* 200 * Atapi Error Status 201 */ 202 #define IDE_ERROR_END_OF_MEDIA IDE_ERROR_TRACK0_NOT_FOUND 203 #define IDE_ERROR_ILLEGAL_LENGTH IDE_ERROR_ADDRESS_NOT_FOUND 204 205 /* 206 * ATAPI interrupt reasons 207 */ 208 #define ATAPI_IR_COD 0x01 209 #define ATAPI_IR_IO 0x02 210 211 /* sense key */ 212 #define ATAPI_SENSE_NO_SENSE 0x00 213 #define ATAPI_SENSE_RECOVERED_ERROR 0x01 214 #define ATAPI_SENSE_NOT_READY 0x02 215 #define ATAPI_SENSE_MEDIUM_ERROR 0x03 216 #define ATAPI_SENSE_HARDWARE_ERROR 0x04 217 #define ATAPI_SENSE_ILLEGAL_REQUEST 0x05 218 #define ATAPI_SENSE_UNIT_ATTENTION 0x06 219 #define ATAPI_SENSE_DATA_PROTECT 0x07 220 #define ATAPI_SENSE_BLANK_CHECK 0x08 221 #define ATAPI_SENSE_UNIQUE 0x09 222 #define ATAPI_SENSE_COPY_ABORTED 0x0A 223 #define ATAPI_SENSE_ABORTED_COMMAND 0x0B 224 #define ATAPI_SENSE_EQUAL 0x0C 225 #define ATAPI_SENSE_VOL_OVERFLOW 0x0D 226 #define ATAPI_SENSE_MISCOMPARE 0x0E 227 #define ATAPI_SENSE_RESERVED 0x0F 228 229 /* Additional Sense codes */ 230 #define ATAPI_ASC_NO_SENSE 0x00 231 #define ATAPI_ASC_LUN_NOT_READY 0x04 232 #define ATAPI_ASC_TRACK_ERROR 0x14 233 #define ATAPI_ASC_SEEK_ERROR 0x15 234 #define ATAPI_ASC_REC_DATA_NOECC 0x17 235 #define ATAPI_ASC_REC_DATA_ECC 0x18 236 #define ATAPI_ASC_ILLEGAL_COMMAND 0x20 237 #define ATAPI_ASC_ILLEGAL_BLOCK 0x21 238 #define ATAPI_ASC_INVALID_CDB 0x24 239 #define ATAPI_ASC_INVALID_LUN 0x25 240 #define ATAPI_ASC_PROTECT 0x27 241 #define ATAPI_ASC_MEDIUM_CHANGED 0x28 242 #define ATAPI_ASC_BUS_RESET 0x29 243 #define ATAPI_ASC_NO_MEDIA_IN_DEVICE 0x3a 244 #define ATAPI_ASC_MUSIC_AREA 0xA0 245 #define ATAPI_ASC_DATA_AREA 0xA1 246 #define ATAPI_ASC_VOLUME_OVERFLOW 0xA7 247 248 /* 249 * IDE command definitions ( for ATAPI ) 250 */ 251 252 #define IDE_COMMAND_ATAPI_RESET 0x08 /* Atapi Software Reset command */ 253 #define IDE_COMMAND_ATAPI_PACKET 0xA0 /* Atapi Identify command */ 254 #define IDE_COMMAND_ATAPI_IDENTIFY 0xA1 /* Atapi Packet Command */ 255 256 257 /* 258 * ATAPI command definitions 259 */ 260 261 #define ATAPI_TEST_UNIT_READY 0x00 262 #define ATAPI_REZERO_UNIT 0x01 263 #define ATAPI_REQUEST_SENSE 0x03 264 #define ATAPI_FORMAT_UNIT6 0x04 265 #define ATAPI_FORMAT_UNIT 0x24 266 #define ATAPI_INQUIRY 0x12 267 #define ATAPI_MODE_SELECT 0x15 268 #define ATAPI_MODE_SENSE 0x1A 269 #define ATAPI_START_STOP_UNIT 0x1B 270 #define ATAPI_LOAD_UNLOAD 0x1B 271 #define ATAPI_MEDIUM_REMOVAL 0x1E 272 #define ATAPI_READ_CAPACITY 0x25 273 #define ATAPI_READ 0x28 274 #define ATAPI_WRITE 0x2A 275 #define ATAPI_SEEK 0x2B 276 #define ATAPI_VERIFY 0x2F 277 #define ATAPI_READ_DATA_BUFF 0x3C 278 #define ATAPI_READ_SUB_CHANNEL 0x42 279 #define ATAPI_READ_TOC 0x43 280 #define ATAPI_READ_HEADER 0x44 281 #define ATAPI_GET_CONFIGURATION 0x46 282 #define ATAPI_PLAY_AUDIO_MSF 0x47 283 #define ATAPI_GET_EVENT_STATUS_NOTIFICATION 0x4A 284 #define ATAPI_PAUSE_RESUME 0x4B 285 #define ATAPI_STOP_PLAY_SCAN 0x4E 286 #define ATAPI_READ_DISK_INFORMATION 0x51 287 #define ATAPI_READ_TRACK_INFORMATION 0x52 288 #define ATAPI_MODE_SELECT10 0x55 289 #define ATAPI_MODE_SENSE10 0x5A 290 #define ATAPI_CLOSE_TRACK_SESSION 0x5B 291 #define ATAPI_READ_BUFFER_CAPACITY 0x5C 292 #define ATAPI_BLANK_COMMAND 0xA1 /*Provide the ability to erase any part of a CD-RW disc.*/ 293 #define ATAPI_REPORT_KEY 0xA4 294 #define ATAPI_PLAY_AUDIO 0xA5 295 #define ATAPI_READ12 0xA8 296 #define ATAPI_READ_DVD_STRUCTURE 0xAD 297 #define ATAPI_READ_CD_MSF 0xB9 298 #define ATAPI_SET_CD_SPEED 0xBB 299 #define ATAPI_MECHANISM_STATUS 0xBD 300 #define ATAPI_READ_CD 0xBE 301 #define ATAPI_SET_CDRW_SPEED 0xDA /*WindowsXP need*/ 302 303 #define MODE_DSP_WRITE_PROTECT 0x80 304 305 306 /*************************************************************************** 307 * ATAPI IO Register File 308 ***************************************************************************/ 309 310 311 typedef struct _ATAPI_REGISTERS_2 { 312 UCHAR AlternateStatus; 313 } ATAPI_REGISTERS_2, *PATAPI_REGISTERS_2; 314 315 316 /*************************************************************************** 317 * ATAPI packets 318 ***************************************************************************/ 319 typedef struct _ATAPI_SENSE_DATA { 320 #ifdef __BIG_ENDIAN_BITFIELD 321 UCHAR Valid:1; 322 UCHAR ErrorCode:7; 323 UCHAR SegmentNumber; 324 UCHAR FileMark:1; 325 UCHAR EndOfMedia:1; 326 UCHAR IncorrectLength:1; 327 UCHAR Reserved:1; 328 UCHAR SenseKey:4; 329 #else 330 UCHAR ErrorCode:7; 331 UCHAR Valid:1; 332 UCHAR SegmentNumber; 333 UCHAR SenseKey:4; 334 UCHAR Reserved:1; 335 UCHAR IncorrectLength:1; 336 UCHAR EndOfMedia:1; 337 UCHAR FileMark:1; 338 #endif 339 UCHAR Information[4]; 340 UCHAR AdditionalSenseLength; 341 UCHAR CommandSpecificInformation[4]; 342 UCHAR AdditionalSenseCode; 343 UCHAR AdditionalSenseCodeQualifier; 344 UCHAR FieldReplaceableUnitCode; 345 UCHAR SenseKeySpecific[3]; 346 } ATAPI_SENSE_DATA, *PATAPI_SENSE_DATA; 347 348 /* 349 * IDENTIFY data 350 */ 351 typedef struct _IDENTIFY_DATA { 352 USHORT GeneralConfiguration; /* 00 00 */ 353 USHORT NumberOfCylinders; /* 02 1 */ 354 USHORT Reserved1; /* 04 2 */ 355 USHORT NumberOfHeads; /* 06 3 */ 356 USHORT UnformattedBytesPerTrack; /* 08 4 */ 357 USHORT UnformattedBytesPerSector; /* 0A 5 */ 358 USHORT SectorsPerTrack; /* 0C 6 */ 359 USHORT VendorUnique1[3]; /* 0E 7-9 */ 360 USHORT SerialNumber[10]; /* 14 10-19 */ 361 USHORT BufferType; /* 28 20 */ 362 USHORT BufferSectorSize; /* 2A 21 */ 363 USHORT NumberOfEccBytes; /* 2C 22 */ 364 USHORT FirmwareRevision[4]; /* 2E 23-26 */ 365 USHORT ModelNumber[20]; /* 36 27-46 */ 366 UCHAR MaximumBlockTransfer; /* 5E 47 */ 367 UCHAR VendorUnique2; /* 5F */ 368 USHORT DoubleWordIo; /* 60 48 */ 369 USHORT Capabilities; /* 62 49 */ 370 USHORT Reserved2; /* 64 50 */ 371 UCHAR VendorUnique3; /* 66 51 */ 372 UCHAR PioCycleTimingMode; /* 67 */ 373 UCHAR VendorUnique4; /* 68 52 */ 374 UCHAR DmaCycleTimingMode; /* 69 */ 375 USHORT TranslationFieldsValid; /* 6A 53 */ 376 USHORT NumberOfCurrentCylinders; /* 6C 54 */ 377 USHORT NumberOfCurrentHeads; /* 6E 55 */ 378 USHORT CurrentSectorsPerTrack; /* 70 56 */ 379 ULONG CurrentSectorCapacity; /* 72 57-58 */ 380 USHORT CurrentMultiSectorSetting; /* 76 59 */ 381 ULONG UserAddressableSectors; /* 78 60-61 */ 382 UCHAR SingleWordDMASupport; /* 7C 62 */ 383 UCHAR SingleWordDMAActive; /* 7D */ 384 UCHAR MultiWordDMASupport; /* 7E 63 */ 385 UCHAR MultiWordDMAActive; /* 7F */ 386 UCHAR AdvancedPIOModes; /* 80 64 */ 387 UCHAR Reserved4; /* 81 */ 388 USHORT MinimumMWXferCycleTime; /* 82 65 */ 389 USHORT RecommendedMWXferCycleTime; /* 84 66 */ 390 USHORT MinimumPIOCycleTime; /* 86 67 */ 391 USHORT MinimumPIOCycleTimeIORDY; /* 88 68 */ 392 USHORT Reserved5[2]; /* 8A 69-70 */ 393 USHORT ReleaseTimeOverlapped; /* 8E 71 */ 394 USHORT ReleaseTimeServiceCommand; /* 90 72 */ 395 USHORT MajorRevision; /* 92 73 */ 396 USHORT MinorRevision; /* 94 74 */ 397 USHORT MaxQueueDepth; /* 96 75 */ 398 USHORT SataCapability; /* 76 */ 399 USHORT Reserved6[9]; /* 98 77-85 */ 400 USHORT CommandSupport; /* 86 */ 401 USHORT CommandEnable; /* 87 */ 402 USHORT UtralDmaMode; /* 88 */ 403 USHORT Reserved7[11]; /* 89-99 */ 404 ULONG Lba48BitLow; /* 101-100 */ 405 ULONG Lba48BitHigh; /* 103-102 */ 406 USHORT Reserved8[23]; /* 104-126 */ 407 USHORT SpecialFunctionsEnabled; /* 127 */ 408 USHORT Reserved9[128]; /* 128-255 */ 409 410 } IDENTIFY_DATA, *PIDENTIFY_DATA; 411 412 typedef struct _CONFIGURATION_IDENTIFY_DATA { 413 USHORT Revision; 414 USHORT MWDMAModeSupported; 415 USHORT UDMAModeSupported; 416 ULONG MaximumLbaLow; 417 ULONG MaximumLbaHigh; 418 USHORT CommandSupport; 419 USHORT Reserved[247]; 420 UCHAR Signature; /* 0xA5 */ 421 UCHAR CheckSum; 422 } 423 CONFIGURATION_IDENTIFY_DATA, *PCONFIGURATION_IDENTIFY_DATA; 424 425 /* */ 426 /* Identify data without the Reserved4. */ 427 /* */ 428 typedef struct _IDENTIFY_DATA2 { 429 USHORT GeneralConfiguration; /* 00 00 */ 430 USHORT NumberOfCylinders; /* 02 1 */ 431 USHORT Reserved1; /* 04 2 */ 432 USHORT NumberOfHeads; /* 06 3 */ 433 USHORT UnformattedBytesPerTrack; /* 08 4 */ 434 USHORT UnformattedBytesPerSector; /* 0A 5 */ 435 USHORT SectorsPerTrack; /* 0C 6 */ 436 USHORT VendorUnique1[3]; /* 0E 7-9 */ 437 USHORT SerialNumber[10]; /* 14 10-19 */ 438 USHORT BufferType; /* 28 20 */ 439 USHORT BufferSectorSize; /* 2A 21 */ 440 USHORT NumberOfEccBytes; /* 2C 22 */ 441 USHORT FirmwareRevision[4]; /* 2E 23-26 */ 442 USHORT ModelNumber[20]; /* 36 27-46 */ 443 UCHAR MaximumBlockTransfer; /* 5E 47 */ 444 UCHAR VendorUnique2; /* 5F */ 445 USHORT DoubleWordIo; /* 60 48 */ 446 USHORT Capabilities; /* 62 49 */ 447 USHORT Reserved2; /* 64 50 */ 448 UCHAR VendorUnique3; /* 66 51 */ 449 UCHAR PioCycleTimingMode; /* 67 */ 450 UCHAR VendorUnique4; /* 68 52 */ 451 UCHAR DmaCycleTimingMode; /* 69 */ 452 USHORT TranslationFieldsValid; /* 6A 53 */ 453 USHORT NumberOfCurrentCylinders; /* 6C 54 */ 454 USHORT NumberOfCurrentHeads; /* 6E 55 */ 455 USHORT CurrentSectorsPerTrack; /* 70 56 */ 456 ULONG CurrentSectorCapacity; /* 72 57-58 */ 457 USHORT CurrentMultiSectorSetting; /* 59 */ 458 ULONG UserAddressableSectors; /* 60-61 */ 459 UCHAR SingleWordDMASupport; /* 62 */ 460 UCHAR SingleWordDMAActive; 461 UCHAR MultiWordDMASupport; /* 63 */ 462 UCHAR MultiWordDMAActive; 463 UCHAR AdvancedPIOModes; /* 64 */ 464 UCHAR Reserved4; 465 USHORT MinimumMWXferCycleTime; /* 65 */ 466 USHORT RecommendedMWXferCycleTime; /* 66 */ 467 USHORT MinimumPIOCycleTime; /* 67 */ 468 USHORT MinimumPIOCycleTimeIORDY; /* 68 */ 469 USHORT Reserved5[2]; /* 69-70 */ 470 USHORT ReleaseTimeOverlapped; /* 71 */ 471 USHORT ReleaseTimeServiceCommand; /* 72 */ 472 USHORT MajorRevision; /* 73 */ 473 USHORT MinorRevision; /* 74 */ 474 /* USHORT Reserved6[14]; // 75-88 */ 475 } IDENTIFY_DATA2, *PIDENTIFY_DATA2; 476 477 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA2) 478 479 /* */ 480 /* IDENTIFY DMA timing cycle modes. */ 481 /* */ 482 483 #define IDENTIFY_DMA_CYCLES_MODE_0 0x00 484 #define IDENTIFY_DMA_CYCLES_MODE_1 0x01 485 #define IDENTIFY_DMA_CYCLES_MODE_2 0x02 486 487 /* 488 * Mode definitions 489 */ 490 typedef enum _DISK_MODE 491 { 492 IDE_PIO_0 = 0, 493 IDE_PIO_1, 494 IDE_PIO_2, 495 IDE_PIO_3, 496 IDE_PIO_4, 497 IDE_MWDMA_0, 498 IDE_MWDMA_1, 499 IDE_MWDMA_2, 500 IDE_UDMA_0, 501 IDE_UDMA_1, 502 IDE_UDMA_2, 503 IDE_UDMA_3, 504 IDE_UDMA_4, 505 IDE_UDMA_5, 506 IDE_UDMA_6, 507 IDE_UDMA_7, 508 } DISK_MODE; 509 510 /*************************************************************************** 511 * IDE Macro 512 ***************************************************************************/ 513 #ifndef MAX_LBA_T 514 #define MAX_LBA_T ((LBA_T)-1) 515 #endif 516 517 #define SECTOR_TO_BYTE_SHIFT 9 518 #define SECTOR_TO_BYTE(x) ((ULONG)(x) << SECTOR_TO_BYTE_SHIFT) 519 520 #define mGetStatus(IOPort2) (UCHAR)InPort(&IOPort2->AlternateStatus) 521 #define mUnitControl(IOPort2, Value) OutPort(&IOPort2->AlternateStatus,(UCHAR)(Value)) 522 523 #define mGetErrorCode(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->Data+1) 524 #define mSetFeaturePort(IOPort,x) OutPort((PUCHAR)&IOPort->Data+1, x) 525 #define mSetBlockCount(IOPort,x) OutPort(&IOPort->BlockCount, x) 526 #define mGetBlockCount(IOPort) (UCHAR)InPort(&IOPort->BlockCount) 527 #define mGetInterruptReason(IOPort) (UCHAR)InPort(&IOPort->BlockCount) 528 #define mSetBlockNumber(IOPort,x) OutPort(&IOPort->BlockNumber, x) 529 #define mGetBlockNumber(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->BlockNumber) 530 #define mGetByteLow(IOPort) (UCHAR)InPort(&IOPort->CylinderLow) 531 #define mSetCylinderLow(IOPort,x) OutPort(&IOPort->CylinderLow, x) 532 #define mGetByteHigh(IOPort) (UCHAR)InPort(&IOPort->CylinderHigh) 533 #define mSetCylinderHigh(IOPort,x) OutPort(&IOPort->CylinderHigh, x) 534 #define mGetBaseStatus(IOPort) (UCHAR)InPort(&IOPort->Command) 535 #ifdef SUPPORT_HPT601 536 #define mSelectUnit(IOPort,UnitId) do {\ 537 OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\ 538 OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\ 539 } while (0) 540 #else 541 #define mSelectUnit(IOPort,UnitId) OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId)) 542 #endif 543 #define mGetUnitNumber(IOPort) InPort(&IOPort->DriveSelect) 544 #define mIssueCommand(IOPort,Cmd) OutPort(&IOPort->Command, (UCHAR)(Cmd)) 545 546 /* 547 * WDC old disk, don't care right now 548 */ 549 #define WDC_MW1_FIX_FLAG_OFFSET 129 550 #define WDC_MW1_FIX_FLAG_VALUE 0x00005555 551 552 #pragma pack() 553 #endif 554 555 556 557