1 /*- 2 * Copyright (c) 2011 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <dev/hpt27xx/hpt27xx_config.h> 30 31 #ifndef _HPT_HIM_H_ 32 #define _HPT_HIM_H_ 33 34 #define VERMAGIC_HIM 55 35 36 #if defined(__cplusplus) 37 extern "C" { 38 #endif 39 40 #include <dev/hpt27xx/list.h> 41 42 #define SECTOR_TO_BYTE_SHIFT 9 43 #define SECTOR_TO_BYTE(x) ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT) 44 #define BYTE_TO_SECTOR(x) ((x)>>SECTOR_TO_BYTE_SHIFT) 45 46 typedef struct _PCI_ID 47 { 48 HPT_U16 vid; 49 HPT_U16 did; 50 HPT_U32 subsys; 51 HPT_U8 rev; 52 HPT_U8 nbase; 53 HPT_U16 reserve; 54 } 55 PCI_ID; 56 57 typedef struct _PCI_ADDRESS 58 { 59 HPT_U8 tree; 60 HPT_U8 bus; 61 HPT_U8 device; 62 HPT_U8 function; 63 } 64 PCI_ADDRESS; 65 66 typedef struct _HIM_ADAPTER_CONFIG 67 { 68 PCI_ADDRESS pci_addr; 69 PCI_ID pci_id; 70 71 HPT_U8 max_devices; 72 73 HPT_U8 bProbeInInitializing:1; 74 75 HPT_U8 bSpinupOneDevEachTime:1; 76 77 HPT_U8 bGlobalNcq:1; 78 HPT_U8 bSGPIOPartSupport:1; 79 80 HPT_U8 bNeedSASIdleTimer:1; 81 HPT_U8 reserved:3; 82 83 HPT_U8 bDevsPerBus; 84 HPT_U8 first_on_slot; 85 86 HPT_U8 bChipType; 87 HPT_U8 bChipIntrNum; 88 HPT_U8 bChipFlags; 89 HPT_U8 bNumBuses; 90 91 HPT_U8 szVendorID[36]; 92 HPT_U8 szProductID[36]; 93 HPT_U32 nvramSize; 94 HPT_U64 nvramAddress; 95 HPT_U8 slot_index; 96 HPT_U8 reserved2[11]; 97 } 98 HIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG; 99 100 typedef struct _HIM_CHANNEL_CONFIG 101 { 102 HPT_U32 io_port; 103 HPT_U32 ctl_port; 104 } HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG; 105 106 typedef struct _HIM_DEVICE_FLAGS 107 { 108 HPT_UINT df_atapi :1; 109 HPT_UINT df_removable_drive :1; 110 HPT_UINT df_on_line :1; 111 HPT_UINT df_reduce_mode :1; 112 HPT_UINT df_sata :1; 113 HPT_UINT df_on_pm_port :1; 114 HPT_UINT df_support_read_ahead :1; 115 HPT_UINT df_read_ahead_enabled :1; 116 HPT_UINT df_support_write_cache :1; 117 HPT_UINT df_write_cache_enabled :1; 118 HPT_UINT df_cdrom_device :1; 119 HPT_UINT df_tape_device :1; 120 HPT_UINT df_support_tcq :1; 121 HPT_UINT df_tcq_enabled :1; 122 HPT_UINT df_support_ncq :1; 123 HPT_UINT df_ncq_enabled :1; 124 HPT_UINT df_sas :1; 125 HPT_UINT df_in_enclosure :1; 126 HPT_UINT df_ssd :1; 127 } DEVICE_FLAGS, *PDEVICE_FLAGS; 128 129 #pragma pack(1) 130 typedef struct _IDENTIFY_DATA { 131 HPT_U16 GeneralConfiguration; 132 HPT_U16 NumberOfCylinders; 133 HPT_U16 Reserved1; 134 HPT_U16 NumberOfHeads; 135 HPT_U16 UnformattedBytesPerTrack; 136 HPT_U16 UnformattedBytesPerSector; 137 HPT_U8 SasAddress[8]; 138 HPT_U16 SerialNumber[10]; 139 HPT_U16 BufferType; 140 HPT_U16 BufferSectorSize; 141 HPT_U16 NumberOfEccBytes; 142 HPT_U16 FirmwareRevision[4]; 143 HPT_U16 ModelNumber[20]; 144 HPT_U8 MaximumBlockTransfer; 145 HPT_U8 VendorUnique2; 146 HPT_U16 DoubleWordIo; 147 HPT_U16 Capabilities; 148 HPT_U16 Reserved2; 149 HPT_U8 VendorUnique3; 150 HPT_U8 PioCycleTimingMode; 151 HPT_U8 VendorUnique4; 152 HPT_U8 DmaCycleTimingMode; 153 HPT_U16 TranslationFieldsValid; 154 HPT_U16 NumberOfCurrentCylinders; 155 HPT_U16 NumberOfCurrentHeads; 156 HPT_U16 CurrentSectorsPerTrack; 157 HPT_U32 CurrentSectorCapacity; 158 HPT_U16 CurrentMultiSectorSetting; 159 HPT_U32 UserAddressableSectors; 160 HPT_U8 SingleWordDMASupport; 161 HPT_U8 SingleWordDMAActive; 162 HPT_U8 MultiWordDMASupport; 163 HPT_U8 MultiWordDMAActive; 164 HPT_U8 AdvancedPIOModes; 165 HPT_U8 Reserved4; 166 HPT_U16 MinimumMWXferCycleTime; 167 HPT_U16 RecommendedMWXferCycleTime; 168 HPT_U16 MinimumPIOCycleTime; 169 HPT_U16 MinimumPIOCycleTimeIORDY; 170 HPT_U16 Reserved5[2]; 171 HPT_U16 ReleaseTimeOverlapped; 172 HPT_U16 ReleaseTimeServiceCommand; 173 HPT_U16 MajorRevision; 174 HPT_U16 MinorRevision; 175 HPT_U16 MaxQueueDepth; 176 HPT_U16 SataCapability; 177 HPT_U16 Reserved6[9]; 178 HPT_U16 CommandSupport; 179 HPT_U16 CommandEnable; 180 HPT_U16 UtralDmaMode; 181 HPT_U16 Reserved7[11]; 182 HPT_U32 Lba48BitLow; 183 HPT_U32 Lba48BitHigh; 184 HPT_U16 Reserved8[23]; 185 HPT_U16 SpecialFunctionsEnabled; 186 HPT_U16 Reserved9[128]; 187 } 188 #ifdef __GNUC__ 189 __attribute__((packed)) 190 #endif 191 IDENTIFY_DATA, *PIDENTIFY_DATA; 192 #pragma pack() 193 194 typedef struct _HIM_DEVICE_CONFIG 195 { 196 HPT_U64 capacity; 197 198 DEVICE_FLAGS flags; 199 200 HPT_U8 path_id; 201 HPT_U8 target_id; 202 HPT_U8 max_queue_depth; 203 HPT_U8 spin_up_mode; 204 205 HPT_U8 reserved; 206 HPT_U8 transfer_mode; 207 HPT_U8 bMaxShowMode; 208 HPT_U8 bDeUsable_Mode; 209 210 HPT_U16 max_sectors_per_cmd; 211 212 PIDENTIFY_DATA pIdentifyData; 213 214 215 HPT_U8 fixed_path_id; /*equals to phy id */ 216 } 217 HIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG; 218 219 220 #define _DIT_MODE 0 221 #define _DIT_601 1 222 #define _DIT_READ_AHEAD 2 223 #define _DIT_WRITE_CACHE 3 224 #define _DIT_TCQ 4 225 #define _DIT_NCQ 5 226 #define _DIT_BEEP_OFF 6 227 #define _DIT_SPIN_UP_MODE 7 228 #define _DIT_IDLE_STANDBY 8 229 #define _DIT_IDENTIFY 9 230 231 #define SPIN_UP_MODE_NOSUPPORT 0 232 #define SPIN_UP_MODE_FULL 1 233 #define SPIN_UP_MODE_STANDBY 2 234 235 struct tcq_control { 236 HPT_U8 enable; 237 HPT_U8 depth; 238 }; 239 240 struct ncq_control { 241 HPT_U8 enable; 242 HPT_U8 depth; 243 }; 244 245 typedef struct _HIM_ALTERABLE_DEV_INFO{ 246 HPT_U8 type; 247 union { 248 HPT_U8 mode; 249 HPT_U8 enable_read_ahead; 250 HPT_U8 enable_read_cache; 251 HPT_U8 enable_write_cache; 252 struct tcq_control tcq; 253 struct ncq_control ncq; 254 void * adapter; 255 HPT_U8 spin_up_mode; 256 HPT_U8 idle_standby_timeout; 257 HPT_U8 identify_indicator; 258 }u; 259 } HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO; 260 261 struct _COMMAND; 262 struct _IOCTL_ARG; 263 264 typedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index); 265 266 typedef struct _HIM { 267 char *name; 268 struct _HIM *next; 269 HPT_UINT max_sg_descriptors; 270 #define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args; 271 #include <dev/hpt27xx/himfuncs.h> 272 } 273 HIM, *PHIM; 274 275 276 #pragma pack(1) 277 #ifdef SG_FLAG_EOT 278 #error "don't use SG_FLAG_EOT with _SG.eot. clean the code!" 279 #endif 280 281 typedef struct _SG { 282 HPT_U32 size; 283 HPT_UINT eot; 284 union { 285 HPT_U8 FAR * _logical; 286 BUS_ADDRESS bus; 287 } 288 addr; 289 } 290 SG, *PSG; 291 #pragma pack() 292 293 typedef struct _AtaCommand 294 { 295 HPT_U64 Lba; 296 HPT_U16 nSectors; 297 HPT_U16 pad; 298 } AtaComm, *PAtaComm; 299 300 #define ATA_CMD_NOP 0x0 301 302 #define ATA_CMD_SET_FEATURES 0xef 303 #define ATA_CMD_FLUSH 0xE7 304 #define ATA_CMD_VERIFY 0x40 305 #define ATA_CMD_STANDBY 0xe2 306 #define ATA_CMD_READ_MULTI 0xC4 307 #define ATA_CMD_READ_MULTI_EXT 0x29 308 #define ATA_CMD_WRITE_MULTI 0xC5 309 #define ATA_CMD_WRITE_MULTI_EXT 0x39 310 #define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE 311 312 #define ATA_CMD_READ_DMA 0xc8 /* IDE DMA read command */ 313 #define ATA_CMD_WRITE_DMA 0xca /* IDE DMA write command */ 314 #define ATA_CMD_READ_DMA_EXT 0x25 315 #define ATA_CMD_READ_QUEUE_EXT 0x26 316 #define ATA_CMD_READ_MAX_ADDR 0x27 317 #define ATA_CMD_READ_EXT 0x24 318 #define ATA_CMD_VERIFY_EXT 0x42 319 #define ATA_CMD_WRITE_DMA_EXT 0x35 320 #define ATA_CMD_WRITE_QUEUE_EXT 0x36 321 #define ATA_CMD_WRITE_EXT 0x34 322 323 #define ATA_SET_FEATURES_XFER 0x3 324 #define ATA_SECTOR_SIZE 512 325 326 typedef struct _PassthroughCmd { 327 HPT_U16 bFeaturesReg; 328 HPT_U16 bSectorCountReg; 329 HPT_U16 bLbaLowReg; 330 HPT_U16 bLbaMidReg; 331 HPT_U16 bLbaHighReg; 332 HPT_U8 bDriveHeadReg; 333 HPT_U8 bCommandReg; 334 HPT_U16 nSectors; 335 HPT_U8 *pDataBuffer; 336 } 337 PassthroughCmd; 338 339 typedef struct _ScsiComm { 340 HPT_U8 cdbLength; 341 HPT_U8 senseLength; 342 HPT_U8 scsiStatus; 343 HPT_U8 reserve1; 344 HPT_U32 dataLength; 345 HPT_U8 *cdb; 346 HPT_U8 *senseBuffer; 347 } 348 ScsiComm; 349 350 351 #define CTRL_CMD_REBUILD 1 352 #define CTRL_CMD_VERIFY 2 353 #define CTRL_CMD_INIT 3 354 355 356 typedef struct _R5ControlCmd { 357 HPT_U64 StripeLine; 358 HPT_U16 Offset; 359 HPT_U8 Command; 360 HPT_U8 reserve1; 361 } 362 R5ControlCmd, *PR5ControlCmd; 363 364 typedef struct _HPT_ADDRESS 365 { 366 HPT_U8 * logical; 367 BUS_ADDRESS bus; 368 } 369 HPT_ADDRESS; 370 371 372 typedef struct ctl_pages { 373 HPT_ADDRESS *pages; 374 HPT_UINT page_size; 375 HPT_UINT npages; 376 HPT_UINT min_sg_descriptors; 377 } CONTROL_PAGES, *PCONTROL_PAGES; 378 379 typedef struct _R1ControlCmd { 380 HPT_U64 Lba; 381 HPT_U16 nSectors; 382 HPT_U8 Command; /* CTRL_CMD_XXX */ 383 HPT_U8 reserve1; 384 PCONTROL_PAGES ctl_pages; 385 } 386 R1ControlCmd, *PR1ControlCmd; 387 388 typedef void (*TQ_PROC)(void *arg); 389 390 struct tq_item { 391 TQ_PROC proc; 392 void *arg; 393 struct tq_item *next; 394 }; 395 396 #define INIT_TQ_ITEM(t, p, a) \ 397 do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0) 398 399 typedef struct _COMMAND 400 { 401 402 struct _VBUS * vbus; 403 404 struct freelist *grplist; 405 HPT_UINT grpcnt; 406 407 408 struct list_head q_link; 409 struct tq_item done_dpc; 410 411 HPT_UINT extsize; 412 void *ext; 413 414 415 416 void *target; 417 void *priv; 418 HPT_UPTR priv2; 419 420 int priority; 421 struct lock_request *owned_lock; 422 struct lock_request *lock_req; 423 void (*dtor)(struct _COMMAND *, void *); 424 void *dtor_arg; 425 426 union{ 427 AtaComm Ide; 428 PassthroughCmd Passthrough; 429 ScsiComm Scsi; 430 R5ControlCmd R5Control; 431 R1ControlCmd R1Control; 432 } uCmd; 433 434 HPT_U8 type; /* CMD_TYPE_* */ 435 436 struct { 437 HPT_U8 physical_sg: 1; 438 HPT_U8 data_in: 1; 439 HPT_U8 data_out: 1; 440 HPT_U8 transform : 1; 441 HPT_U8 hard_flush: 2; 442 HPT_U8 from_cc: 1; 443 HPT_U8 force_cc: 1; 444 } flags; 445 446 /* return status */ 447 HPT_U8 Result; 448 /* retry count */ 449 HPT_U8 RetryCount; 450 451 452 PSG psg; 453 454 455 int (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical); 456 void (*done)(struct _COMMAND *cmd); 457 } 458 COMMAND, *PCOMMAND; 459 460 /* command types */ 461 #define CMD_TYPE_IO 0 462 #define CMD_TYPE_CONTROL 1 463 #define CMD_TYPE_ATAPI 2 464 #define CMD_TYPE_SCSI CMD_TYPE_ATAPI 465 #define CMD_TYPE_PASSTHROUGH 3 466 #define CMD_TYPE_FLUSH 4 467 #define CMD_TYPE_IO_INDIRECT 0x80 468 469 /* flush command flags */ 470 #define CF_HARD_FLUSH_CACHE 1 471 #define CF_HARD_FLUSH_STANDBY 2 472 473 /* command return values */ 474 #define RETURN_PENDING 0 475 #define RETURN_SUCCESS 1 476 #define RETURN_BAD_DEVICE 2 477 #define RETURN_BAD_PARAMETER 3 478 #define RETURN_WRITE_NO_DRQ 4 479 #define RETURN_DEVICE_BUSY 5 480 #define RETURN_INVALID_REQUEST 6 481 #define RETURN_SELECTION_TIMEOUT 7 482 #define RETURN_IDE_ERROR 8 483 #define RETURN_NEED_LOGICAL_SG 9 484 #define RETURN_NEED_PHYSICAL_SG 10 485 #define RETURN_RETRY 11 486 #define RETURN_DATA_ERROR 12 487 #define RETURN_BUS_RESET 13 488 #define RETURN_BAD_TRANSFER_LENGTH 14 489 #define RETURN_INSUFFICIENT_MEMORY 15 490 #define RETURN_SECTOR_ERROR 16 491 #define RETURN_NEED_SPINUP 17 492 493 #if defined(__cplusplus) 494 } 495 #endif 496 #endif 497