1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 HighPoint Technologies, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <dev/hpt27xx/hpt27xx_config.h> 30 31 #ifndef _HPT_HIM_H_ 32 #define _HPT_HIM_H_ 33 34 #define VERMAGIC_HIM 55 35 36 #if defined(__cplusplus) 37 extern "C" { 38 #endif 39 40 #include <dev/hpt27xx/list.h> 41 42 #define SECTOR_TO_BYTE_SHIFT 9 43 #define SECTOR_TO_BYTE(x) ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT) 44 #define BYTE_TO_SECTOR(x) ((x)>>SECTOR_TO_BYTE_SHIFT) 45 46 typedef struct _PCI_ID 47 { 48 HPT_U16 vid; 49 HPT_U16 did; 50 HPT_U32 subsys; 51 HPT_U8 rev; 52 HPT_U8 nbase; 53 HPT_U16 reserve; 54 } 55 PCI_ID; 56 57 typedef struct _PCI_ADDRESS 58 { 59 HPT_U8 tree; 60 HPT_U8 bus; 61 HPT_U8 device; 62 HPT_U8 function; 63 } 64 PCI_ADDRESS; 65 66 typedef struct _HIM_ADAPTER_CONFIG 67 { 68 PCI_ADDRESS pci_addr; 69 PCI_ID pci_id; 70 71 HPT_U8 max_devices; 72 73 HPT_U8 bProbeInInitializing:1; 74 75 HPT_U8 bSpinupOneDevEachTime:1; 76 77 HPT_U8 bGlobalNcq:1; 78 HPT_U8 bSGPIOPartSupport:1; 79 80 HPT_U8 bNeedSASIdleTimer:1; 81 HPT_U8 reserved:3; 82 83 HPT_U8 bDevsPerBus; 84 HPT_U8 first_on_slot; 85 86 HPT_U8 bChipType; 87 HPT_U8 bChipIntrNum; 88 HPT_U8 bChipFlags; 89 HPT_U8 bNumBuses; 90 91 HPT_U8 szVendorID[36]; 92 HPT_U8 szProductID[36]; 93 HPT_U32 nvramSize; 94 HPT_U64 nvramAddress; 95 HPT_U8 slot_index; 96 HPT_U8 maxWidth; 97 HPT_U8 currentWidth; 98 HPT_U8 maxSpeed; 99 HPT_U8 currentSpeed; 100 HPT_U8 reserved2[7]; 101 } 102 HIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG; 103 104 typedef struct _HIM_CHANNEL_CONFIG 105 { 106 HPT_U32 io_port; 107 HPT_U32 ctl_port; 108 } HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG; 109 110 typedef struct _HIM_DEVICE_FLAGS 111 { 112 HPT_UINT df_atapi :1; 113 HPT_UINT df_removable_drive :1; 114 HPT_UINT df_on_line :1; 115 HPT_UINT df_reduce_mode :1; 116 HPT_UINT df_sata :1; 117 HPT_UINT df_on_pm_port :1; 118 HPT_UINT df_support_read_ahead :1; 119 HPT_UINT df_read_ahead_enabled :1; 120 HPT_UINT df_support_write_cache :1; 121 HPT_UINT df_write_cache_enabled :1; 122 HPT_UINT df_cdrom_device :1; 123 HPT_UINT df_tape_device :1; 124 HPT_UINT df_changer_device :1; 125 HPT_UINT df_support_tcq :1; 126 HPT_UINT df_tcq_enabled :1; 127 HPT_UINT df_support_ncq :1; 128 HPT_UINT df_ncq_enabled :1; 129 HPT_UINT df_sas :1; 130 HPT_UINT df_in_enclosure :1; 131 HPT_UINT df_ssd :1; 132 } DEVICE_FLAGS, *PDEVICE_FLAGS; 133 134 #pragma pack(1) 135 typedef struct _IDENTIFY_DATA { 136 HPT_U16 GeneralConfiguration; 137 HPT_U16 NumberOfCylinders; 138 HPT_U16 Reserved1; 139 HPT_U16 NumberOfHeads; 140 HPT_U16 UnformattedBytesPerTrack; 141 HPT_U16 UnformattedBytesPerSector; 142 HPT_U8 SasAddress[8]; 143 HPT_U16 SerialNumber[10]; 144 HPT_U16 BufferType; 145 HPT_U16 BufferSectorSize; 146 HPT_U16 NumberOfEccBytes; 147 HPT_U16 FirmwareRevision[4]; 148 HPT_U16 ModelNumber[20]; 149 HPT_U8 MaximumBlockTransfer; 150 HPT_U8 VendorUnique2; 151 HPT_U16 DoubleWordIo; 152 HPT_U16 Capabilities; 153 HPT_U16 Reserved2; 154 HPT_U8 VendorUnique3; 155 HPT_U8 PioCycleTimingMode; 156 HPT_U8 VendorUnique4; 157 HPT_U8 DmaCycleTimingMode; 158 HPT_U16 TranslationFieldsValid; 159 HPT_U16 NumberOfCurrentCylinders; 160 HPT_U16 NumberOfCurrentHeads; 161 HPT_U16 CurrentSectorsPerTrack; 162 HPT_U32 CurrentSectorCapacity; 163 HPT_U16 CurrentMultiSectorSetting; 164 HPT_U32 UserAddressableSectors; 165 HPT_U8 SingleWordDMASupport; 166 HPT_U8 SingleWordDMAActive; 167 HPT_U8 MultiWordDMASupport; 168 HPT_U8 MultiWordDMAActive; 169 HPT_U8 AdvancedPIOModes; 170 HPT_U8 Reserved4; 171 HPT_U16 MinimumMWXferCycleTime; 172 HPT_U16 RecommendedMWXferCycleTime; 173 HPT_U16 MinimumPIOCycleTime; 174 HPT_U16 MinimumPIOCycleTimeIORDY; 175 HPT_U16 Reserved5[2]; 176 HPT_U16 ReleaseTimeOverlapped; 177 HPT_U16 ReleaseTimeServiceCommand; 178 HPT_U16 MajorRevision; 179 HPT_U16 MinorRevision; 180 HPT_U16 MaxQueueDepth; 181 HPT_U16 SataCapability; 182 HPT_U16 Reserved6[9]; 183 HPT_U16 CommandSupport; 184 HPT_U16 CommandEnable; 185 HPT_U16 UtralDmaMode; 186 HPT_U16 Reserved7[11]; 187 HPT_U32 Lba48BitLow; 188 HPT_U32 Lba48BitHigh; 189 HPT_U16 Reserved8[23]; 190 HPT_U16 SpecialFunctionsEnabled; 191 HPT_U16 Reserved9[128]; 192 } 193 #ifdef __GNUC__ 194 __attribute__((packed)) 195 #endif 196 IDENTIFY_DATA, *PIDENTIFY_DATA; 197 #pragma pack() 198 199 typedef struct _HIM_DEVICE_CONFIG 200 { 201 HPT_U64 capacity; 202 HPT_U32 logical_sector_size; 203 204 DEVICE_FLAGS flags; 205 206 HPT_U8 path_id; 207 HPT_U8 target_id; 208 HPT_U8 max_queue_depth; 209 HPT_U8 spin_up_mode; 210 211 HPT_U8 reserved; 212 HPT_U8 transfer_mode; 213 HPT_U8 bMaxShowMode; 214 HPT_U8 bDeUsable_Mode; 215 216 HPT_U16 max_sectors_per_cmd; 217 218 PIDENTIFY_DATA pIdentifyData; 219 220 221 HPT_U8 fixed_path_id; /*equals to phy id */ 222 } 223 HIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG; 224 225 226 #define _DIT_MODE 0 227 #define _DIT_601 1 228 #define _DIT_READ_AHEAD 2 229 #define _DIT_WRITE_CACHE 3 230 #define _DIT_TCQ 4 231 #define _DIT_NCQ 5 232 #define _DIT_BEEP_OFF 6 233 #define _DIT_SPIN_UP_MODE 7 234 #define _DIT_IDLE_STANDBY 8 235 #define _DIT_IDENTIFY 9 236 237 #define SPIN_UP_MODE_NOSUPPORT 0 238 #define SPIN_UP_MODE_FULL 1 239 #define SPIN_UP_MODE_STANDBY 2 240 241 struct tcq_control { 242 HPT_U8 enable; 243 HPT_U8 depth; 244 }; 245 246 struct ncq_control { 247 HPT_U8 enable; 248 HPT_U8 depth; 249 }; 250 251 typedef struct _HIM_ALTERABLE_DEV_INFO{ 252 HPT_U8 type; 253 union { 254 HPT_U8 mode; 255 HPT_U8 enable_read_ahead; 256 HPT_U8 enable_read_cache; 257 HPT_U8 enable_write_cache; 258 struct tcq_control tcq; 259 struct ncq_control ncq; 260 void * adapter; 261 HPT_U8 spin_up_mode; 262 HPT_U8 idle_standby_timeout; 263 HPT_U8 identify_indicator; 264 }u; 265 } HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO; 266 267 struct _COMMAND; 268 struct _IOCTL_ARG; 269 270 typedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index); 271 272 typedef struct _HIM { 273 char *name; 274 struct _HIM *next; 275 HPT_UINT max_sg_descriptors; 276 #define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args; 277 #include <dev/hpt27xx/himfuncs.h> 278 } 279 HIM, *PHIM; 280 281 282 #pragma pack(1) 283 #ifdef SG_FLAG_EOT 284 #error "don't use SG_FLAG_EOT with _SG.eot. clean the code!" 285 #endif 286 287 typedef struct _SG { 288 HPT_U32 size; 289 HPT_UINT eot; 290 union { 291 HPT_U8 FAR * _logical; 292 BUS_ADDRESS bus; 293 } 294 addr; 295 } 296 SG, *PSG; 297 #pragma pack() 298 299 typedef struct _AtaCommand 300 { 301 HPT_U64 Lba; 302 HPT_U16 nSectors; 303 HPT_U16 pad; 304 } AtaComm, *PAtaComm; 305 306 #define ATA_CMD_NOP 0x0 307 308 #define ATA_CMD_SET_FEATURES 0xef 309 #define ATA_CMD_FLUSH 0xE7 310 #define ATA_CMD_VERIFY 0x40 311 #define ATA_CMD_STANDBY 0xe2 312 #define ATA_CMD_READ_MULTI 0xC4 313 #define ATA_CMD_READ_MULTI_EXT 0x29 314 #define ATA_CMD_WRITE_MULTI 0xC5 315 #define ATA_CMD_WRITE_MULTI_EXT 0x39 316 #define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE 317 318 #define ATA_CMD_READ_DMA 0xc8 /* IDE DMA read command */ 319 #define ATA_CMD_WRITE_DMA 0xca /* IDE DMA write command */ 320 #define ATA_CMD_READ_DMA_EXT 0x25 321 #define ATA_CMD_READ_QUEUE_EXT 0x26 322 #define ATA_CMD_READ_MAX_ADDR 0x27 323 #define ATA_CMD_READ_EXT 0x24 324 #define ATA_CMD_VERIFY_EXT 0x42 325 #define ATA_CMD_WRITE_DMA_EXT 0x35 326 #define ATA_CMD_WRITE_QUEUE_EXT 0x36 327 #define ATA_CMD_WRITE_EXT 0x34 328 329 #define ATA_SET_FEATURES_XFER 0x3 330 #define ATA_SECTOR_SIZE 512 331 332 typedef struct _PassthroughCmd { 333 HPT_U16 bFeaturesReg; 334 HPT_U16 bSectorCountReg; 335 HPT_U16 bLbaLowReg; 336 HPT_U16 bLbaMidReg; 337 HPT_U16 bLbaHighReg; 338 HPT_U8 bDriveHeadReg; 339 HPT_U8 bCommandReg; 340 HPT_U16 nSectors; 341 HPT_U8 *pDataBuffer; 342 } 343 PassthroughCmd; 344 345 typedef struct _ScsiComm { 346 HPT_U8 cdbLength; 347 HPT_U8 senseLength; 348 HPT_U8 scsiStatus; 349 HPT_U8 reserve1; 350 HPT_U32 dataLength; 351 HPT_U8 cdb[16]; 352 HPT_U8 *senseBuffer; 353 } 354 ScsiComm; 355 356 typedef struct _ScsiExtComm { 357 HPT_U8 cdbLength; 358 HPT_U8 senseLength; 359 HPT_U8 scsiStatus; 360 HPT_U8 reserve1; 361 HPT_U32 dataLength; 362 HPT_U8 cdb[16]; 363 HPT_U8 *senseBuffer; 364 HPT_U8 lun[8]; 365 } 366 ScsiExtComm; 367 368 369 #define CTRL_CMD_REBUILD 1 370 #define CTRL_CMD_VERIFY 2 371 #define CTRL_CMD_INIT 3 372 373 374 typedef struct _R5ControlCmd { 375 HPT_U64 StripeLine; 376 HPT_U16 Offset; 377 HPT_U8 Command; 378 HPT_U8 CmdTarget; 379 } 380 R5ControlCmd, *PR5ControlCmd; 381 382 typedef struct _HPT_ADDRESS 383 { 384 HPT_U8 * logical; 385 BUS_ADDRESS bus; 386 } 387 HPT_ADDRESS; 388 389 390 typedef struct ctl_pages { 391 HPT_ADDRESS *pages; 392 HPT_UINT page_size; 393 HPT_UINT npages; 394 HPT_UINT min_sg_descriptors; 395 } CONTROL_PAGES, *PCONTROL_PAGES; 396 397 typedef struct _R1ControlCmd { 398 HPT_U64 Lba; 399 HPT_U16 nSectors; 400 HPT_U8 Command; 401 HPT_U8 CmdTarget; 402 PCONTROL_PAGES ctl_pages; 403 } 404 R1ControlCmd, *PR1ControlCmd; 405 406 typedef void (*TQ_PROC)(void *arg); 407 408 struct tq_item { 409 TQ_PROC proc; 410 void *arg; 411 struct tq_item *next; 412 }; 413 414 #define INIT_TQ_ITEM(t, p, a) \ 415 do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0) 416 417 typedef struct _COMMAND 418 { 419 420 struct _VBUS * vbus; 421 422 struct freelist *grplist; 423 HPT_UINT grpcnt; 424 425 426 struct list_head q_link; 427 struct tq_item done_dpc; 428 429 HPT_UINT extsize; 430 void *ext; 431 432 433 434 void *target; 435 void *priv; 436 HPT_UPTR priv2; 437 438 int priority; 439 struct lock_request *owned_lock; 440 struct lock_request *lock_req; 441 void (*dtor)(struct _COMMAND *, void *); 442 void *dtor_arg; 443 444 union{ 445 AtaComm Ide; 446 PassthroughCmd Passthrough; 447 ScsiComm Scsi; 448 ScsiExtComm ScsiExt; 449 R5ControlCmd R5Control; 450 R1ControlCmd R1Control; 451 } uCmd; 452 453 HPT_U8 type; /* CMD_TYPE_* */ 454 455 struct { 456 HPT_U8 physical_sg: 1; 457 HPT_U8 data_in: 1; 458 HPT_U8 data_out: 1; 459 HPT_U8 transform : 1; 460 HPT_U8 hard_flush: 2; 461 HPT_U8 from_cc: 1; 462 HPT_U8 force_cc: 1; 463 } flags; 464 465 /* return status */ 466 HPT_U8 Result; 467 /* retry count */ 468 HPT_U8 RetryCount; 469 470 471 PSG psg; 472 473 474 int (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical); 475 void (*done)(struct _COMMAND *cmd); 476 } 477 COMMAND, *PCOMMAND; 478 479 /* command types */ 480 #define CMD_TYPE_IO 0 481 #define CMD_TYPE_CONTROL 1 482 #define CMD_TYPE_ATAPI 2 483 #define CMD_TYPE_SCSI CMD_TYPE_ATAPI 484 #define CMD_TYPE_PASSTHROUGH 3 485 #define CMD_TYPE_FLUSH 4 486 #define CMD_TYPE_SCSI_EXT 5 487 #define CMD_TYPE_IO_INDIRECT 0x80 488 489 /* flush command flags */ 490 #define CF_HARD_FLUSH_CACHE 1 491 #define CF_HARD_FLUSH_STANDBY 2 492 493 /* command return values */ 494 #define RETURN_PENDING 0 495 #define RETURN_SUCCESS 1 496 #define RETURN_BAD_DEVICE 2 497 #define RETURN_BAD_PARAMETER 3 498 #define RETURN_WRITE_NO_DRQ 4 499 #define RETURN_DEVICE_BUSY 5 500 #define RETURN_INVALID_REQUEST 6 501 #define RETURN_SELECTION_TIMEOUT 7 502 #define RETURN_IDE_ERROR 8 503 #define RETURN_NEED_LOGICAL_SG 9 504 #define RETURN_NEED_PHYSICAL_SG 10 505 #define RETURN_RETRY 11 506 #define RETURN_DATA_ERROR 12 507 #define RETURN_BUS_RESET 13 508 #define RETURN_BAD_TRANSFER_LENGTH 14 509 #define RETURN_INSUFFICIENT_MEMORY 15 510 #define RETURN_SECTOR_ERROR 16 511 #define RETURN_NEED_SPINUP 17 512 513 #if defined(__cplusplus) 514 } 515 #endif 516 #endif 517