xref: /freebsd/sys/dev/hifn/hifn7751reg.h (revision e4e9813eb92cd7c4d4b819a8fbed5cbd3d92f5d8)
1 /* $FreeBSD$ */
2 /*	$OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $	*/
3 
4 /*-
5  * Invertex AEON / Hifn 7751 driver
6  * Copyright (c) 1999 Invertex Inc. All rights reserved.
7  * Copyright (c) 1999 Theo de Raadt
8  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
9  *			http://www.netsec.net
10  *
11  * Please send any comments, feedback, bug-fixes, or feature requests to
12  * software@invertex.com.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions
16  * are met:
17  *
18  * 1. Redistributions of source code must retain the above copyright
19  *    notice, this list of conditions and the following disclaimer.
20  * 2. Redistributions in binary form must reproduce the above copyright
21  *    notice, this list of conditions and the following disclaimer in the
22  *    documentation and/or other materials provided with the distribution.
23  * 3. The name of the author may not be used to endorse or promote products
24  *    derived from this software without specific prior written permission.
25  *
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  *
38  * Effort sponsored in part by the Defense Advanced Research Projects
39  * Agency (DARPA) and Air Force Research Laboratory, Air Force
40  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
41  *
42  */
43 #ifndef __HIFN_H__
44 #define	__HIFN_H__
45 
46 #include <sys/endian.h>
47 
48 /*
49  * Some PCI configuration space offset defines.  The names were made
50  * identical to the names used by the Linux kernel.
51  */
52 #define	HIFN_BAR0		PCIR_BAR(0)	/* PUC register map */
53 #define	HIFN_BAR1		PCIR_BAR(1)	/* DMA register map */
54 #define	HIFN_TRDY_TIMEOUT	0x40
55 #define	HIFN_RETRY_TIMEOUT	0x41
56 
57 /*
58  * PCI vendor and device identifiers
59  * (the names are preserved from their OpenBSD source).
60  */
61 #define	PCI_VENDOR_HIFN		0x13a3		/* Hifn */
62 #define	PCI_PRODUCT_HIFN_7751	0x0005		/* 7751 */
63 #define	PCI_PRODUCT_HIFN_6500	0x0006		/* 6500 */
64 #define	PCI_PRODUCT_HIFN_7811	0x0007		/* 7811 */
65 #define	PCI_PRODUCT_HIFN_7951	0x0012		/* 7951 */
66 #define	PCI_PRODUCT_HIFN_7955	0x0020		/* 7954/7955 */
67 #define	PCI_PRODUCT_HIFN_7956	0x001d		/* 7956 */
68 
69 #define	PCI_VENDOR_INVERTEX	0x14e1		/* Invertex */
70 #define	PCI_PRODUCT_INVERTEX_AEON 0x0005	/* AEON */
71 
72 #define	PCI_VENDOR_NETSEC	0x1660		/* NetSec */
73 #define	PCI_PRODUCT_NETSEC_7751	0x7751		/* 7751 */
74 
75 /*
76  * The values below should multiple of 4 -- and be large enough to handle
77  * any command the driver implements.
78  *
79  * MAX_COMMAND = base command + mac command + encrypt command +
80  *			mac-key + rc4-key
81  * MAX_RESULT  = base result + mac result + mac + encrypt result
82  *
83  *
84  */
85 #define	HIFN_MAX_COMMAND	(8 + 8 + 8 + 64 + 260)
86 #define	HIFN_MAX_RESULT		(8 + 4 + 20 + 4)
87 
88 /*
89  * hifn_desc_t
90  *
91  * Holds an individual descriptor for any of the rings.
92  */
93 typedef struct hifn_desc {
94 	volatile u_int32_t l;		/* length and status bits */
95 	volatile u_int32_t p;
96 } hifn_desc_t;
97 
98 /*
99  * Masks for the "length" field of struct hifn_desc.
100  */
101 #define	HIFN_D_LENGTH		0x0000ffff	/* length bit mask */
102 #define	HIFN_D_MASKDONEIRQ	0x02000000	/* mask the done interrupt */
103 #define	HIFN_D_DESTOVER		0x04000000	/* destination overflow */
104 #define	HIFN_D_OVER		0x08000000	/* overflow */
105 #define	HIFN_D_LAST		0x20000000	/* last descriptor in chain */
106 #define	HIFN_D_JUMP		0x40000000	/* jump descriptor */
107 #define	HIFN_D_VALID		0x80000000	/* valid bit */
108 
109 
110 /*
111  * Processing Unit Registers (offset from BASEREG0)
112  */
113 #define	HIFN_0_PUDATA		0x00	/* Processing Unit Data */
114 #define	HIFN_0_PUCTRL		0x04	/* Processing Unit Control */
115 #define	HIFN_0_PUISR		0x08	/* Processing Unit Interrupt Status */
116 #define	HIFN_0_PUCNFG		0x0c	/* Processing Unit Configuration */
117 #define	HIFN_0_PUIER		0x10	/* Processing Unit Interrupt Enable */
118 #define	HIFN_0_PUSTAT		0x14	/* Processing Unit Status/Chip ID */
119 #define	HIFN_0_FIFOSTAT		0x18	/* FIFO Status */
120 #define	HIFN_0_FIFOCNFG		0x1c	/* FIFO Configuration */
121 #define	HIFN_0_SPACESIZE	0x20	/* Register space size */
122 
123 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
124 #define	HIFN_PUCTRL_CLRSRCFIFO	0x0010	/* clear source fifo */
125 #define	HIFN_PUCTRL_STOP	0x0008	/* stop pu */
126 #define	HIFN_PUCTRL_LOCKRAM	0x0004	/* lock ram */
127 #define	HIFN_PUCTRL_DMAENA	0x0002	/* enable dma */
128 #define	HIFN_PUCTRL_RESET	0x0001	/* Reset processing unit */
129 
130 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
131 #define	HIFN_PUISR_CMDINVAL	0x8000	/* Invalid command interrupt */
132 #define	HIFN_PUISR_DATAERR	0x4000	/* Data error interrupt */
133 #define	HIFN_PUISR_SRCFIFO	0x2000	/* Source FIFO ready interrupt */
134 #define	HIFN_PUISR_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */
135 #define	HIFN_PUISR_DSTOVER	0x0200	/* Destination overrun interrupt */
136 #define	HIFN_PUISR_SRCCMD	0x0080	/* Source command interrupt */
137 #define	HIFN_PUISR_SRCCTX	0x0040	/* Source context interrupt */
138 #define	HIFN_PUISR_SRCDATA	0x0020	/* Source data interrupt */
139 #define	HIFN_PUISR_DSTDATA	0x0010	/* Destination data interrupt */
140 #define	HIFN_PUISR_DSTRESULT	0x0004	/* Destination result interrupt */
141 
142 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
143 #define	HIFN_PUCNFG_DRAMMASK	0xe000	/* DRAM size mask */
144 #define	HIFN_PUCNFG_DSZ_256K	0x0000	/* 256k dram */
145 #define	HIFN_PUCNFG_DSZ_512K	0x2000	/* 512k dram */
146 #define	HIFN_PUCNFG_DSZ_1M	0x4000	/* 1m dram */
147 #define	HIFN_PUCNFG_DSZ_2M	0x6000	/* 2m dram */
148 #define	HIFN_PUCNFG_DSZ_4M	0x8000	/* 4m dram */
149 #define	HIFN_PUCNFG_DSZ_8M	0xa000	/* 8m dram */
150 #define	HIFN_PUNCFG_DSZ_16M	0xc000	/* 16m dram */
151 #define	HIFN_PUCNFG_DSZ_32M	0xe000	/* 32m dram */
152 #define	HIFN_PUCNFG_DRAMREFRESH	0x1800	/* DRAM refresh rate mask */
153 #define	HIFN_PUCNFG_DRFR_512	0x0000	/* 512 divisor of ECLK */
154 #define	HIFN_PUCNFG_DRFR_256	0x0800	/* 256 divisor of ECLK */
155 #define	HIFN_PUCNFG_DRFR_128	0x1000	/* 128 divisor of ECLK */
156 #define	HIFN_PUCNFG_TCALLPHASES	0x0200	/* your guess is as good as mine... */
157 #define	HIFN_PUCNFG_TCDRVTOTEM	0x0100	/* your guess is as good as mine... */
158 #define	HIFN_PUCNFG_BIGENDIAN	0x0080	/* DMA big endian mode */
159 #define	HIFN_PUCNFG_BUS32	0x0040	/* Bus width 32bits */
160 #define	HIFN_PUCNFG_BUS16	0x0000	/* Bus width 16 bits */
161 #define	HIFN_PUCNFG_CHIPID	0x0020	/* Allow chipid from PUSTAT */
162 #define	HIFN_PUCNFG_DRAM	0x0010	/* Context RAM is DRAM */
163 #define	HIFN_PUCNFG_SRAM	0x0000	/* Context RAM is SRAM */
164 #define	HIFN_PUCNFG_COMPSING	0x0004	/* Enable single compression context */
165 #define	HIFN_PUCNFG_ENCCNFG	0x0002	/* Encryption configuration */
166 
167 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
168 #define	HIFN_PUIER_CMDINVAL	0x8000	/* Invalid command interrupt */
169 #define	HIFN_PUIER_DATAERR	0x4000	/* Data error interrupt */
170 #define	HIFN_PUIER_SRCFIFO	0x2000	/* Source FIFO ready interrupt */
171 #define	HIFN_PUIER_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */
172 #define	HIFN_PUIER_DSTOVER	0x0200	/* Destination overrun interrupt */
173 #define	HIFN_PUIER_SRCCMD	0x0080	/* Source command interrupt */
174 #define	HIFN_PUIER_SRCCTX	0x0040	/* Source context interrupt */
175 #define	HIFN_PUIER_SRCDATA	0x0020	/* Source data interrupt */
176 #define	HIFN_PUIER_DSTDATA	0x0010	/* Destination data interrupt */
177 #define	HIFN_PUIER_DSTRESULT	0x0004	/* Destination result interrupt */
178 
179 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
180 #define	HIFN_PUSTAT_CMDINVAL	0x8000	/* Invalid command interrupt */
181 #define	HIFN_PUSTAT_DATAERR	0x4000	/* Data error interrupt */
182 #define	HIFN_PUSTAT_SRCFIFO	0x2000	/* Source FIFO ready interrupt */
183 #define	HIFN_PUSTAT_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */
184 #define	HIFN_PUSTAT_DSTOVER	0x0200	/* Destination overrun interrupt */
185 #define	HIFN_PUSTAT_SRCCMD	0x0080	/* Source command interrupt */
186 #define	HIFN_PUSTAT_SRCCTX	0x0040	/* Source context interrupt */
187 #define	HIFN_PUSTAT_SRCDATA	0x0020	/* Source data interrupt */
188 #define	HIFN_PUSTAT_DSTDATA	0x0010	/* Destination data interrupt */
189 #define	HIFN_PUSTAT_DSTRESULT	0x0004	/* Destination result interrupt */
190 #define	HIFN_PUSTAT_CHIPREV	0x00ff	/* Chip revision mask */
191 #define	HIFN_PUSTAT_CHIPENA	0xff00	/* Chip enabled mask */
192 #define	HIFN_PUSTAT_ENA_2	0x1100	/* Level 2 enabled */
193 #define	HIFN_PUSTAT_ENA_1	0x1000	/* Level 1 enabled */
194 #define	HIFN_PUSTAT_ENA_0	0x3000	/* Level 0 enabled */
195 #define	HIFN_PUSTAT_REV_2	0x0020	/* 7751 PT6/2 */
196 #define	HIFN_PUSTAT_REV_3	0x0030	/* 7751 PT6/3 */
197 
198 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
199 #define	HIFN_FIFOSTAT_SRC	0x7f00	/* Source FIFO available */
200 #define	HIFN_FIFOSTAT_DST	0x007f	/* Destination FIFO available */
201 
202 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
203 #define	HIFN_FIFOCNFG_THRESHOLD	0x0400	/* must be written as 1 */
204 
205 /*
206  * DMA Interface Registers (offset from BASEREG1)
207  */
208 #define	HIFN_1_DMA_CRAR		0x0c	/* DMA Command Ring Address */
209 #define	HIFN_1_DMA_SRAR		0x1c	/* DMA Source Ring Address */
210 #define	HIFN_1_DMA_RRAR		0x2c	/* DMA Result Ring Address */
211 #define	HIFN_1_DMA_DRAR		0x3c	/* DMA Destination Ring Address */
212 #define	HIFN_1_DMA_CSR		0x40	/* DMA Status and Control */
213 #define	HIFN_1_DMA_IER		0x44	/* DMA Interrupt Enable */
214 #define	HIFN_1_DMA_CNFG		0x48	/* DMA Configuration */
215 #define	HIFN_1_PLL		0x4c	/* 7955/7956: PLL config */
216 #define	HIFN_1_7811_RNGENA	0x60	/* 7811: rng enable */
217 #define	HIFN_1_7811_RNGCFG	0x64	/* 7811: rng config */
218 #define	HIFN_1_7811_RNGDAT	0x68	/* 7811: rng data */
219 #define	HIFN_1_7811_RNGSTS	0x6c	/* 7811: rng status */
220 #define	HIFN_1_7811_MIPSRST	0x94	/* 7811: MIPS reset */
221 #define	HIFN_1_REVID		0x98	/* Revision ID */
222 
223 #define	HIFN_1_PUB_RESET	0x204	/* Public/RNG Reset */
224 #define	HIFN_1_PUB_BASE		0x300	/* Public Base Address */
225 #define	HIFN_1_PUB_OPLEN	0x304	/* Public Operand Length */
226 #define	HIFN_1_PUB_OP		0x308	/* Public Operand */
227 #define	HIFN_1_PUB_STATUS	0x30c	/* Public Status */
228 #define	HIFN_1_PUB_IEN		0x310	/* Public Interrupt nable */
229 #define	HIFN_1_RNG_CONFIG	0x314	/* RNG config */
230 #define	HIFN_1_RNG_DATA		0x318	/* RNG data */
231 #define	HIFN_1_PUB_MEM		0x400	/* start of Public key memory */
232 #define	HIFN_1_PUB_MEMEND	0xbff	/* end of Public key memory */
233 
234 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
235 #define	HIFN_DMACSR_D_CTRLMASK	0xc0000000	/* Destinition Ring Control */
236 #define	HIFN_DMACSR_D_CTRL_NOP	0x00000000	/* Dest. Control: no-op */
237 #define	HIFN_DMACSR_D_CTRL_DIS	0x40000000	/* Dest. Control: disable */
238 #define	HIFN_DMACSR_D_CTRL_ENA	0x80000000	/* Dest. Control: enable */
239 #define	HIFN_DMACSR_D_ABORT	0x20000000	/* Destinition Ring PCIAbort */
240 #define	HIFN_DMACSR_D_DONE	0x10000000	/* Destinition Ring Done */
241 #define	HIFN_DMACSR_D_LAST	0x08000000	/* Destinition Ring Last */
242 #define	HIFN_DMACSR_D_WAIT	0x04000000	/* Destinition Ring Waiting */
243 #define	HIFN_DMACSR_D_OVER	0x02000000	/* Destinition Ring Overflow */
244 #define	HIFN_DMACSR_R_CTRL	0x00c00000	/* Result Ring Control */
245 #define	HIFN_DMACSR_R_CTRL_NOP	0x00000000	/* Result Control: no-op */
246 #define	HIFN_DMACSR_R_CTRL_DIS	0x00400000	/* Result Control: disable */
247 #define	HIFN_DMACSR_R_CTRL_ENA	0x00800000	/* Result Control: enable */
248 #define	HIFN_DMACSR_R_ABORT	0x00200000	/* Result Ring PCI Abort */
249 #define	HIFN_DMACSR_R_DONE	0x00100000	/* Result Ring Done */
250 #define	HIFN_DMACSR_R_LAST	0x00080000	/* Result Ring Last */
251 #define	HIFN_DMACSR_R_WAIT	0x00040000	/* Result Ring Waiting */
252 #define	HIFN_DMACSR_R_OVER	0x00020000	/* Result Ring Overflow */
253 #define	HIFN_DMACSR_S_CTRL	0x0000c000	/* Source Ring Control */
254 #define	HIFN_DMACSR_S_CTRL_NOP	0x00000000	/* Source Control: no-op */
255 #define	HIFN_DMACSR_S_CTRL_DIS	0x00004000	/* Source Control: disable */
256 #define	HIFN_DMACSR_S_CTRL_ENA	0x00008000	/* Source Control: enable */
257 #define	HIFN_DMACSR_S_ABORT	0x00002000	/* Source Ring PCI Abort */
258 #define	HIFN_DMACSR_S_DONE	0x00001000	/* Source Ring Done */
259 #define	HIFN_DMACSR_S_LAST	0x00000800	/* Source Ring Last */
260 #define	HIFN_DMACSR_S_WAIT	0x00000400	/* Source Ring Waiting */
261 #define	HIFN_DMACSR_ILLW	0x00000200	/* Illegal write (7811 only) */
262 #define	HIFN_DMACSR_ILLR	0x00000100	/* Illegal read (7811 only) */
263 #define	HIFN_DMACSR_C_CTRL	0x000000c0	/* Command Ring Control */
264 #define	HIFN_DMACSR_C_CTRL_NOP	0x00000000	/* Command Control: no-op */
265 #define	HIFN_DMACSR_C_CTRL_DIS	0x00000040	/* Command Control: disable */
266 #define	HIFN_DMACSR_C_CTRL_ENA	0x00000080	/* Command Control: enable */
267 #define	HIFN_DMACSR_C_ABORT	0x00000020	/* Command Ring PCI Abort */
268 #define	HIFN_DMACSR_C_DONE	0x00000010	/* Command Ring Done */
269 #define	HIFN_DMACSR_C_LAST	0x00000008	/* Command Ring Last */
270 #define	HIFN_DMACSR_C_WAIT	0x00000004	/* Command Ring Waiting */
271 #define	HIFN_DMACSR_PUBDONE	0x00000002	/* Public op done (7951 only) */
272 #define	HIFN_DMACSR_ENGINE	0x00000001	/* Command Ring Engine IRQ */
273 
274 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
275 #define	HIFN_DMAIER_D_ABORT	0x20000000	/* Destination Ring PCIAbort */
276 #define	HIFN_DMAIER_D_DONE	0x10000000	/* Destination Ring Done */
277 #define	HIFN_DMAIER_D_LAST	0x08000000	/* Destination Ring Last */
278 #define	HIFN_DMAIER_D_WAIT	0x04000000	/* Destination Ring Waiting */
279 #define	HIFN_DMAIER_D_OVER	0x02000000	/* Destination Ring Overflow */
280 #define	HIFN_DMAIER_R_ABORT	0x00200000	/* Result Ring PCI Abort */
281 #define	HIFN_DMAIER_R_DONE	0x00100000	/* Result Ring Done */
282 #define	HIFN_DMAIER_R_LAST	0x00080000	/* Result Ring Last */
283 #define	HIFN_DMAIER_R_WAIT	0x00040000	/* Result Ring Waiting */
284 #define	HIFN_DMAIER_R_OVER	0x00020000	/* Result Ring Overflow */
285 #define	HIFN_DMAIER_S_ABORT	0x00002000	/* Source Ring PCI Abort */
286 #define	HIFN_DMAIER_S_DONE	0x00001000	/* Source Ring Done */
287 #define	HIFN_DMAIER_S_LAST	0x00000800	/* Source Ring Last */
288 #define	HIFN_DMAIER_S_WAIT	0x00000400	/* Source Ring Waiting */
289 #define	HIFN_DMAIER_ILLW	0x00000200	/* Illegal write (7811 only) */
290 #define	HIFN_DMAIER_ILLR	0x00000100	/* Illegal read (7811 only) */
291 #define	HIFN_DMAIER_C_ABORT	0x00000020	/* Command Ring PCI Abort */
292 #define	HIFN_DMAIER_C_DONE	0x00000010	/* Command Ring Done */
293 #define	HIFN_DMAIER_C_LAST	0x00000008	/* Command Ring Last */
294 #define	HIFN_DMAIER_C_WAIT	0x00000004	/* Command Ring Waiting */
295 #define	HIFN_DMAIER_PUBDONE	0x00000002	/* public op done (7951 only) */
296 #define	HIFN_DMAIER_ENGINE	0x00000001	/* Engine IRQ */
297 
298 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
299 #define	HIFN_DMACNFG_BIGENDIAN	0x10000000	/* big endian mode */
300 #define	HIFN_DMACNFG_POLLFREQ	0x00ff0000	/* Poll frequency mask */
301 #define	HIFN_DMACNFG_UNLOCK	0x00000800
302 #define	HIFN_DMACNFG_POLLINVAL	0x00000700	/* Invalid Poll Scalar */
303 #define	HIFN_DMACNFG_LAST	0x00000010	/* Host control LAST bit */
304 #define	HIFN_DMACNFG_MODE	0x00000004	/* DMA mode */
305 #define	HIFN_DMACNFG_DMARESET	0x00000002	/* DMA Reset # */
306 #define	HIFN_DMACNFG_MSTRESET	0x00000001	/* Master Reset # */
307 
308 /* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */
309 #define	HIFN_7811_RNGENA_ENA	0x00000001	/* enable RNG */
310 
311 /* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */
312 #define	HIFN_7811_RNGCFG_PRE1	0x00000f00	/* first prescalar */
313 #define	HIFN_7811_RNGCFG_OPRE	0x00000080	/* output prescalar */
314 #define	HIFN_7811_RNGCFG_DEFL	0x00000f80	/* 2 words/ 1/100 sec */
315 
316 /* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */
317 #define	HIFN_7811_RNGSTS_RDY	0x00004000	/* two numbers in FIFO */
318 #define	HIFN_7811_RNGSTS_UFL	0x00001000	/* rng underflow */
319 
320 /* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */
321 #define	HIFN_MIPSRST_BAR2SIZE	0xffff0000	/* sdram size */
322 #define	HIFN_MIPSRST_GPRAMINIT	0x00008000	/* gpram can be accessed */
323 #define	HIFN_MIPSRST_CRAMINIT	0x00004000	/* ctxram can be accessed */
324 #define	HIFN_MIPSRST_LED2	0x00000400	/* external LED2 */
325 #define	HIFN_MIPSRST_LED1	0x00000200	/* external LED1 */
326 #define	HIFN_MIPSRST_LED0	0x00000100	/* external LED0 */
327 #define	HIFN_MIPSRST_MIPSDIS	0x00000004	/* disable MIPS */
328 #define	HIFN_MIPSRST_MIPSRST	0x00000002	/* warm reset MIPS */
329 #define	HIFN_MIPSRST_MIPSCOLD	0x00000001	/* cold reset MIPS */
330 
331 /* Public key reset register (HIFN_1_PUB_RESET) */
332 #define	HIFN_PUBRST_RESET	0x00000001	/* reset public/rng unit */
333 
334 /* Public operation register (HIFN_1_PUB_OP) */
335 #define	HIFN_PUBOP_AOFFSET	0x0000003e	/* A offset */
336 #define	HIFN_PUBOP_BOFFSET	0x00000fc0	/* B offset */
337 #define	HIFN_PUBOP_MOFFSET	0x0003f000	/* M offset */
338 #define	HIFN_PUBOP_OP_MASK	0x003c0000	/* Opcode: */
339 #define	HIFN_PUBOP_OP_NOP	0x00000000	/*  NOP */
340 #define	HIFN_PUBOP_OP_ADD	0x00040000	/*  ADD */
341 #define	HIFN_PUBOP_OP_ADDC	0x00080000	/*  ADD w/carry */
342 #define	HIFN_PUBOP_OP_SUB	0x000c0000	/*  SUB */
343 #define	HIFN_PUBOP_OP_SUBC	0x00100000	/*  SUB w/carry */
344 #define	HIFN_PUBOP_OP_MODADD	0x00140000	/*  Modular ADD */
345 #define	HIFN_PUBOP_OP_MODSUB	0x00180000	/*  Modular SUB */
346 #define	HIFN_PUBOP_OP_INCA	0x001c0000	/*  INC A */
347 #define	HIFN_PUBOP_OP_DECA	0x00200000	/*  DEC A */
348 #define	HIFN_PUBOP_OP_MULT	0x00240000	/*  MULT */
349 #define	HIFN_PUBOP_OP_MODMULT	0x00280000	/*  Modular MULT */
350 #define	HIFN_PUBOP_OP_MODRED	0x002c0000	/*  Modular Red */
351 #define	HIFN_PUBOP_OP_MODEXP	0x00300000	/*  Modular Exp */
352 
353 /* Public operand length register (HIFN_1_PUB_OPLEN) */
354 #define	HIFN_PUBOPLEN_MODLEN	0x0000007f
355 #define	HIFN_PUBOPLEN_EXPLEN	0x0003ff80
356 #define	HIFN_PUBOPLEN_REDLEN	0x003c0000
357 
358 /* Public status register (HIFN_1_PUB_STATUS) */
359 #define	HIFN_PUBSTS_DONE	0x00000001	/* operation done */
360 #define	HIFN_PUBSTS_CARRY	0x00000002	/* carry */
361 
362 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
363 #define	HIFN_PUBIEN_DONE	0x00000001	/* operation done interrupt */
364 
365 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
366 #define	HIFN_RNGCFG_ENA		0x00000001	/* enable rng */
367 
368 /*
369  * Register offsets in register set 1
370  */
371 
372 #define	HIFN_UNLOCK_SECRET1	0xf4
373 #define	HIFN_UNLOCK_SECRET2	0xfc
374 
375 /*
376  * PLL config register
377  *
378  * This register is present only on 7954/7955/7956 parts. It must be
379  * programmed according to the bus interface method used by the h/w.
380  * Note that the parts require a stable clock.  Since the PCI clock
381  * may vary the reference clock must usually be used.  To avoid
382  * overclocking the core logic, setup must be done carefully, refer
383  * to the driver for details.  The exact multiplier required varies
384  * by part and system configuration; refer to the Hifn documentation.
385  */
386 #define	HIFN_PLL_REF_SEL	0x00000001	/* REF/HBI clk selection */
387 #define	HIFN_PLL_BP		0x00000002	/* bypass (used during setup) */
388 /* bit 2 reserved */
389 #define	HIFN_PLL_PK_CLK_SEL	0x00000008	/* public key clk select */
390 #define	HIFN_PLL_PE_CLK_SEL	0x00000010	/* packet engine clk select */
391 /* bits 5-9 reserved */
392 #define	HIFN_PLL_MBSET		0x00000400	/* must be set to 1 */
393 #define	HIFN_PLL_ND		0x00003800	/* Fpll_ref multiplier select */
394 #define	HIFN_PLL_ND_SHIFT	11
395 #define	HIFN_PLL_ND_2		0x00000000	/* 2x */
396 #define	HIFN_PLL_ND_4		0x00000800	/* 4x */
397 #define	HIFN_PLL_ND_6		0x00001000	/* 6x */
398 #define	HIFN_PLL_ND_8		0x00001800	/* 8x */
399 #define	HIFN_PLL_ND_10		0x00002000	/* 10x */
400 #define	HIFN_PLL_ND_12		0x00002800	/* 12x */
401 /* bits 14-15 reserved */
402 #define	HIFN_PLL_IS		0x00010000	/* charge pump current select */
403 /* bits 17-31 reserved */
404 
405 /*
406  * Board configuration specifies only these bits.
407  */
408 #define	HIFN_PLL_CONFIG		(HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL)
409 
410 /*********************************************************************
411  * Structs for board commands
412  *
413  *********************************************************************/
414 
415 /*
416  * Structure to help build up the command data structure.
417  */
418 typedef struct hifn_base_command {
419 	volatile u_int16_t masks;
420 	volatile u_int16_t session_num;
421 	volatile u_int16_t total_source_count;
422 	volatile u_int16_t total_dest_count;
423 } hifn_base_command_t;
424 
425 #define	HIFN_BASE_CMD_MAC		0x0400
426 #define	HIFN_BASE_CMD_CRYPT		0x0800
427 #define	HIFN_BASE_CMD_DECODE		0x2000
428 #define	HIFN_BASE_CMD_SRCLEN_M		0xc000
429 #define	HIFN_BASE_CMD_SRCLEN_S		14
430 #define	HIFN_BASE_CMD_DSTLEN_M		0x3000
431 #define	HIFN_BASE_CMD_DSTLEN_S		12
432 #define	HIFN_BASE_CMD_LENMASK_HI	0x30000
433 #define	HIFN_BASE_CMD_LENMASK_LO	0x0ffff
434 
435 /*
436  * Structure to help build up the command data structure.
437  */
438 typedef struct hifn_crypt_command {
439 	volatile u_int16_t masks;
440 	volatile u_int16_t header_skip;
441 	volatile u_int16_t source_count;
442 	volatile u_int16_t reserved;
443 } hifn_crypt_command_t;
444 
445 #define	HIFN_CRYPT_CMD_ALG_MASK		0x0003		/* algorithm: */
446 #define	HIFN_CRYPT_CMD_ALG_DES		0x0000		/*   DES */
447 #define	HIFN_CRYPT_CMD_ALG_3DES		0x0001		/*   3DES */
448 #define	HIFN_CRYPT_CMD_ALG_RC4		0x0002		/*   RC4 */
449 #define	HIFN_CRYPT_CMD_ALG_AES		0x0003		/*   AES */
450 #define	HIFN_CRYPT_CMD_MODE_MASK	0x0018		/* Encrypt mode: */
451 #define	HIFN_CRYPT_CMD_MODE_ECB		0x0000		/*   ECB */
452 #define	HIFN_CRYPT_CMD_MODE_CBC		0x0008		/*   CBC */
453 #define	HIFN_CRYPT_CMD_MODE_CFB		0x0010		/*   CFB */
454 #define	HIFN_CRYPT_CMD_MODE_OFB		0x0018		/*   OFB */
455 #define	HIFN_CRYPT_CMD_CLR_CTX		0x0040		/* clear context */
456 #define	HIFN_CRYPT_CMD_NEW_KEY		0x0800		/* expect new key */
457 #define	HIFN_CRYPT_CMD_NEW_IV		0x1000		/* expect new iv */
458 
459 #define	HIFN_CRYPT_CMD_SRCLEN_M		0xc000
460 #define	HIFN_CRYPT_CMD_SRCLEN_S		14
461 
462 #define	HIFN_CRYPT_CMD_KSZ_MASK		0x0600		/* AES key size: */
463 #define	HIFN_CRYPT_CMD_KSZ_128		0x0000		/*   128 bit */
464 #define	HIFN_CRYPT_CMD_KSZ_192		0x0200		/*   192 bit */
465 #define	HIFN_CRYPT_CMD_KSZ_256		0x0400		/*   256 bit */
466 
467 /*
468  * Structure to help build up the command data structure.
469  */
470 typedef struct hifn_mac_command {
471 	volatile u_int16_t masks;
472 	volatile u_int16_t header_skip;
473 	volatile u_int16_t source_count;
474 	volatile u_int16_t reserved;
475 } hifn_mac_command_t;
476 
477 #define	HIFN_MAC_CMD_ALG_MASK		0x0001
478 #define	HIFN_MAC_CMD_ALG_SHA1		0x0000
479 #define	HIFN_MAC_CMD_ALG_MD5		0x0001
480 #define	HIFN_MAC_CMD_MODE_MASK		0x000c
481 #define	HIFN_MAC_CMD_MODE_HMAC		0x0000
482 #define	HIFN_MAC_CMD_MODE_SSL_MAC	0x0004
483 #define	HIFN_MAC_CMD_MODE_HASH		0x0008
484 #define	HIFN_MAC_CMD_MODE_FULL		0x0004
485 #define	HIFN_MAC_CMD_TRUNC		0x0010
486 #define	HIFN_MAC_CMD_RESULT		0x0020
487 #define	HIFN_MAC_CMD_APPEND		0x0040
488 #define	HIFN_MAC_CMD_SRCLEN_M		0xc000
489 #define	HIFN_MAC_CMD_SRCLEN_S		14
490 
491 /*
492  * MAC POS IPsec initiates authentication after encryption on encodes
493  * and before decryption on decodes.
494  */
495 #define	HIFN_MAC_CMD_POS_IPSEC		0x0200
496 #define	HIFN_MAC_CMD_NEW_KEY		0x0800
497 
498 /*
499  * The poll frequency and poll scalar defines are unshifted values used
500  * to set fields in the DMA Configuration Register.
501  */
502 #ifndef HIFN_POLL_FREQUENCY
503 #define	HIFN_POLL_FREQUENCY	0x1
504 #endif
505 
506 #ifndef HIFN_POLL_SCALAR
507 #define	HIFN_POLL_SCALAR	0x0
508 #endif
509 
510 #define	HIFN_MAX_SEGLEN 	0xffff		/* maximum dma segment len */
511 #define	HIFN_MAX_DMALEN		0x3ffff		/* maximum dma length */
512 #endif /* __HIFN_H__ */
513