1 /* $FreeBSD$ */ 2 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 3 4 /* 5 * Invertex AEON / Hifn 7751 driver 6 * Copyright (c) 1999 Invertex Inc. All rights reserved. 7 * Copyright (c) 1999 Theo de Raadt 8 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 9 * http://www.netsec.net 10 * 11 * This driver is based on a previous driver by Invertex, for which they 12 * requested: Please send any comments, feedback, bug-fixes, or feature 13 * requests to software@invertex.com. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Effort sponsored in part by the Defense Advanced Research Projects 39 * Agency (DARPA) and Air Force Research Laboratory, Air Force 40 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41 * 42 */ 43 44 /* 45 * Driver for the Hifn 7751 encryption processor. 46 */ 47 #include "opt_hifn.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/proc.h> 52 #include <sys/errno.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/mbuf.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/sysctl.h> 59 60 #include <vm/vm.h> 61 #include <vm/pmap.h> 62 63 #include <machine/clock.h> 64 #include <machine/bus.h> 65 #include <machine/resource.h> 66 #include <sys/bus.h> 67 #include <sys/rman.h> 68 69 #include <opencrypto/cryptodev.h> 70 #include <sys/random.h> 71 72 #include <pci/pcivar.h> 73 #include <pci/pcireg.h> 74 75 #ifdef HIFN_RNDTEST 76 #include <dev/rndtest/rndtest.h> 77 #endif 78 #include <dev/hifn/hifn7751reg.h> 79 #include <dev/hifn/hifn7751var.h> 80 81 /* 82 * Prototypes and count for the pci_device structure 83 */ 84 static int hifn_probe(device_t); 85 static int hifn_attach(device_t); 86 static int hifn_detach(device_t); 87 static int hifn_suspend(device_t); 88 static int hifn_resume(device_t); 89 static void hifn_shutdown(device_t); 90 91 static device_method_t hifn_methods[] = { 92 /* Device interface */ 93 DEVMETHOD(device_probe, hifn_probe), 94 DEVMETHOD(device_attach, hifn_attach), 95 DEVMETHOD(device_detach, hifn_detach), 96 DEVMETHOD(device_suspend, hifn_suspend), 97 DEVMETHOD(device_resume, hifn_resume), 98 DEVMETHOD(device_shutdown, hifn_shutdown), 99 100 /* bus interface */ 101 DEVMETHOD(bus_print_child, bus_generic_print_child), 102 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 103 104 { 0, 0 } 105 }; 106 static driver_t hifn_driver = { 107 "hifn", 108 hifn_methods, 109 sizeof (struct hifn_softc) 110 }; 111 static devclass_t hifn_devclass; 112 113 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 114 MODULE_DEPEND(hifn, crypto, 1, 1, 1); 115 #ifdef HIFN_RNDTEST 116 MODULE_DEPEND(hifn, rndtest, 1, 1, 1); 117 #endif 118 119 static void hifn_reset_board(struct hifn_softc *, int); 120 static void hifn_reset_puc(struct hifn_softc *); 121 static void hifn_puc_wait(struct hifn_softc *); 122 static int hifn_enable_crypto(struct hifn_softc *); 123 static void hifn_set_retry(struct hifn_softc *sc); 124 static void hifn_init_dma(struct hifn_softc *); 125 static void hifn_init_pci_registers(struct hifn_softc *); 126 static int hifn_sramsize(struct hifn_softc *); 127 static int hifn_dramsize(struct hifn_softc *); 128 static int hifn_ramtype(struct hifn_softc *); 129 static void hifn_sessions(struct hifn_softc *); 130 static void hifn_intr(void *); 131 static u_int hifn_write_command(struct hifn_command *, u_int8_t *); 132 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 133 static int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 134 static int hifn_freesession(void *, u_int64_t); 135 static int hifn_process(void *, struct cryptop *, int); 136 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 137 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 138 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 139 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 140 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 141 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 142 static int hifn_init_pubrng(struct hifn_softc *); 143 static void hifn_rng(void *); 144 static void hifn_tick(void *); 145 static void hifn_abort(struct hifn_softc *); 146 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 147 148 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 149 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 150 151 static __inline__ u_int32_t 152 READ_REG_0(struct hifn_softc *sc, bus_size_t reg) 153 { 154 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 155 sc->sc_bar0_lastreg = (bus_size_t) -1; 156 return (v); 157 } 158 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 159 160 static __inline__ u_int32_t 161 READ_REG_1(struct hifn_softc *sc, bus_size_t reg) 162 { 163 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 164 sc->sc_bar1_lastreg = (bus_size_t) -1; 165 return (v); 166 } 167 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 168 169 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 170 171 #ifdef HIFN_DEBUG 172 static int hifn_debug = 0; 173 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 174 0, "control debugging msgs"); 175 #endif 176 177 static struct hifn_stats hifnstats; 178 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 179 hifn_stats, "driver statistics"); 180 static int hifn_maxbatch = 1; 181 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 182 0, "max ops to batch w/o interrupt"); 183 184 /* 185 * Probe for a supported device. The PCI vendor and device 186 * IDs are used to detect devices we know how to handle. 187 */ 188 static int 189 hifn_probe(device_t dev) 190 { 191 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 192 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 193 return (0); 194 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 195 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 196 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 197 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 198 return (0); 199 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 200 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 201 return (0); 202 return (ENXIO); 203 } 204 205 static void 206 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 207 { 208 bus_addr_t *paddr = (bus_addr_t*) arg; 209 *paddr = segs->ds_addr; 210 } 211 212 static const char* 213 hifn_partname(struct hifn_softc *sc) 214 { 215 /* XXX sprintf numbers when not decoded */ 216 switch (pci_get_vendor(sc->sc_dev)) { 217 case PCI_VENDOR_HIFN: 218 switch (pci_get_device(sc->sc_dev)) { 219 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 220 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 221 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 222 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 223 } 224 return "Hifn unknown-part"; 225 case PCI_VENDOR_INVERTEX: 226 switch (pci_get_device(sc->sc_dev)) { 227 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 228 } 229 return "Invertex unknown-part"; 230 case PCI_VENDOR_NETSEC: 231 switch (pci_get_device(sc->sc_dev)) { 232 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 233 } 234 return "NetSec unknown-part"; 235 } 236 return "Unknown-vendor unknown-part"; 237 } 238 239 static void 240 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 241 { 242 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 243 } 244 245 /* 246 * Attach an interface that successfully probed. 247 */ 248 static int 249 hifn_attach(device_t dev) 250 { 251 struct hifn_softc *sc = device_get_softc(dev); 252 u_int32_t cmd; 253 caddr_t kva; 254 int rseg, rid; 255 char rbase; 256 u_int16_t ena, rev; 257 258 KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 259 bzero(sc, sizeof (*sc)); 260 sc->sc_dev = dev; 261 262 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 263 264 /* XXX handle power management */ 265 266 /* 267 * The 7951 has a random number generator and 268 * public key support; note this. 269 */ 270 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 271 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951) 272 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 273 /* 274 * The 7811 has a random number generator and 275 * we also note it's identity 'cuz of some quirks. 276 */ 277 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 278 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 279 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 280 281 /* 282 * Configure support for memory-mapped access to 283 * registers and for DMA operations. 284 */ 285 #define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 286 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 287 cmd |= PCIM_ENA; 288 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 289 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 290 if ((cmd & PCIM_ENA) != PCIM_ENA) { 291 device_printf(dev, "failed to enable %s\n", 292 (cmd & PCIM_ENA) == 0 ? 293 "memory mapping & bus mastering" : 294 (cmd & PCIM_CMD_MEMEN) == 0 ? 295 "memory mapping" : "bus mastering"); 296 goto fail_pci; 297 } 298 #undef PCIM_ENA 299 300 /* 301 * Setup PCI resources. Note that we record the bus 302 * tag and handle for each register mapping, this is 303 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 304 * and WRITE_REG_1 macros throughout the driver. 305 */ 306 rid = HIFN_BAR0; 307 sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 308 0, ~0, 1, RF_ACTIVE); 309 if (sc->sc_bar0res == NULL) { 310 device_printf(dev, "cannot map bar%d register space\n", 0); 311 goto fail_pci; 312 } 313 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 314 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 315 sc->sc_bar0_lastreg = (bus_size_t) -1; 316 317 rid = HIFN_BAR1; 318 sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 319 0, ~0, 1, RF_ACTIVE); 320 if (sc->sc_bar1res == NULL) { 321 device_printf(dev, "cannot map bar%d register space\n", 1); 322 goto fail_io0; 323 } 324 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 325 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 326 sc->sc_bar1_lastreg = (bus_size_t) -1; 327 328 hifn_set_retry(sc); 329 330 /* 331 * Setup the area where the Hifn DMA's descriptors 332 * and associated data structures. 333 */ 334 if (bus_dma_tag_create(NULL, /* parent */ 335 1, 0, /* alignment,boundary */ 336 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 337 BUS_SPACE_MAXADDR, /* highaddr */ 338 NULL, NULL, /* filter, filterarg */ 339 HIFN_MAX_DMALEN, /* maxsize */ 340 MAX_SCATTER, /* nsegments */ 341 HIFN_MAX_SEGLEN, /* maxsegsize */ 342 BUS_DMA_ALLOCNOW, /* flags */ 343 &sc->sc_dmat)) { 344 device_printf(dev, "cannot allocate DMA tag\n"); 345 goto fail_io1; 346 } 347 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 348 device_printf(dev, "cannot create dma map\n"); 349 bus_dma_tag_destroy(sc->sc_dmat); 350 goto fail_io1; 351 } 352 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 353 device_printf(dev, "cannot alloc dma buffer\n"); 354 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 355 bus_dma_tag_destroy(sc->sc_dmat); 356 goto fail_io1; 357 } 358 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 359 sizeof (*sc->sc_dma), 360 hifn_dmamap_cb, &sc->sc_dma_physaddr, 361 BUS_DMA_NOWAIT)) { 362 device_printf(dev, "cannot load dma map\n"); 363 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 364 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 365 bus_dma_tag_destroy(sc->sc_dmat); 366 goto fail_io1; 367 } 368 sc->sc_dma = (struct hifn_dma *)kva; 369 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 370 371 KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!")); 372 KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!")); 373 KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!")); 374 KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!")); 375 376 /* 377 * Reset the board and do the ``secret handshake'' 378 * to enable the crypto support. Then complete the 379 * initialization procedure by setting up the interrupt 380 * and hooking in to the system crypto support so we'll 381 * get used for system services like the crypto device, 382 * IPsec, RNG device, etc. 383 */ 384 hifn_reset_board(sc, 0); 385 386 if (hifn_enable_crypto(sc) != 0) { 387 device_printf(dev, "crypto enabling failed\n"); 388 goto fail_mem; 389 } 390 hifn_reset_puc(sc); 391 392 hifn_init_dma(sc); 393 hifn_init_pci_registers(sc); 394 395 if (hifn_ramtype(sc)) 396 goto fail_mem; 397 398 if (sc->sc_drammodel == 0) 399 hifn_sramsize(sc); 400 else 401 hifn_dramsize(sc); 402 403 /* 404 * Workaround for NetSec 7751 rev A: half ram size because two 405 * of the address lines were left floating 406 */ 407 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 408 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 409 pci_get_revid(dev) == 0x61) /*XXX???*/ 410 sc->sc_ramsize >>= 1; 411 412 /* 413 * Arrange the interrupt line. 414 */ 415 rid = 0; 416 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 417 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 418 if (sc->sc_irq == NULL) { 419 device_printf(dev, "could not map interrupt\n"); 420 goto fail_mem; 421 } 422 /* 423 * NB: Network code assumes we are blocked with splimp() 424 * so make sure the IRQ is marked appropriately. 425 */ 426 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 427 hifn_intr, sc, &sc->sc_intrhand)) { 428 device_printf(dev, "could not setup interrupt\n"); 429 goto fail_intr2; 430 } 431 432 hifn_sessions(sc); 433 434 /* 435 * NB: Keep only the low 16 bits; this masks the chip id 436 * from the 7951. 437 */ 438 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 439 440 rseg = sc->sc_ramsize / 1024; 441 rbase = 'K'; 442 if (sc->sc_ramsize >= (1024 * 1024)) { 443 rbase = 'M'; 444 rseg /= 1024; 445 } 446 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 447 hifn_partname(sc), rev, 448 rseg, rbase, sc->sc_drammodel ? 'd' : 's', 449 sc->sc_maxses); 450 451 sc->sc_cid = crypto_get_driverid(0); 452 if (sc->sc_cid < 0) { 453 device_printf(dev, "could not get crypto driver id\n"); 454 goto fail_intr; 455 } 456 457 WRITE_REG_0(sc, HIFN_0_PUCNFG, 458 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 459 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 460 461 switch (ena) { 462 case HIFN_PUSTAT_ENA_2: 463 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 464 hifn_newsession, hifn_freesession, hifn_process, sc); 465 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 466 hifn_newsession, hifn_freesession, hifn_process, sc); 467 /*FALLTHROUGH*/ 468 case HIFN_PUSTAT_ENA_1: 469 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 470 hifn_newsession, hifn_freesession, hifn_process, sc); 471 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 472 hifn_newsession, hifn_freesession, hifn_process, sc); 473 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 474 hifn_newsession, hifn_freesession, hifn_process, sc); 475 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 476 hifn_newsession, hifn_freesession, hifn_process, sc); 477 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 478 hifn_newsession, hifn_freesession, hifn_process, sc); 479 break; 480 } 481 482 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 484 485 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 486 hifn_init_pubrng(sc); 487 488 /* NB: 1 means the callout runs w/o Giant locked */ 489 callout_init(&sc->sc_tickto, 1); 490 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 491 492 return (0); 493 494 fail_intr: 495 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 496 fail_intr2: 497 /* XXX don't store rid */ 498 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 499 fail_mem: 500 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 501 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 502 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 503 bus_dma_tag_destroy(sc->sc_dmat); 504 505 /* Turn off DMA polling */ 506 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 507 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 508 fail_io1: 509 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 510 fail_io0: 511 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 512 fail_pci: 513 mtx_destroy(&sc->sc_mtx); 514 return (ENXIO); 515 } 516 517 /* 518 * Detach an interface that successfully probed. 519 */ 520 static int 521 hifn_detach(device_t dev) 522 { 523 struct hifn_softc *sc = device_get_softc(dev); 524 525 KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 526 527 HIFN_LOCK(sc); 528 529 /*XXX other resources */ 530 callout_stop(&sc->sc_tickto); 531 callout_stop(&sc->sc_rngto); 532 533 /* Turn off DMA polling */ 534 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 535 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 536 537 crypto_unregister_all(sc->sc_cid); 538 539 bus_generic_detach(dev); /*XXX should be no children, right? */ 540 541 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 542 /* XXX don't store rid */ 543 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 544 545 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 546 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 547 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 548 bus_dma_tag_destroy(sc->sc_dmat); 549 550 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 551 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 552 553 HIFN_UNLOCK(sc); 554 555 mtx_destroy(&sc->sc_mtx); 556 557 return (0); 558 } 559 560 /* 561 * Stop all chip I/O so that the kernel's probe routines don't 562 * get confused by errant DMAs when rebooting. 563 */ 564 static void 565 hifn_shutdown(device_t dev) 566 { 567 #ifdef notyet 568 hifn_stop(device_get_softc(dev)); 569 #endif 570 } 571 572 /* 573 * Device suspend routine. Stop the interface and save some PCI 574 * settings in case the BIOS doesn't restore them properly on 575 * resume. 576 */ 577 static int 578 hifn_suspend(device_t dev) 579 { 580 struct hifn_softc *sc = device_get_softc(dev); 581 #ifdef notyet 582 int i; 583 584 hifn_stop(sc); 585 for (i = 0; i < 5; i++) 586 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 587 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 588 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 589 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 590 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 591 #endif 592 sc->sc_suspended = 1; 593 594 return (0); 595 } 596 597 /* 598 * Device resume routine. Restore some PCI settings in case the BIOS 599 * doesn't, re-enable busmastering, and restart the interface if 600 * appropriate. 601 */ 602 static int 603 hifn_resume(device_t dev) 604 { 605 struct hifn_softc *sc = device_get_softc(dev); 606 #ifdef notyet 607 int i; 608 609 /* better way to do this? */ 610 for (i = 0; i < 5; i++) 611 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 612 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 613 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 614 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 615 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 616 617 /* reenable busmastering */ 618 pci_enable_busmaster(dev); 619 pci_enable_io(dev, HIFN_RES); 620 621 /* reinitialize interface if necessary */ 622 if (ifp->if_flags & IFF_UP) 623 rl_init(sc); 624 #endif 625 sc->sc_suspended = 0; 626 627 return (0); 628 } 629 630 static int 631 hifn_init_pubrng(struct hifn_softc *sc) 632 { 633 u_int32_t r; 634 int i; 635 636 #ifdef HIFN_RNDTEST 637 sc->sc_rndtest = rndtest_attach(sc->sc_dev); 638 if (sc->sc_rndtest) 639 sc->sc_harvest = rndtest_harvest; 640 else 641 sc->sc_harvest = default_harvest; 642 #else 643 sc->sc_harvest = default_harvest; 644 #endif 645 if ((sc->sc_flags & HIFN_IS_7811) == 0) { 646 /* Reset 7951 public key/rng engine */ 647 WRITE_REG_1(sc, HIFN_1_PUB_RESET, 648 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 649 650 for (i = 0; i < 100; i++) { 651 DELAY(1000); 652 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 653 HIFN_PUBRST_RESET) == 0) 654 break; 655 } 656 657 if (i == 100) { 658 device_printf(sc->sc_dev, "public key init failed\n"); 659 return (1); 660 } 661 } 662 663 /* Enable the rng, if available */ 664 if (sc->sc_flags & HIFN_HAS_RNG) { 665 if (sc->sc_flags & HIFN_IS_7811) { 666 r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 667 if (r & HIFN_7811_RNGENA_ENA) { 668 r &= ~HIFN_7811_RNGENA_ENA; 669 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 670 } 671 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 672 HIFN_7811_RNGCFG_DEFL); 673 r |= HIFN_7811_RNGENA_ENA; 674 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 675 } else 676 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 677 READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 678 HIFN_RNGCFG_ENA); 679 680 sc->sc_rngfirst = 1; 681 if (hz >= 100) 682 sc->sc_rnghz = hz / 100; 683 else 684 sc->sc_rnghz = 1; 685 /* NB: 1 means the callout runs w/o Giant locked */ 686 callout_init(&sc->sc_rngto, 1); 687 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 688 } 689 690 /* Enable public key engine, if available */ 691 if (sc->sc_flags & HIFN_HAS_PUBLIC) { 692 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 693 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 694 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 695 } 696 697 return (0); 698 } 699 700 static void 701 hifn_rng(void *vsc) 702 { 703 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 704 struct hifn_softc *sc = vsc; 705 u_int32_t sts, num[2]; 706 int i; 707 708 if (sc->sc_flags & HIFN_IS_7811) { 709 for (i = 0; i < 5; i++) { 710 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 711 if (sts & HIFN_7811_RNGSTS_UFL) { 712 device_printf(sc->sc_dev, 713 "RNG underflow: disabling\n"); 714 return; 715 } 716 if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 717 break; 718 719 /* 720 * There are at least two words in the RNG FIFO 721 * at this point. 722 */ 723 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 724 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 725 /* NB: discard first data read */ 726 if (sc->sc_rngfirst) 727 sc->sc_rngfirst = 0; 728 else 729 (*sc->sc_harvest)(sc->sc_rndtest, 730 num, sizeof (num)); 731 } 732 } else { 733 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 734 735 /* NB: discard first data read */ 736 if (sc->sc_rngfirst) 737 sc->sc_rngfirst = 0; 738 else 739 (*sc->sc_harvest)(sc->sc_rndtest, 740 num, sizeof (num[0])); 741 } 742 743 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 744 #undef RANDOM_BITS 745 } 746 747 static void 748 hifn_puc_wait(struct hifn_softc *sc) 749 { 750 int i; 751 752 for (i = 5000; i > 0; i--) { 753 DELAY(1); 754 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 755 break; 756 } 757 if (!i) 758 device_printf(sc->sc_dev, "proc unit did not reset\n"); 759 } 760 761 /* 762 * Reset the processing unit. 763 */ 764 static void 765 hifn_reset_puc(struct hifn_softc *sc) 766 { 767 /* Reset processing unit */ 768 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 769 hifn_puc_wait(sc); 770 } 771 772 /* 773 * Set the Retry and TRDY registers; note that we set them to 774 * zero because the 7811 locks up when forced to retry (section 775 * 3.6 of "Specification Update SU-0014-04". Not clear if we 776 * should do this for all Hifn parts, but it doesn't seem to hurt. 777 */ 778 static void 779 hifn_set_retry(struct hifn_softc *sc) 780 { 781 /* NB: RETRY only responds to 8-bit reads/writes */ 782 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 783 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 784 } 785 786 /* 787 * Resets the board. Values in the regesters are left as is 788 * from the reset (i.e. initial values are assigned elsewhere). 789 */ 790 static void 791 hifn_reset_board(struct hifn_softc *sc, int full) 792 { 793 u_int32_t reg; 794 795 /* 796 * Set polling in the DMA configuration register to zero. 0x7 avoids 797 * resetting the board and zeros out the other fields. 798 */ 799 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 800 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 801 802 /* 803 * Now that polling has been disabled, we have to wait 1 ms 804 * before resetting the board. 805 */ 806 DELAY(1000); 807 808 /* Reset the DMA unit */ 809 if (full) { 810 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 811 DELAY(1000); 812 } else { 813 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 814 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 815 hifn_reset_puc(sc); 816 } 817 818 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 819 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 820 821 /* Bring dma unit out of reset */ 822 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 823 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 824 825 hifn_puc_wait(sc); 826 hifn_set_retry(sc); 827 828 if (sc->sc_flags & HIFN_IS_7811) { 829 for (reg = 0; reg < 1000; reg++) { 830 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 831 HIFN_MIPSRST_CRAMINIT) 832 break; 833 DELAY(1000); 834 } 835 if (reg == 1000) 836 printf(": cram init timeout\n"); 837 } 838 } 839 840 static u_int32_t 841 hifn_next_signature(u_int32_t a, u_int cnt) 842 { 843 int i; 844 u_int32_t v; 845 846 for (i = 0; i < cnt; i++) { 847 848 /* get the parity */ 849 v = a & 0x80080125; 850 v ^= v >> 16; 851 v ^= v >> 8; 852 v ^= v >> 4; 853 v ^= v >> 2; 854 v ^= v >> 1; 855 856 a = (v & 1) ^ (a << 1); 857 } 858 859 return a; 860 } 861 862 struct pci2id { 863 u_short pci_vendor; 864 u_short pci_prod; 865 char card_id[13]; 866 }; 867 static struct pci2id pci2id[] = { 868 { 869 PCI_VENDOR_HIFN, 870 PCI_PRODUCT_HIFN_7951, 871 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 872 0x00, 0x00, 0x00, 0x00, 0x00 } 873 }, { 874 PCI_VENDOR_NETSEC, 875 PCI_PRODUCT_NETSEC_7751, 876 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 877 0x00, 0x00, 0x00, 0x00, 0x00 } 878 }, { 879 PCI_VENDOR_INVERTEX, 880 PCI_PRODUCT_INVERTEX_AEON, 881 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 882 0x00, 0x00, 0x00, 0x00, 0x00 } 883 }, { 884 PCI_VENDOR_HIFN, 885 PCI_PRODUCT_HIFN_7811, 886 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 887 0x00, 0x00, 0x00, 0x00, 0x00 } 888 }, { 889 /* 890 * Other vendors share this PCI ID as well, such as 891 * http://www.powercrypt.com, and obviously they also 892 * use the same key. 893 */ 894 PCI_VENDOR_HIFN, 895 PCI_PRODUCT_HIFN_7751, 896 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 897 0x00, 0x00, 0x00, 0x00, 0x00 } 898 }, 899 }; 900 901 /* 902 * Checks to see if crypto is already enabled. If crypto isn't enable, 903 * "hifn_enable_crypto" is called to enable it. The check is important, 904 * as enabling crypto twice will lock the board. 905 */ 906 static int 907 hifn_enable_crypto(struct hifn_softc *sc) 908 { 909 u_int32_t dmacfg, ramcfg, encl, addr, i; 910 char *offtbl = NULL; 911 912 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 913 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 914 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 915 offtbl = pci2id[i].card_id; 916 break; 917 } 918 } 919 if (offtbl == NULL) { 920 device_printf(sc->sc_dev, "Unknown card!\n"); 921 return (1); 922 } 923 924 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 925 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 926 927 /* 928 * The RAM config register's encrypt level bit needs to be set before 929 * every read performed on the encryption level register. 930 */ 931 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 932 933 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 934 935 /* 936 * Make sure we don't re-unlock. Two unlocks kills chip until the 937 * next reboot. 938 */ 939 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 940 #ifdef HIFN_DEBUG 941 if (hifn_debug) 942 device_printf(sc->sc_dev, 943 "Strong crypto already enabled!\n"); 944 #endif 945 goto report; 946 } 947 948 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 949 #ifdef HIFN_DEBUG 950 if (hifn_debug) 951 device_printf(sc->sc_dev, 952 "Unknown encryption level 0x%x\n", encl); 953 #endif 954 return 1; 955 } 956 957 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 958 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 959 DELAY(1000); 960 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 961 DELAY(1000); 962 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 963 DELAY(1000); 964 965 for (i = 0; i <= 12; i++) { 966 addr = hifn_next_signature(addr, offtbl[i] + 0x101); 967 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 968 969 DELAY(1000); 970 } 971 972 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 973 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 974 975 #ifdef HIFN_DEBUG 976 if (hifn_debug) { 977 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 978 device_printf(sc->sc_dev, "Engine is permanently " 979 "locked until next system reset!\n"); 980 else 981 device_printf(sc->sc_dev, "Engine enabled " 982 "successfully!\n"); 983 } 984 #endif 985 986 report: 987 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 988 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 989 990 switch (encl) { 991 case HIFN_PUSTAT_ENA_1: 992 case HIFN_PUSTAT_ENA_2: 993 break; 994 case HIFN_PUSTAT_ENA_0: 995 default: 996 device_printf(sc->sc_dev, "disabled"); 997 break; 998 } 999 1000 return 0; 1001 } 1002 1003 /* 1004 * Give initial values to the registers listed in the "Register Space" 1005 * section of the HIFN Software Development reference manual. 1006 */ 1007 static void 1008 hifn_init_pci_registers(struct hifn_softc *sc) 1009 { 1010 /* write fixed values needed by the Initialization registers */ 1011 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1012 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1013 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1014 1015 /* write all 4 ring address registers */ 1016 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1017 offsetof(struct hifn_dma, cmdr[0])); 1018 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1019 offsetof(struct hifn_dma, srcr[0])); 1020 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1021 offsetof(struct hifn_dma, dstr[0])); 1022 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1023 offsetof(struct hifn_dma, resr[0])); 1024 1025 DELAY(2000); 1026 1027 /* write status register */ 1028 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1029 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1030 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1031 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1032 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1033 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1034 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1035 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1036 HIFN_DMACSR_S_WAIT | 1037 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1038 HIFN_DMACSR_C_WAIT | 1039 HIFN_DMACSR_ENGINE | 1040 ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1041 HIFN_DMACSR_PUBDONE : 0) | 1042 ((sc->sc_flags & HIFN_IS_7811) ? 1043 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1044 1045 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1046 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1047 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1048 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1049 ((sc->sc_flags & HIFN_IS_7811) ? 1050 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1051 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1052 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1053 1054 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1055 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1056 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1057 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1058 1059 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1060 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1061 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1062 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1063 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1064 } 1065 1066 /* 1067 * The maximum number of sessions supported by the card 1068 * is dependent on the amount of context ram, which 1069 * encryption algorithms are enabled, and how compression 1070 * is configured. This should be configured before this 1071 * routine is called. 1072 */ 1073 static void 1074 hifn_sessions(struct hifn_softc *sc) 1075 { 1076 u_int32_t pucnfg; 1077 int ctxsize; 1078 1079 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1080 1081 if (pucnfg & HIFN_PUCNFG_COMPSING) { 1082 if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1083 ctxsize = 128; 1084 else 1085 ctxsize = 512; 1086 sc->sc_maxses = 1 + 1087 ((sc->sc_ramsize - 32768) / ctxsize); 1088 } else 1089 sc->sc_maxses = sc->sc_ramsize / 16384; 1090 1091 if (sc->sc_maxses > 2048) 1092 sc->sc_maxses = 2048; 1093 } 1094 1095 /* 1096 * Determine ram type (sram or dram). Board should be just out of a reset 1097 * state when this is called. 1098 */ 1099 static int 1100 hifn_ramtype(struct hifn_softc *sc) 1101 { 1102 u_int8_t data[8], dataexpect[8]; 1103 int i; 1104 1105 for (i = 0; i < sizeof(data); i++) 1106 data[i] = dataexpect[i] = 0x55; 1107 if (hifn_writeramaddr(sc, 0, data)) 1108 return (-1); 1109 if (hifn_readramaddr(sc, 0, data)) 1110 return (-1); 1111 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1112 sc->sc_drammodel = 1; 1113 return (0); 1114 } 1115 1116 for (i = 0; i < sizeof(data); i++) 1117 data[i] = dataexpect[i] = 0xaa; 1118 if (hifn_writeramaddr(sc, 0, data)) 1119 return (-1); 1120 if (hifn_readramaddr(sc, 0, data)) 1121 return (-1); 1122 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1123 sc->sc_drammodel = 1; 1124 return (0); 1125 } 1126 1127 return (0); 1128 } 1129 1130 #define HIFN_SRAM_MAX (32 << 20) 1131 #define HIFN_SRAM_STEP_SIZE 16384 1132 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1133 1134 static int 1135 hifn_sramsize(struct hifn_softc *sc) 1136 { 1137 u_int32_t a; 1138 u_int8_t data[8]; 1139 u_int8_t dataexpect[sizeof(data)]; 1140 int32_t i; 1141 1142 for (i = 0; i < sizeof(data); i++) 1143 data[i] = dataexpect[i] = i ^ 0x5a; 1144 1145 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1146 a = i * HIFN_SRAM_STEP_SIZE; 1147 bcopy(&i, data, sizeof(i)); 1148 hifn_writeramaddr(sc, a, data); 1149 } 1150 1151 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1152 a = i * HIFN_SRAM_STEP_SIZE; 1153 bcopy(&i, dataexpect, sizeof(i)); 1154 if (hifn_readramaddr(sc, a, data) < 0) 1155 return (0); 1156 if (bcmp(data, dataexpect, sizeof(data)) != 0) 1157 return (0); 1158 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1159 } 1160 1161 return (0); 1162 } 1163 1164 /* 1165 * XXX For dram boards, one should really try all of the 1166 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1167 * is already set up correctly. 1168 */ 1169 static int 1170 hifn_dramsize(struct hifn_softc *sc) 1171 { 1172 u_int32_t cnfg; 1173 1174 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1175 HIFN_PUCNFG_DRAMMASK; 1176 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1177 return (0); 1178 } 1179 1180 static void 1181 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1182 { 1183 struct hifn_dma *dma = sc->sc_dma; 1184 1185 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1186 dma->cmdi = 0; 1187 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1188 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1189 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1190 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1191 } 1192 *cmdp = dma->cmdi++; 1193 dma->cmdk = dma->cmdi; 1194 1195 if (dma->srci == HIFN_D_SRC_RSIZE) { 1196 dma->srci = 0; 1197 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1198 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1199 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1201 } 1202 *srcp = dma->srci++; 1203 dma->srck = dma->srci; 1204 1205 if (dma->dsti == HIFN_D_DST_RSIZE) { 1206 dma->dsti = 0; 1207 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1208 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1209 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1210 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1211 } 1212 *dstp = dma->dsti++; 1213 dma->dstk = dma->dsti; 1214 1215 if (dma->resi == HIFN_D_RES_RSIZE) { 1216 dma->resi = 0; 1217 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1218 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1219 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1221 } 1222 *resp = dma->resi++; 1223 dma->resk = dma->resi; 1224 } 1225 1226 static int 1227 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1228 { 1229 struct hifn_dma *dma = sc->sc_dma; 1230 hifn_base_command_t wc; 1231 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1232 int r, cmdi, resi, srci, dsti; 1233 1234 wc.masks = htole16(3 << 13); 1235 wc.session_num = htole16(addr >> 14); 1236 wc.total_source_count = htole16(8); 1237 wc.total_dest_count = htole16(addr & 0x3fff); 1238 1239 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1240 1241 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1242 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1243 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1244 1245 /* build write command */ 1246 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1247 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1248 bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1249 1250 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1251 + offsetof(struct hifn_dma, test_src)); 1252 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1253 + offsetof(struct hifn_dma, test_dst)); 1254 1255 dma->cmdr[cmdi].l = htole32(16 | masks); 1256 dma->srcr[srci].l = htole32(8 | masks); 1257 dma->dstr[dsti].l = htole32(4 | masks); 1258 dma->resr[resi].l = htole32(4 | masks); 1259 1260 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1261 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1262 1263 for (r = 10000; r >= 0; r--) { 1264 DELAY(10); 1265 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1266 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1267 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1268 break; 1269 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1270 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1271 } 1272 if (r == 0) { 1273 device_printf(sc->sc_dev, "writeramaddr -- " 1274 "result[%d](addr %d) still valid\n", resi, addr); 1275 r = -1; 1276 return (-1); 1277 } else 1278 r = 0; 1279 1280 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1281 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1282 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1283 1284 return (r); 1285 } 1286 1287 static int 1288 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1289 { 1290 struct hifn_dma *dma = sc->sc_dma; 1291 hifn_base_command_t rc; 1292 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1293 int r, cmdi, srci, dsti, resi; 1294 1295 rc.masks = htole16(2 << 13); 1296 rc.session_num = htole16(addr >> 14); 1297 rc.total_source_count = htole16(addr & 0x3fff); 1298 rc.total_dest_count = htole16(8); 1299 1300 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1301 1302 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1303 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1304 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1305 1306 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1307 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1308 1309 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1310 offsetof(struct hifn_dma, test_src)); 1311 dma->test_src = 0; 1312 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1313 offsetof(struct hifn_dma, test_dst)); 1314 dma->test_dst = 0; 1315 dma->cmdr[cmdi].l = htole32(8 | masks); 1316 dma->srcr[srci].l = htole32(8 | masks); 1317 dma->dstr[dsti].l = htole32(8 | masks); 1318 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1319 1320 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1321 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1322 1323 for (r = 10000; r >= 0; r--) { 1324 DELAY(10); 1325 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1326 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1327 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1328 break; 1329 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1330 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1331 } 1332 if (r == 0) { 1333 device_printf(sc->sc_dev, "readramaddr -- " 1334 "result[%d](addr %d) still valid\n", resi, addr); 1335 r = -1; 1336 } else { 1337 r = 0; 1338 bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1339 } 1340 1341 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1342 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1343 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1344 1345 return (r); 1346 } 1347 1348 /* 1349 * Initialize the descriptor rings. 1350 */ 1351 static void 1352 hifn_init_dma(struct hifn_softc *sc) 1353 { 1354 struct hifn_dma *dma = sc->sc_dma; 1355 int i; 1356 1357 hifn_set_retry(sc); 1358 1359 /* initialize static pointer values */ 1360 for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1361 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1362 offsetof(struct hifn_dma, command_bufs[i][0])); 1363 for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1364 dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1365 offsetof(struct hifn_dma, result_bufs[i][0])); 1366 1367 dma->cmdr[HIFN_D_CMD_RSIZE].p = 1368 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1369 dma->srcr[HIFN_D_SRC_RSIZE].p = 1370 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1371 dma->dstr[HIFN_D_DST_RSIZE].p = 1372 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1373 dma->resr[HIFN_D_RES_RSIZE].p = 1374 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1375 1376 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1377 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1378 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1379 } 1380 1381 /* 1382 * Writes out the raw command buffer space. Returns the 1383 * command buffer size. 1384 */ 1385 static u_int 1386 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1387 { 1388 u_int8_t *buf_pos; 1389 hifn_base_command_t *base_cmd; 1390 hifn_mac_command_t *mac_cmd; 1391 hifn_crypt_command_t *cry_cmd; 1392 int using_mac, using_crypt, len; 1393 u_int32_t dlen, slen; 1394 1395 buf_pos = buf; 1396 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1397 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1398 1399 base_cmd = (hifn_base_command_t *)buf_pos; 1400 base_cmd->masks = htole16(cmd->base_masks); 1401 slen = cmd->src_mapsize; 1402 if (cmd->sloplen) 1403 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1404 else 1405 dlen = cmd->dst_mapsize; 1406 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1407 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1408 dlen >>= 16; 1409 slen >>= 16; 1410 base_cmd->session_num = htole16(cmd->session_num | 1411 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1412 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1413 buf_pos += sizeof(hifn_base_command_t); 1414 1415 if (using_mac) { 1416 mac_cmd = (hifn_mac_command_t *)buf_pos; 1417 dlen = cmd->maccrd->crd_len; 1418 mac_cmd->source_count = htole16(dlen & 0xffff); 1419 dlen >>= 16; 1420 mac_cmd->masks = htole16(cmd->mac_masks | 1421 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1422 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1423 mac_cmd->reserved = 0; 1424 buf_pos += sizeof(hifn_mac_command_t); 1425 } 1426 1427 if (using_crypt) { 1428 cry_cmd = (hifn_crypt_command_t *)buf_pos; 1429 dlen = cmd->enccrd->crd_len; 1430 cry_cmd->source_count = htole16(dlen & 0xffff); 1431 dlen >>= 16; 1432 cry_cmd->masks = htole16(cmd->cry_masks | 1433 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1434 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1435 cry_cmd->reserved = 0; 1436 buf_pos += sizeof(hifn_crypt_command_t); 1437 } 1438 1439 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1440 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1441 buf_pos += HIFN_MAC_KEY_LENGTH; 1442 } 1443 1444 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1445 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1446 case HIFN_CRYPT_CMD_ALG_3DES: 1447 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1448 buf_pos += HIFN_3DES_KEY_LENGTH; 1449 break; 1450 case HIFN_CRYPT_CMD_ALG_DES: 1451 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1452 buf_pos += cmd->cklen; 1453 break; 1454 case HIFN_CRYPT_CMD_ALG_RC4: 1455 len = 256; 1456 do { 1457 int clen; 1458 1459 clen = MIN(cmd->cklen, len); 1460 bcopy(cmd->ck, buf_pos, clen); 1461 len -= clen; 1462 buf_pos += clen; 1463 } while (len > 0); 1464 bzero(buf_pos, 4); 1465 buf_pos += 4; 1466 break; 1467 } 1468 } 1469 1470 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1471 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH); 1472 buf_pos += HIFN_IV_LENGTH; 1473 } 1474 1475 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1476 bzero(buf_pos, 8); 1477 buf_pos += 8; 1478 } 1479 1480 return (buf_pos - buf); 1481 } 1482 1483 static int 1484 hifn_dmamap_aligned(struct hifn_operand *op) 1485 { 1486 int i; 1487 1488 for (i = 0; i < op->nsegs; i++) { 1489 if (op->segs[i].ds_addr & 3) 1490 return (0); 1491 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1492 return (0); 1493 } 1494 return (1); 1495 } 1496 1497 static int 1498 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1499 { 1500 struct hifn_dma *dma = sc->sc_dma; 1501 struct hifn_operand *dst = &cmd->dst; 1502 u_int32_t p, l; 1503 int idx, used = 0, i; 1504 1505 idx = dma->dsti; 1506 for (i = 0; i < dst->nsegs - 1; i++) { 1507 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1508 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1509 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1510 HIFN_DSTR_SYNC(sc, idx, 1511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1512 used++; 1513 1514 if (++idx == HIFN_D_DST_RSIZE) { 1515 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1516 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1517 HIFN_DSTR_SYNC(sc, idx, 1518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1519 idx = 0; 1520 } 1521 } 1522 1523 if (cmd->sloplen == 0) { 1524 p = dst->segs[i].ds_addr; 1525 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1526 dst->segs[i].ds_len; 1527 } else { 1528 p = sc->sc_dma_physaddr + 1529 offsetof(struct hifn_dma, slop[cmd->slopidx]); 1530 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1531 sizeof(u_int32_t); 1532 1533 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1534 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1535 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1536 HIFN_D_MASKDONEIRQ | 1537 (dst->segs[i].ds_len - cmd->sloplen)); 1538 HIFN_DSTR_SYNC(sc, idx, 1539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1540 used++; 1541 1542 if (++idx == HIFN_D_DST_RSIZE) { 1543 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1544 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1545 HIFN_DSTR_SYNC(sc, idx, 1546 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1547 idx = 0; 1548 } 1549 } 1550 } 1551 dma->dstr[idx].p = htole32(p); 1552 dma->dstr[idx].l = htole32(l); 1553 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1554 used++; 1555 1556 if (++idx == HIFN_D_DST_RSIZE) { 1557 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1558 HIFN_D_MASKDONEIRQ); 1559 HIFN_DSTR_SYNC(sc, idx, 1560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1561 idx = 0; 1562 } 1563 1564 dma->dsti = idx; 1565 dma->dstu += used; 1566 return (idx); 1567 } 1568 1569 static int 1570 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1571 { 1572 struct hifn_dma *dma = sc->sc_dma; 1573 struct hifn_operand *src = &cmd->src; 1574 int idx, i; 1575 u_int32_t last = 0; 1576 1577 idx = dma->srci; 1578 for (i = 0; i < src->nsegs; i++) { 1579 if (i == src->nsegs - 1) 1580 last = HIFN_D_LAST; 1581 1582 dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1583 dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1584 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1585 HIFN_SRCR_SYNC(sc, idx, 1586 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1587 1588 if (++idx == HIFN_D_SRC_RSIZE) { 1589 dma->srcr[idx].l = htole32(HIFN_D_VALID | 1590 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1591 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1593 idx = 0; 1594 } 1595 } 1596 dma->srci = idx; 1597 dma->srcu += src->nsegs; 1598 return (idx); 1599 } 1600 1601 static void 1602 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1603 { 1604 struct hifn_operand *op = arg; 1605 1606 KASSERT(nsegs <= MAX_SCATTER, 1607 ("hifn_op_cb: too many DMA segments (%u > %u) " 1608 "returned when mapping operand", nsegs, MAX_SCATTER)); 1609 op->mapsize = mapsize; 1610 op->nsegs = nsegs; 1611 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1612 } 1613 1614 static int 1615 hifn_crypto( 1616 struct hifn_softc *sc, 1617 struct hifn_command *cmd, 1618 struct cryptop *crp, 1619 int hint) 1620 { 1621 struct hifn_dma *dma = sc->sc_dma; 1622 u_int32_t cmdlen; 1623 int cmdi, resi, err = 0; 1624 1625 /* 1626 * need 1 cmd, and 1 res 1627 * 1628 * NB: check this first since it's easy. 1629 */ 1630 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1631 (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1632 #ifdef HIFN_DEBUG 1633 if (hifn_debug) { 1634 device_printf(sc->sc_dev, 1635 "cmd/result exhaustion, cmdu %u resu %u\n", 1636 dma->cmdu, dma->resu); 1637 } 1638 #endif 1639 hifnstats.hst_nomem_cr++; 1640 return (ERESTART); 1641 } 1642 1643 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1644 hifnstats.hst_nomem_map++; 1645 return (ENOMEM); 1646 } 1647 1648 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1649 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1650 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1651 hifnstats.hst_nomem_load++; 1652 err = ENOMEM; 1653 goto err_srcmap1; 1654 } 1655 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1656 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1657 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1658 hifnstats.hst_nomem_load++; 1659 err = ENOMEM; 1660 goto err_srcmap1; 1661 } 1662 } else { 1663 err = EINVAL; 1664 goto err_srcmap1; 1665 } 1666 1667 if (hifn_dmamap_aligned(&cmd->src)) { 1668 cmd->sloplen = cmd->src_mapsize & 3; 1669 cmd->dst = cmd->src; 1670 } else { 1671 if (crp->crp_flags & CRYPTO_F_IOV) { 1672 err = EINVAL; 1673 goto err_srcmap; 1674 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1675 int totlen, len; 1676 struct mbuf *m, *m0, *mlast; 1677 1678 KASSERT(cmd->dst_m == cmd->src_m, 1679 ("hifn_crypto: dst_m initialized improperly")); 1680 hifnstats.hst_unaligned++; 1681 /* 1682 * Source is not aligned on a longword boundary. 1683 * Copy the data to insure alignment. If we fail 1684 * to allocate mbufs or clusters while doing this 1685 * we return ERESTART so the operation is requeued 1686 * at the crypto later, but only if there are 1687 * ops already posted to the hardware; otherwise we 1688 * have no guarantee that we'll be re-entered. 1689 */ 1690 totlen = cmd->src_mapsize; 1691 if (cmd->src_m->m_flags & M_PKTHDR) { 1692 len = MHLEN; 1693 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1694 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1695 m_free(m0); 1696 m0 = NULL; 1697 } 1698 } else { 1699 len = MLEN; 1700 MGET(m0, M_DONTWAIT, MT_DATA); 1701 } 1702 if (m0 == NULL) { 1703 hifnstats.hst_nomem_mbuf++; 1704 err = dma->cmdu ? ERESTART : ENOMEM; 1705 goto err_srcmap; 1706 } 1707 if (totlen >= MINCLSIZE) { 1708 MCLGET(m0, M_DONTWAIT); 1709 if ((m0->m_flags & M_EXT) == 0) { 1710 hifnstats.hst_nomem_mcl++; 1711 err = dma->cmdu ? ERESTART : ENOMEM; 1712 m_freem(m0); 1713 goto err_srcmap; 1714 } 1715 len = MCLBYTES; 1716 } 1717 totlen -= len; 1718 m0->m_pkthdr.len = m0->m_len = len; 1719 mlast = m0; 1720 1721 while (totlen > 0) { 1722 MGET(m, M_DONTWAIT, MT_DATA); 1723 if (m == NULL) { 1724 hifnstats.hst_nomem_mbuf++; 1725 err = dma->cmdu ? ERESTART : ENOMEM; 1726 m_freem(m0); 1727 goto err_srcmap; 1728 } 1729 len = MLEN; 1730 if (totlen >= MINCLSIZE) { 1731 MCLGET(m, M_DONTWAIT); 1732 if ((m->m_flags & M_EXT) == 0) { 1733 hifnstats.hst_nomem_mcl++; 1734 err = dma->cmdu ? ERESTART : ENOMEM; 1735 mlast->m_next = m; 1736 m_freem(m0); 1737 goto err_srcmap; 1738 } 1739 len = MCLBYTES; 1740 } 1741 1742 m->m_len = len; 1743 m0->m_pkthdr.len += len; 1744 totlen -= len; 1745 1746 mlast->m_next = m; 1747 mlast = m; 1748 } 1749 cmd->dst_m = m0; 1750 } 1751 } 1752 1753 if (cmd->dst_map == NULL) { 1754 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1755 hifnstats.hst_nomem_map++; 1756 err = ENOMEM; 1757 goto err_srcmap; 1758 } 1759 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1760 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1761 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1762 hifnstats.hst_nomem_map++; 1763 err = ENOMEM; 1764 goto err_dstmap1; 1765 } 1766 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1767 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1768 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1769 hifnstats.hst_nomem_load++; 1770 err = ENOMEM; 1771 goto err_dstmap1; 1772 } 1773 } 1774 } 1775 1776 #ifdef HIFN_DEBUG 1777 if (hifn_debug) { 1778 device_printf(sc->sc_dev, 1779 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1780 READ_REG_1(sc, HIFN_1_DMA_CSR), 1781 READ_REG_1(sc, HIFN_1_DMA_IER), 1782 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1783 cmd->src_nsegs, cmd->dst_nsegs); 1784 } 1785 #endif 1786 1787 if (cmd->src_map == cmd->dst_map) { 1788 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1789 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1790 } else { 1791 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1792 BUS_DMASYNC_PREWRITE); 1793 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1794 BUS_DMASYNC_PREREAD); 1795 } 1796 1797 /* 1798 * need N src, and N dst 1799 */ 1800 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1801 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1802 #ifdef HIFN_DEBUG 1803 if (hifn_debug) { 1804 device_printf(sc->sc_dev, 1805 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1806 dma->srcu, cmd->src_nsegs, 1807 dma->dstu, cmd->dst_nsegs); 1808 } 1809 #endif 1810 hifnstats.hst_nomem_sd++; 1811 err = ERESTART; 1812 goto err_dstmap; 1813 } 1814 1815 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1816 dma->cmdi = 0; 1817 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1818 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1819 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1820 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1821 } 1822 cmdi = dma->cmdi++; 1823 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1824 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1825 1826 /* .p for command/result already set */ 1827 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1828 HIFN_D_MASKDONEIRQ); 1829 HIFN_CMDR_SYNC(sc, cmdi, 1830 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1831 dma->cmdu++; 1832 if (sc->sc_c_busy == 0) { 1833 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1834 sc->sc_c_busy = 1; 1835 } 1836 1837 /* 1838 * We don't worry about missing an interrupt (which a "command wait" 1839 * interrupt salvages us from), unless there is more than one command 1840 * in the queue. 1841 */ 1842 if (dma->cmdu > 1) { 1843 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1844 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1845 } 1846 1847 hifnstats.hst_ipackets++; 1848 hifnstats.hst_ibytes += cmd->src_mapsize; 1849 1850 hifn_dmamap_load_src(sc, cmd); 1851 if (sc->sc_s_busy == 0) { 1852 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1853 sc->sc_s_busy = 1; 1854 } 1855 1856 /* 1857 * Unlike other descriptors, we don't mask done interrupt from 1858 * result descriptor. 1859 */ 1860 #ifdef HIFN_DEBUG 1861 if (hifn_debug) 1862 printf("load res\n"); 1863 #endif 1864 if (dma->resi == HIFN_D_RES_RSIZE) { 1865 dma->resi = 0; 1866 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1867 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1868 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1869 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1870 } 1871 resi = dma->resi++; 1872 KASSERT(dma->hifn_commands[resi] == NULL, 1873 ("hifn_crypto: command slot %u busy", resi)); 1874 dma->hifn_commands[resi] = cmd; 1875 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1876 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1877 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1878 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1879 sc->sc_curbatch++; 1880 if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1881 hifnstats.hst_maxbatch = sc->sc_curbatch; 1882 hifnstats.hst_totbatch++; 1883 } else { 1884 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1885 HIFN_D_VALID | HIFN_D_LAST); 1886 sc->sc_curbatch = 0; 1887 } 1888 HIFN_RESR_SYNC(sc, resi, 1889 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1890 dma->resu++; 1891 if (sc->sc_r_busy == 0) { 1892 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1893 sc->sc_r_busy = 1; 1894 } 1895 1896 if (cmd->sloplen) 1897 cmd->slopidx = resi; 1898 1899 hifn_dmamap_load_dst(sc, cmd); 1900 1901 if (sc->sc_d_busy == 0) { 1902 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1903 sc->sc_d_busy = 1; 1904 } 1905 1906 #ifdef HIFN_DEBUG 1907 if (hifn_debug) { 1908 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1909 READ_REG_1(sc, HIFN_1_DMA_CSR), 1910 READ_REG_1(sc, HIFN_1_DMA_IER)); 1911 } 1912 #endif 1913 1914 sc->sc_active = 5; 1915 KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1916 return (err); /* success */ 1917 1918 err_dstmap: 1919 if (cmd->src_map != cmd->dst_map) 1920 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1921 err_dstmap1: 1922 if (cmd->src_map != cmd->dst_map) 1923 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 1924 err_srcmap: 1925 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1926 if (cmd->src_m != cmd->dst_m) 1927 m_freem(cmd->dst_m); 1928 } 1929 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 1930 err_srcmap1: 1931 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 1932 return (err); 1933 } 1934 1935 static void 1936 hifn_tick(void* vsc) 1937 { 1938 struct hifn_softc *sc = vsc; 1939 1940 HIFN_LOCK(sc); 1941 if (sc->sc_active == 0) { 1942 struct hifn_dma *dma = sc->sc_dma; 1943 u_int32_t r = 0; 1944 1945 if (dma->cmdu == 0 && sc->sc_c_busy) { 1946 sc->sc_c_busy = 0; 1947 r |= HIFN_DMACSR_C_CTRL_DIS; 1948 } 1949 if (dma->srcu == 0 && sc->sc_s_busy) { 1950 sc->sc_s_busy = 0; 1951 r |= HIFN_DMACSR_S_CTRL_DIS; 1952 } 1953 if (dma->dstu == 0 && sc->sc_d_busy) { 1954 sc->sc_d_busy = 0; 1955 r |= HIFN_DMACSR_D_CTRL_DIS; 1956 } 1957 if (dma->resu == 0 && sc->sc_r_busy) { 1958 sc->sc_r_busy = 0; 1959 r |= HIFN_DMACSR_R_CTRL_DIS; 1960 } 1961 if (r) 1962 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 1963 } else 1964 sc->sc_active--; 1965 HIFN_UNLOCK(sc); 1966 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 1967 } 1968 1969 static void 1970 hifn_intr(void *arg) 1971 { 1972 struct hifn_softc *sc = arg; 1973 struct hifn_dma *dma; 1974 u_int32_t dmacsr, restart; 1975 int i, u; 1976 1977 HIFN_LOCK(sc); 1978 dma = sc->sc_dma; 1979 1980 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 1981 1982 #ifdef HIFN_DEBUG 1983 if (hifn_debug) { 1984 device_printf(sc->sc_dev, 1985 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 1986 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 1987 dma->cmdi, dma->srci, dma->dsti, dma->resi, 1988 dma->cmdk, dma->srck, dma->dstk, dma->resk, 1989 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 1990 } 1991 #endif 1992 1993 /* Nothing in the DMA unit interrupted */ 1994 if ((dmacsr & sc->sc_dmaier) == 0) { 1995 hifnstats.hst_noirq++; 1996 HIFN_UNLOCK(sc); 1997 return; 1998 } 1999 2000 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2001 2002 if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2003 (dmacsr & HIFN_DMACSR_PUBDONE)) 2004 WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2005 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2006 2007 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2008 if (restart) 2009 device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2010 2011 if (sc->sc_flags & HIFN_IS_7811) { 2012 if (dmacsr & HIFN_DMACSR_ILLR) 2013 device_printf(sc->sc_dev, "illegal read\n"); 2014 if (dmacsr & HIFN_DMACSR_ILLW) 2015 device_printf(sc->sc_dev, "illegal write\n"); 2016 } 2017 2018 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2019 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2020 if (restart) { 2021 device_printf(sc->sc_dev, "abort, resetting.\n"); 2022 hifnstats.hst_abort++; 2023 hifn_abort(sc); 2024 HIFN_UNLOCK(sc); 2025 return; 2026 } 2027 2028 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2029 /* 2030 * If no slots to process and we receive a "waiting on 2031 * command" interrupt, we disable the "waiting on command" 2032 * (by clearing it). 2033 */ 2034 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2035 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2036 } 2037 2038 /* clear the rings */ 2039 i = dma->resk; u = dma->resu; 2040 while (u != 0) { 2041 HIFN_RESR_SYNC(sc, i, 2042 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2043 if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2044 HIFN_RESR_SYNC(sc, i, 2045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2046 break; 2047 } 2048 2049 if (i != HIFN_D_RES_RSIZE) { 2050 struct hifn_command *cmd; 2051 u_int8_t *macbuf = NULL; 2052 2053 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2054 cmd = dma->hifn_commands[i]; 2055 KASSERT(cmd != NULL, 2056 ("hifn_intr: null command slot %u", i)); 2057 dma->hifn_commands[i] = NULL; 2058 2059 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2060 macbuf = dma->result_bufs[i]; 2061 macbuf += 12; 2062 } 2063 2064 hifn_callback(sc, cmd, macbuf); 2065 hifnstats.hst_opackets++; 2066 u--; 2067 } 2068 2069 if (++i == (HIFN_D_RES_RSIZE + 1)) 2070 i = 0; 2071 } 2072 dma->resk = i; dma->resu = u; 2073 2074 i = dma->srck; u = dma->srcu; 2075 while (u != 0) { 2076 if (i == HIFN_D_SRC_RSIZE) 2077 i = 0; 2078 HIFN_SRCR_SYNC(sc, i, 2079 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2080 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2081 HIFN_SRCR_SYNC(sc, i, 2082 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2083 break; 2084 } 2085 i++, u--; 2086 } 2087 dma->srck = i; dma->srcu = u; 2088 2089 i = dma->cmdk; u = dma->cmdu; 2090 while (u != 0) { 2091 HIFN_CMDR_SYNC(sc, i, 2092 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2093 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2094 HIFN_CMDR_SYNC(sc, i, 2095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2096 break; 2097 } 2098 if (i != HIFN_D_CMD_RSIZE) { 2099 u--; 2100 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2101 } 2102 if (++i == (HIFN_D_CMD_RSIZE + 1)) 2103 i = 0; 2104 } 2105 dma->cmdk = i; dma->cmdu = u; 2106 2107 if (sc->sc_needwakeup) { /* XXX check high watermark */ 2108 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2109 #ifdef HIFN_DEBUG 2110 if (hifn_debug) 2111 device_printf(sc->sc_dev, 2112 "wakeup crypto (%x) u %d/%d/%d/%d\n", 2113 sc->sc_needwakeup, 2114 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2115 #endif 2116 sc->sc_needwakeup &= ~wakeup; 2117 crypto_unblock(sc->sc_cid, wakeup); 2118 } 2119 HIFN_UNLOCK(sc); 2120 } 2121 2122 /* 2123 * Allocate a new 'session' and return an encoded session id. 'sidp' 2124 * contains our registration id, and should contain an encoded session 2125 * id on successful allocation. 2126 */ 2127 static int 2128 hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2129 { 2130 struct cryptoini *c; 2131 struct hifn_softc *sc = arg; 2132 int i, mac = 0, cry = 0; 2133 2134 KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2135 if (sidp == NULL || cri == NULL || sc == NULL) 2136 return (EINVAL); 2137 2138 for (i = 0; i < sc->sc_maxses; i++) 2139 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2140 break; 2141 if (i == sc->sc_maxses) 2142 return (ENOMEM); 2143 2144 for (c = cri; c != NULL; c = c->cri_next) { 2145 switch (c->cri_alg) { 2146 case CRYPTO_MD5: 2147 case CRYPTO_SHA1: 2148 case CRYPTO_MD5_HMAC: 2149 case CRYPTO_SHA1_HMAC: 2150 if (mac) 2151 return (EINVAL); 2152 mac = 1; 2153 break; 2154 case CRYPTO_DES_CBC: 2155 case CRYPTO_3DES_CBC: 2156 /* XXX this may read fewer, does it matter? */ 2157 read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH); 2158 /*FALLTHROUGH*/ 2159 case CRYPTO_ARC4: 2160 if (cry) 2161 return (EINVAL); 2162 cry = 1; 2163 break; 2164 default: 2165 return (EINVAL); 2166 } 2167 } 2168 if (mac == 0 && cry == 0) 2169 return (EINVAL); 2170 2171 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2172 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2173 2174 return (0); 2175 } 2176 2177 /* 2178 * Deallocate a session. 2179 * XXX this routine should run a zero'd mac/encrypt key into context ram. 2180 * XXX to blow away any keys already stored there. 2181 */ 2182 static int 2183 hifn_freesession(void *arg, u_int64_t tid) 2184 { 2185 struct hifn_softc *sc = arg; 2186 int session; 2187 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 2188 2189 KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2190 if (sc == NULL) 2191 return (EINVAL); 2192 2193 session = HIFN_SESSION(sid); 2194 if (session >= sc->sc_maxses) 2195 return (EINVAL); 2196 2197 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2198 return (0); 2199 } 2200 2201 static int 2202 hifn_process(void *arg, struct cryptop *crp, int hint) 2203 { 2204 struct hifn_softc *sc = arg; 2205 struct hifn_command *cmd = NULL; 2206 int session, err; 2207 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2208 2209 if (crp == NULL || crp->crp_callback == NULL) { 2210 hifnstats.hst_invalid++; 2211 return (EINVAL); 2212 } 2213 session = HIFN_SESSION(crp->crp_sid); 2214 2215 if (sc == NULL || session >= sc->sc_maxses) { 2216 err = EINVAL; 2217 goto errout; 2218 } 2219 2220 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2221 if (cmd == NULL) { 2222 hifnstats.hst_nomem++; 2223 err = ENOMEM; 2224 goto errout; 2225 } 2226 2227 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2228 cmd->src_m = (struct mbuf *)crp->crp_buf; 2229 cmd->dst_m = (struct mbuf *)crp->crp_buf; 2230 } else if (crp->crp_flags & CRYPTO_F_IOV) { 2231 cmd->src_io = (struct uio *)crp->crp_buf; 2232 cmd->dst_io = (struct uio *)crp->crp_buf; 2233 } else { 2234 err = EINVAL; 2235 goto errout; /* XXX we don't handle contiguous buffers! */ 2236 } 2237 2238 crd1 = crp->crp_desc; 2239 if (crd1 == NULL) { 2240 err = EINVAL; 2241 goto errout; 2242 } 2243 crd2 = crd1->crd_next; 2244 2245 if (crd2 == NULL) { 2246 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2247 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2248 crd1->crd_alg == CRYPTO_SHA1 || 2249 crd1->crd_alg == CRYPTO_MD5) { 2250 maccrd = crd1; 2251 enccrd = NULL; 2252 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2253 crd1->crd_alg == CRYPTO_3DES_CBC || 2254 crd1->crd_alg == CRYPTO_ARC4) { 2255 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2256 cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2257 maccrd = NULL; 2258 enccrd = crd1; 2259 } else { 2260 err = EINVAL; 2261 goto errout; 2262 } 2263 } else { 2264 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2265 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2266 crd1->crd_alg == CRYPTO_MD5 || 2267 crd1->crd_alg == CRYPTO_SHA1) && 2268 (crd2->crd_alg == CRYPTO_DES_CBC || 2269 crd2->crd_alg == CRYPTO_3DES_CBC || 2270 crd2->crd_alg == CRYPTO_ARC4) && 2271 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2272 cmd->base_masks = HIFN_BASE_CMD_DECODE; 2273 maccrd = crd1; 2274 enccrd = crd2; 2275 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2276 crd1->crd_alg == CRYPTO_ARC4 || 2277 crd1->crd_alg == CRYPTO_3DES_CBC) && 2278 (crd2->crd_alg == CRYPTO_MD5_HMAC || 2279 crd2->crd_alg == CRYPTO_SHA1_HMAC || 2280 crd2->crd_alg == CRYPTO_MD5 || 2281 crd2->crd_alg == CRYPTO_SHA1) && 2282 (crd1->crd_flags & CRD_F_ENCRYPT)) { 2283 enccrd = crd1; 2284 maccrd = crd2; 2285 } else { 2286 /* 2287 * We cannot order the 7751 as requested 2288 */ 2289 err = EINVAL; 2290 goto errout; 2291 } 2292 } 2293 2294 if (enccrd) { 2295 cmd->enccrd = enccrd; 2296 cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2297 switch (enccrd->crd_alg) { 2298 case CRYPTO_ARC4: 2299 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2300 if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2301 != sc->sc_sessions[session].hs_prev_op) 2302 sc->sc_sessions[session].hs_state = 2303 HS_STATE_USED; 2304 break; 2305 case CRYPTO_DES_CBC: 2306 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2307 HIFN_CRYPT_CMD_MODE_CBC | 2308 HIFN_CRYPT_CMD_NEW_IV; 2309 break; 2310 case CRYPTO_3DES_CBC: 2311 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2312 HIFN_CRYPT_CMD_MODE_CBC | 2313 HIFN_CRYPT_CMD_NEW_IV; 2314 break; 2315 default: 2316 err = EINVAL; 2317 goto errout; 2318 } 2319 if (enccrd->crd_alg != CRYPTO_ARC4) { 2320 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2321 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2322 bcopy(enccrd->crd_iv, cmd->iv, 2323 HIFN_IV_LENGTH); 2324 else 2325 bcopy(sc->sc_sessions[session].hs_iv, 2326 cmd->iv, HIFN_IV_LENGTH); 2327 2328 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2329 == 0) { 2330 if (crp->crp_flags & CRYPTO_F_IMBUF) 2331 m_copyback(cmd->src_m, 2332 enccrd->crd_inject, 2333 HIFN_IV_LENGTH, cmd->iv); 2334 else if (crp->crp_flags & CRYPTO_F_IOV) 2335 cuio_copyback(cmd->src_io, 2336 enccrd->crd_inject, 2337 HIFN_IV_LENGTH, cmd->iv); 2338 } 2339 } else { 2340 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2341 bcopy(enccrd->crd_iv, cmd->iv, 2342 HIFN_IV_LENGTH); 2343 else if (crp->crp_flags & CRYPTO_F_IMBUF) 2344 m_copydata(cmd->src_m, 2345 enccrd->crd_inject, 2346 HIFN_IV_LENGTH, cmd->iv); 2347 else if (crp->crp_flags & CRYPTO_F_IOV) 2348 cuio_copydata(cmd->src_io, 2349 enccrd->crd_inject, 2350 HIFN_IV_LENGTH, cmd->iv); 2351 } 2352 } 2353 2354 cmd->ck = enccrd->crd_key; 2355 cmd->cklen = enccrd->crd_klen >> 3; 2356 2357 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2358 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2359 } 2360 2361 if (maccrd) { 2362 cmd->maccrd = maccrd; 2363 cmd->base_masks |= HIFN_BASE_CMD_MAC; 2364 2365 switch (maccrd->crd_alg) { 2366 case CRYPTO_MD5: 2367 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2368 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2369 HIFN_MAC_CMD_POS_IPSEC; 2370 break; 2371 case CRYPTO_MD5_HMAC: 2372 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2373 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2374 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2375 break; 2376 case CRYPTO_SHA1: 2377 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2378 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2379 HIFN_MAC_CMD_POS_IPSEC; 2380 break; 2381 case CRYPTO_SHA1_HMAC: 2382 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2383 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2384 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2385 break; 2386 } 2387 2388 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2389 maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2390 sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2391 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2392 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2393 bzero(cmd->mac + (maccrd->crd_klen >> 3), 2394 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2395 } 2396 } 2397 2398 cmd->crp = crp; 2399 cmd->session_num = session; 2400 cmd->softc = sc; 2401 2402 err = hifn_crypto(sc, cmd, crp, hint); 2403 if (!err) { 2404 if (enccrd) 2405 sc->sc_sessions[session].hs_prev_op = 2406 enccrd->crd_flags & CRD_F_ENCRYPT; 2407 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2408 sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2409 return 0; 2410 } else if (err == ERESTART) { 2411 /* 2412 * There weren't enough resources to dispatch the request 2413 * to the part. Notify the caller so they'll requeue this 2414 * request and resubmit it again soon. 2415 */ 2416 #ifdef HIFN_DEBUG 2417 if (hifn_debug) 2418 device_printf(sc->sc_dev, "requeue request\n"); 2419 #endif 2420 free(cmd, M_DEVBUF); 2421 sc->sc_needwakeup |= CRYPTO_SYMQ; 2422 return (err); 2423 } 2424 2425 errout: 2426 if (cmd != NULL) 2427 free(cmd, M_DEVBUF); 2428 if (err == EINVAL) 2429 hifnstats.hst_invalid++; 2430 else 2431 hifnstats.hst_nomem++; 2432 crp->crp_etype = err; 2433 crypto_done(crp); 2434 return (err); 2435 } 2436 2437 static void 2438 hifn_abort(struct hifn_softc *sc) 2439 { 2440 struct hifn_dma *dma = sc->sc_dma; 2441 struct hifn_command *cmd; 2442 struct cryptop *crp; 2443 int i, u; 2444 2445 i = dma->resk; u = dma->resu; 2446 while (u != 0) { 2447 cmd = dma->hifn_commands[i]; 2448 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2449 dma->hifn_commands[i] = NULL; 2450 crp = cmd->crp; 2451 2452 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2453 /* Salvage what we can. */ 2454 u_int8_t *macbuf; 2455 2456 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2457 macbuf = dma->result_bufs[i]; 2458 macbuf += 12; 2459 } else 2460 macbuf = NULL; 2461 hifnstats.hst_opackets++; 2462 hifn_callback(sc, cmd, macbuf); 2463 } else { 2464 if (cmd->src_map == cmd->dst_map) { 2465 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2466 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2467 } else { 2468 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2469 BUS_DMASYNC_POSTWRITE); 2470 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2471 BUS_DMASYNC_POSTREAD); 2472 } 2473 2474 if (cmd->src_m != cmd->dst_m) { 2475 m_freem(cmd->src_m); 2476 crp->crp_buf = (caddr_t)cmd->dst_m; 2477 } 2478 2479 /* non-shared buffers cannot be restarted */ 2480 if (cmd->src_map != cmd->dst_map) { 2481 /* 2482 * XXX should be EAGAIN, delayed until 2483 * after the reset. 2484 */ 2485 crp->crp_etype = ENOMEM; 2486 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2487 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2488 } else 2489 crp->crp_etype = ENOMEM; 2490 2491 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2492 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2493 2494 free(cmd, M_DEVBUF); 2495 if (crp->crp_etype != EAGAIN) 2496 crypto_done(crp); 2497 } 2498 2499 if (++i == HIFN_D_RES_RSIZE) 2500 i = 0; 2501 u--; 2502 } 2503 dma->resk = i; dma->resu = u; 2504 2505 /* Force upload of key next time */ 2506 for (i = 0; i < sc->sc_maxses; i++) 2507 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2508 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2509 2510 hifn_reset_board(sc, 1); 2511 hifn_init_dma(sc); 2512 hifn_init_pci_registers(sc); 2513 } 2514 2515 static void 2516 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2517 { 2518 struct hifn_dma *dma = sc->sc_dma; 2519 struct cryptop *crp = cmd->crp; 2520 struct cryptodesc *crd; 2521 struct mbuf *m; 2522 int totlen, i, u; 2523 2524 if (cmd->src_map == cmd->dst_map) { 2525 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2526 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2527 } else { 2528 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2529 BUS_DMASYNC_POSTWRITE); 2530 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2531 BUS_DMASYNC_POSTREAD); 2532 } 2533 2534 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2535 if (cmd->src_m != cmd->dst_m) { 2536 crp->crp_buf = (caddr_t)cmd->dst_m; 2537 totlen = cmd->src_mapsize; 2538 for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2539 if (totlen < m->m_len) { 2540 m->m_len = totlen; 2541 totlen = 0; 2542 } else 2543 totlen -= m->m_len; 2544 } 2545 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2546 m_freem(cmd->src_m); 2547 } 2548 } 2549 2550 if (cmd->sloplen != 0) { 2551 if (crp->crp_flags & CRYPTO_F_IMBUF) 2552 m_copyback((struct mbuf *)crp->crp_buf, 2553 cmd->src_mapsize - cmd->sloplen, 2554 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2555 else if (crp->crp_flags & CRYPTO_F_IOV) 2556 cuio_copyback((struct uio *)crp->crp_buf, 2557 cmd->src_mapsize - cmd->sloplen, 2558 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2559 } 2560 2561 i = dma->dstk; u = dma->dstu; 2562 while (u != 0) { 2563 if (i == HIFN_D_DST_RSIZE) 2564 i = 0; 2565 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2566 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2567 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2568 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2570 break; 2571 } 2572 i++, u--; 2573 } 2574 dma->dstk = i; dma->dstu = u; 2575 2576 hifnstats.hst_obytes += cmd->dst_mapsize; 2577 2578 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2579 HIFN_BASE_CMD_CRYPT) { 2580 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2581 if (crd->crd_alg != CRYPTO_DES_CBC && 2582 crd->crd_alg != CRYPTO_3DES_CBC) 2583 continue; 2584 if (crp->crp_flags & CRYPTO_F_IMBUF) 2585 m_copydata((struct mbuf *)crp->crp_buf, 2586 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2587 HIFN_IV_LENGTH, 2588 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2589 else if (crp->crp_flags & CRYPTO_F_IOV) { 2590 cuio_copydata((struct uio *)crp->crp_buf, 2591 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2592 HIFN_IV_LENGTH, 2593 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2594 } 2595 break; 2596 } 2597 } 2598 2599 if (macbuf != NULL) { 2600 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2601 int len; 2602 2603 if (crd->crd_alg == CRYPTO_MD5) 2604 len = 16; 2605 else if (crd->crd_alg == CRYPTO_SHA1) 2606 len = 20; 2607 else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2608 crd->crd_alg == CRYPTO_SHA1_HMAC) 2609 len = 12; 2610 else 2611 continue; 2612 2613 if (crp->crp_flags & CRYPTO_F_IMBUF) 2614 m_copyback((struct mbuf *)crp->crp_buf, 2615 crd->crd_inject, len, macbuf); 2616 else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2617 bcopy((caddr_t)macbuf, crp->crp_mac, len); 2618 break; 2619 } 2620 } 2621 2622 if (cmd->src_map != cmd->dst_map) { 2623 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2624 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2625 } 2626 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2627 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2628 free(cmd, M_DEVBUF); 2629 crypto_done(crp); 2630 } 2631 2632 /* 2633 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2634 * and Group 1 registers; avoid conditions that could create 2635 * burst writes by doing a read in between the writes. 2636 * 2637 * NB: The read we interpose is always to the same register; 2638 * we do this because reading from an arbitrary (e.g. last) 2639 * register may not always work. 2640 */ 2641 static void 2642 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2643 { 2644 if (sc->sc_flags & HIFN_IS_7811) { 2645 if (sc->sc_bar0_lastreg == reg - 4) 2646 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2647 sc->sc_bar0_lastreg = reg; 2648 } 2649 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2650 } 2651 2652 static void 2653 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2654 { 2655 if (sc->sc_flags & HIFN_IS_7811) { 2656 if (sc->sc_bar1_lastreg == reg - 4) 2657 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2658 sc->sc_bar1_lastreg = reg; 2659 } 2660 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2661 } 2662