1 /* $FreeBSD$ */ 2 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 3 4 /* 5 * Invertex AEON / Hifn 7751 driver 6 * Copyright (c) 1999 Invertex Inc. All rights reserved. 7 * Copyright (c) 1999 Theo de Raadt 8 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 9 * http://www.netsec.net 10 * 11 * This driver is based on a previous driver by Invertex, for which they 12 * requested: Please send any comments, feedback, bug-fixes, or feature 13 * requests to software@invertex.com. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Effort sponsored in part by the Defense Advanced Research Projects 39 * Agency (DARPA) and Air Force Research Laboratory, Air Force 40 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41 * 42 */ 43 44 #define HIFN_DEBUG 45 46 /* 47 * Driver for the Hifn 7751 encryption processor. 48 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/sysctl.h> 60 61 #include <vm/vm.h> 62 #include <vm/pmap.h> 63 64 #include <machine/clock.h> 65 #include <machine/bus.h> 66 #include <machine/resource.h> 67 #include <sys/bus.h> 68 #include <sys/rman.h> 69 70 #include <opencrypto/cryptodev.h> 71 #include <sys/random.h> 72 73 #include <pci/pcivar.h> 74 #include <pci/pcireg.h> 75 #include <dev/hifn/hifn7751reg.h> 76 #include <dev/hifn/hifn7751var.h> 77 78 /* 79 * Prototypes and count for the pci_device structure 80 */ 81 static int hifn_probe(device_t); 82 static int hifn_attach(device_t); 83 static int hifn_detach(device_t); 84 static int hifn_suspend(device_t); 85 static int hifn_resume(device_t); 86 static void hifn_shutdown(device_t); 87 88 static device_method_t hifn_methods[] = { 89 /* Device interface */ 90 DEVMETHOD(device_probe, hifn_probe), 91 DEVMETHOD(device_attach, hifn_attach), 92 DEVMETHOD(device_detach, hifn_detach), 93 DEVMETHOD(device_suspend, hifn_suspend), 94 DEVMETHOD(device_resume, hifn_resume), 95 DEVMETHOD(device_shutdown, hifn_shutdown), 96 97 /* bus interface */ 98 DEVMETHOD(bus_print_child, bus_generic_print_child), 99 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 100 101 { 0, 0 } 102 }; 103 static driver_t hifn_driver = { 104 "hifn", 105 hifn_methods, 106 sizeof (struct hifn_softc) 107 }; 108 static devclass_t hifn_devclass; 109 110 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 111 MODULE_DEPEND(hifn, crypto, 1, 1, 1); 112 113 static void hifn_reset_board(struct hifn_softc *, int); 114 static void hifn_reset_puc(struct hifn_softc *); 115 static void hifn_puc_wait(struct hifn_softc *); 116 static int hifn_enable_crypto(struct hifn_softc *); 117 static void hifn_set_retry(struct hifn_softc *sc); 118 static void hifn_init_dma(struct hifn_softc *); 119 static void hifn_init_pci_registers(struct hifn_softc *); 120 static int hifn_sramsize(struct hifn_softc *); 121 static int hifn_dramsize(struct hifn_softc *); 122 static int hifn_ramtype(struct hifn_softc *); 123 static void hifn_sessions(struct hifn_softc *); 124 static void hifn_intr(void *); 125 static u_int hifn_write_command(struct hifn_command *, u_int8_t *); 126 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 127 static int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 128 static int hifn_freesession(void *, u_int64_t); 129 static int hifn_process(void *, struct cryptop *, int); 130 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 131 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 132 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 133 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 134 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 135 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 136 static int hifn_init_pubrng(struct hifn_softc *); 137 static void hifn_rng(void *); 138 static void hifn_tick(void *); 139 static void hifn_abort(struct hifn_softc *); 140 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 141 142 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 143 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 144 145 static __inline__ u_int32_t 146 READ_REG_0(struct hifn_softc *sc, bus_size_t reg) 147 { 148 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 149 sc->sc_bar0_lastreg = (bus_size_t) -1; 150 return (v); 151 } 152 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 153 154 static __inline__ u_int32_t 155 READ_REG_1(struct hifn_softc *sc, bus_size_t reg) 156 { 157 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 158 sc->sc_bar1_lastreg = (bus_size_t) -1; 159 return (v); 160 } 161 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 162 163 #ifdef HIFN_DEBUG 164 static int hifn_debug = 0; 165 SYSCTL_INT(_debug, OID_AUTO, hifn, CTLFLAG_RW, &hifn_debug, 166 0, "Hifn driver debugging printfs"); 167 #endif 168 169 static struct hifn_stats hifnstats; 170 SYSCTL_STRUCT(_kern, OID_AUTO, hifn_stats, CTLFLAG_RD, &hifnstats, 171 hifn_stats, "Hifn driver statistics"); 172 static int hifn_maxbatch = 2; /* XXX tune based on part+sys speed */ 173 SYSCTL_INT(_kern, OID_AUTO, hifn_maxbatch, CTLFLAG_RW, &hifn_maxbatch, 174 0, "Hifn driver: max ops to batch w/o interrupt"); 175 176 /* 177 * Probe for a supported device. The PCI vendor and device 178 * IDs are used to detect devices we know how to handle. 179 */ 180 static int 181 hifn_probe(device_t dev) 182 { 183 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 184 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 185 return (0); 186 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 187 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 188 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 189 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 190 return (0); 191 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 192 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 193 return (0); 194 return (ENXIO); 195 } 196 197 static void 198 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 199 { 200 bus_addr_t *paddr = (bus_addr_t*) arg; 201 *paddr = segs->ds_addr; 202 } 203 204 static const char* 205 hifn_partname(struct hifn_softc *sc) 206 { 207 /* XXX sprintf numbers when not decoded */ 208 switch (pci_get_vendor(sc->sc_dev)) { 209 case PCI_VENDOR_HIFN: 210 switch (pci_get_device(sc->sc_dev)) { 211 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 212 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 213 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 214 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 215 } 216 return "Hifn unknown-part"; 217 case PCI_VENDOR_INVERTEX: 218 switch (pci_get_device(sc->sc_dev)) { 219 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 220 } 221 return "Invertex unknown-part"; 222 case PCI_VENDOR_NETSEC: 223 switch (pci_get_device(sc->sc_dev)) { 224 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 225 } 226 return "NetSec unknown-part"; 227 } 228 return "Unknown-vendor unknown-part"; 229 } 230 231 /* 232 * Attach an interface that successfully probed. 233 */ 234 static int 235 hifn_attach(device_t dev) 236 { 237 struct hifn_softc *sc = device_get_softc(dev); 238 u_int32_t cmd; 239 caddr_t kva; 240 int rseg, rid; 241 char rbase; 242 u_int16_t ena, rev; 243 244 KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 245 bzero(sc, sizeof (*sc)); 246 sc->sc_dev = dev; 247 248 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 249 250 /* XXX handle power management */ 251 252 /* 253 * The 7951 has a random number generator and 254 * public key support; note this. 255 */ 256 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 257 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951) 258 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 259 /* 260 * The 7811 has a random number generator and 261 * we also note it's identity 'cuz of some quirks. 262 */ 263 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 264 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 265 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 266 267 /* 268 * Configure support for memory-mapped access to 269 * registers and for DMA operations. 270 */ 271 #define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 272 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 273 cmd |= PCIM_ENA; 274 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 275 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 276 if ((cmd & PCIM_ENA) != PCIM_ENA) { 277 device_printf(dev, "failed to enable %s\n", 278 (cmd & PCIM_ENA) == 0 ? 279 "memory mapping & bus mastering" : 280 (cmd & PCIM_CMD_MEMEN) == 0 ? 281 "memory mapping" : "bus mastering"); 282 goto fail_pci; 283 } 284 #undef PCIM_ENA 285 286 /* 287 * Setup PCI resources. Note that we record the bus 288 * tag and handle for each register mapping, this is 289 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 290 * and WRITE_REG_1 macros throughout the driver. 291 */ 292 rid = HIFN_BAR0; 293 sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 294 0, ~0, 1, RF_ACTIVE); 295 if (sc->sc_bar0res == NULL) { 296 device_printf(dev, "cannot map bar%d register space\n", 0); 297 goto fail_pci; 298 } 299 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 300 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 301 sc->sc_bar0_lastreg = (bus_size_t) -1; 302 303 rid = HIFN_BAR1; 304 sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 305 0, ~0, 1, RF_ACTIVE); 306 if (sc->sc_bar1res == NULL) { 307 device_printf(dev, "cannot map bar%d register space\n", 1); 308 goto fail_io0; 309 } 310 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 311 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 312 sc->sc_bar1_lastreg = (bus_size_t) -1; 313 314 hifn_set_retry(sc); 315 316 /* 317 * Setup the area where the Hifn DMA's descriptors 318 * and associated data structures. 319 */ 320 if (bus_dma_tag_create(NULL, /* parent */ 321 1, 0, /* alignment,boundary */ 322 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 323 BUS_SPACE_MAXADDR, /* highaddr */ 324 NULL, NULL, /* filter, filterarg */ 325 HIFN_MAX_DMALEN, /* maxsize */ 326 MAX_SCATTER, /* nsegments */ 327 HIFN_MAX_SEGLEN, /* maxsegsize */ 328 BUS_DMA_ALLOCNOW, /* flags */ 329 &sc->sc_dmat)) { 330 device_printf(dev, "cannot allocate DMA tag\n"); 331 goto fail_io1; 332 } 333 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 334 device_printf(dev, "cannot create dma map\n"); 335 bus_dma_tag_destroy(sc->sc_dmat); 336 goto fail_io1; 337 } 338 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 339 device_printf(dev, "cannot alloc dma buffer\n"); 340 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 341 bus_dma_tag_destroy(sc->sc_dmat); 342 goto fail_io1; 343 } 344 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 345 sizeof (*sc->sc_dma), 346 hifn_dmamap_cb, &sc->sc_dma_physaddr, 347 BUS_DMA_NOWAIT)) { 348 device_printf(dev, "cannot load dma map\n"); 349 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 350 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 351 bus_dma_tag_destroy(sc->sc_dmat); 352 goto fail_io1; 353 } 354 sc->sc_dma = (struct hifn_dma *)kva; 355 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 356 357 KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!")); 358 KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!")); 359 KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!")); 360 KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!")); 361 362 /* 363 * Reset the board and do the ``secret handshake'' 364 * to enable the crypto support. Then complete the 365 * initialization procedure by setting up the interrupt 366 * and hooking in to the system crypto support so we'll 367 * get used for system services like the crypto device, 368 * IPsec, RNG device, etc. 369 */ 370 hifn_reset_board(sc, 0); 371 372 if (hifn_enable_crypto(sc) != 0) { 373 device_printf(dev, "crypto enabling failed\n"); 374 goto fail_mem; 375 } 376 hifn_reset_puc(sc); 377 378 hifn_init_dma(sc); 379 hifn_init_pci_registers(sc); 380 381 if (hifn_ramtype(sc)) 382 goto fail_mem; 383 384 if (sc->sc_drammodel == 0) 385 hifn_sramsize(sc); 386 else 387 hifn_dramsize(sc); 388 389 /* 390 * Workaround for NetSec 7751 rev A: half ram size because two 391 * of the address lines were left floating 392 */ 393 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 394 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 395 pci_get_revid(dev) == 0x61) /*XXX???*/ 396 sc->sc_ramsize >>= 1; 397 398 /* 399 * Arrange the interrupt line. 400 */ 401 rid = 0; 402 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 403 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 404 if (sc->sc_irq == NULL) { 405 device_printf(dev, "could not map interrupt\n"); 406 goto fail_mem; 407 } 408 /* 409 * NB: Network code assumes we are blocked with splimp() 410 * so make sure the IRQ is marked appropriately. 411 */ 412 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 413 hifn_intr, sc, &sc->sc_intrhand)) { 414 device_printf(dev, "could not setup interrupt\n"); 415 goto fail_intr2; 416 } 417 418 hifn_sessions(sc); 419 420 /* 421 * NB: Keep only the low 16 bits; this masks the chip id 422 * from the 7951. 423 */ 424 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 425 426 rseg = sc->sc_ramsize / 1024; 427 rbase = 'K'; 428 if (sc->sc_ramsize >= (1024 * 1024)) { 429 rbase = 'M'; 430 rseg /= 1024; 431 } 432 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 433 hifn_partname(sc), rev, 434 rseg, rbase, sc->sc_drammodel ? 'd' : 's', 435 sc->sc_maxses); 436 437 sc->sc_cid = crypto_get_driverid(0); 438 if (sc->sc_cid < 0) { 439 device_printf(dev, "could not get crypto driver id\n"); 440 goto fail_intr; 441 } 442 443 WRITE_REG_0(sc, HIFN_0_PUCNFG, 444 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 445 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 446 447 switch (ena) { 448 case HIFN_PUSTAT_ENA_2: 449 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 450 hifn_newsession, hifn_freesession, hifn_process, sc); 451 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 452 hifn_newsession, hifn_freesession, hifn_process, sc); 453 /*FALLTHROUGH*/ 454 case HIFN_PUSTAT_ENA_1: 455 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 456 hifn_newsession, hifn_freesession, hifn_process, sc); 457 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 458 hifn_newsession, hifn_freesession, hifn_process, sc); 459 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 460 hifn_newsession, hifn_freesession, hifn_process, sc); 461 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 462 hifn_newsession, hifn_freesession, hifn_process, sc); 463 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 464 hifn_newsession, hifn_freesession, hifn_process, sc); 465 break; 466 } 467 468 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 470 471 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 472 hifn_init_pubrng(sc); 473 474 /* NB: 1 means the callout runs w/o Giant locked */ 475 callout_init(&sc->sc_tickto, 1); 476 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 477 478 return (0); 479 480 fail_intr: 481 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 482 fail_intr2: 483 /* XXX don't store rid */ 484 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 485 fail_mem: 486 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 487 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 488 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 489 bus_dma_tag_destroy(sc->sc_dmat); 490 491 /* Turn off DMA polling */ 492 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 493 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 494 fail_io1: 495 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 496 fail_io0: 497 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 498 fail_pci: 499 mtx_destroy(&sc->sc_mtx); 500 return (ENXIO); 501 } 502 503 /* 504 * Detach an interface that successfully probed. 505 */ 506 static int 507 hifn_detach(device_t dev) 508 { 509 struct hifn_softc *sc = device_get_softc(dev); 510 511 KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 512 513 HIFN_LOCK(sc); 514 515 /*XXX other resources */ 516 callout_stop(&sc->sc_tickto); 517 callout_stop(&sc->sc_rngto); 518 519 /* Turn off DMA polling */ 520 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 521 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 522 523 crypto_unregister_all(sc->sc_cid); 524 525 bus_generic_detach(dev); /*XXX should be no children, right? */ 526 527 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 528 /* XXX don't store rid */ 529 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 530 531 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 532 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 533 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 534 bus_dma_tag_destroy(sc->sc_dmat); 535 536 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 537 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 538 539 HIFN_UNLOCK(sc); 540 541 mtx_destroy(&sc->sc_mtx); 542 543 return (0); 544 } 545 546 /* 547 * Stop all chip I/O so that the kernel's probe routines don't 548 * get confused by errant DMAs when rebooting. 549 */ 550 static void 551 hifn_shutdown(device_t dev) 552 { 553 #ifdef notyet 554 hifn_stop(device_get_softc(dev)); 555 #endif 556 } 557 558 /* 559 * Device suspend routine. Stop the interface and save some PCI 560 * settings in case the BIOS doesn't restore them properly on 561 * resume. 562 */ 563 static int 564 hifn_suspend(device_t dev) 565 { 566 struct hifn_softc *sc = device_get_softc(dev); 567 #ifdef notyet 568 int i; 569 570 hifn_stop(sc); 571 for (i = 0; i < 5; i++) 572 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 573 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 574 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 575 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 576 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 577 #endif 578 sc->sc_suspended = 1; 579 580 return (0); 581 } 582 583 /* 584 * Device resume routine. Restore some PCI settings in case the BIOS 585 * doesn't, re-enable busmastering, and restart the interface if 586 * appropriate. 587 */ 588 static int 589 hifn_resume(device_t dev) 590 { 591 struct hifn_softc *sc = device_get_softc(dev); 592 #ifdef notyet 593 int i; 594 595 /* better way to do this? */ 596 for (i = 0; i < 5; i++) 597 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 598 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 599 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 600 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 601 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 602 603 /* reenable busmastering */ 604 pci_enable_busmaster(dev); 605 pci_enable_io(dev, HIFN_RES); 606 607 /* reinitialize interface if necessary */ 608 if (ifp->if_flags & IFF_UP) 609 rl_init(sc); 610 #endif 611 sc->sc_suspended = 0; 612 613 return (0); 614 } 615 616 static int 617 hifn_init_pubrng(struct hifn_softc *sc) 618 { 619 u_int32_t r; 620 int i; 621 622 if ((sc->sc_flags & HIFN_IS_7811) == 0) { 623 /* Reset 7951 public key/rng engine */ 624 WRITE_REG_1(sc, HIFN_1_PUB_RESET, 625 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 626 627 for (i = 0; i < 100; i++) { 628 DELAY(1000); 629 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 630 HIFN_PUBRST_RESET) == 0) 631 break; 632 } 633 634 if (i == 100) { 635 device_printf(sc->sc_dev, "public key init failed\n"); 636 return (1); 637 } 638 } 639 640 /* Enable the rng, if available */ 641 if (sc->sc_flags & HIFN_HAS_RNG) { 642 if (sc->sc_flags & HIFN_IS_7811) { 643 r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 644 if (r & HIFN_7811_RNGENA_ENA) { 645 r &= ~HIFN_7811_RNGENA_ENA; 646 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 647 } 648 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 649 HIFN_7811_RNGCFG_DEFL); 650 r |= HIFN_7811_RNGENA_ENA; 651 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 652 } else 653 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 654 READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 655 HIFN_RNGCFG_ENA); 656 657 sc->sc_rngfirst = 1; 658 if (hz >= 100) 659 sc->sc_rnghz = hz / 100; 660 else 661 sc->sc_rnghz = 1; 662 /* NB: 1 means the callout runs w/o Giant locked */ 663 callout_init(&sc->sc_rngto, 1); 664 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 665 } 666 667 /* Enable public key engine, if available */ 668 if (sc->sc_flags & HIFN_HAS_PUBLIC) { 669 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 670 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 671 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 672 } 673 674 return (0); 675 } 676 677 static void 678 hifn_rng(void *vsc) 679 { 680 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 681 struct hifn_softc *sc = vsc; 682 u_int32_t sts, num[2]; 683 int i; 684 685 if (sc->sc_flags & HIFN_IS_7811) { 686 for (i = 0; i < 5; i++) { 687 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 688 if (sts & HIFN_7811_RNGSTS_UFL) { 689 device_printf(sc->sc_dev, 690 "RNG underflow: disabling\n"); 691 return; 692 } 693 if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 694 break; 695 696 /* 697 * There are at least two words in the RNG FIFO 698 * at this point. 699 */ 700 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 701 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 702 /* NB: discard first data read */ 703 if (sc->sc_rngfirst) 704 sc->sc_rngfirst = 0; 705 else 706 random_harvest(num, RANDOM_BITS(2), RANDOM_PURE); 707 } 708 } else { 709 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 710 711 /* NB: discard first data read */ 712 if (sc->sc_rngfirst) 713 sc->sc_rngfirst = 0; 714 else 715 random_harvest(num, RANDOM_BITS(1), RANDOM_PURE); 716 } 717 718 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 719 #undef RANDOM_BITS 720 } 721 722 static void 723 hifn_puc_wait(struct hifn_softc *sc) 724 { 725 int i; 726 727 for (i = 5000; i > 0; i--) { 728 DELAY(1); 729 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 730 break; 731 } 732 if (!i) 733 device_printf(sc->sc_dev, "proc unit did not reset\n"); 734 } 735 736 /* 737 * Reset the processing unit. 738 */ 739 static void 740 hifn_reset_puc(struct hifn_softc *sc) 741 { 742 /* Reset processing unit */ 743 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 744 hifn_puc_wait(sc); 745 } 746 747 /* 748 * Set the Retry and TRDY registers; note that we set them to 749 * zero because the 7811 locks up when forced to retry (section 750 * 3.6 of "Specification Update SU-0014-04". Not clear if we 751 * should do this for all Hifn parts, but it doesn't seem to hurt. 752 */ 753 static void 754 hifn_set_retry(struct hifn_softc *sc) 755 { 756 /* NB: RETRY only responds to 8-bit reads/writes */ 757 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 758 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 759 } 760 761 /* 762 * Resets the board. Values in the regesters are left as is 763 * from the reset (i.e. initial values are assigned elsewhere). 764 */ 765 static void 766 hifn_reset_board(struct hifn_softc *sc, int full) 767 { 768 u_int32_t reg; 769 770 /* 771 * Set polling in the DMA configuration register to zero. 0x7 avoids 772 * resetting the board and zeros out the other fields. 773 */ 774 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 775 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 776 777 /* 778 * Now that polling has been disabled, we have to wait 1 ms 779 * before resetting the board. 780 */ 781 DELAY(1000); 782 783 /* Reset the DMA unit */ 784 if (full) { 785 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 786 DELAY(1000); 787 } else { 788 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 789 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 790 hifn_reset_puc(sc); 791 } 792 793 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 794 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 795 796 /* Bring dma unit out of reset */ 797 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 798 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 799 800 hifn_puc_wait(sc); 801 hifn_set_retry(sc); 802 803 if (sc->sc_flags & HIFN_IS_7811) { 804 for (reg = 0; reg < 1000; reg++) { 805 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 806 HIFN_MIPSRST_CRAMINIT) 807 break; 808 DELAY(1000); 809 } 810 if (reg == 1000) 811 printf(": cram init timeout\n"); 812 } 813 } 814 815 static u_int32_t 816 hifn_next_signature(u_int32_t a, u_int cnt) 817 { 818 int i; 819 u_int32_t v; 820 821 for (i = 0; i < cnt; i++) { 822 823 /* get the parity */ 824 v = a & 0x80080125; 825 v ^= v >> 16; 826 v ^= v >> 8; 827 v ^= v >> 4; 828 v ^= v >> 2; 829 v ^= v >> 1; 830 831 a = (v & 1) ^ (a << 1); 832 } 833 834 return a; 835 } 836 837 struct pci2id { 838 u_short pci_vendor; 839 u_short pci_prod; 840 char card_id[13]; 841 }; 842 static struct pci2id pci2id[] = { 843 { 844 PCI_VENDOR_HIFN, 845 PCI_PRODUCT_HIFN_7951, 846 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 847 0x00, 0x00, 0x00, 0x00, 0x00 } 848 }, { 849 PCI_VENDOR_NETSEC, 850 PCI_PRODUCT_NETSEC_7751, 851 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 852 0x00, 0x00, 0x00, 0x00, 0x00 } 853 }, { 854 PCI_VENDOR_INVERTEX, 855 PCI_PRODUCT_INVERTEX_AEON, 856 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 857 0x00, 0x00, 0x00, 0x00, 0x00 } 858 }, { 859 PCI_VENDOR_HIFN, 860 PCI_PRODUCT_HIFN_7811, 861 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 862 0x00, 0x00, 0x00, 0x00, 0x00 } 863 }, { 864 /* 865 * Other vendors share this PCI ID as well, such as 866 * http://www.powercrypt.com, and obviously they also 867 * use the same key. 868 */ 869 PCI_VENDOR_HIFN, 870 PCI_PRODUCT_HIFN_7751, 871 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 872 0x00, 0x00, 0x00, 0x00, 0x00 } 873 }, 874 }; 875 876 /* 877 * Checks to see if crypto is already enabled. If crypto isn't enable, 878 * "hifn_enable_crypto" is called to enable it. The check is important, 879 * as enabling crypto twice will lock the board. 880 */ 881 static int 882 hifn_enable_crypto(struct hifn_softc *sc) 883 { 884 u_int32_t dmacfg, ramcfg, encl, addr, i; 885 char *offtbl = NULL; 886 887 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 888 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 889 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 890 offtbl = pci2id[i].card_id; 891 break; 892 } 893 } 894 if (offtbl == NULL) { 895 device_printf(sc->sc_dev, "Unknown card!\n"); 896 return (1); 897 } 898 899 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 900 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 901 902 /* 903 * The RAM config register's encrypt level bit needs to be set before 904 * every read performed on the encryption level register. 905 */ 906 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 907 908 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 909 910 /* 911 * Make sure we don't re-unlock. Two unlocks kills chip until the 912 * next reboot. 913 */ 914 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 915 #ifdef HIFN_DEBUG 916 if (hifn_debug) 917 device_printf(sc->sc_dev, 918 "Strong crypto already enabled!\n"); 919 #endif 920 goto report; 921 } 922 923 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 924 #ifdef HIFN_DEBUG 925 if (hifn_debug) 926 device_printf(sc->sc_dev, 927 "Unknown encryption level 0x%x\n", encl); 928 #endif 929 return 1; 930 } 931 932 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 933 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 934 DELAY(1000); 935 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 936 DELAY(1000); 937 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 938 DELAY(1000); 939 940 for (i = 0; i <= 12; i++) { 941 addr = hifn_next_signature(addr, offtbl[i] + 0x101); 942 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 943 944 DELAY(1000); 945 } 946 947 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 948 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 949 950 #ifdef HIFN_DEBUG 951 if (hifn_debug) { 952 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 953 device_printf(sc->sc_dev, "Engine is permanently " 954 "locked until next system reset!\n"); 955 else 956 device_printf(sc->sc_dev, "Engine enabled " 957 "successfully!\n"); 958 } 959 #endif 960 961 report: 962 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 963 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 964 965 switch (encl) { 966 case HIFN_PUSTAT_ENA_1: 967 case HIFN_PUSTAT_ENA_2: 968 break; 969 case HIFN_PUSTAT_ENA_0: 970 default: 971 device_printf(sc->sc_dev, "disabled"); 972 break; 973 } 974 975 return 0; 976 } 977 978 /* 979 * Give initial values to the registers listed in the "Register Space" 980 * section of the HIFN Software Development reference manual. 981 */ 982 static void 983 hifn_init_pci_registers(struct hifn_softc *sc) 984 { 985 /* write fixed values needed by the Initialization registers */ 986 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 987 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 988 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 989 990 /* write all 4 ring address registers */ 991 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 992 offsetof(struct hifn_dma, cmdr[0])); 993 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 994 offsetof(struct hifn_dma, srcr[0])); 995 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 996 offsetof(struct hifn_dma, dstr[0])); 997 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 998 offsetof(struct hifn_dma, resr[0])); 999 1000 DELAY(2000); 1001 1002 /* write status register */ 1003 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1004 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1005 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1006 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1007 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1008 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1009 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1010 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1011 HIFN_DMACSR_S_WAIT | 1012 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1013 HIFN_DMACSR_C_WAIT | 1014 HIFN_DMACSR_ENGINE | 1015 ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1016 HIFN_DMACSR_PUBDONE : 0) | 1017 ((sc->sc_flags & HIFN_IS_7811) ? 1018 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1019 1020 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1021 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1022 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1023 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1024 ((sc->sc_flags & HIFN_IS_7811) ? 1025 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1026 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1027 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1028 1029 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1030 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1031 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1032 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1033 1034 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1035 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1036 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1037 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1038 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1039 } 1040 1041 /* 1042 * The maximum number of sessions supported by the card 1043 * is dependent on the amount of context ram, which 1044 * encryption algorithms are enabled, and how compression 1045 * is configured. This should be configured before this 1046 * routine is called. 1047 */ 1048 static void 1049 hifn_sessions(struct hifn_softc *sc) 1050 { 1051 u_int32_t pucnfg; 1052 int ctxsize; 1053 1054 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1055 1056 if (pucnfg & HIFN_PUCNFG_COMPSING) { 1057 if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1058 ctxsize = 128; 1059 else 1060 ctxsize = 512; 1061 sc->sc_maxses = 1 + 1062 ((sc->sc_ramsize - 32768) / ctxsize); 1063 } else 1064 sc->sc_maxses = sc->sc_ramsize / 16384; 1065 1066 if (sc->sc_maxses > 2048) 1067 sc->sc_maxses = 2048; 1068 } 1069 1070 /* 1071 * Determine ram type (sram or dram). Board should be just out of a reset 1072 * state when this is called. 1073 */ 1074 static int 1075 hifn_ramtype(struct hifn_softc *sc) 1076 { 1077 u_int8_t data[8], dataexpect[8]; 1078 int i; 1079 1080 for (i = 0; i < sizeof(data); i++) 1081 data[i] = dataexpect[i] = 0x55; 1082 if (hifn_writeramaddr(sc, 0, data)) 1083 return (-1); 1084 if (hifn_readramaddr(sc, 0, data)) 1085 return (-1); 1086 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1087 sc->sc_drammodel = 1; 1088 return (0); 1089 } 1090 1091 for (i = 0; i < sizeof(data); i++) 1092 data[i] = dataexpect[i] = 0xaa; 1093 if (hifn_writeramaddr(sc, 0, data)) 1094 return (-1); 1095 if (hifn_readramaddr(sc, 0, data)) 1096 return (-1); 1097 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1098 sc->sc_drammodel = 1; 1099 return (0); 1100 } 1101 1102 return (0); 1103 } 1104 1105 #define HIFN_SRAM_MAX (32 << 20) 1106 #define HIFN_SRAM_STEP_SIZE 16384 1107 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1108 1109 static int 1110 hifn_sramsize(struct hifn_softc *sc) 1111 { 1112 u_int32_t a; 1113 u_int8_t data[8]; 1114 u_int8_t dataexpect[sizeof(data)]; 1115 int32_t i; 1116 1117 for (i = 0; i < sizeof(data); i++) 1118 data[i] = dataexpect[i] = i ^ 0x5a; 1119 1120 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1121 a = i * HIFN_SRAM_STEP_SIZE; 1122 bcopy(&i, data, sizeof(i)); 1123 hifn_writeramaddr(sc, a, data); 1124 } 1125 1126 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1127 a = i * HIFN_SRAM_STEP_SIZE; 1128 bcopy(&i, dataexpect, sizeof(i)); 1129 if (hifn_readramaddr(sc, a, data) < 0) 1130 return (0); 1131 if (bcmp(data, dataexpect, sizeof(data)) != 0) 1132 return (0); 1133 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1134 } 1135 1136 return (0); 1137 } 1138 1139 /* 1140 * XXX For dram boards, one should really try all of the 1141 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1142 * is already set up correctly. 1143 */ 1144 static int 1145 hifn_dramsize(struct hifn_softc *sc) 1146 { 1147 u_int32_t cnfg; 1148 1149 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1150 HIFN_PUCNFG_DRAMMASK; 1151 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1152 return (0); 1153 } 1154 1155 static void 1156 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1157 { 1158 struct hifn_dma *dma = sc->sc_dma; 1159 1160 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1161 dma->cmdi = 0; 1162 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1163 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1164 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1165 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1166 } 1167 *cmdp = dma->cmdi++; 1168 dma->cmdk = dma->cmdi; 1169 1170 if (dma->srci == HIFN_D_SRC_RSIZE) { 1171 dma->srci = 0; 1172 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1173 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1174 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1176 } 1177 *srcp = dma->srci++; 1178 dma->srck = dma->srci; 1179 1180 if (dma->dsti == HIFN_D_DST_RSIZE) { 1181 dma->dsti = 0; 1182 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1183 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1184 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1186 } 1187 *dstp = dma->dsti++; 1188 dma->dstk = dma->dsti; 1189 1190 if (dma->resi == HIFN_D_RES_RSIZE) { 1191 dma->resi = 0; 1192 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1193 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1194 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1196 } 1197 *resp = dma->resi++; 1198 dma->resk = dma->resi; 1199 } 1200 1201 static int 1202 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1203 { 1204 struct hifn_dma *dma = sc->sc_dma; 1205 hifn_base_command_t wc; 1206 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1207 int r, cmdi, resi, srci, dsti; 1208 1209 wc.masks = htole16(3 << 13); 1210 wc.session_num = htole16(addr >> 14); 1211 wc.total_source_count = htole16(8); 1212 wc.total_dest_count = htole16(addr & 0x3fff); 1213 1214 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1215 1216 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1217 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1218 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1219 1220 /* build write command */ 1221 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1222 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1223 bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1224 1225 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1226 + offsetof(struct hifn_dma, test_src)); 1227 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1228 + offsetof(struct hifn_dma, test_dst)); 1229 1230 dma->cmdr[cmdi].l = htole32(16 | masks); 1231 dma->srcr[srci].l = htole32(8 | masks); 1232 dma->dstr[dsti].l = htole32(4 | masks); 1233 dma->resr[resi].l = htole32(4 | masks); 1234 1235 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1236 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1237 1238 for (r = 10000; r >= 0; r--) { 1239 DELAY(10); 1240 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1241 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1242 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1243 break; 1244 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1245 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1246 } 1247 if (r == 0) { 1248 device_printf(sc->sc_dev, "writeramaddr -- " 1249 "result[%d](addr %d) still valid\n", resi, addr); 1250 r = -1; 1251 return (-1); 1252 } else 1253 r = 0; 1254 1255 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1256 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1257 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1258 1259 return (r); 1260 } 1261 1262 static int 1263 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1264 { 1265 struct hifn_dma *dma = sc->sc_dma; 1266 hifn_base_command_t rc; 1267 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1268 int r, cmdi, srci, dsti, resi; 1269 1270 rc.masks = htole16(2 << 13); 1271 rc.session_num = htole16(addr >> 14); 1272 rc.total_source_count = htole16(addr & 0x3fff); 1273 rc.total_dest_count = htole16(8); 1274 1275 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1276 1277 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1278 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1279 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1280 1281 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1282 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1283 1284 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1285 offsetof(struct hifn_dma, test_src)); 1286 dma->test_src = 0; 1287 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1288 offsetof(struct hifn_dma, test_dst)); 1289 dma->test_dst = 0; 1290 dma->cmdr[cmdi].l = htole32(8 | masks); 1291 dma->srcr[srci].l = htole32(8 | masks); 1292 dma->dstr[dsti].l = htole32(8 | masks); 1293 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1294 1295 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1296 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1297 1298 for (r = 10000; r >= 0; r--) { 1299 DELAY(10); 1300 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1302 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1303 break; 1304 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1305 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1306 } 1307 if (r == 0) { 1308 device_printf(sc->sc_dev, "readramaddr -- " 1309 "result[%d](addr %d) still valid\n", resi, addr); 1310 r = -1; 1311 } else { 1312 r = 0; 1313 bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1314 } 1315 1316 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1317 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1318 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1319 1320 return (r); 1321 } 1322 1323 /* 1324 * Initialize the descriptor rings. 1325 */ 1326 static void 1327 hifn_init_dma(struct hifn_softc *sc) 1328 { 1329 struct hifn_dma *dma = sc->sc_dma; 1330 int i; 1331 1332 hifn_set_retry(sc); 1333 1334 /* initialize static pointer values */ 1335 for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1336 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1337 offsetof(struct hifn_dma, command_bufs[i][0])); 1338 for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1339 dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1340 offsetof(struct hifn_dma, result_bufs[i][0])); 1341 1342 dma->cmdr[HIFN_D_CMD_RSIZE].p = 1343 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1344 dma->srcr[HIFN_D_SRC_RSIZE].p = 1345 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1346 dma->dstr[HIFN_D_DST_RSIZE].p = 1347 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1348 dma->resr[HIFN_D_RES_RSIZE].p = 1349 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1350 1351 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1352 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1353 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1354 } 1355 1356 /* 1357 * Writes out the raw command buffer space. Returns the 1358 * command buffer size. 1359 */ 1360 static u_int 1361 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1362 { 1363 #define MIN(a,b) ((a)<(b)?(a):(b)) 1364 u_int8_t *buf_pos; 1365 hifn_base_command_t *base_cmd; 1366 hifn_mac_command_t *mac_cmd; 1367 hifn_crypt_command_t *cry_cmd; 1368 int using_mac, using_crypt, len; 1369 u_int32_t dlen, slen; 1370 1371 buf_pos = buf; 1372 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1373 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1374 1375 base_cmd = (hifn_base_command_t *)buf_pos; 1376 base_cmd->masks = htole16(cmd->base_masks); 1377 slen = cmd->src_mapsize; 1378 if (cmd->sloplen) 1379 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1380 else 1381 dlen = cmd->dst_mapsize; 1382 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1383 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1384 dlen >>= 16; 1385 slen >>= 16; 1386 base_cmd->session_num = htole16(cmd->session_num | 1387 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1388 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1389 buf_pos += sizeof(hifn_base_command_t); 1390 1391 if (using_mac) { 1392 mac_cmd = (hifn_mac_command_t *)buf_pos; 1393 dlen = cmd->maccrd->crd_len; 1394 mac_cmd->source_count = htole16(dlen & 0xffff); 1395 dlen >>= 16; 1396 mac_cmd->masks = htole16(cmd->mac_masks | 1397 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1398 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1399 mac_cmd->reserved = 0; 1400 buf_pos += sizeof(hifn_mac_command_t); 1401 } 1402 1403 if (using_crypt) { 1404 cry_cmd = (hifn_crypt_command_t *)buf_pos; 1405 dlen = cmd->enccrd->crd_len; 1406 cry_cmd->source_count = htole16(dlen & 0xffff); 1407 dlen >>= 16; 1408 cry_cmd->masks = htole16(cmd->cry_masks | 1409 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1410 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1411 cry_cmd->reserved = 0; 1412 buf_pos += sizeof(hifn_crypt_command_t); 1413 } 1414 1415 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1416 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1417 buf_pos += HIFN_MAC_KEY_LENGTH; 1418 } 1419 1420 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1421 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1422 case HIFN_CRYPT_CMD_ALG_3DES: 1423 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1424 buf_pos += HIFN_3DES_KEY_LENGTH; 1425 break; 1426 case HIFN_CRYPT_CMD_ALG_DES: 1427 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1428 buf_pos += cmd->cklen; 1429 break; 1430 case HIFN_CRYPT_CMD_ALG_RC4: 1431 len = 256; 1432 do { 1433 int clen; 1434 1435 clen = MIN(cmd->cklen, len); 1436 bcopy(cmd->ck, buf_pos, clen); 1437 len -= clen; 1438 buf_pos += clen; 1439 } while (len > 0); 1440 bzero(buf_pos, 4); 1441 buf_pos += 4; 1442 break; 1443 } 1444 } 1445 1446 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1447 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH); 1448 buf_pos += HIFN_IV_LENGTH; 1449 } 1450 1451 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1452 bzero(buf_pos, 8); 1453 buf_pos += 8; 1454 } 1455 1456 return (buf_pos - buf); 1457 #undef MIN 1458 } 1459 1460 static int 1461 hifn_dmamap_aligned(struct hifn_operand *op) 1462 { 1463 int i; 1464 1465 for (i = 0; i < op->nsegs; i++) { 1466 if (op->segs[i].ds_addr & 3) 1467 return (0); 1468 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1469 return (0); 1470 } 1471 return (1); 1472 } 1473 1474 static int 1475 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1476 { 1477 struct hifn_dma *dma = sc->sc_dma; 1478 struct hifn_operand *dst = &cmd->dst; 1479 u_int32_t p, l; 1480 int idx, used = 0, i; 1481 1482 idx = dma->dsti; 1483 for (i = 0; i < dst->nsegs - 1; i++) { 1484 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1485 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1486 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1487 HIFN_DSTR_SYNC(sc, idx, 1488 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1489 used++; 1490 1491 if (++idx == HIFN_D_DST_RSIZE) { 1492 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1493 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1494 HIFN_DSTR_SYNC(sc, idx, 1495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1496 idx = 0; 1497 } 1498 } 1499 1500 if (cmd->sloplen == 0) { 1501 p = dst->segs[i].ds_addr; 1502 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1503 dst->segs[i].ds_len; 1504 } else { 1505 p = sc->sc_dma_physaddr + 1506 offsetof(struct hifn_dma, slop[cmd->slopidx]); 1507 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1508 sizeof(u_int32_t); 1509 1510 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1511 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1512 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1513 HIFN_D_MASKDONEIRQ | 1514 (dst->segs[i].ds_len - cmd->sloplen)); 1515 HIFN_DSTR_SYNC(sc, idx, 1516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1517 used++; 1518 1519 if (++idx == HIFN_D_DST_RSIZE) { 1520 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1521 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1522 HIFN_DSTR_SYNC(sc, idx, 1523 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1524 idx = 0; 1525 } 1526 } 1527 } 1528 dma->dstr[idx].p = htole32(p); 1529 dma->dstr[idx].l = htole32(l); 1530 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1531 used++; 1532 1533 if (++idx == HIFN_D_DST_RSIZE) { 1534 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1535 HIFN_D_MASKDONEIRQ); 1536 HIFN_DSTR_SYNC(sc, idx, 1537 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1538 idx = 0; 1539 } 1540 1541 dma->dsti = idx; 1542 dma->dstu += used; 1543 return (idx); 1544 } 1545 1546 static int 1547 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1548 { 1549 struct hifn_dma *dma = sc->sc_dma; 1550 struct hifn_operand *src = &cmd->src; 1551 int idx, i; 1552 u_int32_t last = 0; 1553 1554 idx = dma->srci; 1555 for (i = 0; i < src->nsegs; i++) { 1556 if (i == src->nsegs - 1) 1557 last = HIFN_D_LAST; 1558 1559 dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1560 dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1561 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1562 HIFN_SRCR_SYNC(sc, idx, 1563 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1564 1565 if (++idx == HIFN_D_SRC_RSIZE) { 1566 dma->srcr[idx].l = htole32(HIFN_D_VALID | 1567 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1568 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1569 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1570 idx = 0; 1571 } 1572 } 1573 dma->srci = idx; 1574 dma->srcu += src->nsegs; 1575 return (idx); 1576 } 1577 1578 static void 1579 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1580 { 1581 struct hifn_operand *op = arg; 1582 1583 KASSERT(nsegs <= MAX_SCATTER, 1584 ("hifn_op_cb: too many DMA segments (%u > %u) " 1585 "returned when mapping operand", nsegs, MAX_SCATTER)); 1586 op->mapsize = mapsize; 1587 op->nsegs = nsegs; 1588 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1589 } 1590 1591 static int 1592 hifn_crypto( 1593 struct hifn_softc *sc, 1594 struct hifn_command *cmd, 1595 struct cryptop *crp, 1596 int hint) 1597 { 1598 struct hifn_dma *dma = sc->sc_dma; 1599 u_int32_t cmdlen; 1600 int cmdi, resi, err = 0; 1601 1602 /* 1603 * need 1 cmd, and 1 res 1604 * 1605 * NB: check this first since it's easy. 1606 */ 1607 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1608 (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1609 #ifdef HIFN_DEBUG 1610 if (hifn_debug) { 1611 device_printf(sc->sc_dev, 1612 "cmd/result exhaustion, cmdu %u resu %u\n", 1613 dma->cmdu, dma->resu); 1614 } 1615 #endif 1616 hifnstats.hst_nomem_cr++; 1617 return (ERESTART); 1618 } 1619 1620 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1621 hifnstats.hst_nomem_map++; 1622 return (ENOMEM); 1623 } 1624 1625 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1626 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1627 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1628 hifnstats.hst_nomem_load++; 1629 err = ENOMEM; 1630 goto err_srcmap1; 1631 } 1632 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1633 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1634 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1635 hifnstats.hst_nomem_load++; 1636 err = ENOMEM; 1637 goto err_srcmap1; 1638 } 1639 } else { 1640 err = EINVAL; 1641 goto err_srcmap1; 1642 } 1643 1644 if (hifn_dmamap_aligned(&cmd->src)) { 1645 cmd->sloplen = cmd->src_mapsize & 3; 1646 cmd->dst = cmd->src; 1647 } else { 1648 if (crp->crp_flags & CRYPTO_F_IOV) { 1649 err = EINVAL; 1650 goto err_srcmap; 1651 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1652 int totlen, len; 1653 struct mbuf *m, *m0, *mlast; 1654 1655 KASSERT(cmd->dst_m == cmd->src_m, 1656 ("hifn_crypto: dst_m initialized improperly")); 1657 hifnstats.hst_unaligned++; 1658 /* 1659 * Source is not aligned on a longword boundary. 1660 * Copy the data to insure alignment. If we fail 1661 * to allocate mbufs or clusters while doing this 1662 * we return ERESTART so the operation is requeued 1663 * at the crypto later, but only if there are 1664 * ops already posted to the hardware; otherwise we 1665 * have no guarantee that we'll be re-entered. 1666 */ 1667 totlen = cmd->src_mapsize; 1668 if (cmd->src_m->m_flags & M_PKTHDR) { 1669 len = MHLEN; 1670 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1671 } else { 1672 len = MLEN; 1673 MGET(m0, M_DONTWAIT, MT_DATA); 1674 } 1675 if (m0 == NULL) { 1676 hifnstats.hst_nomem_mbuf++; 1677 err = dma->cmdu ? ERESTART : ENOMEM; 1678 goto err_srcmap; 1679 } 1680 if (len == MHLEN) { 1681 M_COPY_PKTHDR(m0, cmd->src_m); 1682 } 1683 if (totlen >= MINCLSIZE) { 1684 MCLGET(m0, M_DONTWAIT); 1685 if ((m0->m_flags & M_EXT) == 0) { 1686 hifnstats.hst_nomem_mcl++; 1687 err = dma->cmdu ? ERESTART : ENOMEM; 1688 m_freem(m0); 1689 goto err_srcmap; 1690 } 1691 len = MCLBYTES; 1692 } 1693 totlen -= len; 1694 m0->m_pkthdr.len = m0->m_len = len; 1695 mlast = m0; 1696 1697 while (totlen > 0) { 1698 MGET(m, M_DONTWAIT, MT_DATA); 1699 if (m == NULL) { 1700 hifnstats.hst_nomem_mbuf++; 1701 err = dma->cmdu ? ERESTART : ENOMEM; 1702 m_freem(m0); 1703 goto err_srcmap; 1704 } 1705 len = MLEN; 1706 if (totlen >= MINCLSIZE) { 1707 MCLGET(m, M_DONTWAIT); 1708 if ((m->m_flags & M_EXT) == 0) { 1709 hifnstats.hst_nomem_mcl++; 1710 err = dma->cmdu ? ERESTART : ENOMEM; 1711 mlast->m_next = m; 1712 m_freem(m0); 1713 goto err_srcmap; 1714 } 1715 len = MCLBYTES; 1716 } 1717 1718 m->m_len = len; 1719 m0->m_pkthdr.len += len; 1720 totlen -= len; 1721 1722 mlast->m_next = m; 1723 mlast = m; 1724 } 1725 cmd->dst_m = m0; 1726 } 1727 } 1728 1729 if (cmd->dst_map == NULL) { 1730 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1731 hifnstats.hst_nomem_map++; 1732 err = ENOMEM; 1733 goto err_srcmap; 1734 } 1735 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1736 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1737 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1738 hifnstats.hst_nomem_map++; 1739 err = ENOMEM; 1740 goto err_dstmap1; 1741 } 1742 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1743 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1744 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1745 hifnstats.hst_nomem_load++; 1746 err = ENOMEM; 1747 goto err_dstmap1; 1748 } 1749 } 1750 } 1751 1752 #ifdef HIFN_DEBUG 1753 if (hifn_debug) { 1754 device_printf(sc->sc_dev, 1755 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1756 READ_REG_1(sc, HIFN_1_DMA_CSR), 1757 READ_REG_1(sc, HIFN_1_DMA_IER), 1758 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1759 cmd->src_nsegs, cmd->dst_nsegs); 1760 } 1761 #endif 1762 1763 if (cmd->src_map == cmd->dst_map) { 1764 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1765 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1766 } else { 1767 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1768 BUS_DMASYNC_PREWRITE); 1769 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1770 BUS_DMASYNC_PREREAD); 1771 } 1772 1773 /* 1774 * need N src, and N dst 1775 */ 1776 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1777 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1778 #ifdef HIFN_DEBUG 1779 if (hifn_debug) { 1780 device_printf(sc->sc_dev, 1781 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1782 dma->srcu, cmd->src_nsegs, 1783 dma->dstu, cmd->dst_nsegs); 1784 } 1785 #endif 1786 hifnstats.hst_nomem_sd++; 1787 err = ERESTART; 1788 goto err_dstmap; 1789 } 1790 1791 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1792 dma->cmdi = 0; 1793 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1794 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1795 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1796 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1797 } 1798 cmdi = dma->cmdi++; 1799 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1800 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1801 1802 /* .p for command/result already set */ 1803 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1804 HIFN_D_MASKDONEIRQ); 1805 HIFN_CMDR_SYNC(sc, cmdi, 1806 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1807 dma->cmdu++; 1808 if (sc->sc_c_busy == 0) { 1809 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1810 sc->sc_c_busy = 1; 1811 } 1812 1813 /* 1814 * We don't worry about missing an interrupt (which a "command wait" 1815 * interrupt salvages us from), unless there is more than one command 1816 * in the queue. 1817 */ 1818 if (dma->cmdu > 1) { 1819 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1820 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1821 } 1822 1823 hifnstats.hst_ipackets++; 1824 hifnstats.hst_ibytes += cmd->src_mapsize; 1825 1826 hifn_dmamap_load_src(sc, cmd); 1827 if (sc->sc_s_busy == 0) { 1828 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1829 sc->sc_s_busy = 1; 1830 } 1831 1832 /* 1833 * Unlike other descriptors, we don't mask done interrupt from 1834 * result descriptor. 1835 */ 1836 #ifdef HIFN_DEBUG 1837 if (hifn_debug) 1838 printf("load res\n"); 1839 #endif 1840 if (dma->resi == HIFN_D_RES_RSIZE) { 1841 dma->resi = 0; 1842 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1843 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1844 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1845 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1846 } 1847 resi = dma->resi++; 1848 KASSERT(dma->hifn_commands[resi] == NULL, 1849 ("hifn_crypto: command slot %u busy", resi)); 1850 dma->hifn_commands[resi] = cmd; 1851 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1852 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1853 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1854 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1855 sc->sc_curbatch++; 1856 if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1857 hifnstats.hst_maxbatch = sc->sc_curbatch; 1858 hifnstats.hst_totbatch++; 1859 } else { 1860 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1861 HIFN_D_VALID | HIFN_D_LAST); 1862 sc->sc_curbatch = 0; 1863 } 1864 HIFN_RESR_SYNC(sc, resi, 1865 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1866 dma->resu++; 1867 if (sc->sc_r_busy == 0) { 1868 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1869 sc->sc_r_busy = 1; 1870 } 1871 1872 if (cmd->sloplen) 1873 cmd->slopidx = resi; 1874 1875 hifn_dmamap_load_dst(sc, cmd); 1876 1877 if (sc->sc_d_busy == 0) { 1878 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1879 sc->sc_d_busy = 1; 1880 } 1881 1882 #ifdef HIFN_DEBUG 1883 if (hifn_debug) { 1884 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1885 READ_REG_1(sc, HIFN_1_DMA_CSR), 1886 READ_REG_1(sc, HIFN_1_DMA_IER)); 1887 } 1888 #endif 1889 1890 sc->sc_active = 5; 1891 KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1892 return (err); /* success */ 1893 1894 err_dstmap: 1895 if (cmd->src_map != cmd->dst_map) 1896 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1897 err_dstmap1: 1898 if (cmd->src_map != cmd->dst_map) 1899 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 1900 err_srcmap: 1901 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1902 if (cmd->src_m != cmd->dst_m) 1903 m_freem(cmd->dst_m); 1904 } 1905 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 1906 err_srcmap1: 1907 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 1908 return (err); 1909 } 1910 1911 static void 1912 hifn_tick(void* vsc) 1913 { 1914 struct hifn_softc *sc = vsc; 1915 1916 HIFN_LOCK(sc); 1917 if (sc->sc_active == 0) { 1918 struct hifn_dma *dma = sc->sc_dma; 1919 u_int32_t r = 0; 1920 1921 if (dma->cmdu == 0 && sc->sc_c_busy) { 1922 sc->sc_c_busy = 0; 1923 r |= HIFN_DMACSR_C_CTRL_DIS; 1924 } 1925 if (dma->srcu == 0 && sc->sc_s_busy) { 1926 sc->sc_s_busy = 0; 1927 r |= HIFN_DMACSR_S_CTRL_DIS; 1928 } 1929 if (dma->dstu == 0 && sc->sc_d_busy) { 1930 sc->sc_d_busy = 0; 1931 r |= HIFN_DMACSR_D_CTRL_DIS; 1932 } 1933 if (dma->resu == 0 && sc->sc_r_busy) { 1934 sc->sc_r_busy = 0; 1935 r |= HIFN_DMACSR_R_CTRL_DIS; 1936 } 1937 if (r) 1938 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 1939 } else 1940 sc->sc_active--; 1941 HIFN_UNLOCK(sc); 1942 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 1943 } 1944 1945 static void 1946 hifn_intr(void *arg) 1947 { 1948 struct hifn_softc *sc = arg; 1949 struct hifn_dma *dma; 1950 u_int32_t dmacsr, restart; 1951 int i, u; 1952 1953 HIFN_LOCK(sc); 1954 dma = sc->sc_dma; 1955 1956 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 1957 1958 #ifdef HIFN_DEBUG 1959 if (hifn_debug) { 1960 device_printf(sc->sc_dev, 1961 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 1962 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 1963 dma->cmdi, dma->srci, dma->dsti, dma->resi, 1964 dma->cmdk, dma->srck, dma->dstk, dma->resk, 1965 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 1966 } 1967 #endif 1968 1969 /* Nothing in the DMA unit interrupted */ 1970 if ((dmacsr & sc->sc_dmaier) == 0) { 1971 hifnstats.hst_noirq++; 1972 HIFN_UNLOCK(sc); 1973 return; 1974 } 1975 1976 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 1977 1978 if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 1979 (dmacsr & HIFN_DMACSR_PUBDONE)) 1980 WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 1981 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 1982 1983 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 1984 if (restart) 1985 device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 1986 1987 if (sc->sc_flags & HIFN_IS_7811) { 1988 if (dmacsr & HIFN_DMACSR_ILLR) 1989 device_printf(sc->sc_dev, "illegal read\n"); 1990 if (dmacsr & HIFN_DMACSR_ILLW) 1991 device_printf(sc->sc_dev, "illegal write\n"); 1992 } 1993 1994 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 1995 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 1996 if (restart) { 1997 device_printf(sc->sc_dev, "abort, resetting.\n"); 1998 hifnstats.hst_abort++; 1999 hifn_abort(sc); 2000 HIFN_UNLOCK(sc); 2001 return; 2002 } 2003 2004 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2005 /* 2006 * If no slots to process and we receive a "waiting on 2007 * command" interrupt, we disable the "waiting on command" 2008 * (by clearing it). 2009 */ 2010 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2011 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2012 } 2013 2014 /* clear the rings */ 2015 i = dma->resk; u = dma->resu; 2016 while (u != 0) { 2017 HIFN_RESR_SYNC(sc, i, 2018 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2019 if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2020 HIFN_RESR_SYNC(sc, i, 2021 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2022 break; 2023 } 2024 2025 if (i != HIFN_D_RES_RSIZE) { 2026 struct hifn_command *cmd; 2027 u_int8_t *macbuf = NULL; 2028 2029 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2030 cmd = dma->hifn_commands[i]; 2031 KASSERT(cmd != NULL, 2032 ("hifn_intr: null command slot %u", i)); 2033 dma->hifn_commands[i] = NULL; 2034 2035 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2036 macbuf = dma->result_bufs[i]; 2037 macbuf += 12; 2038 } 2039 2040 hifn_callback(sc, cmd, macbuf); 2041 hifnstats.hst_opackets++; 2042 u--; 2043 } 2044 2045 if (++i == (HIFN_D_RES_RSIZE + 1)) 2046 i = 0; 2047 } 2048 dma->resk = i; dma->resu = u; 2049 2050 i = dma->srck; u = dma->srcu; 2051 while (u != 0) { 2052 if (i == HIFN_D_SRC_RSIZE) 2053 i = 0; 2054 HIFN_SRCR_SYNC(sc, i, 2055 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2056 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2057 HIFN_SRCR_SYNC(sc, i, 2058 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2059 break; 2060 } 2061 i++, u--; 2062 } 2063 dma->srck = i; dma->srcu = u; 2064 2065 i = dma->cmdk; u = dma->cmdu; 2066 while (u != 0) { 2067 HIFN_CMDR_SYNC(sc, i, 2068 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2069 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2070 HIFN_CMDR_SYNC(sc, i, 2071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2072 break; 2073 } 2074 if (i != HIFN_D_CMD_RSIZE) { 2075 u--; 2076 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2077 } 2078 if (++i == (HIFN_D_CMD_RSIZE + 1)) 2079 i = 0; 2080 } 2081 dma->cmdk = i; dma->cmdu = u; 2082 2083 if (sc->sc_needwakeup) { /* XXX check high watermark */ 2084 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2085 #ifdef HIFN_DEBUG 2086 if (hifn_debug) 2087 device_printf(sc->sc_dev, 2088 "wakeup crypto (%x) u %d/%d/%d/%d\n", 2089 sc->sc_needwakeup, 2090 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2091 #endif 2092 sc->sc_needwakeup &= ~wakeup; 2093 crypto_unblock(sc->sc_cid, wakeup); 2094 } 2095 HIFN_UNLOCK(sc); 2096 } 2097 2098 /* 2099 * Allocate a new 'session' and return an encoded session id. 'sidp' 2100 * contains our registration id, and should contain an encoded session 2101 * id on successful allocation. 2102 */ 2103 static int 2104 hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2105 { 2106 struct cryptoini *c; 2107 struct hifn_softc *sc = arg; 2108 int i, mac = 0, cry = 0; 2109 2110 KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2111 if (sidp == NULL || cri == NULL || sc == NULL) 2112 return (EINVAL); 2113 2114 for (i = 0; i < sc->sc_maxses; i++) 2115 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2116 break; 2117 if (i == sc->sc_maxses) 2118 return (ENOMEM); 2119 2120 for (c = cri; c != NULL; c = c->cri_next) { 2121 switch (c->cri_alg) { 2122 case CRYPTO_MD5: 2123 case CRYPTO_SHA1: 2124 case CRYPTO_MD5_HMAC: 2125 case CRYPTO_SHA1_HMAC: 2126 if (mac) 2127 return (EINVAL); 2128 mac = 1; 2129 break; 2130 case CRYPTO_DES_CBC: 2131 case CRYPTO_3DES_CBC: 2132 /* XXX this may read fewer, does it matter? */ 2133 read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH); 2134 /*FALLTHROUGH*/ 2135 case CRYPTO_ARC4: 2136 if (cry) 2137 return (EINVAL); 2138 cry = 1; 2139 break; 2140 default: 2141 return (EINVAL); 2142 } 2143 } 2144 if (mac == 0 && cry == 0) 2145 return (EINVAL); 2146 2147 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2148 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2149 2150 return (0); 2151 } 2152 2153 /* 2154 * Deallocate a session. 2155 * XXX this routine should run a zero'd mac/encrypt key into context ram. 2156 * XXX to blow away any keys already stored there. 2157 */ 2158 static int 2159 hifn_freesession(void *arg, u_int64_t tid) 2160 { 2161 struct hifn_softc *sc = arg; 2162 int session; 2163 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 2164 2165 KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2166 if (sc == NULL) 2167 return (EINVAL); 2168 2169 session = HIFN_SESSION(sid); 2170 if (session >= sc->sc_maxses) 2171 return (EINVAL); 2172 2173 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2174 return (0); 2175 } 2176 2177 static int 2178 hifn_process(void *arg, struct cryptop *crp, int hint) 2179 { 2180 struct hifn_softc *sc = arg; 2181 struct hifn_command *cmd = NULL; 2182 int session, err; 2183 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2184 2185 if (crp == NULL || crp->crp_callback == NULL) { 2186 hifnstats.hst_invalid++; 2187 return (EINVAL); 2188 } 2189 session = HIFN_SESSION(crp->crp_sid); 2190 2191 if (sc == NULL || session >= sc->sc_maxses) { 2192 err = EINVAL; 2193 goto errout; 2194 } 2195 2196 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2197 if (cmd == NULL) { 2198 hifnstats.hst_nomem++; 2199 err = ENOMEM; 2200 goto errout; 2201 } 2202 2203 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2204 cmd->src_m = (struct mbuf *)crp->crp_buf; 2205 cmd->dst_m = (struct mbuf *)crp->crp_buf; 2206 } else if (crp->crp_flags & CRYPTO_F_IOV) { 2207 cmd->src_io = (struct uio *)crp->crp_buf; 2208 cmd->dst_io = (struct uio *)crp->crp_buf; 2209 } else { 2210 err = EINVAL; 2211 goto errout; /* XXX we don't handle contiguous buffers! */ 2212 } 2213 2214 crd1 = crp->crp_desc; 2215 if (crd1 == NULL) { 2216 err = EINVAL; 2217 goto errout; 2218 } 2219 crd2 = crd1->crd_next; 2220 2221 if (crd2 == NULL) { 2222 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2223 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2224 crd1->crd_alg == CRYPTO_SHA1 || 2225 crd1->crd_alg == CRYPTO_MD5) { 2226 maccrd = crd1; 2227 enccrd = NULL; 2228 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2229 crd1->crd_alg == CRYPTO_3DES_CBC || 2230 crd1->crd_alg == CRYPTO_ARC4) { 2231 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2232 cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2233 maccrd = NULL; 2234 enccrd = crd1; 2235 } else { 2236 err = EINVAL; 2237 goto errout; 2238 } 2239 } else { 2240 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2241 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2242 crd1->crd_alg == CRYPTO_MD5 || 2243 crd1->crd_alg == CRYPTO_SHA1) && 2244 (crd2->crd_alg == CRYPTO_DES_CBC || 2245 crd2->crd_alg == CRYPTO_3DES_CBC || 2246 crd2->crd_alg == CRYPTO_ARC4) && 2247 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2248 cmd->base_masks = HIFN_BASE_CMD_DECODE; 2249 maccrd = crd1; 2250 enccrd = crd2; 2251 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2252 crd1->crd_alg == CRYPTO_ARC4 || 2253 crd1->crd_alg == CRYPTO_3DES_CBC) && 2254 (crd2->crd_alg == CRYPTO_MD5_HMAC || 2255 crd2->crd_alg == CRYPTO_SHA1_HMAC || 2256 crd2->crd_alg == CRYPTO_MD5 || 2257 crd2->crd_alg == CRYPTO_SHA1) && 2258 (crd1->crd_flags & CRD_F_ENCRYPT)) { 2259 enccrd = crd1; 2260 maccrd = crd2; 2261 } else { 2262 /* 2263 * We cannot order the 7751 as requested 2264 */ 2265 err = EINVAL; 2266 goto errout; 2267 } 2268 } 2269 2270 if (enccrd) { 2271 cmd->enccrd = enccrd; 2272 cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2273 switch (enccrd->crd_alg) { 2274 case CRYPTO_ARC4: 2275 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2276 if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2277 != sc->sc_sessions[session].hs_prev_op) 2278 sc->sc_sessions[session].hs_state = 2279 HS_STATE_USED; 2280 break; 2281 case CRYPTO_DES_CBC: 2282 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2283 HIFN_CRYPT_CMD_MODE_CBC | 2284 HIFN_CRYPT_CMD_NEW_IV; 2285 break; 2286 case CRYPTO_3DES_CBC: 2287 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2288 HIFN_CRYPT_CMD_MODE_CBC | 2289 HIFN_CRYPT_CMD_NEW_IV; 2290 break; 2291 default: 2292 err = EINVAL; 2293 goto errout; 2294 } 2295 if (enccrd->crd_alg != CRYPTO_ARC4) { 2296 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2297 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2298 bcopy(enccrd->crd_iv, cmd->iv, 2299 HIFN_IV_LENGTH); 2300 else 2301 bcopy(sc->sc_sessions[session].hs_iv, 2302 cmd->iv, HIFN_IV_LENGTH); 2303 2304 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2305 == 0) { 2306 if (crp->crp_flags & CRYPTO_F_IMBUF) 2307 m_copyback(cmd->src_m, 2308 enccrd->crd_inject, 2309 HIFN_IV_LENGTH, cmd->iv); 2310 else if (crp->crp_flags & CRYPTO_F_IOV) 2311 cuio_copyback(cmd->src_io, 2312 enccrd->crd_inject, 2313 HIFN_IV_LENGTH, cmd->iv); 2314 } 2315 } else { 2316 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2317 bcopy(enccrd->crd_iv, cmd->iv, 2318 HIFN_IV_LENGTH); 2319 else if (crp->crp_flags & CRYPTO_F_IMBUF) 2320 m_copydata(cmd->src_m, 2321 enccrd->crd_inject, 2322 HIFN_IV_LENGTH, cmd->iv); 2323 else if (crp->crp_flags & CRYPTO_F_IOV) 2324 cuio_copydata(cmd->src_io, 2325 enccrd->crd_inject, 2326 HIFN_IV_LENGTH, cmd->iv); 2327 } 2328 } 2329 2330 cmd->ck = enccrd->crd_key; 2331 cmd->cklen = enccrd->crd_klen >> 3; 2332 2333 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2334 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2335 } 2336 2337 if (maccrd) { 2338 cmd->maccrd = maccrd; 2339 cmd->base_masks |= HIFN_BASE_CMD_MAC; 2340 2341 switch (maccrd->crd_alg) { 2342 case CRYPTO_MD5: 2343 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2344 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2345 HIFN_MAC_CMD_POS_IPSEC; 2346 break; 2347 case CRYPTO_MD5_HMAC: 2348 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2349 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2350 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2351 break; 2352 case CRYPTO_SHA1: 2353 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2354 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2355 HIFN_MAC_CMD_POS_IPSEC; 2356 break; 2357 case CRYPTO_SHA1_HMAC: 2358 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2359 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2360 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2361 break; 2362 } 2363 2364 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2365 maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2366 sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2367 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2368 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2369 bzero(cmd->mac + (maccrd->crd_klen >> 3), 2370 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2371 } 2372 } 2373 2374 cmd->crp = crp; 2375 cmd->session_num = session; 2376 cmd->softc = sc; 2377 2378 err = hifn_crypto(sc, cmd, crp, hint); 2379 if (!err) { 2380 if (enccrd) 2381 sc->sc_sessions[session].hs_prev_op = 2382 enccrd->crd_flags & CRD_F_ENCRYPT; 2383 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2384 sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2385 return 0; 2386 } else if (err == ERESTART) { 2387 /* 2388 * There weren't enough resources to dispatch the request 2389 * to the part. Notify the caller so they'll requeue this 2390 * request and resubmit it again soon. 2391 */ 2392 #ifdef HIFN_DEBUG 2393 if (hifn_debug) 2394 device_printf(sc->sc_dev, "requeue request\n"); 2395 #endif 2396 free(cmd, M_DEVBUF); 2397 sc->sc_needwakeup |= CRYPTO_SYMQ; 2398 return (err); 2399 } 2400 2401 errout: 2402 if (cmd != NULL) 2403 free(cmd, M_DEVBUF); 2404 if (err == EINVAL) 2405 hifnstats.hst_invalid++; 2406 else 2407 hifnstats.hst_nomem++; 2408 crp->crp_etype = err; 2409 crypto_done(crp); 2410 return (err); 2411 } 2412 2413 static void 2414 hifn_abort(struct hifn_softc *sc) 2415 { 2416 struct hifn_dma *dma = sc->sc_dma; 2417 struct hifn_command *cmd; 2418 struct cryptop *crp; 2419 int i, u; 2420 2421 i = dma->resk; u = dma->resu; 2422 while (u != 0) { 2423 cmd = dma->hifn_commands[i]; 2424 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2425 dma->hifn_commands[i] = NULL; 2426 crp = cmd->crp; 2427 2428 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2429 /* Salvage what we can. */ 2430 u_int8_t *macbuf; 2431 2432 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2433 macbuf = dma->result_bufs[i]; 2434 macbuf += 12; 2435 } else 2436 macbuf = NULL; 2437 hifnstats.hst_opackets++; 2438 hifn_callback(sc, cmd, macbuf); 2439 } else { 2440 if (cmd->src_map == cmd->dst_map) { 2441 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2442 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2443 } else { 2444 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2445 BUS_DMASYNC_POSTWRITE); 2446 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2447 BUS_DMASYNC_POSTREAD); 2448 } 2449 2450 if (cmd->src_m != cmd->dst_m) { 2451 m_freem(cmd->src_m); 2452 crp->crp_buf = (caddr_t)cmd->dst_m; 2453 } 2454 2455 /* non-shared buffers cannot be restarted */ 2456 if (cmd->src_map != cmd->dst_map) { 2457 /* 2458 * XXX should be EAGAIN, delayed until 2459 * after the reset. 2460 */ 2461 crp->crp_etype = ENOMEM; 2462 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2463 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2464 } else 2465 crp->crp_etype = ENOMEM; 2466 2467 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2468 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2469 2470 free(cmd, M_DEVBUF); 2471 if (crp->crp_etype != EAGAIN) 2472 crypto_done(crp); 2473 } 2474 2475 if (++i == HIFN_D_RES_RSIZE) 2476 i = 0; 2477 u--; 2478 } 2479 dma->resk = i; dma->resu = u; 2480 2481 /* Force upload of key next time */ 2482 for (i = 0; i < sc->sc_maxses; i++) 2483 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2484 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2485 2486 hifn_reset_board(sc, 1); 2487 hifn_init_dma(sc); 2488 hifn_init_pci_registers(sc); 2489 } 2490 2491 static void 2492 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2493 { 2494 struct hifn_dma *dma = sc->sc_dma; 2495 struct cryptop *crp = cmd->crp; 2496 struct cryptodesc *crd; 2497 struct mbuf *m; 2498 int totlen, i, u; 2499 2500 if (cmd->src_map == cmd->dst_map) { 2501 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2502 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2503 } else { 2504 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2505 BUS_DMASYNC_POSTWRITE); 2506 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2507 BUS_DMASYNC_POSTREAD); 2508 } 2509 2510 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2511 if (cmd->src_m != cmd->dst_m) { 2512 crp->crp_buf = (caddr_t)cmd->dst_m; 2513 totlen = cmd->src_mapsize; 2514 for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2515 if (totlen < m->m_len) { 2516 m->m_len = totlen; 2517 totlen = 0; 2518 } else 2519 totlen -= m->m_len; 2520 } 2521 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2522 m_freem(cmd->src_m); 2523 } 2524 } 2525 2526 if (cmd->sloplen != 0) { 2527 if (crp->crp_flags & CRYPTO_F_IMBUF) 2528 m_copyback((struct mbuf *)crp->crp_buf, 2529 cmd->src_mapsize - cmd->sloplen, 2530 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2531 else if (crp->crp_flags & CRYPTO_F_IOV) 2532 cuio_copyback((struct uio *)crp->crp_buf, 2533 cmd->src_mapsize - cmd->sloplen, 2534 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2535 } 2536 2537 i = dma->dstk; u = dma->dstu; 2538 while (u != 0) { 2539 if (i == HIFN_D_DST_RSIZE) 2540 i = 0; 2541 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2542 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2543 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2544 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2545 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2546 break; 2547 } 2548 i++, u--; 2549 } 2550 dma->dstk = i; dma->dstu = u; 2551 2552 hifnstats.hst_obytes += cmd->dst_mapsize; 2553 2554 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2555 HIFN_BASE_CMD_CRYPT) { 2556 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2557 if (crd->crd_alg != CRYPTO_DES_CBC && 2558 crd->crd_alg != CRYPTO_3DES_CBC) 2559 continue; 2560 if (crp->crp_flags & CRYPTO_F_IMBUF) 2561 m_copydata((struct mbuf *)crp->crp_buf, 2562 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2563 HIFN_IV_LENGTH, 2564 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2565 else if (crp->crp_flags & CRYPTO_F_IOV) { 2566 cuio_copydata((struct uio *)crp->crp_buf, 2567 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2568 HIFN_IV_LENGTH, 2569 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2570 } 2571 break; 2572 } 2573 } 2574 2575 if (macbuf != NULL) { 2576 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2577 int len; 2578 2579 if (crd->crd_alg == CRYPTO_MD5) 2580 len = 16; 2581 else if (crd->crd_alg == CRYPTO_SHA1) 2582 len = 20; 2583 else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2584 crd->crd_alg == CRYPTO_SHA1_HMAC) 2585 len = 12; 2586 else 2587 continue; 2588 2589 if (crp->crp_flags & CRYPTO_F_IMBUF) 2590 m_copyback((struct mbuf *)crp->crp_buf, 2591 crd->crd_inject, len, macbuf); 2592 else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2593 bcopy((caddr_t)macbuf, crp->crp_mac, len); 2594 break; 2595 } 2596 } 2597 2598 if (cmd->src_map != cmd->dst_map) { 2599 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2600 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2601 } 2602 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2603 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2604 free(cmd, M_DEVBUF); 2605 crypto_done(crp); 2606 } 2607 2608 /* 2609 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2610 * and Group 1 registers; avoid conditions that could create 2611 * burst writes by doing a read in between the writes. 2612 * 2613 * NB: The read we interpose is always to the same register; 2614 * we do this because reading from an arbitrary (e.g. last) 2615 * register may not always work. 2616 */ 2617 static void 2618 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2619 { 2620 if (sc->sc_flags & HIFN_IS_7811) { 2621 if (sc->sc_bar0_lastreg == reg - 4) 2622 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2623 sc->sc_bar0_lastreg = reg; 2624 } 2625 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2626 } 2627 2628 static void 2629 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2630 { 2631 if (sc->sc_flags & HIFN_IS_7811) { 2632 if (sc->sc_bar1_lastreg == reg - 4) 2633 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2634 sc->sc_bar1_lastreg = reg; 2635 } 2636 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2637 } 2638