16d161891SSam Leffler /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 26d161891SSam Leffler 3098ca2bdSWarner Losh /*- 46d161891SSam Leffler * Invertex AEON / Hifn 7751 driver 56d161891SSam Leffler * Copyright (c) 1999 Invertex Inc. All rights reserved. 66d161891SSam Leffler * Copyright (c) 1999 Theo de Raadt 76d161891SSam Leffler * Copyright (c) 2000-2001 Network Security Technologies, Inc. 86d161891SSam Leffler * http://www.netsec.net 917b66701SSam Leffler * Copyright (c) 2003 Hifn Inc. 106d161891SSam Leffler * 116d161891SSam Leffler * This driver is based on a previous driver by Invertex, for which they 126d161891SSam Leffler * requested: Please send any comments, feedback, bug-fixes, or feature 136d161891SSam Leffler * requests to software@invertex.com. 146d161891SSam Leffler * 156d161891SSam Leffler * Redistribution and use in source and binary forms, with or without 166d161891SSam Leffler * modification, are permitted provided that the following conditions 176d161891SSam Leffler * are met: 186d161891SSam Leffler * 196d161891SSam Leffler * 1. Redistributions of source code must retain the above copyright 206d161891SSam Leffler * notice, this list of conditions and the following disclaimer. 216d161891SSam Leffler * 2. Redistributions in binary form must reproduce the above copyright 226d161891SSam Leffler * notice, this list of conditions and the following disclaimer in the 236d161891SSam Leffler * documentation and/or other materials provided with the distribution. 246d161891SSam Leffler * 3. The name of the author may not be used to endorse or promote products 256d161891SSam Leffler * derived from this software without specific prior written permission. 266d161891SSam Leffler * 276d161891SSam Leffler * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 286d161891SSam Leffler * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 296d161891SSam Leffler * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 306d161891SSam Leffler * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 316d161891SSam Leffler * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 326d161891SSam Leffler * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 336d161891SSam Leffler * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 346d161891SSam Leffler * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 356d161891SSam Leffler * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 366d161891SSam Leffler * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 376d161891SSam Leffler * 386d161891SSam Leffler * Effort sponsored in part by the Defense Advanced Research Projects 396d161891SSam Leffler * Agency (DARPA) and Air Force Research Laboratory, Air Force 406d161891SSam Leffler * Materiel Command, USAF, under agreement number F30602-01-2-0537. 416d161891SSam Leffler */ 426d161891SSam Leffler 43aad970f1SDavid E. O'Brien #include <sys/cdefs.h> 44aad970f1SDavid E. O'Brien __FBSDID("$FreeBSD$"); 45aad970f1SDavid E. O'Brien 466d161891SSam Leffler /* 4717b66701SSam Leffler * Driver for various Hifn encryption processors. 486d161891SSam Leffler */ 49b7c4858fSSam Leffler #include "opt_hifn.h" 506d161891SSam Leffler 516d161891SSam Leffler #include <sys/param.h> 526d161891SSam Leffler #include <sys/systm.h> 536d161891SSam Leffler #include <sys/proc.h> 546d161891SSam Leffler #include <sys/errno.h> 556d161891SSam Leffler #include <sys/malloc.h> 566d161891SSam Leffler #include <sys/kernel.h> 57fe12f24bSPoul-Henning Kamp #include <sys/module.h> 586d161891SSam Leffler #include <sys/mbuf.h> 596d161891SSam Leffler #include <sys/lock.h> 606d161891SSam Leffler #include <sys/mutex.h> 616d161891SSam Leffler #include <sys/sysctl.h> 626d161891SSam Leffler 636d161891SSam Leffler #include <vm/vm.h> 646d161891SSam Leffler #include <vm/pmap.h> 656d161891SSam Leffler 666d161891SSam Leffler #include <machine/bus.h> 676d161891SSam Leffler #include <machine/resource.h> 686d161891SSam Leffler #include <sys/bus.h> 696d161891SSam Leffler #include <sys/rman.h> 706d161891SSam Leffler 716d161891SSam Leffler #include <opencrypto/cryptodev.h> 726d161891SSam Leffler #include <sys/random.h> 736810ad6fSSam Leffler #include <sys/kobj.h> 746810ad6fSSam Leffler 756810ad6fSSam Leffler #include "cryptodev_if.h" 766d161891SSam Leffler 7777e6a3b2SWarner Losh #include <dev/pci/pcivar.h> 7877e6a3b2SWarner Losh #include <dev/pci/pcireg.h> 79b7c4858fSSam Leffler 80b7c4858fSSam Leffler #ifdef HIFN_RNDTEST 81b7c4858fSSam Leffler #include <dev/rndtest/rndtest.h> 82b7c4858fSSam Leffler #endif 836d161891SSam Leffler #include <dev/hifn/hifn7751reg.h> 846d161891SSam Leffler #include <dev/hifn/hifn7751var.h> 856d161891SSam Leffler 866810ad6fSSam Leffler #ifdef HIFN_VULCANDEV 876810ad6fSSam Leffler #include <sys/conf.h> 886810ad6fSSam Leffler #include <sys/uio.h> 896810ad6fSSam Leffler 906810ad6fSSam Leffler static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ 916810ad6fSSam Leffler #endif 926810ad6fSSam Leffler 936d161891SSam Leffler /* 946d161891SSam Leffler * Prototypes and count for the pci_device structure 956d161891SSam Leffler */ 966d161891SSam Leffler static int hifn_probe(device_t); 976d161891SSam Leffler static int hifn_attach(device_t); 986d161891SSam Leffler static int hifn_detach(device_t); 996d161891SSam Leffler static int hifn_suspend(device_t); 1006d161891SSam Leffler static int hifn_resume(device_t); 101a6340ec8SWarner Losh static int hifn_shutdown(device_t); 1026d161891SSam Leffler 1036810ad6fSSam Leffler static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); 1046810ad6fSSam Leffler static int hifn_freesession(device_t, u_int64_t); 1056810ad6fSSam Leffler static int hifn_process(device_t, struct cryptop *, int); 1066810ad6fSSam Leffler 1076d161891SSam Leffler static device_method_t hifn_methods[] = { 1086d161891SSam Leffler /* Device interface */ 1096d161891SSam Leffler DEVMETHOD(device_probe, hifn_probe), 1106d161891SSam Leffler DEVMETHOD(device_attach, hifn_attach), 1116d161891SSam Leffler DEVMETHOD(device_detach, hifn_detach), 1126d161891SSam Leffler DEVMETHOD(device_suspend, hifn_suspend), 1136d161891SSam Leffler DEVMETHOD(device_resume, hifn_resume), 1146d161891SSam Leffler DEVMETHOD(device_shutdown, hifn_shutdown), 1156d161891SSam Leffler 1166d161891SSam Leffler /* bus interface */ 1176d161891SSam Leffler DEVMETHOD(bus_print_child, bus_generic_print_child), 1186d161891SSam Leffler DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1196d161891SSam Leffler 1206810ad6fSSam Leffler /* crypto device methods */ 1216810ad6fSSam Leffler DEVMETHOD(cryptodev_newsession, hifn_newsession), 1226810ad6fSSam Leffler DEVMETHOD(cryptodev_freesession,hifn_freesession), 1236810ad6fSSam Leffler DEVMETHOD(cryptodev_process, hifn_process), 1246810ad6fSSam Leffler 1256d161891SSam Leffler { 0, 0 } 1266d161891SSam Leffler }; 1276d161891SSam Leffler static driver_t hifn_driver = { 1286d161891SSam Leffler "hifn", 1296d161891SSam Leffler hifn_methods, 1306d161891SSam Leffler sizeof (struct hifn_softc) 1316d161891SSam Leffler }; 1326d161891SSam Leffler static devclass_t hifn_devclass; 1336d161891SSam Leffler 1346d161891SSam Leffler DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 135f544a528SMark Murray MODULE_DEPEND(hifn, crypto, 1, 1, 1); 136b7c4858fSSam Leffler #ifdef HIFN_RNDTEST 137b7c4858fSSam Leffler MODULE_DEPEND(hifn, rndtest, 1, 1, 1); 138b7c4858fSSam Leffler #endif 1396d161891SSam Leffler 1406d161891SSam Leffler static void hifn_reset_board(struct hifn_softc *, int); 1416d161891SSam Leffler static void hifn_reset_puc(struct hifn_softc *); 1426d161891SSam Leffler static void hifn_puc_wait(struct hifn_softc *); 1436d161891SSam Leffler static int hifn_enable_crypto(struct hifn_softc *); 1446d161891SSam Leffler static void hifn_set_retry(struct hifn_softc *sc); 1456d161891SSam Leffler static void hifn_init_dma(struct hifn_softc *); 1466d161891SSam Leffler static void hifn_init_pci_registers(struct hifn_softc *); 1476d161891SSam Leffler static int hifn_sramsize(struct hifn_softc *); 1486d161891SSam Leffler static int hifn_dramsize(struct hifn_softc *); 1496d161891SSam Leffler static int hifn_ramtype(struct hifn_softc *); 1506d161891SSam Leffler static void hifn_sessions(struct hifn_softc *); 1516d161891SSam Leffler static void hifn_intr(void *); 1526d161891SSam Leffler static u_int hifn_write_command(struct hifn_command *, u_int8_t *); 1536d161891SSam Leffler static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 1546d161891SSam Leffler static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 1556d161891SSam Leffler static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 1566d161891SSam Leffler static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 1576d161891SSam Leffler static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 1586d161891SSam Leffler static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 1596d161891SSam Leffler static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 1606d161891SSam Leffler static int hifn_init_pubrng(struct hifn_softc *); 1616d161891SSam Leffler static void hifn_rng(void *); 1626d161891SSam Leffler static void hifn_tick(void *); 1636d161891SSam Leffler static void hifn_abort(struct hifn_softc *); 1646d161891SSam Leffler static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 1656d161891SSam Leffler 1666d161891SSam Leffler static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 1676d161891SSam Leffler static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 1686d161891SSam Leffler 1695908d366SStefan Farfeleder static __inline u_int32_t 1706d161891SSam Leffler READ_REG_0(struct hifn_softc *sc, bus_size_t reg) 1716d161891SSam Leffler { 1726d161891SSam Leffler u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 1736d161891SSam Leffler sc->sc_bar0_lastreg = (bus_size_t) -1; 1746d161891SSam Leffler return (v); 1756d161891SSam Leffler } 1766d161891SSam Leffler #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 1776d161891SSam Leffler 1785908d366SStefan Farfeleder static __inline u_int32_t 1796d161891SSam Leffler READ_REG_1(struct hifn_softc *sc, bus_size_t reg) 1806d161891SSam Leffler { 1816d161891SSam Leffler u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 1826d161891SSam Leffler sc->sc_bar1_lastreg = (bus_size_t) -1; 1836d161891SSam Leffler return (v); 1846d161891SSam Leffler } 1856d161891SSam Leffler #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 1866d161891SSam Leffler 18770be8cbaSSam Leffler SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 18870be8cbaSSam Leffler 1896d161891SSam Leffler #ifdef HIFN_DEBUG 1906d161891SSam Leffler static int hifn_debug = 0; 19170be8cbaSSam Leffler SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 19270be8cbaSSam Leffler 0, "control debugging msgs"); 1936d161891SSam Leffler #endif 1946d161891SSam Leffler 1956d161891SSam Leffler static struct hifn_stats hifnstats; 19670be8cbaSSam Leffler SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 19770be8cbaSSam Leffler hifn_stats, "driver statistics"); 198bd17515bSSam Leffler static int hifn_maxbatch = 1; 19970be8cbaSSam Leffler SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 20070be8cbaSSam Leffler 0, "max ops to batch w/o interrupt"); 2016d161891SSam Leffler 2026d161891SSam Leffler /* 2036d161891SSam Leffler * Probe for a supported device. The PCI vendor and device 2046d161891SSam Leffler * IDs are used to detect devices we know how to handle. 2056d161891SSam Leffler */ 2066d161891SSam Leffler static int 2076d161891SSam Leffler hifn_probe(device_t dev) 2086d161891SSam Leffler { 2096d161891SSam Leffler if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 2106d161891SSam Leffler pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 211538565c4SWarner Losh return (BUS_PROBE_DEFAULT); 2126d161891SSam Leffler if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 2136d161891SSam Leffler (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 2146d161891SSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 21517b66701SSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 21617b66701SSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 2176d161891SSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 218538565c4SWarner Losh return (BUS_PROBE_DEFAULT); 2196d161891SSam Leffler if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 2206d161891SSam Leffler pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 221538565c4SWarner Losh return (BUS_PROBE_DEFAULT); 2226d161891SSam Leffler return (ENXIO); 2236d161891SSam Leffler } 2246d161891SSam Leffler 2256d161891SSam Leffler static void 2266d161891SSam Leffler hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2276d161891SSam Leffler { 2286d161891SSam Leffler bus_addr_t *paddr = (bus_addr_t*) arg; 2296d161891SSam Leffler *paddr = segs->ds_addr; 2306d161891SSam Leffler } 2316d161891SSam Leffler 2326d161891SSam Leffler static const char* 2336d161891SSam Leffler hifn_partname(struct hifn_softc *sc) 2346d161891SSam Leffler { 2356d161891SSam Leffler /* XXX sprintf numbers when not decoded */ 2366d161891SSam Leffler switch (pci_get_vendor(sc->sc_dev)) { 2376d161891SSam Leffler case PCI_VENDOR_HIFN: 2386d161891SSam Leffler switch (pci_get_device(sc->sc_dev)) { 2396d161891SSam Leffler case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 2406d161891SSam Leffler case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 2416d161891SSam Leffler case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 2426d161891SSam Leffler case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 24317b66701SSam Leffler case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 24417b66701SSam Leffler case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 2456d161891SSam Leffler } 2466d161891SSam Leffler return "Hifn unknown-part"; 2476d161891SSam Leffler case PCI_VENDOR_INVERTEX: 2486d161891SSam Leffler switch (pci_get_device(sc->sc_dev)) { 2496d161891SSam Leffler case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 2506d161891SSam Leffler } 2516d161891SSam Leffler return "Invertex unknown-part"; 2526d161891SSam Leffler case PCI_VENDOR_NETSEC: 2536d161891SSam Leffler switch (pci_get_device(sc->sc_dev)) { 2546d161891SSam Leffler case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 2556d161891SSam Leffler } 2566d161891SSam Leffler return "NetSec unknown-part"; 2576d161891SSam Leffler } 2586d161891SSam Leffler return "Unknown-vendor unknown-part"; 2596d161891SSam Leffler } 2606d161891SSam Leffler 261b7c4858fSSam Leffler static void 262b7c4858fSSam Leffler default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 263b7c4858fSSam Leffler { 264b7c4858fSSam Leffler random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 265b7c4858fSSam Leffler } 266b7c4858fSSam Leffler 267aa959e0dSSam Leffler static u_int 268aa959e0dSSam Leffler checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max) 269aa959e0dSSam Leffler { 270aa959e0dSSam Leffler if (v > max) { 271aa959e0dSSam Leffler device_printf(dev, "Warning, %s %u out of range, " 272aa959e0dSSam Leffler "using max %u\n", what, v, max); 273aa959e0dSSam Leffler v = max; 274aa959e0dSSam Leffler } else if (v < min) { 275aa959e0dSSam Leffler device_printf(dev, "Warning, %s %u out of range, " 276aa959e0dSSam Leffler "using min %u\n", what, v, min); 277aa959e0dSSam Leffler v = min; 278aa959e0dSSam Leffler } 279aa959e0dSSam Leffler return v; 280aa959e0dSSam Leffler } 281aa959e0dSSam Leffler 282aa959e0dSSam Leffler /* 283aa959e0dSSam Leffler * Select PLL configuration for 795x parts. This is complicated in 284aa959e0dSSam Leffler * that we cannot determine the optimal parameters without user input. 285aa959e0dSSam Leffler * The reference clock is derived from an external clock through a 286aa959e0dSSam Leffler * multiplier. The external clock is either the host bus (i.e. PCI) 287aa959e0dSSam Leffler * or an external clock generator. When using the PCI bus we assume 288aa959e0dSSam Leffler * the clock is either 33 or 66 MHz; for an external source we cannot 289aa959e0dSSam Leffler * tell the speed. 290aa959e0dSSam Leffler * 291aa959e0dSSam Leffler * PLL configuration is done with a string: "pci" for PCI bus, or "ext" 292aa959e0dSSam Leffler * for an external source, followed by the frequency. We calculate 293aa959e0dSSam Leffler * the appropriate multiplier and PLL register contents accordingly. 294aa959e0dSSam Leffler * When no configuration is given we default to "pci66" since that 295aa959e0dSSam Leffler * always will allow the card to work. If a card is using the PCI 296aa959e0dSSam Leffler * bus clock and in a 33MHz slot then it will be operating at half 297aa959e0dSSam Leffler * speed until the correct information is provided. 2986810ad6fSSam Leffler * 2996810ad6fSSam Leffler * We use a default setting of "ext66" because according to Mike Ham 3006810ad6fSSam Leffler * of HiFn, almost every board in existence has an external crystal 3016810ad6fSSam Leffler * populated at 66Mhz. Using PCI can be a problem on modern motherboards, 3026810ad6fSSam Leffler * because PCI33 can have clocks from 0 to 33Mhz, and some have 3036810ad6fSSam Leffler * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. 304aa959e0dSSam Leffler */ 305aa959e0dSSam Leffler static void 306aa959e0dSSam Leffler hifn_getpllconfig(device_t dev, u_int *pll) 307aa959e0dSSam Leffler { 308aa959e0dSSam Leffler const char *pllspec; 309aa959e0dSSam Leffler u_int freq, mul, fl, fh; 310aa959e0dSSam Leffler u_int32_t pllconfig; 311aa959e0dSSam Leffler char *nxt; 312aa959e0dSSam Leffler 313aa959e0dSSam Leffler if (resource_string_value("hifn", device_get_unit(dev), 314aa959e0dSSam Leffler "pllconfig", &pllspec)) 3156810ad6fSSam Leffler pllspec = "ext66"; 316aa959e0dSSam Leffler fl = 33, fh = 66; 317aa959e0dSSam Leffler pllconfig = 0; 318aa959e0dSSam Leffler if (strncmp(pllspec, "ext", 3) == 0) { 319aa959e0dSSam Leffler pllspec += 3; 320aa959e0dSSam Leffler pllconfig |= HIFN_PLL_REF_SEL; 321aa959e0dSSam Leffler switch (pci_get_device(dev)) { 322aa959e0dSSam Leffler case PCI_PRODUCT_HIFN_7955: 323aa959e0dSSam Leffler case PCI_PRODUCT_HIFN_7956: 324aa959e0dSSam Leffler fl = 20, fh = 100; 325aa959e0dSSam Leffler break; 326aa959e0dSSam Leffler #ifdef notyet 327aa959e0dSSam Leffler case PCI_PRODUCT_HIFN_7954: 328aa959e0dSSam Leffler fl = 20, fh = 66; 329aa959e0dSSam Leffler break; 330aa959e0dSSam Leffler #endif 331aa959e0dSSam Leffler } 332aa959e0dSSam Leffler } else if (strncmp(pllspec, "pci", 3) == 0) 333aa959e0dSSam Leffler pllspec += 3; 334aa959e0dSSam Leffler freq = strtoul(pllspec, &nxt, 10); 335aa959e0dSSam Leffler if (nxt == pllspec) 336aa959e0dSSam Leffler freq = 66; 337aa959e0dSSam Leffler else 338aa959e0dSSam Leffler freq = checkmaxmin(dev, "frequency", freq, fl, fh); 339aa959e0dSSam Leffler /* 340aa959e0dSSam Leffler * Calculate multiplier. We target a Fck of 266 MHz, 341aa959e0dSSam Leffler * allowing only even values, possibly rounded down. 342aa959e0dSSam Leffler * Multipliers > 8 must set the charge pump current. 343aa959e0dSSam Leffler */ 344aa959e0dSSam Leffler mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); 345aa959e0dSSam Leffler pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; 346aa959e0dSSam Leffler if (mul > 8) 347aa959e0dSSam Leffler pllconfig |= HIFN_PLL_IS; 348aa959e0dSSam Leffler *pll = pllconfig; 349aa959e0dSSam Leffler } 350aa959e0dSSam Leffler 3516d161891SSam Leffler /* 3526d161891SSam Leffler * Attach an interface that successfully probed. 3536d161891SSam Leffler */ 3546d161891SSam Leffler static int 3556d161891SSam Leffler hifn_attach(device_t dev) 3566d161891SSam Leffler { 3576d161891SSam Leffler struct hifn_softc *sc = device_get_softc(dev); 3586d161891SSam Leffler caddr_t kva; 3596d161891SSam Leffler int rseg, rid; 3606d161891SSam Leffler char rbase; 3616d161891SSam Leffler u_int16_t ena, rev; 3626d161891SSam Leffler 3636d161891SSam Leffler sc->sc_dev = dev; 3646d161891SSam Leffler 3654f28f7d7SSam Leffler mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 3666d161891SSam Leffler 3676d161891SSam Leffler /* XXX handle power management */ 3686d161891SSam Leffler 3696d161891SSam Leffler /* 37017b66701SSam Leffler * The 7951 and 795x have a random number generator and 3716d161891SSam Leffler * public key support; note this. 3726d161891SSam Leffler */ 3736d161891SSam Leffler if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 37417b66701SSam Leffler (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 37517b66701SSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 37617b66701SSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 3776d161891SSam Leffler sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 3786d161891SSam Leffler /* 3796d161891SSam Leffler * The 7811 has a random number generator and 3806d161891SSam Leffler * we also note it's identity 'cuz of some quirks. 3816d161891SSam Leffler */ 3826d161891SSam Leffler if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 3836d161891SSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 3846d161891SSam Leffler sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 3856d161891SSam Leffler 3866d161891SSam Leffler /* 38717b66701SSam Leffler * The 795x parts support AES. 38817b66701SSam Leffler */ 38917b66701SSam Leffler if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 39017b66701SSam Leffler (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 391aa959e0dSSam Leffler pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { 39217b66701SSam Leffler sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 393aa959e0dSSam Leffler /* 394aa959e0dSSam Leffler * Select PLL configuration. This depends on the 395aa959e0dSSam Leffler * bus and board design and must be manually configured 396aa959e0dSSam Leffler * if the default setting is unacceptable. 397aa959e0dSSam Leffler */ 398aa959e0dSSam Leffler hifn_getpllconfig(dev, &sc->sc_pllconfig); 399aa959e0dSSam Leffler } 40017b66701SSam Leffler 40117b66701SSam Leffler /* 4026d161891SSam Leffler * Setup PCI resources. Note that we record the bus 4036d161891SSam Leffler * tag and handle for each register mapping, this is 4046d161891SSam Leffler * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 4056d161891SSam Leffler * and WRITE_REG_1 macros throughout the driver. 4066d161891SSam Leffler */ 407*8dca9d33STijl Coosemans pci_enable_busmaster(dev); 408*8dca9d33STijl Coosemans 4096d161891SSam Leffler rid = HIFN_BAR0; 4105f96beb9SNate Lawson sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 4115f96beb9SNate Lawson RF_ACTIVE); 4126d161891SSam Leffler if (sc->sc_bar0res == NULL) { 4136d161891SSam Leffler device_printf(dev, "cannot map bar%d register space\n", 0); 4146d161891SSam Leffler goto fail_pci; 4156d161891SSam Leffler } 4166d161891SSam Leffler sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 4176d161891SSam Leffler sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 4186d161891SSam Leffler sc->sc_bar0_lastreg = (bus_size_t) -1; 4196d161891SSam Leffler 4206d161891SSam Leffler rid = HIFN_BAR1; 4215f96beb9SNate Lawson sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 4225f96beb9SNate Lawson RF_ACTIVE); 4236d161891SSam Leffler if (sc->sc_bar1res == NULL) { 4246d161891SSam Leffler device_printf(dev, "cannot map bar%d register space\n", 1); 4256d161891SSam Leffler goto fail_io0; 4266d161891SSam Leffler } 4276d161891SSam Leffler sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 4286d161891SSam Leffler sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 4296d161891SSam Leffler sc->sc_bar1_lastreg = (bus_size_t) -1; 4306d161891SSam Leffler 4316d161891SSam Leffler hifn_set_retry(sc); 4326d161891SSam Leffler 4336d161891SSam Leffler /* 4346d161891SSam Leffler * Setup the area where the Hifn DMA's descriptors 4356d161891SSam Leffler * and associated data structures. 4366d161891SSam Leffler */ 4376d161891SSam Leffler if (bus_dma_tag_create(NULL, /* parent */ 4386d161891SSam Leffler 1, 0, /* alignment,boundary */ 4396d161891SSam Leffler BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4406d161891SSam Leffler BUS_SPACE_MAXADDR, /* highaddr */ 4416d161891SSam Leffler NULL, NULL, /* filter, filterarg */ 4426d161891SSam Leffler HIFN_MAX_DMALEN, /* maxsize */ 4436d161891SSam Leffler MAX_SCATTER, /* nsegments */ 4446d161891SSam Leffler HIFN_MAX_SEGLEN, /* maxsegsize */ 4456d161891SSam Leffler BUS_DMA_ALLOCNOW, /* flags */ 446f6b1c44dSScott Long NULL, /* lockfunc */ 447f6b1c44dSScott Long NULL, /* lockarg */ 4486d161891SSam Leffler &sc->sc_dmat)) { 4496d161891SSam Leffler device_printf(dev, "cannot allocate DMA tag\n"); 4506d161891SSam Leffler goto fail_io1; 4516d161891SSam Leffler } 4526d161891SSam Leffler if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 4536d161891SSam Leffler device_printf(dev, "cannot create dma map\n"); 4546d161891SSam Leffler bus_dma_tag_destroy(sc->sc_dmat); 4556d161891SSam Leffler goto fail_io1; 4566d161891SSam Leffler } 4576d161891SSam Leffler if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 4586d161891SSam Leffler device_printf(dev, "cannot alloc dma buffer\n"); 4596d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 4606d161891SSam Leffler bus_dma_tag_destroy(sc->sc_dmat); 4616d161891SSam Leffler goto fail_io1; 4626d161891SSam Leffler } 4636d161891SSam Leffler if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 4646d161891SSam Leffler sizeof (*sc->sc_dma), 4656d161891SSam Leffler hifn_dmamap_cb, &sc->sc_dma_physaddr, 4666d161891SSam Leffler BUS_DMA_NOWAIT)) { 4676d161891SSam Leffler device_printf(dev, "cannot load dma map\n"); 4686d161891SSam Leffler bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 4696d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 4706d161891SSam Leffler bus_dma_tag_destroy(sc->sc_dmat); 4716d161891SSam Leffler goto fail_io1; 4726d161891SSam Leffler } 4736d161891SSam Leffler sc->sc_dma = (struct hifn_dma *)kva; 4746d161891SSam Leffler bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 4756d161891SSam Leffler 476a2bf609dSSam Leffler KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 477a2bf609dSSam Leffler KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 478a2bf609dSSam Leffler KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 479a2bf609dSSam Leffler KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 4806d161891SSam Leffler 4816d161891SSam Leffler /* 4826d161891SSam Leffler * Reset the board and do the ``secret handshake'' 4836d161891SSam Leffler * to enable the crypto support. Then complete the 4846d161891SSam Leffler * initialization procedure by setting up the interrupt 4856d161891SSam Leffler * and hooking in to the system crypto support so we'll 4866d161891SSam Leffler * get used for system services like the crypto device, 4876d161891SSam Leffler * IPsec, RNG device, etc. 4886d161891SSam Leffler */ 4896d161891SSam Leffler hifn_reset_board(sc, 0); 4906d161891SSam Leffler 4916d161891SSam Leffler if (hifn_enable_crypto(sc) != 0) { 4926d161891SSam Leffler device_printf(dev, "crypto enabling failed\n"); 4936d161891SSam Leffler goto fail_mem; 4946d161891SSam Leffler } 4956d161891SSam Leffler hifn_reset_puc(sc); 4966d161891SSam Leffler 4976d161891SSam Leffler hifn_init_dma(sc); 4986d161891SSam Leffler hifn_init_pci_registers(sc); 4996d161891SSam Leffler 50017b66701SSam Leffler /* XXX can't dynamically determine ram type for 795x; force dram */ 50117b66701SSam Leffler if (sc->sc_flags & HIFN_IS_7956) 50217b66701SSam Leffler sc->sc_drammodel = 1; 50317b66701SSam Leffler else if (hifn_ramtype(sc)) 5046d161891SSam Leffler goto fail_mem; 5056d161891SSam Leffler 5066d161891SSam Leffler if (sc->sc_drammodel == 0) 5076d161891SSam Leffler hifn_sramsize(sc); 5086d161891SSam Leffler else 5096d161891SSam Leffler hifn_dramsize(sc); 5106d161891SSam Leffler 5116d161891SSam Leffler /* 5126d161891SSam Leffler * Workaround for NetSec 7751 rev A: half ram size because two 5136d161891SSam Leffler * of the address lines were left floating 5146d161891SSam Leffler */ 5156d161891SSam Leffler if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 5166d161891SSam Leffler pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 5176d161891SSam Leffler pci_get_revid(dev) == 0x61) /*XXX???*/ 5186d161891SSam Leffler sc->sc_ramsize >>= 1; 5196d161891SSam Leffler 5206d161891SSam Leffler /* 5216d161891SSam Leffler * Arrange the interrupt line. 5226d161891SSam Leffler */ 5236d161891SSam Leffler rid = 0; 5245f96beb9SNate Lawson sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5255f96beb9SNate Lawson RF_SHAREABLE|RF_ACTIVE); 5266d161891SSam Leffler if (sc->sc_irq == NULL) { 5276d161891SSam Leffler device_printf(dev, "could not map interrupt\n"); 5286d161891SSam Leffler goto fail_mem; 5296d161891SSam Leffler } 5306d161891SSam Leffler /* 5316d161891SSam Leffler * NB: Network code assumes we are blocked with splimp() 5326d161891SSam Leffler * so make sure the IRQ is marked appropriately. 5336d161891SSam Leffler */ 5344f28f7d7SSam Leffler if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 535ef544f63SPaolo Pisati NULL, hifn_intr, sc, &sc->sc_intrhand)) { 5366d161891SSam Leffler device_printf(dev, "could not setup interrupt\n"); 5376d161891SSam Leffler goto fail_intr2; 5386d161891SSam Leffler } 5396d161891SSam Leffler 5406d161891SSam Leffler hifn_sessions(sc); 5416d161891SSam Leffler 5426d161891SSam Leffler /* 5436d161891SSam Leffler * NB: Keep only the low 16 bits; this masks the chip id 5446d161891SSam Leffler * from the 7951. 5456d161891SSam Leffler */ 5466d161891SSam Leffler rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 5476d161891SSam Leffler 5486d161891SSam Leffler rseg = sc->sc_ramsize / 1024; 5496d161891SSam Leffler rbase = 'K'; 5506d161891SSam Leffler if (sc->sc_ramsize >= (1024 * 1024)) { 5516d161891SSam Leffler rbase = 'M'; 5526d161891SSam Leffler rseg /= 1024; 5536d161891SSam Leffler } 554aa959e0dSSam Leffler device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", 5556d161891SSam Leffler hifn_partname(sc), rev, 556fe9b390bSSam Leffler rseg, rbase, sc->sc_drammodel ? 'd' : 's'); 557aa959e0dSSam Leffler if (sc->sc_flags & HIFN_IS_7956) 558aa959e0dSSam Leffler printf(", pll=0x%x<%s clk, %ux mult>", 559aa959e0dSSam Leffler sc->sc_pllconfig, 560aa959e0dSSam Leffler sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", 561aa959e0dSSam Leffler 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); 562aa959e0dSSam Leffler printf("\n"); 5636d161891SSam Leffler 5646810ad6fSSam Leffler sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 5656d161891SSam Leffler if (sc->sc_cid < 0) { 5666d161891SSam Leffler device_printf(dev, "could not get crypto driver id\n"); 5676d161891SSam Leffler goto fail_intr; 5686d161891SSam Leffler } 5696d161891SSam Leffler 5706d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUCNFG, 5716d161891SSam Leffler READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 5726d161891SSam Leffler ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 5736d161891SSam Leffler 5746d161891SSam Leffler switch (ena) { 5756d161891SSam Leffler case HIFN_PUSTAT_ENA_2: 5766810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 5776810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); 57817b66701SSam Leffler if (sc->sc_flags & HIFN_HAS_AES) 5796810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 5806d161891SSam Leffler /*FALLTHROUGH*/ 5816d161891SSam Leffler case HIFN_PUSTAT_ENA_1: 5826810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); 5836810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); 5846810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 5856810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 5866810ad6fSSam Leffler crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 5876d161891SSam Leffler break; 5886d161891SSam Leffler } 5896d161891SSam Leffler 5906d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 5916d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5926d161891SSam Leffler 5936d161891SSam Leffler if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 5946d161891SSam Leffler hifn_init_pubrng(sc); 5956d161891SSam Leffler 596c06eb4e2SSam Leffler callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 5976d161891SSam Leffler callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 5986d161891SSam Leffler 5996d161891SSam Leffler return (0); 6006d161891SSam Leffler 6016d161891SSam Leffler fail_intr: 6026d161891SSam Leffler bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 6036d161891SSam Leffler fail_intr2: 6046d161891SSam Leffler /* XXX don't store rid */ 6056d161891SSam Leffler bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 6066d161891SSam Leffler fail_mem: 6076d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 6086d161891SSam Leffler bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 6096d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 6106d161891SSam Leffler bus_dma_tag_destroy(sc->sc_dmat); 6116d161891SSam Leffler 6126d161891SSam Leffler /* Turn off DMA polling */ 6136d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 6146d161891SSam Leffler HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 6156d161891SSam Leffler fail_io1: 6166d161891SSam Leffler bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 6176d161891SSam Leffler fail_io0: 6186d161891SSam Leffler bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 6196d161891SSam Leffler fail_pci: 6206d161891SSam Leffler mtx_destroy(&sc->sc_mtx); 6216d161891SSam Leffler return (ENXIO); 6226d161891SSam Leffler } 6236d161891SSam Leffler 6246d161891SSam Leffler /* 6256d161891SSam Leffler * Detach an interface that successfully probed. 6266d161891SSam Leffler */ 6276d161891SSam Leffler static int 6286d161891SSam Leffler hifn_detach(device_t dev) 6296d161891SSam Leffler { 6306d161891SSam Leffler struct hifn_softc *sc = device_get_softc(dev); 6316d161891SSam Leffler 6326d161891SSam Leffler KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 6336d161891SSam Leffler 6344f28f7d7SSam Leffler /* disable interrupts */ 6354f28f7d7SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 6366d161891SSam Leffler 6376d161891SSam Leffler /*XXX other resources */ 6386d161891SSam Leffler callout_stop(&sc->sc_tickto); 6396d161891SSam Leffler callout_stop(&sc->sc_rngto); 640236266eeSSam Leffler #ifdef HIFN_RNDTEST 641236266eeSSam Leffler if (sc->sc_rndtest) 642bba9599aSSam Leffler rndtest_detach(sc->sc_rndtest); 643236266eeSSam Leffler #endif 6446d161891SSam Leffler 6456d161891SSam Leffler /* Turn off DMA polling */ 6466d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 6476d161891SSam Leffler HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 6486d161891SSam Leffler 6496d161891SSam Leffler crypto_unregister_all(sc->sc_cid); 6506d161891SSam Leffler 6516d161891SSam Leffler bus_generic_detach(dev); /*XXX should be no children, right? */ 6526d161891SSam Leffler 6536d161891SSam Leffler bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 6546d161891SSam Leffler /* XXX don't store rid */ 6556d161891SSam Leffler bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 6566d161891SSam Leffler 6576d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 6586d161891SSam Leffler bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 6596d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 6606d161891SSam Leffler bus_dma_tag_destroy(sc->sc_dmat); 6616d161891SSam Leffler 6626d161891SSam Leffler bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 6636d161891SSam Leffler bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 6646d161891SSam Leffler 6656d161891SSam Leffler mtx_destroy(&sc->sc_mtx); 6666d161891SSam Leffler 6676d161891SSam Leffler return (0); 6686d161891SSam Leffler } 6696d161891SSam Leffler 6706d161891SSam Leffler /* 6716d161891SSam Leffler * Stop all chip I/O so that the kernel's probe routines don't 6726d161891SSam Leffler * get confused by errant DMAs when rebooting. 6736d161891SSam Leffler */ 674a6340ec8SWarner Losh static int 6756d161891SSam Leffler hifn_shutdown(device_t dev) 6766d161891SSam Leffler { 6776d161891SSam Leffler #ifdef notyet 6786d161891SSam Leffler hifn_stop(device_get_softc(dev)); 6796d161891SSam Leffler #endif 680a6340ec8SWarner Losh return (0); 6816d161891SSam Leffler } 6826d161891SSam Leffler 6836d161891SSam Leffler /* 6846d161891SSam Leffler * Device suspend routine. Stop the interface and save some PCI 6856d161891SSam Leffler * settings in case the BIOS doesn't restore them properly on 6866d161891SSam Leffler * resume. 6876d161891SSam Leffler */ 6886d161891SSam Leffler static int 6896d161891SSam Leffler hifn_suspend(device_t dev) 6906d161891SSam Leffler { 6916d161891SSam Leffler struct hifn_softc *sc = device_get_softc(dev); 6926d161891SSam Leffler #ifdef notyet 6936d161891SSam Leffler hifn_stop(sc); 6946d161891SSam Leffler #endif 6956d161891SSam Leffler sc->sc_suspended = 1; 6966d161891SSam Leffler 6976d161891SSam Leffler return (0); 6986d161891SSam Leffler } 6996d161891SSam Leffler 7006d161891SSam Leffler /* 7016d161891SSam Leffler * Device resume routine. Restore some PCI settings in case the BIOS 7026d161891SSam Leffler * doesn't, re-enable busmastering, and restart the interface if 7036d161891SSam Leffler * appropriate. 7046d161891SSam Leffler */ 7056d161891SSam Leffler static int 7066d161891SSam Leffler hifn_resume(device_t dev) 7076d161891SSam Leffler { 7086d161891SSam Leffler struct hifn_softc *sc = device_get_softc(dev); 7096d161891SSam Leffler #ifdef notyet 7106d161891SSam Leffler /* reinitialize interface if necessary */ 7116d161891SSam Leffler if (ifp->if_flags & IFF_UP) 7126d161891SSam Leffler rl_init(sc); 7136d161891SSam Leffler #endif 7146d161891SSam Leffler sc->sc_suspended = 0; 7156d161891SSam Leffler 7166d161891SSam Leffler return (0); 7176d161891SSam Leffler } 7186d161891SSam Leffler 7196d161891SSam Leffler static int 7206d161891SSam Leffler hifn_init_pubrng(struct hifn_softc *sc) 7216d161891SSam Leffler { 7226d161891SSam Leffler u_int32_t r; 7236d161891SSam Leffler int i; 7246d161891SSam Leffler 725b7c4858fSSam Leffler #ifdef HIFN_RNDTEST 726b7c4858fSSam Leffler sc->sc_rndtest = rndtest_attach(sc->sc_dev); 727b7c4858fSSam Leffler if (sc->sc_rndtest) 728b7c4858fSSam Leffler sc->sc_harvest = rndtest_harvest; 729b7c4858fSSam Leffler else 730b7c4858fSSam Leffler sc->sc_harvest = default_harvest; 731b7c4858fSSam Leffler #else 732b7c4858fSSam Leffler sc->sc_harvest = default_harvest; 733b7c4858fSSam Leffler #endif 7346d161891SSam Leffler if ((sc->sc_flags & HIFN_IS_7811) == 0) { 7356d161891SSam Leffler /* Reset 7951 public key/rng engine */ 7366d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_PUB_RESET, 7376d161891SSam Leffler READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 7386d161891SSam Leffler 7396d161891SSam Leffler for (i = 0; i < 100; i++) { 7406d161891SSam Leffler DELAY(1000); 7416d161891SSam Leffler if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 7426d161891SSam Leffler HIFN_PUBRST_RESET) == 0) 7436d161891SSam Leffler break; 7446d161891SSam Leffler } 7456d161891SSam Leffler 7466d161891SSam Leffler if (i == 100) { 7476d161891SSam Leffler device_printf(sc->sc_dev, "public key init failed\n"); 7486d161891SSam Leffler return (1); 7496d161891SSam Leffler } 7506d161891SSam Leffler } 7516d161891SSam Leffler 7526d161891SSam Leffler /* Enable the rng, if available */ 7536d161891SSam Leffler if (sc->sc_flags & HIFN_HAS_RNG) { 7546d161891SSam Leffler if (sc->sc_flags & HIFN_IS_7811) { 7556d161891SSam Leffler r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 7566d161891SSam Leffler if (r & HIFN_7811_RNGENA_ENA) { 7576d161891SSam Leffler r &= ~HIFN_7811_RNGENA_ENA; 7586d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 7596d161891SSam Leffler } 7606d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 7616d161891SSam Leffler HIFN_7811_RNGCFG_DEFL); 7626d161891SSam Leffler r |= HIFN_7811_RNGENA_ENA; 7636d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 7646d161891SSam Leffler } else 7656d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 7666d161891SSam Leffler READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 7676d161891SSam Leffler HIFN_RNGCFG_ENA); 7686d161891SSam Leffler 7696d161891SSam Leffler sc->sc_rngfirst = 1; 7706d161891SSam Leffler if (hz >= 100) 7716d161891SSam Leffler sc->sc_rnghz = hz / 100; 7726d161891SSam Leffler else 7736d161891SSam Leffler sc->sc_rnghz = 1; 774c06eb4e2SSam Leffler callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 7756d161891SSam Leffler callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 7766d161891SSam Leffler } 7776d161891SSam Leffler 7786d161891SSam Leffler /* Enable public key engine, if available */ 7796d161891SSam Leffler if (sc->sc_flags & HIFN_HAS_PUBLIC) { 7806d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 7816d161891SSam Leffler sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 7826d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 7836810ad6fSSam Leffler #ifdef HIFN_VULCANDEV 7846810ad6fSSam Leffler sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, 7856810ad6fSSam Leffler UID_ROOT, GID_WHEEL, 0666, 7866810ad6fSSam Leffler "vulcanpk"); 7876810ad6fSSam Leffler sc->sc_pkdev->si_drv1 = sc; 7886810ad6fSSam Leffler #endif 7896d161891SSam Leffler } 7906d161891SSam Leffler 7916d161891SSam Leffler return (0); 7926d161891SSam Leffler } 7936d161891SSam Leffler 7946d161891SSam Leffler static void 7956d161891SSam Leffler hifn_rng(void *vsc) 7966d161891SSam Leffler { 7976d161891SSam Leffler #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 7986d161891SSam Leffler struct hifn_softc *sc = vsc; 7996d161891SSam Leffler u_int32_t sts, num[2]; 8006d161891SSam Leffler int i; 8016d161891SSam Leffler 8026d161891SSam Leffler if (sc->sc_flags & HIFN_IS_7811) { 8036810ad6fSSam Leffler /* ONLY VALID ON 7811!!!! */ 8046d161891SSam Leffler for (i = 0; i < 5; i++) { 8056d161891SSam Leffler sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 8066d161891SSam Leffler if (sts & HIFN_7811_RNGSTS_UFL) { 8076d161891SSam Leffler device_printf(sc->sc_dev, 8086d161891SSam Leffler "RNG underflow: disabling\n"); 8096d161891SSam Leffler return; 8106d161891SSam Leffler } 8116d161891SSam Leffler if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 8126d161891SSam Leffler break; 8136d161891SSam Leffler 8146d161891SSam Leffler /* 8156d161891SSam Leffler * There are at least two words in the RNG FIFO 8166d161891SSam Leffler * at this point. 8176d161891SSam Leffler */ 8186d161891SSam Leffler num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 8196d161891SSam Leffler num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 8206d161891SSam Leffler /* NB: discard first data read */ 8216d161891SSam Leffler if (sc->sc_rngfirst) 8226d161891SSam Leffler sc->sc_rngfirst = 0; 8236d161891SSam Leffler else 824b7c4858fSSam Leffler (*sc->sc_harvest)(sc->sc_rndtest, 825b7c4858fSSam Leffler num, sizeof (num)); 8266d161891SSam Leffler } 8276d161891SSam Leffler } else { 8286d161891SSam Leffler num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 8296d161891SSam Leffler 8306d161891SSam Leffler /* NB: discard first data read */ 8316d161891SSam Leffler if (sc->sc_rngfirst) 8326d161891SSam Leffler sc->sc_rngfirst = 0; 8336d161891SSam Leffler else 834b7c4858fSSam Leffler (*sc->sc_harvest)(sc->sc_rndtest, 835b7c4858fSSam Leffler num, sizeof (num[0])); 8366d161891SSam Leffler } 8376d161891SSam Leffler 8386d161891SSam Leffler callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 8396d161891SSam Leffler #undef RANDOM_BITS 8406d161891SSam Leffler } 8416d161891SSam Leffler 8426d161891SSam Leffler static void 8436d161891SSam Leffler hifn_puc_wait(struct hifn_softc *sc) 8446d161891SSam Leffler { 8456d161891SSam Leffler int i; 8466810ad6fSSam Leffler int reg = HIFN_0_PUCTRL; 8476810ad6fSSam Leffler 8486810ad6fSSam Leffler if (sc->sc_flags & HIFN_IS_7956) { 8496810ad6fSSam Leffler reg = HIFN_0_PUCTRL2; 8506810ad6fSSam Leffler } 8516d161891SSam Leffler 8526d161891SSam Leffler for (i = 5000; i > 0; i--) { 8536d161891SSam Leffler DELAY(1); 8546810ad6fSSam Leffler if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) 8556d161891SSam Leffler break; 8566d161891SSam Leffler } 8576d161891SSam Leffler if (!i) 8586d161891SSam Leffler device_printf(sc->sc_dev, "proc unit did not reset\n"); 8596d161891SSam Leffler } 8606d161891SSam Leffler 8616d161891SSam Leffler /* 8626d161891SSam Leffler * Reset the processing unit. 8636d161891SSam Leffler */ 8646d161891SSam Leffler static void 8656d161891SSam Leffler hifn_reset_puc(struct hifn_softc *sc) 8666d161891SSam Leffler { 8676d161891SSam Leffler /* Reset processing unit */ 8686810ad6fSSam Leffler int reg = HIFN_0_PUCTRL; 8696810ad6fSSam Leffler 8706810ad6fSSam Leffler if (sc->sc_flags & HIFN_IS_7956) { 8716810ad6fSSam Leffler reg = HIFN_0_PUCTRL2; 8726810ad6fSSam Leffler } 8736810ad6fSSam Leffler WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); 8746810ad6fSSam Leffler 8756d161891SSam Leffler hifn_puc_wait(sc); 8766d161891SSam Leffler } 8776d161891SSam Leffler 8786d161891SSam Leffler /* 8796d161891SSam Leffler * Set the Retry and TRDY registers; note that we set them to 8806d161891SSam Leffler * zero because the 7811 locks up when forced to retry (section 8816d161891SSam Leffler * 3.6 of "Specification Update SU-0014-04". Not clear if we 8826d161891SSam Leffler * should do this for all Hifn parts, but it doesn't seem to hurt. 8836d161891SSam Leffler */ 8846d161891SSam Leffler static void 8856d161891SSam Leffler hifn_set_retry(struct hifn_softc *sc) 8866d161891SSam Leffler { 8876d161891SSam Leffler /* NB: RETRY only responds to 8-bit reads/writes */ 8886d161891SSam Leffler pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 889*8dca9d33STijl Coosemans pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1); 8906d161891SSam Leffler } 8916d161891SSam Leffler 8926d161891SSam Leffler /* 8936d161891SSam Leffler * Resets the board. Values in the regesters are left as is 8946d161891SSam Leffler * from the reset (i.e. initial values are assigned elsewhere). 8956d161891SSam Leffler */ 8966d161891SSam Leffler static void 8976d161891SSam Leffler hifn_reset_board(struct hifn_softc *sc, int full) 8986d161891SSam Leffler { 8996d161891SSam Leffler u_int32_t reg; 9006d161891SSam Leffler 9016d161891SSam Leffler /* 9026d161891SSam Leffler * Set polling in the DMA configuration register to zero. 0x7 avoids 9036d161891SSam Leffler * resetting the board and zeros out the other fields. 9046d161891SSam Leffler */ 9056d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 9066d161891SSam Leffler HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 9076d161891SSam Leffler 9086d161891SSam Leffler /* 9096d161891SSam Leffler * Now that polling has been disabled, we have to wait 1 ms 9106d161891SSam Leffler * before resetting the board. 9116d161891SSam Leffler */ 9126d161891SSam Leffler DELAY(1000); 9136d161891SSam Leffler 9146d161891SSam Leffler /* Reset the DMA unit */ 9156d161891SSam Leffler if (full) { 9166d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 9176d161891SSam Leffler DELAY(1000); 9186d161891SSam Leffler } else { 9196d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 9206d161891SSam Leffler HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 9216d161891SSam Leffler hifn_reset_puc(sc); 9226d161891SSam Leffler } 9236d161891SSam Leffler 9246d161891SSam Leffler KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 9256d161891SSam Leffler bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 9266d161891SSam Leffler 9276d161891SSam Leffler /* Bring dma unit out of reset */ 9286d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 9296d161891SSam Leffler HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 9306d161891SSam Leffler 9316d161891SSam Leffler hifn_puc_wait(sc); 9326d161891SSam Leffler hifn_set_retry(sc); 9336d161891SSam Leffler 9346d161891SSam Leffler if (sc->sc_flags & HIFN_IS_7811) { 9356d161891SSam Leffler for (reg = 0; reg < 1000; reg++) { 9366d161891SSam Leffler if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 9376d161891SSam Leffler HIFN_MIPSRST_CRAMINIT) 9386d161891SSam Leffler break; 9396d161891SSam Leffler DELAY(1000); 9406d161891SSam Leffler } 9416d161891SSam Leffler if (reg == 1000) 9426d161891SSam Leffler printf(": cram init timeout\n"); 9436810ad6fSSam Leffler } else { 9446810ad6fSSam Leffler /* set up DMA configuration register #2 */ 9456810ad6fSSam Leffler /* turn off all PK and BAR0 swaps */ 9466810ad6fSSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, 9476810ad6fSSam Leffler (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| 9486810ad6fSSam Leffler (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| 9496810ad6fSSam Leffler (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| 9506810ad6fSSam Leffler (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); 9516d161891SSam Leffler } 9526810ad6fSSam Leffler 9536d161891SSam Leffler } 9546d161891SSam Leffler 9556d161891SSam Leffler static u_int32_t 9566d161891SSam Leffler hifn_next_signature(u_int32_t a, u_int cnt) 9576d161891SSam Leffler { 9586d161891SSam Leffler int i; 9596d161891SSam Leffler u_int32_t v; 9606d161891SSam Leffler 9616d161891SSam Leffler for (i = 0; i < cnt; i++) { 9626d161891SSam Leffler 9636d161891SSam Leffler /* get the parity */ 9646d161891SSam Leffler v = a & 0x80080125; 9656d161891SSam Leffler v ^= v >> 16; 9666d161891SSam Leffler v ^= v >> 8; 9676d161891SSam Leffler v ^= v >> 4; 9686d161891SSam Leffler v ^= v >> 2; 9696d161891SSam Leffler v ^= v >> 1; 9706d161891SSam Leffler 9716d161891SSam Leffler a = (v & 1) ^ (a << 1); 9726d161891SSam Leffler } 9736d161891SSam Leffler 9746d161891SSam Leffler return a; 9756d161891SSam Leffler } 9766d161891SSam Leffler 9776d161891SSam Leffler struct pci2id { 9786d161891SSam Leffler u_short pci_vendor; 9796d161891SSam Leffler u_short pci_prod; 9806d161891SSam Leffler char card_id[13]; 9816d161891SSam Leffler }; 9826d161891SSam Leffler static struct pci2id pci2id[] = { 9836d161891SSam Leffler { 9846d161891SSam Leffler PCI_VENDOR_HIFN, 9856d161891SSam Leffler PCI_PRODUCT_HIFN_7951, 9866d161891SSam Leffler { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 9876d161891SSam Leffler 0x00, 0x00, 0x00, 0x00, 0x00 } 9886d161891SSam Leffler }, { 98917b66701SSam Leffler PCI_VENDOR_HIFN, 99017b66701SSam Leffler PCI_PRODUCT_HIFN_7955, 99117b66701SSam Leffler { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 99217b66701SSam Leffler 0x00, 0x00, 0x00, 0x00, 0x00 } 99317b66701SSam Leffler }, { 99417b66701SSam Leffler PCI_VENDOR_HIFN, 99517b66701SSam Leffler PCI_PRODUCT_HIFN_7956, 99617b66701SSam Leffler { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 99717b66701SSam Leffler 0x00, 0x00, 0x00, 0x00, 0x00 } 99817b66701SSam Leffler }, { 9996d161891SSam Leffler PCI_VENDOR_NETSEC, 10006d161891SSam Leffler PCI_PRODUCT_NETSEC_7751, 10016d161891SSam Leffler { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 10026d161891SSam Leffler 0x00, 0x00, 0x00, 0x00, 0x00 } 10036d161891SSam Leffler }, { 10046d161891SSam Leffler PCI_VENDOR_INVERTEX, 10056d161891SSam Leffler PCI_PRODUCT_INVERTEX_AEON, 10066d161891SSam Leffler { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 10076d161891SSam Leffler 0x00, 0x00, 0x00, 0x00, 0x00 } 10086d161891SSam Leffler }, { 10096d161891SSam Leffler PCI_VENDOR_HIFN, 10106d161891SSam Leffler PCI_PRODUCT_HIFN_7811, 10116d161891SSam Leffler { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 10126d161891SSam Leffler 0x00, 0x00, 0x00, 0x00, 0x00 } 10136d161891SSam Leffler }, { 10146d161891SSam Leffler /* 10156d161891SSam Leffler * Other vendors share this PCI ID as well, such as 10166d161891SSam Leffler * http://www.powercrypt.com, and obviously they also 10176d161891SSam Leffler * use the same key. 10186d161891SSam Leffler */ 10196d161891SSam Leffler PCI_VENDOR_HIFN, 10206d161891SSam Leffler PCI_PRODUCT_HIFN_7751, 10216d161891SSam Leffler { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 10226d161891SSam Leffler 0x00, 0x00, 0x00, 0x00, 0x00 } 10236d161891SSam Leffler }, 10246d161891SSam Leffler }; 10256d161891SSam Leffler 10266d161891SSam Leffler /* 10276d161891SSam Leffler * Checks to see if crypto is already enabled. If crypto isn't enable, 10286d161891SSam Leffler * "hifn_enable_crypto" is called to enable it. The check is important, 10296d161891SSam Leffler * as enabling crypto twice will lock the board. 10306d161891SSam Leffler */ 10316d161891SSam Leffler static int 10326d161891SSam Leffler hifn_enable_crypto(struct hifn_softc *sc) 10336d161891SSam Leffler { 10346d161891SSam Leffler u_int32_t dmacfg, ramcfg, encl, addr, i; 10356d161891SSam Leffler char *offtbl = NULL; 10366d161891SSam Leffler 10376d161891SSam Leffler for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 10386d161891SSam Leffler if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 10396d161891SSam Leffler pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 10406d161891SSam Leffler offtbl = pci2id[i].card_id; 10416d161891SSam Leffler break; 10426d161891SSam Leffler } 10436d161891SSam Leffler } 10446d161891SSam Leffler if (offtbl == NULL) { 10456d161891SSam Leffler device_printf(sc->sc_dev, "Unknown card!\n"); 10466d161891SSam Leffler return (1); 10476d161891SSam Leffler } 10486d161891SSam Leffler 10496d161891SSam Leffler ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 10506d161891SSam Leffler dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 10516d161891SSam Leffler 10526d161891SSam Leffler /* 10536d161891SSam Leffler * The RAM config register's encrypt level bit needs to be set before 10546d161891SSam Leffler * every read performed on the encryption level register. 10556d161891SSam Leffler */ 10566d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 10576d161891SSam Leffler 10586d161891SSam Leffler encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 10596d161891SSam Leffler 10606d161891SSam Leffler /* 10616d161891SSam Leffler * Make sure we don't re-unlock. Two unlocks kills chip until the 10626d161891SSam Leffler * next reboot. 10636d161891SSam Leffler */ 10646d161891SSam Leffler if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 10656d161891SSam Leffler #ifdef HIFN_DEBUG 10666d161891SSam Leffler if (hifn_debug) 10676d161891SSam Leffler device_printf(sc->sc_dev, 10686d161891SSam Leffler "Strong crypto already enabled!\n"); 10696d161891SSam Leffler #endif 10706d161891SSam Leffler goto report; 10716d161891SSam Leffler } 10726d161891SSam Leffler 10736d161891SSam Leffler if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 10746d161891SSam Leffler #ifdef HIFN_DEBUG 10756d161891SSam Leffler if (hifn_debug) 10766d161891SSam Leffler device_printf(sc->sc_dev, 10776d161891SSam Leffler "Unknown encryption level 0x%x\n", encl); 10786d161891SSam Leffler #endif 10796d161891SSam Leffler return 1; 10806d161891SSam Leffler } 10816d161891SSam Leffler 10826d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 10836d161891SSam Leffler HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 10846d161891SSam Leffler DELAY(1000); 10856d161891SSam Leffler addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 10866d161891SSam Leffler DELAY(1000); 10876d161891SSam Leffler WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 10886d161891SSam Leffler DELAY(1000); 10896d161891SSam Leffler 10906d161891SSam Leffler for (i = 0; i <= 12; i++) { 10916d161891SSam Leffler addr = hifn_next_signature(addr, offtbl[i] + 0x101); 10926d161891SSam Leffler WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 10936d161891SSam Leffler 10946d161891SSam Leffler DELAY(1000); 10956d161891SSam Leffler } 10966d161891SSam Leffler 10976d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 10986d161891SSam Leffler encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 10996d161891SSam Leffler 11006d161891SSam Leffler #ifdef HIFN_DEBUG 11016d161891SSam Leffler if (hifn_debug) { 11026d161891SSam Leffler if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 11036d161891SSam Leffler device_printf(sc->sc_dev, "Engine is permanently " 11046d161891SSam Leffler "locked until next system reset!\n"); 11056d161891SSam Leffler else 11066d161891SSam Leffler device_printf(sc->sc_dev, "Engine enabled " 11076d161891SSam Leffler "successfully!\n"); 11086d161891SSam Leffler } 11096d161891SSam Leffler #endif 11106d161891SSam Leffler 11116d161891SSam Leffler report: 11126d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 11136d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 11146d161891SSam Leffler 11156d161891SSam Leffler switch (encl) { 11166d161891SSam Leffler case HIFN_PUSTAT_ENA_1: 11176d161891SSam Leffler case HIFN_PUSTAT_ENA_2: 11186d161891SSam Leffler break; 11196d161891SSam Leffler case HIFN_PUSTAT_ENA_0: 11206d161891SSam Leffler default: 11216d161891SSam Leffler device_printf(sc->sc_dev, "disabled"); 11226d161891SSam Leffler break; 11236d161891SSam Leffler } 11246d161891SSam Leffler 11256d161891SSam Leffler return 0; 11266d161891SSam Leffler } 11276d161891SSam Leffler 11286d161891SSam Leffler /* 11296d161891SSam Leffler * Give initial values to the registers listed in the "Register Space" 11306d161891SSam Leffler * section of the HIFN Software Development reference manual. 11316d161891SSam Leffler */ 11326d161891SSam Leffler static void 11336d161891SSam Leffler hifn_init_pci_registers(struct hifn_softc *sc) 11346d161891SSam Leffler { 11356d161891SSam Leffler /* write fixed values needed by the Initialization registers */ 11366d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 11376d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 11386d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 11396d161891SSam Leffler 11406d161891SSam Leffler /* write all 4 ring address registers */ 11416d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 11426d161891SSam Leffler offsetof(struct hifn_dma, cmdr[0])); 11436d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 11446d161891SSam Leffler offsetof(struct hifn_dma, srcr[0])); 11456d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 11466d161891SSam Leffler offsetof(struct hifn_dma, dstr[0])); 11476d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 11486d161891SSam Leffler offsetof(struct hifn_dma, resr[0])); 11496d161891SSam Leffler 11506d161891SSam Leffler DELAY(2000); 11516d161891SSam Leffler 11526d161891SSam Leffler /* write status register */ 11536d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, 11546d161891SSam Leffler HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 11556d161891SSam Leffler HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 11566d161891SSam Leffler HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 11576d161891SSam Leffler HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 11586d161891SSam Leffler HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 11596d161891SSam Leffler HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 11606d161891SSam Leffler HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 11616d161891SSam Leffler HIFN_DMACSR_S_WAIT | 11626d161891SSam Leffler HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 11636d161891SSam Leffler HIFN_DMACSR_C_WAIT | 11646d161891SSam Leffler HIFN_DMACSR_ENGINE | 11656d161891SSam Leffler ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 11666d161891SSam Leffler HIFN_DMACSR_PUBDONE : 0) | 11676d161891SSam Leffler ((sc->sc_flags & HIFN_IS_7811) ? 11686d161891SSam Leffler HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 11696d161891SSam Leffler 11706d161891SSam Leffler sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 11716d161891SSam Leffler sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 11726d161891SSam Leffler HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 11736d161891SSam Leffler HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 11746d161891SSam Leffler ((sc->sc_flags & HIFN_IS_7811) ? 11756d161891SSam Leffler HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 11766d161891SSam Leffler sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 11776d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 11786d161891SSam Leffler 117917b66701SSam Leffler 118017b66701SSam Leffler if (sc->sc_flags & HIFN_IS_7956) { 1181aa959e0dSSam Leffler u_int32_t pll; 1182aa959e0dSSam Leffler 118317b66701SSam Leffler WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 118417b66701SSam Leffler HIFN_PUCNFG_TCALLPHASES | 118517b66701SSam Leffler HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1186aa959e0dSSam Leffler 1187aa959e0dSSam Leffler /* turn off the clocks and insure bypass is set */ 1188aa959e0dSSam Leffler pll = READ_REG_1(sc, HIFN_1_PLL); 1189aa959e0dSSam Leffler pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) 11906810ad6fSSam Leffler | HIFN_PLL_BP | HIFN_PLL_MBSET; 1191aa959e0dSSam Leffler WRITE_REG_1(sc, HIFN_1_PLL, pll); 1192aa959e0dSSam Leffler DELAY(10*1000); /* 10ms */ 11936810ad6fSSam Leffler 1194aa959e0dSSam Leffler /* change configuration */ 1195aa959e0dSSam Leffler pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; 1196aa959e0dSSam Leffler WRITE_REG_1(sc, HIFN_1_PLL, pll); 1197aa959e0dSSam Leffler DELAY(10*1000); /* 10ms */ 11986810ad6fSSam Leffler 1199aa959e0dSSam Leffler /* disable bypass */ 1200aa959e0dSSam Leffler pll &= ~HIFN_PLL_BP; 1201aa959e0dSSam Leffler WRITE_REG_1(sc, HIFN_1_PLL, pll); 1202aa959e0dSSam Leffler /* enable clocks with new configuration */ 1203aa959e0dSSam Leffler pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; 1204aa959e0dSSam Leffler WRITE_REG_1(sc, HIFN_1_PLL, pll); 120517b66701SSam Leffler } else { 12066d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 12076d161891SSam Leffler HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 12086d161891SSam Leffler HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 12096d161891SSam Leffler (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 121017b66701SSam Leffler } 12116d161891SSam Leffler 12126d161891SSam Leffler WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 12136d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 12146d161891SSam Leffler HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 12156d161891SSam Leffler ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 12166d161891SSam Leffler ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 12176d161891SSam Leffler } 12186d161891SSam Leffler 12196d161891SSam Leffler /* 12206d161891SSam Leffler * The maximum number of sessions supported by the card 12216d161891SSam Leffler * is dependent on the amount of context ram, which 12226d161891SSam Leffler * encryption algorithms are enabled, and how compression 12236d161891SSam Leffler * is configured. This should be configured before this 12246d161891SSam Leffler * routine is called. 12256d161891SSam Leffler */ 12266d161891SSam Leffler static void 12276d161891SSam Leffler hifn_sessions(struct hifn_softc *sc) 12286d161891SSam Leffler { 12296d161891SSam Leffler u_int32_t pucnfg; 12306d161891SSam Leffler int ctxsize; 12316d161891SSam Leffler 12326d161891SSam Leffler pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 12336d161891SSam Leffler 12346d161891SSam Leffler if (pucnfg & HIFN_PUCNFG_COMPSING) { 12356d161891SSam Leffler if (pucnfg & HIFN_PUCNFG_ENCCNFG) 12366d161891SSam Leffler ctxsize = 128; 12376d161891SSam Leffler else 12386d161891SSam Leffler ctxsize = 512; 123917b66701SSam Leffler /* 124017b66701SSam Leffler * 7955/7956 has internal context memory of 32K 124117b66701SSam Leffler */ 124217b66701SSam Leffler if (sc->sc_flags & HIFN_IS_7956) 124317b66701SSam Leffler sc->sc_maxses = 32768 / ctxsize; 124417b66701SSam Leffler else 12456d161891SSam Leffler sc->sc_maxses = 1 + 12466d161891SSam Leffler ((sc->sc_ramsize - 32768) / ctxsize); 12476d161891SSam Leffler } else 12486d161891SSam Leffler sc->sc_maxses = sc->sc_ramsize / 16384; 12496d161891SSam Leffler 12506d161891SSam Leffler if (sc->sc_maxses > 2048) 12516d161891SSam Leffler sc->sc_maxses = 2048; 12526d161891SSam Leffler } 12536d161891SSam Leffler 12546d161891SSam Leffler /* 12556d161891SSam Leffler * Determine ram type (sram or dram). Board should be just out of a reset 12566d161891SSam Leffler * state when this is called. 12576d161891SSam Leffler */ 12586d161891SSam Leffler static int 12596d161891SSam Leffler hifn_ramtype(struct hifn_softc *sc) 12606d161891SSam Leffler { 12616d161891SSam Leffler u_int8_t data[8], dataexpect[8]; 12626d161891SSam Leffler int i; 12636d161891SSam Leffler 12646d161891SSam Leffler for (i = 0; i < sizeof(data); i++) 12656d161891SSam Leffler data[i] = dataexpect[i] = 0x55; 12666d161891SSam Leffler if (hifn_writeramaddr(sc, 0, data)) 12676d161891SSam Leffler return (-1); 12686d161891SSam Leffler if (hifn_readramaddr(sc, 0, data)) 12696d161891SSam Leffler return (-1); 12706d161891SSam Leffler if (bcmp(data, dataexpect, sizeof(data)) != 0) { 12716d161891SSam Leffler sc->sc_drammodel = 1; 12726d161891SSam Leffler return (0); 12736d161891SSam Leffler } 12746d161891SSam Leffler 12756d161891SSam Leffler for (i = 0; i < sizeof(data); i++) 12766d161891SSam Leffler data[i] = dataexpect[i] = 0xaa; 12776d161891SSam Leffler if (hifn_writeramaddr(sc, 0, data)) 12786d161891SSam Leffler return (-1); 12796d161891SSam Leffler if (hifn_readramaddr(sc, 0, data)) 12806d161891SSam Leffler return (-1); 12816d161891SSam Leffler if (bcmp(data, dataexpect, sizeof(data)) != 0) { 12826d161891SSam Leffler sc->sc_drammodel = 1; 12836d161891SSam Leffler return (0); 12846d161891SSam Leffler } 12856d161891SSam Leffler 12866d161891SSam Leffler return (0); 12876d161891SSam Leffler } 12886d161891SSam Leffler 12896d161891SSam Leffler #define HIFN_SRAM_MAX (32 << 20) 12906d161891SSam Leffler #define HIFN_SRAM_STEP_SIZE 16384 12916d161891SSam Leffler #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 12926d161891SSam Leffler 12936d161891SSam Leffler static int 12946d161891SSam Leffler hifn_sramsize(struct hifn_softc *sc) 12956d161891SSam Leffler { 12966d161891SSam Leffler u_int32_t a; 12976d161891SSam Leffler u_int8_t data[8]; 12986d161891SSam Leffler u_int8_t dataexpect[sizeof(data)]; 12996d161891SSam Leffler int32_t i; 13006d161891SSam Leffler 13016d161891SSam Leffler for (i = 0; i < sizeof(data); i++) 13026d161891SSam Leffler data[i] = dataexpect[i] = i ^ 0x5a; 13036d161891SSam Leffler 13046d161891SSam Leffler for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 13056d161891SSam Leffler a = i * HIFN_SRAM_STEP_SIZE; 13066d161891SSam Leffler bcopy(&i, data, sizeof(i)); 13076d161891SSam Leffler hifn_writeramaddr(sc, a, data); 13086d161891SSam Leffler } 13096d161891SSam Leffler 13106d161891SSam Leffler for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 13116d161891SSam Leffler a = i * HIFN_SRAM_STEP_SIZE; 13126d161891SSam Leffler bcopy(&i, dataexpect, sizeof(i)); 13136d161891SSam Leffler if (hifn_readramaddr(sc, a, data) < 0) 13146d161891SSam Leffler return (0); 13156d161891SSam Leffler if (bcmp(data, dataexpect, sizeof(data)) != 0) 13166d161891SSam Leffler return (0); 13176d161891SSam Leffler sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 13186d161891SSam Leffler } 13196d161891SSam Leffler 13206d161891SSam Leffler return (0); 13216d161891SSam Leffler } 13226d161891SSam Leffler 13236d161891SSam Leffler /* 13246d161891SSam Leffler * XXX For dram boards, one should really try all of the 13256d161891SSam Leffler * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 13266d161891SSam Leffler * is already set up correctly. 13276d161891SSam Leffler */ 13286d161891SSam Leffler static int 13296d161891SSam Leffler hifn_dramsize(struct hifn_softc *sc) 13306d161891SSam Leffler { 13316d161891SSam Leffler u_int32_t cnfg; 13326d161891SSam Leffler 133317b66701SSam Leffler if (sc->sc_flags & HIFN_IS_7956) { 133417b66701SSam Leffler /* 133517b66701SSam Leffler * 7955/7956 have a fixed internal ram of only 32K. 133617b66701SSam Leffler */ 133717b66701SSam Leffler sc->sc_ramsize = 32768; 133817b66701SSam Leffler } else { 13396d161891SSam Leffler cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 13406d161891SSam Leffler HIFN_PUCNFG_DRAMMASK; 13416d161891SSam Leffler sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 134217b66701SSam Leffler } 13436d161891SSam Leffler return (0); 13446d161891SSam Leffler } 13456d161891SSam Leffler 13466d161891SSam Leffler static void 13476d161891SSam Leffler hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 13486d161891SSam Leffler { 13496d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 13506d161891SSam Leffler 1351ea14ae7aSOleksandr Tymoshenko if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) { 1352ea14ae7aSOleksandr Tymoshenko sc->sc_cmdi = 0; 13536d161891SSam Leffler dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 13546d161891SSam Leffler HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 13556d161891SSam Leffler HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 13566d161891SSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 13576d161891SSam Leffler } 1358ea14ae7aSOleksandr Tymoshenko *cmdp = sc->sc_cmdi++; 1359ea14ae7aSOleksandr Tymoshenko sc->sc_cmdk = sc->sc_cmdi; 13606d161891SSam Leffler 1361ea14ae7aSOleksandr Tymoshenko if (sc->sc_srci == HIFN_D_SRC_RSIZE) { 1362ea14ae7aSOleksandr Tymoshenko sc->sc_srci = 0; 13636d161891SSam Leffler dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 13646d161891SSam Leffler HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 13656d161891SSam Leffler HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 13666d161891SSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 13676d161891SSam Leffler } 1368ea14ae7aSOleksandr Tymoshenko *srcp = sc->sc_srci++; 1369ea14ae7aSOleksandr Tymoshenko sc->sc_srck = sc->sc_srci; 13706d161891SSam Leffler 1371ea14ae7aSOleksandr Tymoshenko if (sc->sc_dsti == HIFN_D_DST_RSIZE) { 1372ea14ae7aSOleksandr Tymoshenko sc->sc_dsti = 0; 13736d161891SSam Leffler dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 13746d161891SSam Leffler HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 13756d161891SSam Leffler HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 13766d161891SSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 13776d161891SSam Leffler } 1378ea14ae7aSOleksandr Tymoshenko *dstp = sc->sc_dsti++; 1379ea14ae7aSOleksandr Tymoshenko sc->sc_dstk = sc->sc_dsti; 13806d161891SSam Leffler 1381ea14ae7aSOleksandr Tymoshenko if (sc->sc_resi == HIFN_D_RES_RSIZE) { 1382ea14ae7aSOleksandr Tymoshenko sc->sc_resi = 0; 13836d161891SSam Leffler dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 13846d161891SSam Leffler HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 13856d161891SSam Leffler HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 13866d161891SSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 13876d161891SSam Leffler } 1388ea14ae7aSOleksandr Tymoshenko *resp = sc->sc_resi++; 1389ea14ae7aSOleksandr Tymoshenko sc->sc_resk = sc->sc_resi; 13906d161891SSam Leffler } 13916d161891SSam Leffler 13926d161891SSam Leffler static int 13936d161891SSam Leffler hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 13946d161891SSam Leffler { 13956d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 13966d161891SSam Leffler hifn_base_command_t wc; 13976d161891SSam Leffler const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 13986d161891SSam Leffler int r, cmdi, resi, srci, dsti; 13996d161891SSam Leffler 14006d161891SSam Leffler wc.masks = htole16(3 << 13); 14016d161891SSam Leffler wc.session_num = htole16(addr >> 14); 14026d161891SSam Leffler wc.total_source_count = htole16(8); 14036d161891SSam Leffler wc.total_dest_count = htole16(addr & 0x3fff); 14046d161891SSam Leffler 14056d161891SSam Leffler hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 14066d161891SSam Leffler 14076d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, 14086d161891SSam Leffler HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 14096d161891SSam Leffler HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 14106d161891SSam Leffler 14116d161891SSam Leffler /* build write command */ 14126d161891SSam Leffler bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 14136d161891SSam Leffler *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 14146d161891SSam Leffler bcopy(data, &dma->test_src, sizeof(dma->test_src)); 14156d161891SSam Leffler 14166d161891SSam Leffler dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 14176d161891SSam Leffler + offsetof(struct hifn_dma, test_src)); 14186d161891SSam Leffler dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 14196d161891SSam Leffler + offsetof(struct hifn_dma, test_dst)); 14206d161891SSam Leffler 14216d161891SSam Leffler dma->cmdr[cmdi].l = htole32(16 | masks); 14226d161891SSam Leffler dma->srcr[srci].l = htole32(8 | masks); 14236d161891SSam Leffler dma->dstr[dsti].l = htole32(4 | masks); 14246d161891SSam Leffler dma->resr[resi].l = htole32(4 | masks); 14256d161891SSam Leffler 14266d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 14276d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 14286d161891SSam Leffler 14296d161891SSam Leffler for (r = 10000; r >= 0; r--) { 14306d161891SSam Leffler DELAY(10); 14316d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 14326d161891SSam Leffler BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 14336d161891SSam Leffler if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 14346d161891SSam Leffler break; 14356d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 14366d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 14376d161891SSam Leffler } 14386d161891SSam Leffler if (r == 0) { 14396d161891SSam Leffler device_printf(sc->sc_dev, "writeramaddr -- " 14406d161891SSam Leffler "result[%d](addr %d) still valid\n", resi, addr); 14416d161891SSam Leffler r = -1; 14426d161891SSam Leffler return (-1); 14436d161891SSam Leffler } else 14446d161891SSam Leffler r = 0; 14456d161891SSam Leffler 14466d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, 14476d161891SSam Leffler HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 14486d161891SSam Leffler HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 14496d161891SSam Leffler 14506d161891SSam Leffler return (r); 14516d161891SSam Leffler } 14526d161891SSam Leffler 14536d161891SSam Leffler static int 14546d161891SSam Leffler hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 14556d161891SSam Leffler { 14566d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 14576d161891SSam Leffler hifn_base_command_t rc; 14586d161891SSam Leffler const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 14596d161891SSam Leffler int r, cmdi, srci, dsti, resi; 14606d161891SSam Leffler 14616d161891SSam Leffler rc.masks = htole16(2 << 13); 14626d161891SSam Leffler rc.session_num = htole16(addr >> 14); 14636d161891SSam Leffler rc.total_source_count = htole16(addr & 0x3fff); 14646d161891SSam Leffler rc.total_dest_count = htole16(8); 14656d161891SSam Leffler 14666d161891SSam Leffler hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 14676d161891SSam Leffler 14686d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, 14696d161891SSam Leffler HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 14706d161891SSam Leffler HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 14716d161891SSam Leffler 14726d161891SSam Leffler bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 14736d161891SSam Leffler *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 14746d161891SSam Leffler 14756d161891SSam Leffler dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 14766d161891SSam Leffler offsetof(struct hifn_dma, test_src)); 14776d161891SSam Leffler dma->test_src = 0; 14786d161891SSam Leffler dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 14796d161891SSam Leffler offsetof(struct hifn_dma, test_dst)); 14806d161891SSam Leffler dma->test_dst = 0; 14816d161891SSam Leffler dma->cmdr[cmdi].l = htole32(8 | masks); 14826d161891SSam Leffler dma->srcr[srci].l = htole32(8 | masks); 14836d161891SSam Leffler dma->dstr[dsti].l = htole32(8 | masks); 14846d161891SSam Leffler dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 14856d161891SSam Leffler 14866d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 14876d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 14886d161891SSam Leffler 14896d161891SSam Leffler for (r = 10000; r >= 0; r--) { 14906d161891SSam Leffler DELAY(10); 14916d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 14926d161891SSam Leffler BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 14936d161891SSam Leffler if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 14946d161891SSam Leffler break; 14956d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 14966d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 14976d161891SSam Leffler } 14986d161891SSam Leffler if (r == 0) { 14996d161891SSam Leffler device_printf(sc->sc_dev, "readramaddr -- " 15006d161891SSam Leffler "result[%d](addr %d) still valid\n", resi, addr); 15016d161891SSam Leffler r = -1; 15026d161891SSam Leffler } else { 15036d161891SSam Leffler r = 0; 15046d161891SSam Leffler bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 15056d161891SSam Leffler } 15066d161891SSam Leffler 15076d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, 15086d161891SSam Leffler HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 15096d161891SSam Leffler HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 15106d161891SSam Leffler 15116d161891SSam Leffler return (r); 15126d161891SSam Leffler } 15136d161891SSam Leffler 15146d161891SSam Leffler /* 15156d161891SSam Leffler * Initialize the descriptor rings. 15166d161891SSam Leffler */ 15176d161891SSam Leffler static void 15186d161891SSam Leffler hifn_init_dma(struct hifn_softc *sc) 15196d161891SSam Leffler { 15206d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 15216d161891SSam Leffler int i; 15226d161891SSam Leffler 15236d161891SSam Leffler hifn_set_retry(sc); 15246d161891SSam Leffler 15256d161891SSam Leffler /* initialize static pointer values */ 15266d161891SSam Leffler for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 15276d161891SSam Leffler dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 15286d161891SSam Leffler offsetof(struct hifn_dma, command_bufs[i][0])); 15296d161891SSam Leffler for (i = 0; i < HIFN_D_RES_RSIZE; i++) 15306d161891SSam Leffler dma->resr[i].p = htole32(sc->sc_dma_physaddr + 15316d161891SSam Leffler offsetof(struct hifn_dma, result_bufs[i][0])); 15326d161891SSam Leffler 15336d161891SSam Leffler dma->cmdr[HIFN_D_CMD_RSIZE].p = 15346d161891SSam Leffler htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 15356d161891SSam Leffler dma->srcr[HIFN_D_SRC_RSIZE].p = 15366d161891SSam Leffler htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 15376d161891SSam Leffler dma->dstr[HIFN_D_DST_RSIZE].p = 15386d161891SSam Leffler htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 15396d161891SSam Leffler dma->resr[HIFN_D_RES_RSIZE].p = 15406d161891SSam Leffler htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 15416d161891SSam Leffler 1542ea14ae7aSOleksandr Tymoshenko sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0; 1543ea14ae7aSOleksandr Tymoshenko sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0; 1544ea14ae7aSOleksandr Tymoshenko sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0; 15456d161891SSam Leffler } 15466d161891SSam Leffler 15476d161891SSam Leffler /* 15486d161891SSam Leffler * Writes out the raw command buffer space. Returns the 15496d161891SSam Leffler * command buffer size. 15506d161891SSam Leffler */ 15516d161891SSam Leffler static u_int 15526d161891SSam Leffler hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 15536d161891SSam Leffler { 15546d161891SSam Leffler u_int8_t *buf_pos; 15556d161891SSam Leffler hifn_base_command_t *base_cmd; 15566d161891SSam Leffler hifn_mac_command_t *mac_cmd; 15576d161891SSam Leffler hifn_crypt_command_t *cry_cmd; 155817b66701SSam Leffler int using_mac, using_crypt, len, ivlen; 15596d161891SSam Leffler u_int32_t dlen, slen; 15606d161891SSam Leffler 15616d161891SSam Leffler buf_pos = buf; 15626d161891SSam Leffler using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 15636d161891SSam Leffler using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 15646d161891SSam Leffler 15656d161891SSam Leffler base_cmd = (hifn_base_command_t *)buf_pos; 15666d161891SSam Leffler base_cmd->masks = htole16(cmd->base_masks); 15676d161891SSam Leffler slen = cmd->src_mapsize; 15686d161891SSam Leffler if (cmd->sloplen) 15696d161891SSam Leffler dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 15706d161891SSam Leffler else 15716d161891SSam Leffler dlen = cmd->dst_mapsize; 15726d161891SSam Leffler base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 15736d161891SSam Leffler base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 15746d161891SSam Leffler dlen >>= 16; 15756d161891SSam Leffler slen >>= 16; 1576fe9b390bSSam Leffler base_cmd->session_num = htole16( 15776d161891SSam Leffler ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 15786d161891SSam Leffler ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 15796d161891SSam Leffler buf_pos += sizeof(hifn_base_command_t); 15806d161891SSam Leffler 15816d161891SSam Leffler if (using_mac) { 15826d161891SSam Leffler mac_cmd = (hifn_mac_command_t *)buf_pos; 15836d161891SSam Leffler dlen = cmd->maccrd->crd_len; 15846d161891SSam Leffler mac_cmd->source_count = htole16(dlen & 0xffff); 15856d161891SSam Leffler dlen >>= 16; 15866d161891SSam Leffler mac_cmd->masks = htole16(cmd->mac_masks | 15876d161891SSam Leffler ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 15886d161891SSam Leffler mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 15896d161891SSam Leffler mac_cmd->reserved = 0; 15906d161891SSam Leffler buf_pos += sizeof(hifn_mac_command_t); 15916d161891SSam Leffler } 15926d161891SSam Leffler 15936d161891SSam Leffler if (using_crypt) { 15946d161891SSam Leffler cry_cmd = (hifn_crypt_command_t *)buf_pos; 15956d161891SSam Leffler dlen = cmd->enccrd->crd_len; 15966d161891SSam Leffler cry_cmd->source_count = htole16(dlen & 0xffff); 15976d161891SSam Leffler dlen >>= 16; 15986d161891SSam Leffler cry_cmd->masks = htole16(cmd->cry_masks | 15996d161891SSam Leffler ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 16006d161891SSam Leffler cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 16016d161891SSam Leffler cry_cmd->reserved = 0; 16026d161891SSam Leffler buf_pos += sizeof(hifn_crypt_command_t); 16036d161891SSam Leffler } 16046d161891SSam Leffler 16056d161891SSam Leffler if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 16066d161891SSam Leffler bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 16076d161891SSam Leffler buf_pos += HIFN_MAC_KEY_LENGTH; 16086d161891SSam Leffler } 16096d161891SSam Leffler 16106d161891SSam Leffler if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 16116d161891SSam Leffler switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 16126d161891SSam Leffler case HIFN_CRYPT_CMD_ALG_3DES: 16136d161891SSam Leffler bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 16146d161891SSam Leffler buf_pos += HIFN_3DES_KEY_LENGTH; 16156d161891SSam Leffler break; 16166d161891SSam Leffler case HIFN_CRYPT_CMD_ALG_DES: 16176d161891SSam Leffler bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 161817b66701SSam Leffler buf_pos += HIFN_DES_KEY_LENGTH; 16196d161891SSam Leffler break; 16206d161891SSam Leffler case HIFN_CRYPT_CMD_ALG_RC4: 16216d161891SSam Leffler len = 256; 16226d161891SSam Leffler do { 16236d161891SSam Leffler int clen; 16246d161891SSam Leffler 16256d161891SSam Leffler clen = MIN(cmd->cklen, len); 16266d161891SSam Leffler bcopy(cmd->ck, buf_pos, clen); 16276d161891SSam Leffler len -= clen; 16286d161891SSam Leffler buf_pos += clen; 16296d161891SSam Leffler } while (len > 0); 16306d161891SSam Leffler bzero(buf_pos, 4); 16316d161891SSam Leffler buf_pos += 4; 16326d161891SSam Leffler break; 163317b66701SSam Leffler case HIFN_CRYPT_CMD_ALG_AES: 163417b66701SSam Leffler /* 163517b66701SSam Leffler * AES keys are variable 128, 192 and 163617b66701SSam Leffler * 256 bits (16, 24 and 32 bytes). 163717b66701SSam Leffler */ 163817b66701SSam Leffler bcopy(cmd->ck, buf_pos, cmd->cklen); 163917b66701SSam Leffler buf_pos += cmd->cklen; 164017b66701SSam Leffler break; 16416d161891SSam Leffler } 16426d161891SSam Leffler } 16436d161891SSam Leffler 16446d161891SSam Leffler if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 164517b66701SSam Leffler switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 164617b66701SSam Leffler case HIFN_CRYPT_CMD_ALG_AES: 164717b66701SSam Leffler ivlen = HIFN_AES_IV_LENGTH; 164817b66701SSam Leffler break; 164917b66701SSam Leffler default: 165017b66701SSam Leffler ivlen = HIFN_IV_LENGTH; 165117b66701SSam Leffler break; 165217b66701SSam Leffler } 165317b66701SSam Leffler bcopy(cmd->iv, buf_pos, ivlen); 165417b66701SSam Leffler buf_pos += ivlen; 16556d161891SSam Leffler } 16566d161891SSam Leffler 16576d161891SSam Leffler if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 16586d161891SSam Leffler bzero(buf_pos, 8); 16596d161891SSam Leffler buf_pos += 8; 16606d161891SSam Leffler } 16616d161891SSam Leffler 16626d161891SSam Leffler return (buf_pos - buf); 16636d161891SSam Leffler } 16646d161891SSam Leffler 16656d161891SSam Leffler static int 16666d161891SSam Leffler hifn_dmamap_aligned(struct hifn_operand *op) 16676d161891SSam Leffler { 16686d161891SSam Leffler int i; 16696d161891SSam Leffler 16706d161891SSam Leffler for (i = 0; i < op->nsegs; i++) { 16716d161891SSam Leffler if (op->segs[i].ds_addr & 3) 16726d161891SSam Leffler return (0); 16736d161891SSam Leffler if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 16746d161891SSam Leffler return (0); 16756d161891SSam Leffler } 16766d161891SSam Leffler return (1); 16776d161891SSam Leffler } 16786d161891SSam Leffler 16796810ad6fSSam Leffler static __inline int 16806810ad6fSSam Leffler hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) 16816810ad6fSSam Leffler { 16826810ad6fSSam Leffler struct hifn_dma *dma = sc->sc_dma; 16836810ad6fSSam Leffler 16846810ad6fSSam Leffler if (++idx == HIFN_D_DST_RSIZE) { 16856810ad6fSSam Leffler dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 16866810ad6fSSam Leffler HIFN_D_MASKDONEIRQ); 16876810ad6fSSam Leffler HIFN_DSTR_SYNC(sc, idx, 16886810ad6fSSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 16896810ad6fSSam Leffler idx = 0; 16906810ad6fSSam Leffler } 16916810ad6fSSam Leffler return (idx); 16926810ad6fSSam Leffler } 16936810ad6fSSam Leffler 16946d161891SSam Leffler static int 16956d161891SSam Leffler hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 16966d161891SSam Leffler { 16976d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 16986d161891SSam Leffler struct hifn_operand *dst = &cmd->dst; 16996d161891SSam Leffler u_int32_t p, l; 17006d161891SSam Leffler int idx, used = 0, i; 17016d161891SSam Leffler 1702ea14ae7aSOleksandr Tymoshenko idx = sc->sc_dsti; 17036d161891SSam Leffler for (i = 0; i < dst->nsegs - 1; i++) { 17046d161891SSam Leffler dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 17056d161891SSam Leffler dma->dstr[idx].l = htole32(HIFN_D_VALID | 17066d161891SSam Leffler HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 17076d161891SSam Leffler HIFN_DSTR_SYNC(sc, idx, 17086d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 17096d161891SSam Leffler used++; 17106d161891SSam Leffler 17116810ad6fSSam Leffler idx = hifn_dmamap_dstwrap(sc, idx); 17126d161891SSam Leffler } 17136d161891SSam Leffler 17146d161891SSam Leffler if (cmd->sloplen == 0) { 17156d161891SSam Leffler p = dst->segs[i].ds_addr; 17166d161891SSam Leffler l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 17176d161891SSam Leffler dst->segs[i].ds_len; 17186d161891SSam Leffler } else { 17196d161891SSam Leffler p = sc->sc_dma_physaddr + 17206d161891SSam Leffler offsetof(struct hifn_dma, slop[cmd->slopidx]); 17216d161891SSam Leffler l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 17226d161891SSam Leffler sizeof(u_int32_t); 17236d161891SSam Leffler 17246d161891SSam Leffler if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 17256d161891SSam Leffler dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 17266d161891SSam Leffler dma->dstr[idx].l = htole32(HIFN_D_VALID | 17276d161891SSam Leffler HIFN_D_MASKDONEIRQ | 17286d161891SSam Leffler (dst->segs[i].ds_len - cmd->sloplen)); 17296d161891SSam Leffler HIFN_DSTR_SYNC(sc, idx, 17306d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 17316d161891SSam Leffler used++; 17326d161891SSam Leffler 17336810ad6fSSam Leffler idx = hifn_dmamap_dstwrap(sc, idx); 17346d161891SSam Leffler } 17356d161891SSam Leffler } 17366d161891SSam Leffler dma->dstr[idx].p = htole32(p); 17376d161891SSam Leffler dma->dstr[idx].l = htole32(l); 17386d161891SSam Leffler HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 17396d161891SSam Leffler used++; 17406d161891SSam Leffler 17416810ad6fSSam Leffler idx = hifn_dmamap_dstwrap(sc, idx); 17426d161891SSam Leffler 1743ea14ae7aSOleksandr Tymoshenko sc->sc_dsti = idx; 1744ea14ae7aSOleksandr Tymoshenko sc->sc_dstu += used; 17456d161891SSam Leffler return (idx); 17466d161891SSam Leffler } 17476d161891SSam Leffler 17486810ad6fSSam Leffler static __inline int 17496810ad6fSSam Leffler hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) 17506810ad6fSSam Leffler { 17516810ad6fSSam Leffler struct hifn_dma *dma = sc->sc_dma; 17526810ad6fSSam Leffler 17536810ad6fSSam Leffler if (++idx == HIFN_D_SRC_RSIZE) { 17546810ad6fSSam Leffler dma->srcr[idx].l = htole32(HIFN_D_VALID | 17556810ad6fSSam Leffler HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 17566810ad6fSSam Leffler HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 17576810ad6fSSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 17586810ad6fSSam Leffler idx = 0; 17596810ad6fSSam Leffler } 17606810ad6fSSam Leffler return (idx); 17616810ad6fSSam Leffler } 17626810ad6fSSam Leffler 17636d161891SSam Leffler static int 17646d161891SSam Leffler hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 17656d161891SSam Leffler { 17666d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 17676d161891SSam Leffler struct hifn_operand *src = &cmd->src; 17686d161891SSam Leffler int idx, i; 17696d161891SSam Leffler u_int32_t last = 0; 17706d161891SSam Leffler 1771ea14ae7aSOleksandr Tymoshenko idx = sc->sc_srci; 17726d161891SSam Leffler for (i = 0; i < src->nsegs; i++) { 17736d161891SSam Leffler if (i == src->nsegs - 1) 17746d161891SSam Leffler last = HIFN_D_LAST; 17756d161891SSam Leffler 17766d161891SSam Leffler dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 17776d161891SSam Leffler dma->srcr[idx].l = htole32(src->segs[i].ds_len | 17786d161891SSam Leffler HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 17796d161891SSam Leffler HIFN_SRCR_SYNC(sc, idx, 17806d161891SSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 17816d161891SSam Leffler 17826810ad6fSSam Leffler idx = hifn_dmamap_srcwrap(sc, idx); 17836d161891SSam Leffler } 1784ea14ae7aSOleksandr Tymoshenko sc->sc_srci = idx; 1785ea14ae7aSOleksandr Tymoshenko sc->sc_srcu += src->nsegs; 17866d161891SSam Leffler return (idx); 17876d161891SSam Leffler } 17886d161891SSam Leffler 17896d161891SSam Leffler static void 17906d161891SSam Leffler hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 17916d161891SSam Leffler { 17926d161891SSam Leffler struct hifn_operand *op = arg; 17936d161891SSam Leffler 17946d161891SSam Leffler KASSERT(nsegs <= MAX_SCATTER, 17956d161891SSam Leffler ("hifn_op_cb: too many DMA segments (%u > %u) " 17966d161891SSam Leffler "returned when mapping operand", nsegs, MAX_SCATTER)); 17976d161891SSam Leffler op->mapsize = mapsize; 17986d161891SSam Leffler op->nsegs = nsegs; 17996d161891SSam Leffler bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 18006d161891SSam Leffler } 18016d161891SSam Leffler 18026d161891SSam Leffler static int 18036d161891SSam Leffler hifn_crypto( 18046d161891SSam Leffler struct hifn_softc *sc, 18056d161891SSam Leffler struct hifn_command *cmd, 18066d161891SSam Leffler struct cryptop *crp, 18076d161891SSam Leffler int hint) 18086d161891SSam Leffler { 18096d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 18106810ad6fSSam Leffler u_int32_t cmdlen, csr; 18116d161891SSam Leffler int cmdi, resi, err = 0; 18126d161891SSam Leffler 18136d161891SSam Leffler /* 18146d161891SSam Leffler * need 1 cmd, and 1 res 18156d161891SSam Leffler * 18166d161891SSam Leffler * NB: check this first since it's easy. 18176d161891SSam Leffler */ 18184f28f7d7SSam Leffler HIFN_LOCK(sc); 1819ea14ae7aSOleksandr Tymoshenko if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE || 1820ea14ae7aSOleksandr Tymoshenko (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) { 18216d161891SSam Leffler #ifdef HIFN_DEBUG 18226d161891SSam Leffler if (hifn_debug) { 18236d161891SSam Leffler device_printf(sc->sc_dev, 18246d161891SSam Leffler "cmd/result exhaustion, cmdu %u resu %u\n", 1825ea14ae7aSOleksandr Tymoshenko sc->sc_cmdu, sc->sc_resu); 18266d161891SSam Leffler } 18276d161891SSam Leffler #endif 18286d161891SSam Leffler hifnstats.hst_nomem_cr++; 18294f28f7d7SSam Leffler HIFN_UNLOCK(sc); 18306d161891SSam Leffler return (ERESTART); 18316d161891SSam Leffler } 18326d161891SSam Leffler 18336d161891SSam Leffler if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 18346d161891SSam Leffler hifnstats.hst_nomem_map++; 18354f28f7d7SSam Leffler HIFN_UNLOCK(sc); 18366d161891SSam Leffler return (ENOMEM); 18376d161891SSam Leffler } 18386d161891SSam Leffler 18396d161891SSam Leffler if (crp->crp_flags & CRYPTO_F_IMBUF) { 18406d161891SSam Leffler if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 18416d161891SSam Leffler cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 18426d161891SSam Leffler hifnstats.hst_nomem_load++; 18436d161891SSam Leffler err = ENOMEM; 18446d161891SSam Leffler goto err_srcmap1; 18456d161891SSam Leffler } 18466d161891SSam Leffler } else if (crp->crp_flags & CRYPTO_F_IOV) { 18476d161891SSam Leffler if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 18486d161891SSam Leffler cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 18496d161891SSam Leffler hifnstats.hst_nomem_load++; 18506d161891SSam Leffler err = ENOMEM; 18516d161891SSam Leffler goto err_srcmap1; 18526d161891SSam Leffler } 18536d161891SSam Leffler } else { 18546d161891SSam Leffler err = EINVAL; 18556d161891SSam Leffler goto err_srcmap1; 18566d161891SSam Leffler } 18576d161891SSam Leffler 18586d161891SSam Leffler if (hifn_dmamap_aligned(&cmd->src)) { 18596d161891SSam Leffler cmd->sloplen = cmd->src_mapsize & 3; 18606d161891SSam Leffler cmd->dst = cmd->src; 18616d161891SSam Leffler } else { 18626d161891SSam Leffler if (crp->crp_flags & CRYPTO_F_IOV) { 18636d161891SSam Leffler err = EINVAL; 18646d161891SSam Leffler goto err_srcmap; 18656d161891SSam Leffler } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 18666d161891SSam Leffler int totlen, len; 18676d161891SSam Leffler struct mbuf *m, *m0, *mlast; 18686d161891SSam Leffler 18696d161891SSam Leffler KASSERT(cmd->dst_m == cmd->src_m, 18706d161891SSam Leffler ("hifn_crypto: dst_m initialized improperly")); 18716d161891SSam Leffler hifnstats.hst_unaligned++; 18726d161891SSam Leffler /* 18736d161891SSam Leffler * Source is not aligned on a longword boundary. 18746d161891SSam Leffler * Copy the data to insure alignment. If we fail 18756d161891SSam Leffler * to allocate mbufs or clusters while doing this 18766d161891SSam Leffler * we return ERESTART so the operation is requeued 18776d161891SSam Leffler * at the crypto later, but only if there are 18786d161891SSam Leffler * ops already posted to the hardware; otherwise we 18796d161891SSam Leffler * have no guarantee that we'll be re-entered. 18806d161891SSam Leffler */ 18816d161891SSam Leffler totlen = cmd->src_mapsize; 18826d161891SSam Leffler if (cmd->src_m->m_flags & M_PKTHDR) { 18836d161891SSam Leffler len = MHLEN; 1884a163d034SWarner Losh MGETHDR(m0, M_DONTWAIT, MT_DATA); 1885a163d034SWarner Losh if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 18869967cafcSSam Leffler m_free(m0); 18879967cafcSSam Leffler m0 = NULL; 18889967cafcSSam Leffler } 18896d161891SSam Leffler } else { 18906d161891SSam Leffler len = MLEN; 1891a163d034SWarner Losh MGET(m0, M_DONTWAIT, MT_DATA); 18926d161891SSam Leffler } 18936d161891SSam Leffler if (m0 == NULL) { 18946d161891SSam Leffler hifnstats.hst_nomem_mbuf++; 1895ea14ae7aSOleksandr Tymoshenko err = sc->sc_cmdu ? ERESTART : ENOMEM; 18966d161891SSam Leffler goto err_srcmap; 18976d161891SSam Leffler } 18986d161891SSam Leffler if (totlen >= MINCLSIZE) { 1899a163d034SWarner Losh MCLGET(m0, M_DONTWAIT); 19006d161891SSam Leffler if ((m0->m_flags & M_EXT) == 0) { 19016d161891SSam Leffler hifnstats.hst_nomem_mcl++; 1902ea14ae7aSOleksandr Tymoshenko err = sc->sc_cmdu ? ERESTART : ENOMEM; 19036d161891SSam Leffler m_freem(m0); 19046d161891SSam Leffler goto err_srcmap; 19056d161891SSam Leffler } 19066d161891SSam Leffler len = MCLBYTES; 19076d161891SSam Leffler } 19086d161891SSam Leffler totlen -= len; 19096d161891SSam Leffler m0->m_pkthdr.len = m0->m_len = len; 19106d161891SSam Leffler mlast = m0; 19116d161891SSam Leffler 19126d161891SSam Leffler while (totlen > 0) { 1913a163d034SWarner Losh MGET(m, M_DONTWAIT, MT_DATA); 19146d161891SSam Leffler if (m == NULL) { 19156d161891SSam Leffler hifnstats.hst_nomem_mbuf++; 1916ea14ae7aSOleksandr Tymoshenko err = sc->sc_cmdu ? ERESTART : ENOMEM; 19176d161891SSam Leffler m_freem(m0); 19186d161891SSam Leffler goto err_srcmap; 19196d161891SSam Leffler } 19206d161891SSam Leffler len = MLEN; 19216d161891SSam Leffler if (totlen >= MINCLSIZE) { 1922a163d034SWarner Losh MCLGET(m, M_DONTWAIT); 19236d161891SSam Leffler if ((m->m_flags & M_EXT) == 0) { 19246d161891SSam Leffler hifnstats.hst_nomem_mcl++; 1925ea14ae7aSOleksandr Tymoshenko err = sc->sc_cmdu ? ERESTART : ENOMEM; 19266d161891SSam Leffler mlast->m_next = m; 19276d161891SSam Leffler m_freem(m0); 19286d161891SSam Leffler goto err_srcmap; 19296d161891SSam Leffler } 19306d161891SSam Leffler len = MCLBYTES; 19316d161891SSam Leffler } 19326d161891SSam Leffler 19336d161891SSam Leffler m->m_len = len; 19346d161891SSam Leffler m0->m_pkthdr.len += len; 19356d161891SSam Leffler totlen -= len; 19366d161891SSam Leffler 19376d161891SSam Leffler mlast->m_next = m; 19386d161891SSam Leffler mlast = m; 19396d161891SSam Leffler } 19406d161891SSam Leffler cmd->dst_m = m0; 19416d161891SSam Leffler } 19426d161891SSam Leffler } 19436d161891SSam Leffler 19446d161891SSam Leffler if (cmd->dst_map == NULL) { 19456d161891SSam Leffler if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 19466d161891SSam Leffler hifnstats.hst_nomem_map++; 19476d161891SSam Leffler err = ENOMEM; 19486d161891SSam Leffler goto err_srcmap; 19496d161891SSam Leffler } 19506d161891SSam Leffler if (crp->crp_flags & CRYPTO_F_IMBUF) { 19516d161891SSam Leffler if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 19526d161891SSam Leffler cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 19536d161891SSam Leffler hifnstats.hst_nomem_map++; 19546d161891SSam Leffler err = ENOMEM; 19556d161891SSam Leffler goto err_dstmap1; 19566d161891SSam Leffler } 19576d161891SSam Leffler } else if (crp->crp_flags & CRYPTO_F_IOV) { 19586d161891SSam Leffler if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 19596d161891SSam Leffler cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 19606d161891SSam Leffler hifnstats.hst_nomem_load++; 19616d161891SSam Leffler err = ENOMEM; 19626d161891SSam Leffler goto err_dstmap1; 19636d161891SSam Leffler } 19646d161891SSam Leffler } 19656d161891SSam Leffler } 19666d161891SSam Leffler 19676d161891SSam Leffler #ifdef HIFN_DEBUG 19686d161891SSam Leffler if (hifn_debug) { 19696d161891SSam Leffler device_printf(sc->sc_dev, 19706d161891SSam Leffler "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 19716d161891SSam Leffler READ_REG_1(sc, HIFN_1_DMA_CSR), 19726d161891SSam Leffler READ_REG_1(sc, HIFN_1_DMA_IER), 1973ea14ae7aSOleksandr Tymoshenko sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu, 19746d161891SSam Leffler cmd->src_nsegs, cmd->dst_nsegs); 19756d161891SSam Leffler } 19766d161891SSam Leffler #endif 19776d161891SSam Leffler 19786d161891SSam Leffler if (cmd->src_map == cmd->dst_map) { 19796d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 19806d161891SSam Leffler BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 19816d161891SSam Leffler } else { 19826d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 19836d161891SSam Leffler BUS_DMASYNC_PREWRITE); 19846d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 19856d161891SSam Leffler BUS_DMASYNC_PREREAD); 19866d161891SSam Leffler } 19876d161891SSam Leffler 19886d161891SSam Leffler /* 19896d161891SSam Leffler * need N src, and N dst 19906d161891SSam Leffler */ 1991ea14ae7aSOleksandr Tymoshenko if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1992ea14ae7aSOleksandr Tymoshenko (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 19936d161891SSam Leffler #ifdef HIFN_DEBUG 19946d161891SSam Leffler if (hifn_debug) { 19956d161891SSam Leffler device_printf(sc->sc_dev, 19966d161891SSam Leffler "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1997ea14ae7aSOleksandr Tymoshenko sc->sc_srcu, cmd->src_nsegs, 1998ea14ae7aSOleksandr Tymoshenko sc->sc_dstu, cmd->dst_nsegs); 19996d161891SSam Leffler } 20006d161891SSam Leffler #endif 20016d161891SSam Leffler hifnstats.hst_nomem_sd++; 20026d161891SSam Leffler err = ERESTART; 20036d161891SSam Leffler goto err_dstmap; 20046d161891SSam Leffler } 20056d161891SSam Leffler 2006ea14ae7aSOleksandr Tymoshenko if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) { 2007ea14ae7aSOleksandr Tymoshenko sc->sc_cmdi = 0; 20086d161891SSam Leffler dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 20096d161891SSam Leffler HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 20106d161891SSam Leffler HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 20116d161891SSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 20126d161891SSam Leffler } 2013ea14ae7aSOleksandr Tymoshenko cmdi = sc->sc_cmdi++; 20146d161891SSam Leffler cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 20156d161891SSam Leffler HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 20166d161891SSam Leffler 20176d161891SSam Leffler /* .p for command/result already set */ 20186d161891SSam Leffler dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 20196d161891SSam Leffler HIFN_D_MASKDONEIRQ); 20206d161891SSam Leffler HIFN_CMDR_SYNC(sc, cmdi, 20216d161891SSam Leffler BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2022ea14ae7aSOleksandr Tymoshenko sc->sc_cmdu++; 20236d161891SSam Leffler 20246d161891SSam Leffler /* 20256d161891SSam Leffler * We don't worry about missing an interrupt (which a "command wait" 20266d161891SSam Leffler * interrupt salvages us from), unless there is more than one command 20276d161891SSam Leffler * in the queue. 20286d161891SSam Leffler */ 2029ea14ae7aSOleksandr Tymoshenko if (sc->sc_cmdu > 1) { 20306d161891SSam Leffler sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 20316d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 20326d161891SSam Leffler } 20336d161891SSam Leffler 20346d161891SSam Leffler hifnstats.hst_ipackets++; 20356d161891SSam Leffler hifnstats.hst_ibytes += cmd->src_mapsize; 20366d161891SSam Leffler 20376d161891SSam Leffler hifn_dmamap_load_src(sc, cmd); 20386d161891SSam Leffler 20396d161891SSam Leffler /* 20406d161891SSam Leffler * Unlike other descriptors, we don't mask done interrupt from 20416d161891SSam Leffler * result descriptor. 20426d161891SSam Leffler */ 20436d161891SSam Leffler #ifdef HIFN_DEBUG 20446d161891SSam Leffler if (hifn_debug) 20456d161891SSam Leffler printf("load res\n"); 20466d161891SSam Leffler #endif 2047ea14ae7aSOleksandr Tymoshenko if (sc->sc_resi == HIFN_D_RES_RSIZE) { 2048ea14ae7aSOleksandr Tymoshenko sc->sc_resi = 0; 20496d161891SSam Leffler dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 20506d161891SSam Leffler HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 20516d161891SSam Leffler HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 20526d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 20536d161891SSam Leffler } 2054ea14ae7aSOleksandr Tymoshenko resi = sc->sc_resi++; 2055ea14ae7aSOleksandr Tymoshenko KASSERT(sc->sc_hifn_commands[resi] == NULL, 20566d161891SSam Leffler ("hifn_crypto: command slot %u busy", resi)); 2057ea14ae7aSOleksandr Tymoshenko sc->sc_hifn_commands[resi] = cmd; 20586d161891SSam Leffler HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 20596d161891SSam Leffler if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 20606d161891SSam Leffler dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 20616d161891SSam Leffler HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 20626d161891SSam Leffler sc->sc_curbatch++; 20636d161891SSam Leffler if (sc->sc_curbatch > hifnstats.hst_maxbatch) 20646d161891SSam Leffler hifnstats.hst_maxbatch = sc->sc_curbatch; 20656d161891SSam Leffler hifnstats.hst_totbatch++; 20666d161891SSam Leffler } else { 20676d161891SSam Leffler dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 20686d161891SSam Leffler HIFN_D_VALID | HIFN_D_LAST); 20696d161891SSam Leffler sc->sc_curbatch = 0; 20706d161891SSam Leffler } 20716d161891SSam Leffler HIFN_RESR_SYNC(sc, resi, 20726d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2073ea14ae7aSOleksandr Tymoshenko sc->sc_resu++; 20746d161891SSam Leffler 20756d161891SSam Leffler if (cmd->sloplen) 20766d161891SSam Leffler cmd->slopidx = resi; 20776d161891SSam Leffler 20786d161891SSam Leffler hifn_dmamap_load_dst(sc, cmd); 20796d161891SSam Leffler 20806810ad6fSSam Leffler csr = 0; 20816810ad6fSSam Leffler if (sc->sc_c_busy == 0) { 20826810ad6fSSam Leffler csr |= HIFN_DMACSR_C_CTRL_ENA; 20836810ad6fSSam Leffler sc->sc_c_busy = 1; 20846810ad6fSSam Leffler } 20856810ad6fSSam Leffler if (sc->sc_s_busy == 0) { 20866810ad6fSSam Leffler csr |= HIFN_DMACSR_S_CTRL_ENA; 20876810ad6fSSam Leffler sc->sc_s_busy = 1; 20886810ad6fSSam Leffler } 20896810ad6fSSam Leffler if (sc->sc_r_busy == 0) { 20906810ad6fSSam Leffler csr |= HIFN_DMACSR_R_CTRL_ENA; 20916810ad6fSSam Leffler sc->sc_r_busy = 1; 20926810ad6fSSam Leffler } 20936d161891SSam Leffler if (sc->sc_d_busy == 0) { 20946810ad6fSSam Leffler csr |= HIFN_DMACSR_D_CTRL_ENA; 20956d161891SSam Leffler sc->sc_d_busy = 1; 20966d161891SSam Leffler } 20976810ad6fSSam Leffler if (csr) 20986810ad6fSSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); 20996d161891SSam Leffler 21006d161891SSam Leffler #ifdef HIFN_DEBUG 21016d161891SSam Leffler if (hifn_debug) { 21026d161891SSam Leffler device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 21036d161891SSam Leffler READ_REG_1(sc, HIFN_1_DMA_CSR), 21046d161891SSam Leffler READ_REG_1(sc, HIFN_1_DMA_IER)); 21056d161891SSam Leffler } 21066d161891SSam Leffler #endif 21076d161891SSam Leffler 21086d161891SSam Leffler sc->sc_active = 5; 21094f28f7d7SSam Leffler HIFN_UNLOCK(sc); 21106d161891SSam Leffler KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 21116d161891SSam Leffler return (err); /* success */ 21126d161891SSam Leffler 21136d161891SSam Leffler err_dstmap: 21146d161891SSam Leffler if (cmd->src_map != cmd->dst_map) 21156d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 21166d161891SSam Leffler err_dstmap1: 21176d161891SSam Leffler if (cmd->src_map != cmd->dst_map) 21186d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 21196d161891SSam Leffler err_srcmap: 21206d161891SSam Leffler if (crp->crp_flags & CRYPTO_F_IMBUF) { 21216d161891SSam Leffler if (cmd->src_m != cmd->dst_m) 21226d161891SSam Leffler m_freem(cmd->dst_m); 21236d161891SSam Leffler } 21246d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 21256d161891SSam Leffler err_srcmap1: 21266d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 21274f28f7d7SSam Leffler HIFN_UNLOCK(sc); 21286d161891SSam Leffler return (err); 21296d161891SSam Leffler } 21306d161891SSam Leffler 21316d161891SSam Leffler static void 21326d161891SSam Leffler hifn_tick(void* vsc) 21336d161891SSam Leffler { 21346d161891SSam Leffler struct hifn_softc *sc = vsc; 21356d161891SSam Leffler 21366d161891SSam Leffler HIFN_LOCK(sc); 21376d161891SSam Leffler if (sc->sc_active == 0) { 21386d161891SSam Leffler u_int32_t r = 0; 21396d161891SSam Leffler 2140ea14ae7aSOleksandr Tymoshenko if (sc->sc_cmdu == 0 && sc->sc_c_busy) { 21416d161891SSam Leffler sc->sc_c_busy = 0; 21426d161891SSam Leffler r |= HIFN_DMACSR_C_CTRL_DIS; 21436d161891SSam Leffler } 2144ea14ae7aSOleksandr Tymoshenko if (sc->sc_srcu == 0 && sc->sc_s_busy) { 21456d161891SSam Leffler sc->sc_s_busy = 0; 21466d161891SSam Leffler r |= HIFN_DMACSR_S_CTRL_DIS; 21476d161891SSam Leffler } 2148ea14ae7aSOleksandr Tymoshenko if (sc->sc_dstu == 0 && sc->sc_d_busy) { 21496d161891SSam Leffler sc->sc_d_busy = 0; 21506d161891SSam Leffler r |= HIFN_DMACSR_D_CTRL_DIS; 21516d161891SSam Leffler } 2152ea14ae7aSOleksandr Tymoshenko if (sc->sc_resu == 0 && sc->sc_r_busy) { 21536d161891SSam Leffler sc->sc_r_busy = 0; 21546d161891SSam Leffler r |= HIFN_DMACSR_R_CTRL_DIS; 21556d161891SSam Leffler } 21566d161891SSam Leffler if (r) 21576d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 21586d161891SSam Leffler } else 21596d161891SSam Leffler sc->sc_active--; 21606d161891SSam Leffler HIFN_UNLOCK(sc); 21616d161891SSam Leffler callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 21626d161891SSam Leffler } 21636d161891SSam Leffler 21646d161891SSam Leffler static void 21656d161891SSam Leffler hifn_intr(void *arg) 21666d161891SSam Leffler { 21676d161891SSam Leffler struct hifn_softc *sc = arg; 21686d161891SSam Leffler struct hifn_dma *dma; 21696d161891SSam Leffler u_int32_t dmacsr, restart; 21706d161891SSam Leffler int i, u; 21716d161891SSam Leffler 21726d161891SSam Leffler dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 21736d161891SSam Leffler 21744f28f7d7SSam Leffler /* Nothing in the DMA unit interrupted */ 21754f28f7d7SSam Leffler if ((dmacsr & sc->sc_dmaier) == 0) 21764f28f7d7SSam Leffler return; 21774f28f7d7SSam Leffler 21784f28f7d7SSam Leffler HIFN_LOCK(sc); 21794f28f7d7SSam Leffler 21804f28f7d7SSam Leffler dma = sc->sc_dma; 21814f28f7d7SSam Leffler 21826d161891SSam Leffler #ifdef HIFN_DEBUG 21836d161891SSam Leffler if (hifn_debug) { 21846d161891SSam Leffler device_printf(sc->sc_dev, 21856d161891SSam Leffler "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 21866d161891SSam Leffler dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2187ea14ae7aSOleksandr Tymoshenko sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi, 2188ea14ae7aSOleksandr Tymoshenko sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk, 2189ea14ae7aSOleksandr Tymoshenko sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu); 21906d161891SSam Leffler } 21916d161891SSam Leffler #endif 21926d161891SSam Leffler 21936d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 21946d161891SSam Leffler 21956d161891SSam Leffler if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 21966d161891SSam Leffler (dmacsr & HIFN_DMACSR_PUBDONE)) 21976d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 21986d161891SSam Leffler READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 21996d161891SSam Leffler 22006d161891SSam Leffler restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 22016d161891SSam Leffler if (restart) 22026d161891SSam Leffler device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 22036d161891SSam Leffler 22046d161891SSam Leffler if (sc->sc_flags & HIFN_IS_7811) { 22056d161891SSam Leffler if (dmacsr & HIFN_DMACSR_ILLR) 22066d161891SSam Leffler device_printf(sc->sc_dev, "illegal read\n"); 22076d161891SSam Leffler if (dmacsr & HIFN_DMACSR_ILLW) 22086d161891SSam Leffler device_printf(sc->sc_dev, "illegal write\n"); 22096d161891SSam Leffler } 22106d161891SSam Leffler 22116d161891SSam Leffler restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 22126d161891SSam Leffler HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 22136d161891SSam Leffler if (restart) { 22146d161891SSam Leffler device_printf(sc->sc_dev, "abort, resetting.\n"); 22156d161891SSam Leffler hifnstats.hst_abort++; 22166d161891SSam Leffler hifn_abort(sc); 22176d161891SSam Leffler HIFN_UNLOCK(sc); 22186d161891SSam Leffler return; 22196d161891SSam Leffler } 22206d161891SSam Leffler 2221ea14ae7aSOleksandr Tymoshenko if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) { 22226d161891SSam Leffler /* 22236d161891SSam Leffler * If no slots to process and we receive a "waiting on 22246d161891SSam Leffler * command" interrupt, we disable the "waiting on command" 22256d161891SSam Leffler * (by clearing it). 22266d161891SSam Leffler */ 22276d161891SSam Leffler sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 22286d161891SSam Leffler WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 22296d161891SSam Leffler } 22306d161891SSam Leffler 22316d161891SSam Leffler /* clear the rings */ 2232ea14ae7aSOleksandr Tymoshenko i = sc->sc_resk; u = sc->sc_resu; 22336d161891SSam Leffler while (u != 0) { 22346d161891SSam Leffler HIFN_RESR_SYNC(sc, i, 22356d161891SSam Leffler BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 22366d161891SSam Leffler if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 22376d161891SSam Leffler HIFN_RESR_SYNC(sc, i, 22386d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 22396d161891SSam Leffler break; 22406d161891SSam Leffler } 22416d161891SSam Leffler 22426d161891SSam Leffler if (i != HIFN_D_RES_RSIZE) { 22436d161891SSam Leffler struct hifn_command *cmd; 22446d161891SSam Leffler u_int8_t *macbuf = NULL; 22456d161891SSam Leffler 22466d161891SSam Leffler HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2247ea14ae7aSOleksandr Tymoshenko cmd = sc->sc_hifn_commands[i]; 22486d161891SSam Leffler KASSERT(cmd != NULL, 22496d161891SSam Leffler ("hifn_intr: null command slot %u", i)); 2250ea14ae7aSOleksandr Tymoshenko sc->sc_hifn_commands[i] = NULL; 22516d161891SSam Leffler 22526d161891SSam Leffler if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 22536d161891SSam Leffler macbuf = dma->result_bufs[i]; 22546d161891SSam Leffler macbuf += 12; 22556d161891SSam Leffler } 22566d161891SSam Leffler 22576d161891SSam Leffler hifn_callback(sc, cmd, macbuf); 22586d161891SSam Leffler hifnstats.hst_opackets++; 22596d161891SSam Leffler u--; 22606d161891SSam Leffler } 22616d161891SSam Leffler 22626d161891SSam Leffler if (++i == (HIFN_D_RES_RSIZE + 1)) 22636d161891SSam Leffler i = 0; 22646d161891SSam Leffler } 2265ea14ae7aSOleksandr Tymoshenko sc->sc_resk = i; sc->sc_resu = u; 22666d161891SSam Leffler 2267ea14ae7aSOleksandr Tymoshenko i = sc->sc_srck; u = sc->sc_srcu; 22686d161891SSam Leffler while (u != 0) { 22696d161891SSam Leffler if (i == HIFN_D_SRC_RSIZE) 22706d161891SSam Leffler i = 0; 22716d161891SSam Leffler HIFN_SRCR_SYNC(sc, i, 22726d161891SSam Leffler BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 22736d161891SSam Leffler if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 22746d161891SSam Leffler HIFN_SRCR_SYNC(sc, i, 22756d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 22766d161891SSam Leffler break; 22776d161891SSam Leffler } 22786d161891SSam Leffler i++, u--; 22796d161891SSam Leffler } 2280ea14ae7aSOleksandr Tymoshenko sc->sc_srck = i; sc->sc_srcu = u; 22816d161891SSam Leffler 2282ea14ae7aSOleksandr Tymoshenko i = sc->sc_cmdk; u = sc->sc_cmdu; 22836d161891SSam Leffler while (u != 0) { 22846d161891SSam Leffler HIFN_CMDR_SYNC(sc, i, 22856d161891SSam Leffler BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 22866d161891SSam Leffler if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 22876d161891SSam Leffler HIFN_CMDR_SYNC(sc, i, 22886d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 22896d161891SSam Leffler break; 22906d161891SSam Leffler } 22916d161891SSam Leffler if (i != HIFN_D_CMD_RSIZE) { 22926d161891SSam Leffler u--; 22936d161891SSam Leffler HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 22946d161891SSam Leffler } 22956d161891SSam Leffler if (++i == (HIFN_D_CMD_RSIZE + 1)) 22966d161891SSam Leffler i = 0; 22976d161891SSam Leffler } 2298ea14ae7aSOleksandr Tymoshenko sc->sc_cmdk = i; sc->sc_cmdu = u; 22996d161891SSam Leffler 23004f28f7d7SSam Leffler HIFN_UNLOCK(sc); 23014f28f7d7SSam Leffler 23026d161891SSam Leffler if (sc->sc_needwakeup) { /* XXX check high watermark */ 23036d161891SSam Leffler int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 23046d161891SSam Leffler #ifdef HIFN_DEBUG 23056d161891SSam Leffler if (hifn_debug) 23066d161891SSam Leffler device_printf(sc->sc_dev, 23076d161891SSam Leffler "wakeup crypto (%x) u %d/%d/%d/%d\n", 23086d161891SSam Leffler sc->sc_needwakeup, 2309ea14ae7aSOleksandr Tymoshenko sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu); 23106d161891SSam Leffler #endif 23116d161891SSam Leffler sc->sc_needwakeup &= ~wakeup; 23126d161891SSam Leffler crypto_unblock(sc->sc_cid, wakeup); 23136d161891SSam Leffler } 23146d161891SSam Leffler } 23156d161891SSam Leffler 23166d161891SSam Leffler /* 23176d161891SSam Leffler * Allocate a new 'session' and return an encoded session id. 'sidp' 23186d161891SSam Leffler * contains our registration id, and should contain an encoded session 23196d161891SSam Leffler * id on successful allocation. 23206d161891SSam Leffler */ 23216d161891SSam Leffler static int 23226810ad6fSSam Leffler hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 23236d161891SSam Leffler { 23246810ad6fSSam Leffler struct hifn_softc *sc = device_get_softc(dev); 23256d161891SSam Leffler struct cryptoini *c; 2326fe9b390bSSam Leffler int mac = 0, cry = 0, sesn; 23271ab4eff4SSam Leffler struct hifn_session *ses = NULL; 23286d161891SSam Leffler 23296d161891SSam Leffler KASSERT(sc != NULL, ("hifn_newsession: null softc")); 23306d161891SSam Leffler if (sidp == NULL || cri == NULL || sc == NULL) 23316d161891SSam Leffler return (EINVAL); 23326d161891SSam Leffler 23336810ad6fSSam Leffler HIFN_LOCK(sc); 2334fe9b390bSSam Leffler if (sc->sc_sessions == NULL) { 2335fe9b390bSSam Leffler ses = sc->sc_sessions = (struct hifn_session *)malloc( 2336fe9b390bSSam Leffler sizeof(*ses), M_DEVBUF, M_NOWAIT); 23376810ad6fSSam Leffler if (ses == NULL) { 23386810ad6fSSam Leffler HIFN_UNLOCK(sc); 23396d161891SSam Leffler return (ENOMEM); 23406810ad6fSSam Leffler } 2341fe9b390bSSam Leffler sesn = 0; 2342fe9b390bSSam Leffler sc->sc_nsessions = 1; 2343fe9b390bSSam Leffler } else { 2344fe9b390bSSam Leffler for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 2345fe9b390bSSam Leffler if (!sc->sc_sessions[sesn].hs_used) { 2346fe9b390bSSam Leffler ses = &sc->sc_sessions[sesn]; 2347fe9b390bSSam Leffler break; 2348fe9b390bSSam Leffler } 2349fe9b390bSSam Leffler } 2350fe9b390bSSam Leffler 2351fe9b390bSSam Leffler if (ses == NULL) { 2352fe9b390bSSam Leffler sesn = sc->sc_nsessions; 2353fe9b390bSSam Leffler ses = (struct hifn_session *)malloc((sesn + 1) * 2354fe9b390bSSam Leffler sizeof(*ses), M_DEVBUF, M_NOWAIT); 23556810ad6fSSam Leffler if (ses == NULL) { 23566810ad6fSSam Leffler HIFN_UNLOCK(sc); 2357fe9b390bSSam Leffler return (ENOMEM); 23586810ad6fSSam Leffler } 2359fe9b390bSSam Leffler bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 2360fe9b390bSSam Leffler bzero(sc->sc_sessions, sesn * sizeof(*ses)); 2361fe9b390bSSam Leffler free(sc->sc_sessions, M_DEVBUF); 2362fe9b390bSSam Leffler sc->sc_sessions = ses; 2363fe9b390bSSam Leffler ses = &sc->sc_sessions[sesn]; 2364fe9b390bSSam Leffler sc->sc_nsessions++; 2365fe9b390bSSam Leffler } 2366fe9b390bSSam Leffler } 23676810ad6fSSam Leffler HIFN_UNLOCK(sc); 23686810ad6fSSam Leffler 2369fe9b390bSSam Leffler bzero(ses, sizeof(*ses)); 2370fe9b390bSSam Leffler ses->hs_used = 1; 23716d161891SSam Leffler 23726d161891SSam Leffler for (c = cri; c != NULL; c = c->cri_next) { 23736d161891SSam Leffler switch (c->cri_alg) { 23746d161891SSam Leffler case CRYPTO_MD5: 23756d161891SSam Leffler case CRYPTO_SHA1: 23766d161891SSam Leffler case CRYPTO_MD5_HMAC: 23776d161891SSam Leffler case CRYPTO_SHA1_HMAC: 23786d161891SSam Leffler if (mac) 23796d161891SSam Leffler return (EINVAL); 23806d161891SSam Leffler mac = 1; 2381af65c53aSPawel Jakub Dawidek ses->hs_mlen = c->cri_mlen; 2382af65c53aSPawel Jakub Dawidek if (ses->hs_mlen == 0) { 2383af65c53aSPawel Jakub Dawidek switch (c->cri_alg) { 2384af65c53aSPawel Jakub Dawidek case CRYPTO_MD5: 2385af65c53aSPawel Jakub Dawidek case CRYPTO_MD5_HMAC: 2386af65c53aSPawel Jakub Dawidek ses->hs_mlen = 16; 2387af65c53aSPawel Jakub Dawidek break; 2388af65c53aSPawel Jakub Dawidek case CRYPTO_SHA1: 2389af65c53aSPawel Jakub Dawidek case CRYPTO_SHA1_HMAC: 2390af65c53aSPawel Jakub Dawidek ses->hs_mlen = 20; 2391af65c53aSPawel Jakub Dawidek break; 2392af65c53aSPawel Jakub Dawidek } 2393af65c53aSPawel Jakub Dawidek } 23946d161891SSam Leffler break; 23956d161891SSam Leffler case CRYPTO_DES_CBC: 23966d161891SSam Leffler case CRYPTO_3DES_CBC: 239717b66701SSam Leffler case CRYPTO_AES_CBC: 23986d161891SSam Leffler /* XXX this may read fewer, does it matter? */ 2399fe9b390bSSam Leffler read_random(ses->hs_iv, 240017b66701SSam Leffler c->cri_alg == CRYPTO_AES_CBC ? 240117b66701SSam Leffler HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 24026d161891SSam Leffler /*FALLTHROUGH*/ 24036d161891SSam Leffler case CRYPTO_ARC4: 24046d161891SSam Leffler if (cry) 24056d161891SSam Leffler return (EINVAL); 24066d161891SSam Leffler cry = 1; 24076d161891SSam Leffler break; 24086d161891SSam Leffler default: 24096d161891SSam Leffler return (EINVAL); 24106d161891SSam Leffler } 24116d161891SSam Leffler } 24126d161891SSam Leffler if (mac == 0 && cry == 0) 24136d161891SSam Leffler return (EINVAL); 24146d161891SSam Leffler 2415fe9b390bSSam Leffler *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); 24166d161891SSam Leffler 24176d161891SSam Leffler return (0); 24186d161891SSam Leffler } 24196d161891SSam Leffler 24206d161891SSam Leffler /* 24216d161891SSam Leffler * Deallocate a session. 24226d161891SSam Leffler * XXX this routine should run a zero'd mac/encrypt key into context ram. 24236d161891SSam Leffler * XXX to blow away any keys already stored there. 24246d161891SSam Leffler */ 24256d161891SSam Leffler static int 24266810ad6fSSam Leffler hifn_freesession(device_t dev, u_int64_t tid) 24276d161891SSam Leffler { 24286810ad6fSSam Leffler struct hifn_softc *sc = device_get_softc(dev); 24296810ad6fSSam Leffler int session, error; 243007d0c94aSSam Leffler u_int32_t sid = CRYPTO_SESID2LID(tid); 24316d161891SSam Leffler 24326d161891SSam Leffler KASSERT(sc != NULL, ("hifn_freesession: null softc")); 24336d161891SSam Leffler if (sc == NULL) 24346d161891SSam Leffler return (EINVAL); 24356d161891SSam Leffler 24366810ad6fSSam Leffler HIFN_LOCK(sc); 24376d161891SSam Leffler session = HIFN_SESSION(sid); 24386810ad6fSSam Leffler if (session < sc->sc_nsessions) { 24396810ad6fSSam Leffler bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); 24406810ad6fSSam Leffler error = 0; 24416810ad6fSSam Leffler } else 24426810ad6fSSam Leffler error = EINVAL; 24436810ad6fSSam Leffler HIFN_UNLOCK(sc); 24446d161891SSam Leffler 24456810ad6fSSam Leffler return (error); 24466d161891SSam Leffler } 24476d161891SSam Leffler 24486d161891SSam Leffler static int 24496810ad6fSSam Leffler hifn_process(device_t dev, struct cryptop *crp, int hint) 24506d161891SSam Leffler { 24516810ad6fSSam Leffler struct hifn_softc *sc = device_get_softc(dev); 24526d161891SSam Leffler struct hifn_command *cmd = NULL; 245317b66701SSam Leffler int session, err, ivlen; 24546d161891SSam Leffler struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 24556d161891SSam Leffler 24566d161891SSam Leffler if (crp == NULL || crp->crp_callback == NULL) { 24576d161891SSam Leffler hifnstats.hst_invalid++; 24586d161891SSam Leffler return (EINVAL); 24596d161891SSam Leffler } 24606d161891SSam Leffler session = HIFN_SESSION(crp->crp_sid); 24616d161891SSam Leffler 2462fe9b390bSSam Leffler if (sc == NULL || session >= sc->sc_nsessions) { 24636d161891SSam Leffler err = EINVAL; 24646d161891SSam Leffler goto errout; 24656d161891SSam Leffler } 24666d161891SSam Leffler 24676d161891SSam Leffler cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 24686d161891SSam Leffler if (cmd == NULL) { 24696d161891SSam Leffler hifnstats.hst_nomem++; 24706d161891SSam Leffler err = ENOMEM; 24716d161891SSam Leffler goto errout; 24726d161891SSam Leffler } 24736d161891SSam Leffler 24746d161891SSam Leffler if (crp->crp_flags & CRYPTO_F_IMBUF) { 24756d161891SSam Leffler cmd->src_m = (struct mbuf *)crp->crp_buf; 24766d161891SSam Leffler cmd->dst_m = (struct mbuf *)crp->crp_buf; 24776d161891SSam Leffler } else if (crp->crp_flags & CRYPTO_F_IOV) { 24786d161891SSam Leffler cmd->src_io = (struct uio *)crp->crp_buf; 24796d161891SSam Leffler cmd->dst_io = (struct uio *)crp->crp_buf; 24806d161891SSam Leffler } else { 24816d161891SSam Leffler err = EINVAL; 24826d161891SSam Leffler goto errout; /* XXX we don't handle contiguous buffers! */ 24836d161891SSam Leffler } 24846d161891SSam Leffler 24856d161891SSam Leffler crd1 = crp->crp_desc; 24866d161891SSam Leffler if (crd1 == NULL) { 24876d161891SSam Leffler err = EINVAL; 24886d161891SSam Leffler goto errout; 24896d161891SSam Leffler } 24906d161891SSam Leffler crd2 = crd1->crd_next; 24916d161891SSam Leffler 24926d161891SSam Leffler if (crd2 == NULL) { 24936d161891SSam Leffler if (crd1->crd_alg == CRYPTO_MD5_HMAC || 24946d161891SSam Leffler crd1->crd_alg == CRYPTO_SHA1_HMAC || 24956d161891SSam Leffler crd1->crd_alg == CRYPTO_SHA1 || 24966d161891SSam Leffler crd1->crd_alg == CRYPTO_MD5) { 24976d161891SSam Leffler maccrd = crd1; 24986d161891SSam Leffler enccrd = NULL; 24996d161891SSam Leffler } else if (crd1->crd_alg == CRYPTO_DES_CBC || 25006d161891SSam Leffler crd1->crd_alg == CRYPTO_3DES_CBC || 250117b66701SSam Leffler crd1->crd_alg == CRYPTO_AES_CBC || 25026d161891SSam Leffler crd1->crd_alg == CRYPTO_ARC4) { 25036d161891SSam Leffler if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 25046d161891SSam Leffler cmd->base_masks |= HIFN_BASE_CMD_DECODE; 25056d161891SSam Leffler maccrd = NULL; 25066d161891SSam Leffler enccrd = crd1; 25076d161891SSam Leffler } else { 25086d161891SSam Leffler err = EINVAL; 25096d161891SSam Leffler goto errout; 25106d161891SSam Leffler } 25116d161891SSam Leffler } else { 25126d161891SSam Leffler if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 25136d161891SSam Leffler crd1->crd_alg == CRYPTO_SHA1_HMAC || 25146d161891SSam Leffler crd1->crd_alg == CRYPTO_MD5 || 25156d161891SSam Leffler crd1->crd_alg == CRYPTO_SHA1) && 25166d161891SSam Leffler (crd2->crd_alg == CRYPTO_DES_CBC || 25176d161891SSam Leffler crd2->crd_alg == CRYPTO_3DES_CBC || 251817b66701SSam Leffler crd2->crd_alg == CRYPTO_AES_CBC || 25196d161891SSam Leffler crd2->crd_alg == CRYPTO_ARC4) && 25206d161891SSam Leffler ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 25216d161891SSam Leffler cmd->base_masks = HIFN_BASE_CMD_DECODE; 25226d161891SSam Leffler maccrd = crd1; 25236d161891SSam Leffler enccrd = crd2; 25246d161891SSam Leffler } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 25256d161891SSam Leffler crd1->crd_alg == CRYPTO_ARC4 || 252617b66701SSam Leffler crd1->crd_alg == CRYPTO_3DES_CBC || 252717b66701SSam Leffler crd1->crd_alg == CRYPTO_AES_CBC) && 25286d161891SSam Leffler (crd2->crd_alg == CRYPTO_MD5_HMAC || 25296d161891SSam Leffler crd2->crd_alg == CRYPTO_SHA1_HMAC || 25306d161891SSam Leffler crd2->crd_alg == CRYPTO_MD5 || 25316d161891SSam Leffler crd2->crd_alg == CRYPTO_SHA1) && 25326d161891SSam Leffler (crd1->crd_flags & CRD_F_ENCRYPT)) { 25336d161891SSam Leffler enccrd = crd1; 25346d161891SSam Leffler maccrd = crd2; 25356d161891SSam Leffler } else { 25366d161891SSam Leffler /* 25376d161891SSam Leffler * We cannot order the 7751 as requested 25386d161891SSam Leffler */ 25396d161891SSam Leffler err = EINVAL; 25406d161891SSam Leffler goto errout; 25416d161891SSam Leffler } 25426d161891SSam Leffler } 25436d161891SSam Leffler 25446d161891SSam Leffler if (enccrd) { 25456d161891SSam Leffler cmd->enccrd = enccrd; 25466d161891SSam Leffler cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 25476d161891SSam Leffler switch (enccrd->crd_alg) { 25486d161891SSam Leffler case CRYPTO_ARC4: 25496d161891SSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 25506d161891SSam Leffler break; 25516d161891SSam Leffler case CRYPTO_DES_CBC: 25526d161891SSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 25536d161891SSam Leffler HIFN_CRYPT_CMD_MODE_CBC | 25546d161891SSam Leffler HIFN_CRYPT_CMD_NEW_IV; 25556d161891SSam Leffler break; 25566d161891SSam Leffler case CRYPTO_3DES_CBC: 25576d161891SSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 25586d161891SSam Leffler HIFN_CRYPT_CMD_MODE_CBC | 25596d161891SSam Leffler HIFN_CRYPT_CMD_NEW_IV; 25606d161891SSam Leffler break; 256117b66701SSam Leffler case CRYPTO_AES_CBC: 256217b66701SSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 256317b66701SSam Leffler HIFN_CRYPT_CMD_MODE_CBC | 256417b66701SSam Leffler HIFN_CRYPT_CMD_NEW_IV; 256517b66701SSam Leffler break; 25666d161891SSam Leffler default: 25676d161891SSam Leffler err = EINVAL; 25686d161891SSam Leffler goto errout; 25696d161891SSam Leffler } 25706d161891SSam Leffler if (enccrd->crd_alg != CRYPTO_ARC4) { 257117b66701SSam Leffler ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 257217b66701SSam Leffler HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 25736d161891SSam Leffler if (enccrd->crd_flags & CRD_F_ENCRYPT) { 25746d161891SSam Leffler if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 257517b66701SSam Leffler bcopy(enccrd->crd_iv, cmd->iv, ivlen); 25766d161891SSam Leffler else 25776d161891SSam Leffler bcopy(sc->sc_sessions[session].hs_iv, 257817b66701SSam Leffler cmd->iv, ivlen); 25796d161891SSam Leffler 25806d161891SSam Leffler if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 25816d161891SSam Leffler == 0) { 2582f34a967bSPawel Jakub Dawidek crypto_copyback(crp->crp_flags, 2583f34a967bSPawel Jakub Dawidek crp->crp_buf, enccrd->crd_inject, 258417b66701SSam Leffler ivlen, cmd->iv); 25856d161891SSam Leffler } 25866d161891SSam Leffler } else { 25876d161891SSam Leffler if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 258817b66701SSam Leffler bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2589f34a967bSPawel Jakub Dawidek else { 2590f34a967bSPawel Jakub Dawidek crypto_copydata(crp->crp_flags, 2591f34a967bSPawel Jakub Dawidek crp->crp_buf, enccrd->crd_inject, 2592f34a967bSPawel Jakub Dawidek ivlen, cmd->iv); 2593f34a967bSPawel Jakub Dawidek } 25946d161891SSam Leffler } 25956d161891SSam Leffler } 25966d161891SSam Leffler 2597c740ae4bSPoul-Henning Kamp if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2598c740ae4bSPoul-Henning Kamp cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 25996d161891SSam Leffler cmd->ck = enccrd->crd_key; 26006d161891SSam Leffler cmd->cklen = enccrd->crd_klen >> 3; 2601fe9b390bSSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 26026d161891SSam Leffler 260317b66701SSam Leffler /* 260417b66701SSam Leffler * Need to specify the size for the AES key in the masks. 260517b66701SSam Leffler */ 260617b66701SSam Leffler if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 260717b66701SSam Leffler HIFN_CRYPT_CMD_ALG_AES) { 260817b66701SSam Leffler switch (cmd->cklen) { 260917b66701SSam Leffler case 16: 261017b66701SSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 261117b66701SSam Leffler break; 261217b66701SSam Leffler case 24: 261317b66701SSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 261417b66701SSam Leffler break; 261517b66701SSam Leffler case 32: 261617b66701SSam Leffler cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 261717b66701SSam Leffler break; 261817b66701SSam Leffler default: 261917b66701SSam Leffler err = EINVAL; 262017b66701SSam Leffler goto errout; 262117b66701SSam Leffler } 262217b66701SSam Leffler } 26236d161891SSam Leffler } 26246d161891SSam Leffler 26256d161891SSam Leffler if (maccrd) { 26266d161891SSam Leffler cmd->maccrd = maccrd; 26276d161891SSam Leffler cmd->base_masks |= HIFN_BASE_CMD_MAC; 26286d161891SSam Leffler 26296d161891SSam Leffler switch (maccrd->crd_alg) { 26306d161891SSam Leffler case CRYPTO_MD5: 26316d161891SSam Leffler cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 26326d161891SSam Leffler HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 26336d161891SSam Leffler HIFN_MAC_CMD_POS_IPSEC; 26346d161891SSam Leffler break; 26356d161891SSam Leffler case CRYPTO_MD5_HMAC: 26366d161891SSam Leffler cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 26376d161891SSam Leffler HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 26386d161891SSam Leffler HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 26396d161891SSam Leffler break; 26406d161891SSam Leffler case CRYPTO_SHA1: 26416d161891SSam Leffler cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 26426d161891SSam Leffler HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 26436d161891SSam Leffler HIFN_MAC_CMD_POS_IPSEC; 26446d161891SSam Leffler break; 26456d161891SSam Leffler case CRYPTO_SHA1_HMAC: 26466d161891SSam Leffler cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 26476d161891SSam Leffler HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 26486d161891SSam Leffler HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 26496d161891SSam Leffler break; 26506d161891SSam Leffler } 26516d161891SSam Leffler 2652fe9b390bSSam Leffler if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2653fe9b390bSSam Leffler maccrd->crd_alg == CRYPTO_MD5_HMAC) { 26546d161891SSam Leffler cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 26556d161891SSam Leffler bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 26566d161891SSam Leffler bzero(cmd->mac + (maccrd->crd_klen >> 3), 26576d161891SSam Leffler HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 26586d161891SSam Leffler } 26596d161891SSam Leffler } 26606d161891SSam Leffler 26616d161891SSam Leffler cmd->crp = crp; 26626d161891SSam Leffler cmd->session_num = session; 26636d161891SSam Leffler cmd->softc = sc; 26646d161891SSam Leffler 26656d161891SSam Leffler err = hifn_crypto(sc, cmd, crp, hint); 26666d161891SSam Leffler if (!err) { 26676d161891SSam Leffler return 0; 26686d161891SSam Leffler } else if (err == ERESTART) { 26696d161891SSam Leffler /* 26706d161891SSam Leffler * There weren't enough resources to dispatch the request 26716d161891SSam Leffler * to the part. Notify the caller so they'll requeue this 26726d161891SSam Leffler * request and resubmit it again soon. 26736d161891SSam Leffler */ 26746d161891SSam Leffler #ifdef HIFN_DEBUG 26756d161891SSam Leffler if (hifn_debug) 26766d161891SSam Leffler device_printf(sc->sc_dev, "requeue request\n"); 26776d161891SSam Leffler #endif 26786d161891SSam Leffler free(cmd, M_DEVBUF); 26796d161891SSam Leffler sc->sc_needwakeup |= CRYPTO_SYMQ; 26806d161891SSam Leffler return (err); 26816d161891SSam Leffler } 26826d161891SSam Leffler 26836d161891SSam Leffler errout: 26846d161891SSam Leffler if (cmd != NULL) 26856d161891SSam Leffler free(cmd, M_DEVBUF); 26866d161891SSam Leffler if (err == EINVAL) 26876d161891SSam Leffler hifnstats.hst_invalid++; 26886d161891SSam Leffler else 26896d161891SSam Leffler hifnstats.hst_nomem++; 26906d161891SSam Leffler crp->crp_etype = err; 26916d161891SSam Leffler crypto_done(crp); 26926d161891SSam Leffler return (err); 26936d161891SSam Leffler } 26946d161891SSam Leffler 26956d161891SSam Leffler static void 26966d161891SSam Leffler hifn_abort(struct hifn_softc *sc) 26976d161891SSam Leffler { 26986d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 26996d161891SSam Leffler struct hifn_command *cmd; 27006d161891SSam Leffler struct cryptop *crp; 27016d161891SSam Leffler int i, u; 27026d161891SSam Leffler 2703ea14ae7aSOleksandr Tymoshenko i = sc->sc_resk; u = sc->sc_resu; 27046d161891SSam Leffler while (u != 0) { 2705ea14ae7aSOleksandr Tymoshenko cmd = sc->sc_hifn_commands[i]; 27066d161891SSam Leffler KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2707ea14ae7aSOleksandr Tymoshenko sc->sc_hifn_commands[i] = NULL; 27086d161891SSam Leffler crp = cmd->crp; 27096d161891SSam Leffler 27106d161891SSam Leffler if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 27116d161891SSam Leffler /* Salvage what we can. */ 27126d161891SSam Leffler u_int8_t *macbuf; 27136d161891SSam Leffler 27146d161891SSam Leffler if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 27156d161891SSam Leffler macbuf = dma->result_bufs[i]; 27166d161891SSam Leffler macbuf += 12; 27176d161891SSam Leffler } else 27186d161891SSam Leffler macbuf = NULL; 27196d161891SSam Leffler hifnstats.hst_opackets++; 27206d161891SSam Leffler hifn_callback(sc, cmd, macbuf); 27216d161891SSam Leffler } else { 27226d161891SSam Leffler if (cmd->src_map == cmd->dst_map) { 27236d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 27246d161891SSam Leffler BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 27256d161891SSam Leffler } else { 27266d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 27276d161891SSam Leffler BUS_DMASYNC_POSTWRITE); 27286d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 27296d161891SSam Leffler BUS_DMASYNC_POSTREAD); 27306d161891SSam Leffler } 27316d161891SSam Leffler 27326d161891SSam Leffler if (cmd->src_m != cmd->dst_m) { 27336d161891SSam Leffler m_freem(cmd->src_m); 27346d161891SSam Leffler crp->crp_buf = (caddr_t)cmd->dst_m; 27356d161891SSam Leffler } 27366d161891SSam Leffler 27376d161891SSam Leffler /* non-shared buffers cannot be restarted */ 27386d161891SSam Leffler if (cmd->src_map != cmd->dst_map) { 27396d161891SSam Leffler /* 27406d161891SSam Leffler * XXX should be EAGAIN, delayed until 27416d161891SSam Leffler * after the reset. 27426d161891SSam Leffler */ 27436d161891SSam Leffler crp->crp_etype = ENOMEM; 27446d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 27456d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 27466d161891SSam Leffler } else 27476d161891SSam Leffler crp->crp_etype = ENOMEM; 27486d161891SSam Leffler 27496d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 27506d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 27516d161891SSam Leffler 27526d161891SSam Leffler free(cmd, M_DEVBUF); 27536d161891SSam Leffler if (crp->crp_etype != EAGAIN) 27546d161891SSam Leffler crypto_done(crp); 27556d161891SSam Leffler } 27566d161891SSam Leffler 27576d161891SSam Leffler if (++i == HIFN_D_RES_RSIZE) 27586d161891SSam Leffler i = 0; 27596d161891SSam Leffler u--; 27606d161891SSam Leffler } 2761ea14ae7aSOleksandr Tymoshenko sc->sc_resk = i; sc->sc_resu = u; 27626d161891SSam Leffler 27636d161891SSam Leffler hifn_reset_board(sc, 1); 27646d161891SSam Leffler hifn_init_dma(sc); 27656d161891SSam Leffler hifn_init_pci_registers(sc); 27666d161891SSam Leffler } 27676d161891SSam Leffler 27686d161891SSam Leffler static void 27696d161891SSam Leffler hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 27706d161891SSam Leffler { 27716d161891SSam Leffler struct hifn_dma *dma = sc->sc_dma; 27726d161891SSam Leffler struct cryptop *crp = cmd->crp; 27736d161891SSam Leffler struct cryptodesc *crd; 27746d161891SSam Leffler struct mbuf *m; 277517b66701SSam Leffler int totlen, i, u, ivlen; 27766d161891SSam Leffler 27776d161891SSam Leffler if (cmd->src_map == cmd->dst_map) { 27786d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 27796d161891SSam Leffler BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 27806d161891SSam Leffler } else { 27816d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 27826d161891SSam Leffler BUS_DMASYNC_POSTWRITE); 27836d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 27846d161891SSam Leffler BUS_DMASYNC_POSTREAD); 27856d161891SSam Leffler } 27866d161891SSam Leffler 27876d161891SSam Leffler if (crp->crp_flags & CRYPTO_F_IMBUF) { 27886d161891SSam Leffler if (cmd->src_m != cmd->dst_m) { 27896d161891SSam Leffler crp->crp_buf = (caddr_t)cmd->dst_m; 27906d161891SSam Leffler totlen = cmd->src_mapsize; 27916d161891SSam Leffler for (m = cmd->dst_m; m != NULL; m = m->m_next) { 27926d161891SSam Leffler if (totlen < m->m_len) { 27936d161891SSam Leffler m->m_len = totlen; 27946d161891SSam Leffler totlen = 0; 27956d161891SSam Leffler } else 27966d161891SSam Leffler totlen -= m->m_len; 27976d161891SSam Leffler } 27986d161891SSam Leffler cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 27996d161891SSam Leffler m_freem(cmd->src_m); 28006d161891SSam Leffler } 28016d161891SSam Leffler } 28026d161891SSam Leffler 28036d161891SSam Leffler if (cmd->sloplen != 0) { 2804f34a967bSPawel Jakub Dawidek crypto_copyback(crp->crp_flags, crp->crp_buf, 2805f34a967bSPawel Jakub Dawidek cmd->src_mapsize - cmd->sloplen, cmd->sloplen, 2806f34a967bSPawel Jakub Dawidek (caddr_t)&dma->slop[cmd->slopidx]); 28076d161891SSam Leffler } 28086d161891SSam Leffler 2809ea14ae7aSOleksandr Tymoshenko i = sc->sc_dstk; u = sc->sc_dstu; 28106d161891SSam Leffler while (u != 0) { 28116d161891SSam Leffler if (i == HIFN_D_DST_RSIZE) 28126d161891SSam Leffler i = 0; 28136d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 28146d161891SSam Leffler BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 28156d161891SSam Leffler if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 28166d161891SSam Leffler bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 28176d161891SSam Leffler BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 28186d161891SSam Leffler break; 28196d161891SSam Leffler } 28206d161891SSam Leffler i++, u--; 28216d161891SSam Leffler } 2822ea14ae7aSOleksandr Tymoshenko sc->sc_dstk = i; sc->sc_dstu = u; 28236d161891SSam Leffler 28246d161891SSam Leffler hifnstats.hst_obytes += cmd->dst_mapsize; 28256d161891SSam Leffler 28266d161891SSam Leffler if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 28276d161891SSam Leffler HIFN_BASE_CMD_CRYPT) { 28286d161891SSam Leffler for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 28296d161891SSam Leffler if (crd->crd_alg != CRYPTO_DES_CBC && 283017b66701SSam Leffler crd->crd_alg != CRYPTO_3DES_CBC && 283117b66701SSam Leffler crd->crd_alg != CRYPTO_AES_CBC) 28326d161891SSam Leffler continue; 283317b66701SSam Leffler ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 283417b66701SSam Leffler HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2835f34a967bSPawel Jakub Dawidek crypto_copydata(crp->crp_flags, crp->crp_buf, 283617b66701SSam Leffler crd->crd_skip + crd->crd_len - ivlen, ivlen, 28376d161891SSam Leffler cmd->softc->sc_sessions[cmd->session_num].hs_iv); 28386d161891SSam Leffler break; 28396d161891SSam Leffler } 28406d161891SSam Leffler } 28416d161891SSam Leffler 28426d161891SSam Leffler if (macbuf != NULL) { 28436d161891SSam Leffler for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 28446d161891SSam Leffler int len; 28456d161891SSam Leffler 2846af65c53aSPawel Jakub Dawidek if (crd->crd_alg != CRYPTO_MD5 && 2847af65c53aSPawel Jakub Dawidek crd->crd_alg != CRYPTO_SHA1 && 2848af65c53aSPawel Jakub Dawidek crd->crd_alg != CRYPTO_MD5_HMAC && 2849af65c53aSPawel Jakub Dawidek crd->crd_alg != CRYPTO_SHA1_HMAC) { 28506d161891SSam Leffler continue; 2851af65c53aSPawel Jakub Dawidek } 2852af65c53aSPawel Jakub Dawidek len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; 2853f34a967bSPawel Jakub Dawidek crypto_copyback(crp->crp_flags, crp->crp_buf, 2854411da41eSPawel Jakub Dawidek crd->crd_inject, len, macbuf); 28556d161891SSam Leffler break; 28566d161891SSam Leffler } 28576d161891SSam Leffler } 28586d161891SSam Leffler 28596d161891SSam Leffler if (cmd->src_map != cmd->dst_map) { 28606d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 28616d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 28626d161891SSam Leffler } 28636d161891SSam Leffler bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 28646d161891SSam Leffler bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 28656d161891SSam Leffler free(cmd, M_DEVBUF); 28666d161891SSam Leffler crypto_done(crp); 28676d161891SSam Leffler } 28686d161891SSam Leffler 28696d161891SSam Leffler /* 28706d161891SSam Leffler * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 28716d161891SSam Leffler * and Group 1 registers; avoid conditions that could create 28726d161891SSam Leffler * burst writes by doing a read in between the writes. 28736d161891SSam Leffler * 28746d161891SSam Leffler * NB: The read we interpose is always to the same register; 28756d161891SSam Leffler * we do this because reading from an arbitrary (e.g. last) 28766d161891SSam Leffler * register may not always work. 28776d161891SSam Leffler */ 28786d161891SSam Leffler static void 28796d161891SSam Leffler hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 28806d161891SSam Leffler { 28816d161891SSam Leffler if (sc->sc_flags & HIFN_IS_7811) { 28826d161891SSam Leffler if (sc->sc_bar0_lastreg == reg - 4) 28836d161891SSam Leffler bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 28846d161891SSam Leffler sc->sc_bar0_lastreg = reg; 28856d161891SSam Leffler } 28866d161891SSam Leffler bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 28876d161891SSam Leffler } 28886d161891SSam Leffler 28896d161891SSam Leffler static void 28906d161891SSam Leffler hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 28916d161891SSam Leffler { 28926d161891SSam Leffler if (sc->sc_flags & HIFN_IS_7811) { 28936d161891SSam Leffler if (sc->sc_bar1_lastreg == reg - 4) 28946d161891SSam Leffler bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 28956d161891SSam Leffler sc->sc_bar1_lastreg = reg; 28966d161891SSam Leffler } 28976d161891SSam Leffler bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 28986d161891SSam Leffler } 28996810ad6fSSam Leffler 29006810ad6fSSam Leffler #ifdef HIFN_VULCANDEV 29016810ad6fSSam Leffler /* 29026810ad6fSSam Leffler * this code provides support for mapping the PK engine's register 29036810ad6fSSam Leffler * into a userspace program. 29046810ad6fSSam Leffler * 29056810ad6fSSam Leffler */ 29066810ad6fSSam Leffler static int 2907cfd7baceSRobert Noland vulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset, 2908cfd7baceSRobert Noland vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) 29096810ad6fSSam Leffler { 29106810ad6fSSam Leffler struct hifn_softc *sc; 29116810ad6fSSam Leffler vm_paddr_t pd; 29126810ad6fSSam Leffler void *b; 29136810ad6fSSam Leffler 29146810ad6fSSam Leffler sc = dev->si_drv1; 29156810ad6fSSam Leffler 29166810ad6fSSam Leffler pd = rman_get_start(sc->sc_bar1res); 29176810ad6fSSam Leffler b = rman_get_virtual(sc->sc_bar1res); 29186810ad6fSSam Leffler 29196810ad6fSSam Leffler #if 0 2920cfd7baceSRobert Noland printf("vpk mmap: %p(%016llx) offset=%lld\n", b, 2921cfd7baceSRobert Noland (unsigned long long)pd, offset); 29226810ad6fSSam Leffler hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0); 29236810ad6fSSam Leffler #endif 29246810ad6fSSam Leffler 29256810ad6fSSam Leffler if (offset == 0) { 29266810ad6fSSam Leffler *paddr = pd; 29276810ad6fSSam Leffler return (0); 29286810ad6fSSam Leffler } 29296810ad6fSSam Leffler return (-1); 29306810ad6fSSam Leffler } 29316810ad6fSSam Leffler 29326810ad6fSSam Leffler static struct cdevsw vulcanpk_cdevsw = { 29336810ad6fSSam Leffler .d_version = D_VERSION, 29346810ad6fSSam Leffler .d_mmap = vulcanpk_mmap, 29356810ad6fSSam Leffler .d_name = "vulcanpk", 29366810ad6fSSam Leffler }; 29376810ad6fSSam Leffler #endif /* HIFN_VULCANDEV */ 2938