154dfc97bSShailend Chand /*- 254dfc97bSShailend Chand * SPDX-License-Identifier: BSD-3-Clause 354dfc97bSShailend Chand * 454dfc97bSShailend Chand * Copyright (c) 2023 Google LLC 554dfc97bSShailend Chand * 654dfc97bSShailend Chand * Redistribution and use in source and binary forms, with or without modification, 754dfc97bSShailend Chand * are permitted provided that the following conditions are met: 854dfc97bSShailend Chand * 954dfc97bSShailend Chand * 1. Redistributions of source code must retain the above copyright notice, this 1054dfc97bSShailend Chand * list of conditions and the following disclaimer. 1154dfc97bSShailend Chand * 1254dfc97bSShailend Chand * 2. Redistributions in binary form must reproduce the above copyright notice, 1354dfc97bSShailend Chand * this list of conditions and the following disclaimer in the documentation 1454dfc97bSShailend Chand * and/or other materials provided with the distribution. 1554dfc97bSShailend Chand * 1654dfc97bSShailend Chand * 3. Neither the name of the copyright holder nor the names of its contributors 1754dfc97bSShailend Chand * may be used to endorse or promote products derived from this software without 1854dfc97bSShailend Chand * specific prior written permission. 1954dfc97bSShailend Chand * 2054dfc97bSShailend Chand * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 2154dfc97bSShailend Chand * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 2254dfc97bSShailend Chand * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 2354dfc97bSShailend Chand * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 2454dfc97bSShailend Chand * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 2554dfc97bSShailend Chand * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2654dfc97bSShailend Chand * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 2754dfc97bSShailend Chand * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2854dfc97bSShailend Chand * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 2954dfc97bSShailend Chand * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3054dfc97bSShailend Chand */ 3154dfc97bSShailend Chand #ifndef _GVE_DESC_H_ 3254dfc97bSShailend Chand #define _GVE_DESC_H_ 3354dfc97bSShailend Chand 3454dfc97bSShailend Chand #include "gve_plat.h" 3554dfc97bSShailend Chand 3654dfc97bSShailend Chand /* 3754dfc97bSShailend Chand * A note on seg_addrs 3854dfc97bSShailend Chand * 3954dfc97bSShailend Chand * Base addresses encoded in seg_addr are not assumed to be physical 4054dfc97bSShailend Chand * addresses. The ring format assumes these come from some linear address 4154dfc97bSShailend Chand * space. This could be physical memory, kernel virtual memory, user virtual 4254dfc97bSShailend Chand * memory. 4354dfc97bSShailend Chand * 4454dfc97bSShailend Chand * Each queue is assumed to be associated with a single such linear 4554dfc97bSShailend Chand * address space to ensure a consistent meaning for seg_addrs posted to its 4654dfc97bSShailend Chand * rings. 4754dfc97bSShailend Chand */ 4854dfc97bSShailend Chand struct gve_tx_pkt_desc { 4954dfc97bSShailend Chand uint8_t type_flags; /* desc type is lower 4 bits, flags upper */ 5054dfc97bSShailend Chand uint8_t l4_csum_offset; /* relative offset of L4 csum word */ 5154dfc97bSShailend Chand uint8_t l4_hdr_offset; /* Offset of start of L4 headers in packet */ 5254dfc97bSShailend Chand uint8_t desc_cnt; /* Total descriptors for this packet */ 5354dfc97bSShailend Chand __be16 len; /* Total length of this packet (in bytes) */ 5454dfc97bSShailend Chand __be16 seg_len; /* Length of this descriptor's segment */ 5554dfc97bSShailend Chand __be64 seg_addr; /* Base address (see note) of this segment */ 5654dfc97bSShailend Chand } __packed; 5754dfc97bSShailend Chand 5854dfc97bSShailend Chand struct gve_tx_mtd_desc { 5954dfc97bSShailend Chand uint8_t type_flags; /* type is lower 4 bits, subtype upper */ 6054dfc97bSShailend Chand uint8_t path_state; /* state is lower 4 bits, hash type upper */ 6154dfc97bSShailend Chand __be16 reserved0; 6254dfc97bSShailend Chand __be32 path_hash; 6354dfc97bSShailend Chand __be64 reserved1; 6454dfc97bSShailend Chand } __packed; 6554dfc97bSShailend Chand 6654dfc97bSShailend Chand struct gve_tx_seg_desc { 6754dfc97bSShailend Chand uint8_t type_flags; /* type is lower 4 bits, flags upper */ 6854dfc97bSShailend Chand uint8_t l3_offset; /* TSO: 2 byte units to start of IPH */ 6954dfc97bSShailend Chand __be16 reserved; 7054dfc97bSShailend Chand __be16 mss; /* TSO MSS */ 7154dfc97bSShailend Chand __be16 seg_len; 7254dfc97bSShailend Chand __be64 seg_addr; 7354dfc97bSShailend Chand } __packed; 7454dfc97bSShailend Chand 7554dfc97bSShailend Chand /* GVE Transmit Descriptor Types */ 7654dfc97bSShailend Chand #define GVE_TXD_STD (0x0 << 4) /* Std with Host Address */ 7754dfc97bSShailend Chand #define GVE_TXD_TSO (0x1 << 4) /* TSO with Host Address */ 7854dfc97bSShailend Chand #define GVE_TXD_SEG (0x2 << 4) /* Seg with Host Address */ 7954dfc97bSShailend Chand #define GVE_TXD_MTD (0x3 << 4) /* Metadata */ 8054dfc97bSShailend Chand 8154dfc97bSShailend Chand /* GVE Transmit Descriptor Flags for Std Pkts */ 8254dfc97bSShailend Chand #define GVE_TXF_L4CSUM BIT(0) /* Need csum offload */ 8354dfc97bSShailend Chand #define GVE_TXF_TSTAMP BIT(2) /* Timestamp required */ 8454dfc97bSShailend Chand 8554dfc97bSShailend Chand /* GVE Transmit Descriptor Flags for TSO Segs */ 8654dfc97bSShailend Chand #define GVE_TXSF_IPV6 BIT(1) /* IPv6 TSO */ 8754dfc97bSShailend Chand 8854dfc97bSShailend Chand /* GVE Transmit Descriptor Options for MTD Segs */ 8954dfc97bSShailend Chand #define GVE_MTD_SUBTYPE_PATH 0 9054dfc97bSShailend Chand 9154dfc97bSShailend Chand #define GVE_MTD_PATH_STATE_DEFAULT 0 9254dfc97bSShailend Chand #define GVE_MTD_PATH_STATE_TIMEOUT 1 9354dfc97bSShailend Chand #define GVE_MTD_PATH_STATE_CONGESTION 2 9454dfc97bSShailend Chand #define GVE_MTD_PATH_STATE_RETRANSMIT 3 9554dfc97bSShailend Chand 9654dfc97bSShailend Chand #define GVE_MTD_PATH_HASH_NONE (0x0 << 4) 9754dfc97bSShailend Chand #define GVE_MTD_PATH_HASH_L4 (0x1 << 4) 9854dfc97bSShailend Chand 9954dfc97bSShailend Chand /* 10054dfc97bSShailend Chand * GVE Receive Packet Descriptor 10154dfc97bSShailend Chand * 10254dfc97bSShailend Chand * The start of an ethernet packet comes 2 bytes into the rx buffer. 10354dfc97bSShailend Chand * gVNIC adds this padding so that both the DMA and the L3/4 protocol header 10454dfc97bSShailend Chand * access is aligned. 10554dfc97bSShailend Chand */ 10654dfc97bSShailend Chand #define GVE_RX_PAD 2 10754dfc97bSShailend Chand 10854dfc97bSShailend Chand struct gve_rx_desc { 10954dfc97bSShailend Chand uint8_t padding[48]; 11054dfc97bSShailend Chand __be32 rss_hash; /* Receive-side scaling hash (Toeplitz for gVNIC) */ 11154dfc97bSShailend Chand __be16 mss; 11254dfc97bSShailend Chand __be16 reserved; /* Reserved to zero */ 11354dfc97bSShailend Chand uint8_t hdr_len; /* Header length (L2-L4) including padding */ 11454dfc97bSShailend Chand uint8_t hdr_off; /* 64-byte-scaled offset into RX_DATA entry */ 11554dfc97bSShailend Chand uint16_t csum; /* 1's-complement partial checksum of L3+ bytes */ 11654dfc97bSShailend Chand __be16 len; /* Length of the received packet */ 11754dfc97bSShailend Chand __be16 flags_seq; /* Flags [15:3] and sequence number [2:0] (1-7) */ 11854dfc97bSShailend Chand } __packed; 11954dfc97bSShailend Chand _Static_assert(sizeof(struct gve_rx_desc) == 64, "gve: bad desc struct length"); 12054dfc97bSShailend Chand 12154dfc97bSShailend Chand /* 12254dfc97bSShailend Chand * If the device supports raw dma addressing then the addr in data slot is 12354dfc97bSShailend Chand * the dma address of the buffer. 12454dfc97bSShailend Chand * If the device only supports registered segments then the addr is a byte 12554dfc97bSShailend Chand * offset into the registered segment (an ordered list of pages) where the 12654dfc97bSShailend Chand * buffer is. 12754dfc97bSShailend Chand */ 12854dfc97bSShailend Chand union gve_rx_data_slot { 12954dfc97bSShailend Chand __be64 qpl_offset; 13054dfc97bSShailend Chand __be64 addr; 13154dfc97bSShailend Chand }; 13254dfc97bSShailend Chand 133*031800c7SJasper Tran O'Leary /* GVE Receive Packet Descriptor Seq No */ 13454dfc97bSShailend Chand #define GVE_SEQNO(x) (be16toh(x) & 0x7) 13554dfc97bSShailend Chand 136*031800c7SJasper Tran O'Leary /* GVE Receive Packet Descriptor Flags */ 13754dfc97bSShailend Chand #define GVE_RXFLG(x) htobe16(1 << (3 + (x))) 13854dfc97bSShailend Chand #define GVE_RXF_FRAG GVE_RXFLG(3) /* IP Fragment */ 13954dfc97bSShailend Chand #define GVE_RXF_IPV4 GVE_RXFLG(4) /* IPv4 */ 14054dfc97bSShailend Chand #define GVE_RXF_IPV6 GVE_RXFLG(5) /* IPv6 */ 14154dfc97bSShailend Chand #define GVE_RXF_TCP GVE_RXFLG(6) /* TCP Packet */ 14254dfc97bSShailend Chand #define GVE_RXF_UDP GVE_RXFLG(7) /* UDP Packet */ 14354dfc97bSShailend Chand #define GVE_RXF_ERR GVE_RXFLG(8) /* Packet Error Detected */ 14454dfc97bSShailend Chand #define GVE_RXF_PKT_CONT GVE_RXFLG(10) /* Multi Fragment RX packet */ 14554dfc97bSShailend Chand 14654dfc97bSShailend Chand /* GVE IRQ */ 14754dfc97bSShailend Chand #define GVE_IRQ_ACK BIT(31) 14854dfc97bSShailend Chand #define GVE_IRQ_MASK BIT(30) 14954dfc97bSShailend Chand #define GVE_IRQ_EVENT BIT(29) 15054dfc97bSShailend Chand 15154dfc97bSShailend Chand #endif /* _GVE_DESC_H_ */ 152