1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Tom Jones <tj@enoti.me> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Copyright (c) 2016 Mark Kettenis 32 * 33 * Permission to use, copy, modify, and distribute this software for any 34 * purpose with or without fee is hereby granted, provided that the above 35 * copyright notice and this permission notice appear in all copies. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 38 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 39 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 40 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 41 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 42 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 43 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 44 */ 45 #include <sys/cdefs.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/gpio.h> 50 #include <sys/clock.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/endian.h> 54 #include <sys/rman.h> 55 #include <sys/types.h> 56 #include <sys/malloc.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 61 #include <contrib/dev/acpica/include/acpi.h> 62 #include <contrib/dev/acpica/include/accommon.h> 63 64 #include <dev/acpica/acpivar.h> 65 #include <dev/gpio/gpiobusvar.h> 66 67 #include "opt_platform.h" 68 #include "opt_acpi.h" 69 #include "gpio_if.h" 70 71 #include "chvgpio_reg.h" 72 73 /* 74 * Macros for driver mutex locking 75 */ 76 #define CHVGPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 77 #define CHVGPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 78 #define CHVGPIO_LOCK_INIT(_sc) \ 79 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 80 "chvgpio", MTX_SPIN) 81 #define CHVGPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 82 #define CHVGPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 83 #define CHVGPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 84 85 struct chvgpio_softc { 86 device_t sc_dev; 87 device_t sc_busdev; 88 struct mtx sc_mtx; 89 90 ACPI_HANDLE sc_handle; 91 92 int sc_mem_rid; 93 struct resource *sc_mem_res; 94 95 int sc_irq_rid; 96 struct resource *sc_irq_res; 97 void *intr_handle; 98 99 const char *sc_bank_prefix; 100 const int *sc_pins; 101 int sc_npins; 102 int sc_ngroups; 103 const char **sc_pin_names; 104 }; 105 106 static void chvgpio_intr(void *); 107 static int chvgpio_probe(device_t); 108 static int chvgpio_attach(device_t); 109 static int chvgpio_detach(device_t); 110 111 static inline int 112 chvgpio_pad_cfg0_offset(int pin) 113 { 114 return (CHVGPIO_PAD_CFG0 + 1024 * (pin / 15) + 8 * (pin % 15)); 115 } 116 117 static inline int 118 chvgpio_read_pad_cfg0(struct chvgpio_softc *sc, int pin) 119 { 120 return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin)); 121 } 122 123 static inline void 124 chvgpio_write_pad_cfg0(struct chvgpio_softc *sc, int pin, uint32_t val) 125 { 126 bus_write_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin), val); 127 } 128 129 static inline int 130 chvgpio_read_pad_cfg1(struct chvgpio_softc *sc, int pin) 131 { 132 return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin) + 4); 133 } 134 135 static device_t 136 chvgpio_get_bus(device_t dev) 137 { 138 struct chvgpio_softc *sc; 139 140 sc = device_get_softc(dev); 141 142 return (sc->sc_busdev); 143 } 144 145 static int 146 chvgpio_pin_max(device_t dev, int *maxpin) 147 { 148 struct chvgpio_softc *sc; 149 150 sc = device_get_softc(dev); 151 152 *maxpin = sc->sc_npins - 1; 153 154 return (0); 155 } 156 157 static int 158 chvgpio_valid_pin(struct chvgpio_softc *sc, int pin) 159 { 160 if (pin < 0) 161 return EINVAL; 162 if ((pin / 15) >= sc->sc_ngroups) 163 return EINVAL; 164 if ((pin % 15) >= sc->sc_pins[pin / 15]) 165 return EINVAL; 166 return (0); 167 } 168 169 static int 170 chvgpio_pin_getname(device_t dev, uint32_t pin, char *name) 171 { 172 struct chvgpio_softc *sc; 173 174 sc = device_get_softc(dev); 175 if (chvgpio_valid_pin(sc, pin) != 0) 176 return (EINVAL); 177 178 /* return pin name from datasheet */ 179 snprintf(name, GPIOMAXNAME, "%s", sc->sc_pin_names[pin]); 180 name[GPIOMAXNAME - 1] = '\0'; 181 return (0); 182 } 183 184 static int 185 chvgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 186 { 187 struct chvgpio_softc *sc; 188 189 sc = device_get_softc(dev); 190 if (chvgpio_valid_pin(sc, pin) != 0) 191 return (EINVAL); 192 193 *caps = 0; 194 if (chvgpio_valid_pin(sc, pin)) 195 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 196 197 return (0); 198 } 199 200 static int 201 chvgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 202 { 203 struct chvgpio_softc *sc; 204 uint32_t val; 205 206 sc = device_get_softc(dev); 207 if (chvgpio_valid_pin(sc, pin) != 0) 208 return (EINVAL); 209 210 *flags = 0; 211 212 /* Get the current pin state */ 213 CHVGPIO_LOCK(sc); 214 val = chvgpio_read_pad_cfg0(sc, pin); 215 216 if (val & CHVGPIO_PAD_CFG0_GPIOCFG_GPIO || 217 val & CHVGPIO_PAD_CFG0_GPIOCFG_GPO) 218 *flags |= GPIO_PIN_OUTPUT; 219 220 if (val & CHVGPIO_PAD_CFG0_GPIOCFG_GPIO || 221 val & CHVGPIO_PAD_CFG0_GPIOCFG_GPI) 222 *flags |= GPIO_PIN_INPUT; 223 224 val = chvgpio_read_pad_cfg1(sc, pin); 225 226 CHVGPIO_UNLOCK(sc); 227 return (0); 228 } 229 230 static int 231 chvgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 232 { 233 struct chvgpio_softc *sc; 234 uint32_t val; 235 uint32_t allowed; 236 237 sc = device_get_softc(dev); 238 if (chvgpio_valid_pin(sc, pin) != 0) 239 return (EINVAL); 240 241 allowed = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 242 243 /* 244 * Only direction flag allowed 245 */ 246 if (flags & ~allowed) 247 return (EINVAL); 248 249 /* 250 * Not both directions simultaneously 251 */ 252 if ((flags & allowed) == allowed) 253 return (EINVAL); 254 255 /* Set the GPIO mode and state */ 256 CHVGPIO_LOCK(sc); 257 val = chvgpio_read_pad_cfg0(sc, pin); 258 if (flags & GPIO_PIN_INPUT) 259 val = val & CHVGPIO_PAD_CFG0_GPIOCFG_GPI; 260 if (flags & GPIO_PIN_OUTPUT) 261 val = val & CHVGPIO_PAD_CFG0_GPIOCFG_GPO; 262 chvgpio_write_pad_cfg0(sc, pin, val); 263 CHVGPIO_UNLOCK(sc); 264 265 return (0); 266 } 267 268 static int 269 chvgpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 270 { 271 struct chvgpio_softc *sc; 272 uint32_t val; 273 274 sc = device_get_softc(dev); 275 if (chvgpio_valid_pin(sc, pin) != 0) 276 return (EINVAL); 277 278 CHVGPIO_LOCK(sc); 279 val = chvgpio_read_pad_cfg0(sc, pin); 280 if (value == GPIO_PIN_LOW) 281 val = val & ~CHVGPIO_PAD_CFG0_GPIOTXSTATE; 282 else 283 val = val | CHVGPIO_PAD_CFG0_GPIOTXSTATE; 284 chvgpio_write_pad_cfg0(sc, pin, val); 285 CHVGPIO_UNLOCK(sc); 286 287 return (0); 288 } 289 290 static int 291 chvgpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 292 { 293 struct chvgpio_softc *sc; 294 uint32_t val; 295 296 sc = device_get_softc(dev); 297 if (chvgpio_valid_pin(sc, pin) != 0) 298 return (EINVAL); 299 300 CHVGPIO_LOCK(sc); 301 302 /* Read pin value */ 303 val = chvgpio_read_pad_cfg0(sc, pin); 304 if (val & CHVGPIO_PAD_CFG0_GPIORXSTATE) 305 *value = GPIO_PIN_HIGH; 306 else 307 *value = GPIO_PIN_LOW; 308 309 CHVGPIO_UNLOCK(sc); 310 311 return (0); 312 } 313 314 static int 315 chvgpio_pin_toggle(device_t dev, uint32_t pin) 316 { 317 struct chvgpio_softc *sc; 318 uint32_t val; 319 320 sc = device_get_softc(dev); 321 if (chvgpio_valid_pin(sc, pin) != 0) 322 return (EINVAL); 323 324 CHVGPIO_LOCK(sc); 325 326 /* Toggle the pin */ 327 val = chvgpio_read_pad_cfg0(sc, pin); 328 val = val ^ CHVGPIO_PAD_CFG0_GPIOTXSTATE; 329 chvgpio_write_pad_cfg0(sc, pin, val); 330 331 CHVGPIO_UNLOCK(sc); 332 333 return (0); 334 } 335 336 static char *chvgpio_hids[] = { 337 "INT33FF", 338 NULL 339 }; 340 341 static int 342 chvgpio_probe(device_t dev) 343 { 344 int rv; 345 346 if (acpi_disabled("chvgpio")) 347 return (ENXIO); 348 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, chvgpio_hids, NULL); 349 if (rv <= 0) 350 device_set_desc(dev, "Intel Cherry View GPIO"); 351 return (rv); 352 } 353 354 static int 355 chvgpio_attach(device_t dev) 356 { 357 struct chvgpio_softc *sc; 358 ACPI_STATUS status; 359 int uid; 360 int i; 361 int error; 362 363 sc = device_get_softc(dev); 364 sc->sc_dev = dev; 365 sc->sc_handle = acpi_get_handle(dev); 366 367 status = acpi_GetInteger(sc->sc_handle, "_UID", &uid); 368 if (ACPI_FAILURE(status)) { 369 device_printf(dev, "failed to read _UID\n"); 370 return (ENXIO); 371 } 372 373 CHVGPIO_LOCK_INIT(sc); 374 375 switch (uid) { 376 case SW_UID: 377 sc->sc_bank_prefix = SW_BANK_PREFIX; 378 sc->sc_pins = chv_southwest_pins; 379 sc->sc_pin_names = chv_southwest_pin_names; 380 break; 381 case N_UID: 382 sc->sc_bank_prefix = N_BANK_PREFIX; 383 sc->sc_pins = chv_north_pins; 384 sc->sc_pin_names = chv_north_pin_names; 385 break; 386 case E_UID: 387 sc->sc_bank_prefix = E_BANK_PREFIX; 388 sc->sc_pins = chv_east_pins; 389 sc->sc_pin_names = chv_east_pin_names; 390 break; 391 case SE_UID: 392 sc->sc_bank_prefix = SE_BANK_PREFIX; 393 sc->sc_pins = chv_southeast_pins; 394 sc->sc_pin_names = chv_southeast_pin_names; 395 break; 396 default: 397 device_printf(dev, "invalid _UID value: %d\n", uid); 398 return (ENXIO); 399 } 400 401 for (i = 0; sc->sc_pins[i] >= 0; i++) { 402 sc->sc_npins += sc->sc_pins[i]; 403 sc->sc_ngroups++; 404 } 405 406 sc->sc_mem_rid = 0; 407 sc->sc_mem_res = bus_alloc_resource_any(sc->sc_dev, SYS_RES_MEMORY, 408 &sc->sc_mem_rid, RF_ACTIVE); 409 if (sc->sc_mem_res == NULL) { 410 CHVGPIO_LOCK_DESTROY(sc); 411 device_printf(dev, "can't allocate memory resource\n"); 412 return (ENOMEM); 413 } 414 415 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 416 &sc->sc_irq_rid, RF_ACTIVE); 417 418 if (!sc->sc_irq_res) { 419 CHVGPIO_LOCK_DESTROY(sc); 420 bus_release_resource(dev, SYS_RES_MEMORY, 421 sc->sc_mem_rid, sc->sc_mem_res); 422 device_printf(dev, "can't allocate irq resource\n"); 423 return (ENOMEM); 424 } 425 426 error = bus_setup_intr(sc->sc_dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 427 NULL, chvgpio_intr, sc, &sc->intr_handle); 428 429 430 if (error) { 431 device_printf(sc->sc_dev, "unable to setup irq: error %d\n", error); 432 CHVGPIO_LOCK_DESTROY(sc); 433 bus_release_resource(dev, SYS_RES_MEMORY, 434 sc->sc_mem_rid, sc->sc_mem_res); 435 bus_release_resource(dev, SYS_RES_IRQ, 436 sc->sc_irq_rid, sc->sc_irq_res); 437 return (ENXIO); 438 } 439 440 /* Mask and ack all interrupts. */ 441 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_MASK, 0); 442 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 0xffff); 443 444 sc->sc_busdev = gpiobus_attach_bus(dev); 445 if (sc->sc_busdev == NULL) { 446 CHVGPIO_LOCK_DESTROY(sc); 447 bus_release_resource(dev, SYS_RES_MEMORY, 448 sc->sc_mem_rid, sc->sc_mem_res); 449 bus_release_resource(dev, SYS_RES_IRQ, 450 sc->sc_irq_rid, sc->sc_irq_res); 451 return (ENXIO); 452 } 453 454 return (0); 455 } 456 457 static void 458 chvgpio_intr(void *arg) 459 { 460 struct chvgpio_softc *sc = arg; 461 uint32_t reg; 462 int line; 463 464 reg = bus_read_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS); 465 for (line = 0; line < 16; line++) { 466 if ((reg & (1 << line)) == 0) 467 continue; 468 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 1 << line); 469 } 470 } 471 472 static int 473 chvgpio_detach(device_t dev) 474 { 475 struct chvgpio_softc *sc; 476 sc = device_get_softc(dev); 477 478 if (sc->sc_busdev) 479 gpiobus_detach_bus(dev); 480 481 if (sc->intr_handle != NULL) 482 bus_teardown_intr(sc->sc_dev, sc->sc_irq_res, sc->intr_handle); 483 if (sc->sc_irq_res != NULL) 484 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, sc->sc_irq_res); 485 if (sc->sc_mem_res != NULL) 486 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, sc->sc_mem_res); 487 488 CHVGPIO_LOCK_DESTROY(sc); 489 490 return (0); 491 } 492 493 static device_method_t chvgpio_methods[] = { 494 DEVMETHOD(device_probe, chvgpio_probe), 495 DEVMETHOD(device_attach, chvgpio_attach), 496 DEVMETHOD(device_detach, chvgpio_detach), 497 498 /* GPIO protocol */ 499 DEVMETHOD(gpio_get_bus, chvgpio_get_bus), 500 DEVMETHOD(gpio_pin_max, chvgpio_pin_max), 501 DEVMETHOD(gpio_pin_getname, chvgpio_pin_getname), 502 DEVMETHOD(gpio_pin_getflags, chvgpio_pin_getflags), 503 DEVMETHOD(gpio_pin_getcaps, chvgpio_pin_getcaps), 504 DEVMETHOD(gpio_pin_setflags, chvgpio_pin_setflags), 505 DEVMETHOD(gpio_pin_get, chvgpio_pin_get), 506 DEVMETHOD(gpio_pin_set, chvgpio_pin_set), 507 DEVMETHOD(gpio_pin_toggle, chvgpio_pin_toggle), 508 509 DEVMETHOD_END 510 }; 511 512 static driver_t chvgpio_driver = { 513 .name = "gpio", 514 .methods = chvgpio_methods, 515 .size = sizeof(struct chvgpio_softc) 516 }; 517 518 DRIVER_MODULE(chvgpio, acpi, chvgpio_driver, NULL, NULL); 519 MODULE_DEPEND(chvgpio, acpi, 1, 1, 1); 520 MODULE_DEPEND(chvgpio, gpiobus, 1, 1, 1); 521 522 MODULE_VERSION(chvgpio, 1); 523