1 /* $OpenBSD: glxsb.c,v 1.7 2007/02/12 14:31:45 tom Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Tom Cosgrove <tom@openbsd.org> 5 * Copyright (c) 2003, 2004 Theo de Raadt 6 * Copyright (c) 2003 Jason Wright 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for the security block on the AMD Geode LX processors 23 * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234d_lx_ds.pdf 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/errno.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/mbuf.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/proc.h> 40 #include <sys/random.h> 41 #include <sys/rman.h> 42 #include <sys/rwlock.h> 43 #include <sys/sysctl.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/cpufunc.h> 48 #include <machine/resource.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <opencrypto/cryptodev.h> 54 #include <opencrypto/xform.h> 55 56 #include "cryptodev_if.h" 57 #include "glxsb.h" 58 59 #define PCI_VENDOR_AMD 0x1022 /* AMD */ 60 #define PCI_PRODUCT_AMD_GEODE_LX_CRYPTO 0x2082 /* Geode LX Crypto */ 61 62 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */ 63 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */ 64 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */ 65 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */ 66 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */ 67 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */ 68 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */ 69 70 /* For GLD_MSR_CTRL: */ 71 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */ 72 #define SB_GMC_DIV1 0x0001 73 #define SB_GMC_DIV2 0x0002 74 #define SB_GMC_DIV3 0x0003 75 #define SB_GMC_DIV_MASK 0x0003 76 #define SB_GMC_SBI 0x0004 /* AES swap bits */ 77 #define SB_GMC_SBY 0x0008 /* AES swap bytes */ 78 #define SB_GMC_TW 0x0010 /* Time write (EEPROM) */ 79 #define SB_GMC_T_SEL0 0x0000 /* RNG post-proc: none */ 80 #define SB_GMC_T_SEL1 0x0100 /* RNG post-proc: LFSR */ 81 #define SB_GMC_T_SEL2 0x0200 /* RNG post-proc: whitener */ 82 #define SB_GMC_T_SEL3 0x0300 /* RNG LFSR+whitener */ 83 #define SB_GMC_T_SEL_MASK 0x0300 84 #define SB_GMC_T_NE 0x0400 /* Noise (generator) Enable */ 85 #define SB_GMC_T_TM 0x0800 /* RNG test mode */ 86 /* (deterministic) */ 87 88 /* Security Block configuration/control registers (offsets from base) */ 89 #define SB_CTL_A 0x0000 /* RW - SB Control A */ 90 #define SB_CTL_B 0x0004 /* RW - SB Control B */ 91 #define SB_AES_INT 0x0008 /* RW - SB AES Interrupt */ 92 #define SB_SOURCE_A 0x0010 /* RW - Source A */ 93 #define SB_DEST_A 0x0014 /* RW - Destination A */ 94 #define SB_LENGTH_A 0x0018 /* RW - Length A */ 95 #define SB_SOURCE_B 0x0020 /* RW - Source B */ 96 #define SB_DEST_B 0x0024 /* RW - Destination B */ 97 #define SB_LENGTH_B 0x0028 /* RW - Length B */ 98 #define SB_WKEY 0x0030 /* WO - Writable Key 0-3 */ 99 #define SB_WKEY_0 0x0030 /* WO - Writable Key 0 */ 100 #define SB_WKEY_1 0x0034 /* WO - Writable Key 1 */ 101 #define SB_WKEY_2 0x0038 /* WO - Writable Key 2 */ 102 #define SB_WKEY_3 0x003C /* WO - Writable Key 3 */ 103 #define SB_CBC_IV 0x0040 /* RW - CBC IV 0-3 */ 104 #define SB_CBC_IV_0 0x0040 /* RW - CBC IV 0 */ 105 #define SB_CBC_IV_1 0x0044 /* RW - CBC IV 1 */ 106 #define SB_CBC_IV_2 0x0048 /* RW - CBC IV 2 */ 107 #define SB_CBC_IV_3 0x004C /* RW - CBC IV 3 */ 108 #define SB_RANDOM_NUM 0x0050 /* RW - Random Number */ 109 #define SB_RANDOM_NUM_STATUS 0x0054 /* RW - Random Number Status */ 110 #define SB_EEPROM_COMM 0x0800 /* RW - EEPROM Command */ 111 #define SB_EEPROM_ADDR 0x0804 /* RW - EEPROM Address */ 112 #define SB_EEPROM_DATA 0x0808 /* RW - EEPROM Data */ 113 #define SB_EEPROM_SEC_STATE 0x080C /* RW - EEPROM Security State */ 114 115 /* For SB_CTL_A and _B */ 116 #define SB_CTL_ST 0x0001 /* Start operation (enc/dec) */ 117 #define SB_CTL_ENC 0x0002 /* Encrypt (0 is decrypt) */ 118 #define SB_CTL_DEC 0x0000 /* Decrypt */ 119 #define SB_CTL_WK 0x0004 /* Use writable key (we set) */ 120 #define SB_CTL_DC 0x0008 /* Destination coherent */ 121 #define SB_CTL_SC 0x0010 /* Source coherent */ 122 #define SB_CTL_CBC 0x0020 /* CBC (0 is ECB) */ 123 124 /* For SB_AES_INT */ 125 #define SB_AI_DISABLE_AES_A 0x0001 /* Disable AES A compl int */ 126 #define SB_AI_ENABLE_AES_A 0x0000 /* Enable AES A compl int */ 127 #define SB_AI_DISABLE_AES_B 0x0002 /* Disable AES B compl int */ 128 #define SB_AI_ENABLE_AES_B 0x0000 /* Enable AES B compl int */ 129 #define SB_AI_DISABLE_EEPROM 0x0004 /* Disable EEPROM op comp int */ 130 #define SB_AI_ENABLE_EEPROM 0x0000 /* Enable EEPROM op compl int */ 131 #define SB_AI_AES_A_COMPLETE 0x10000 /* AES A operation complete */ 132 #define SB_AI_AES_B_COMPLETE 0x20000 /* AES B operation complete */ 133 #define SB_AI_EEPROM_COMPLETE 0x40000 /* EEPROM operation complete */ 134 135 #define SB_AI_CLEAR_INTR \ 136 (SB_AI_DISABLE_AES_A | SB_AI_DISABLE_AES_B |\ 137 SB_AI_DISABLE_EEPROM | SB_AI_AES_A_COMPLETE |\ 138 SB_AI_AES_B_COMPLETE | SB_AI_EEPROM_COMPLETE) 139 140 #define SB_RNS_TRNG_VALID 0x0001 /* in SB_RANDOM_NUM_STATUS */ 141 142 #define SB_MEM_SIZE 0x0810 /* Size of memory block */ 143 144 #define SB_AES_ALIGN 0x0010 /* Source and dest buffers */ 145 /* must be 16-byte aligned */ 146 #define SB_AES_BLOCK_SIZE 0x0010 147 148 /* 149 * The Geode LX security block AES acceleration doesn't perform scatter- 150 * gather: it just takes source and destination addresses. Therefore the 151 * plain- and ciphertexts need to be contiguous. To this end, we allocate 152 * a buffer for both, and accept the overhead of copying in and out. If 153 * the number of bytes in one operation is bigger than allowed for by the 154 * buffer (buffer is twice the size of the max length, as it has both input 155 * and output) then we have to perform multiple encryptions/decryptions. 156 */ 157 158 #define GLXSB_MAX_AES_LEN 16384 159 160 MALLOC_DEFINE(M_GLXSB, "glxsb_data", "Glxsb Data"); 161 162 struct glxsb_dma_map { 163 bus_dmamap_t dma_map; /* DMA map */ 164 bus_dma_segment_t dma_seg; /* segments */ 165 int dma_nsegs; /* #segments */ 166 int dma_size; /* size */ 167 caddr_t dma_vaddr; /* virtual address */ 168 bus_addr_t dma_paddr; /* physical address */ 169 }; 170 171 struct glxsb_taskop { 172 struct glxsb_session *to_ses; /* crypto session */ 173 struct cryptop *to_crp; /* cryptop to perfom */ 174 }; 175 176 struct glxsb_softc { 177 device_t sc_dev; /* device backpointer */ 178 struct resource *sc_sr; /* resource */ 179 int sc_rid; /* resource rid */ 180 struct callout sc_rngco; /* RNG callout */ 181 int sc_rnghz; /* RNG callout ticks */ 182 bus_dma_tag_t sc_dmat; /* DMA tag */ 183 struct glxsb_dma_map sc_dma; /* DMA map */ 184 int32_t sc_cid; /* crypto tag */ 185 struct mtx sc_task_mtx; /* task mutex */ 186 struct taskqueue *sc_tq; /* task queue */ 187 struct task sc_cryptotask; /* task */ 188 struct glxsb_taskop sc_to; /* task's crypto operation */ 189 int sc_task_count; /* tasks count */ 190 }; 191 192 static int glxsb_probe(device_t); 193 static int glxsb_attach(device_t); 194 static int glxsb_detach(device_t); 195 196 static void glxsb_dmamap_cb(void *, bus_dma_segment_t *, int, int); 197 static int glxsb_dma_alloc(struct glxsb_softc *); 198 static void glxsb_dma_pre_op(struct glxsb_softc *, struct glxsb_dma_map *); 199 static void glxsb_dma_post_op(struct glxsb_softc *, struct glxsb_dma_map *); 200 static void glxsb_dma_free(struct glxsb_softc *, struct glxsb_dma_map *); 201 202 static void glxsb_rnd(void *); 203 static int glxsb_crypto_setup(struct glxsb_softc *); 204 static int glxsb_crypto_probesession(device_t, 205 const struct crypto_session_params *); 206 static int glxsb_crypto_newsession(device_t, crypto_session_t, 207 const struct crypto_session_params *); 208 static void glxsb_crypto_freesession(device_t, crypto_session_t); 209 static int glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t, 210 uint32_t, const void *, int, const void *); 211 212 static int glxsb_crypto_encdec(struct cryptop *, struct glxsb_session *, 213 struct glxsb_softc *); 214 215 static void glxsb_crypto_task(void *, int); 216 static int glxsb_crypto_process(device_t, struct cryptop *, int); 217 218 static device_method_t glxsb_methods[] = { 219 /* device interface */ 220 DEVMETHOD(device_probe, glxsb_probe), 221 DEVMETHOD(device_attach, glxsb_attach), 222 DEVMETHOD(device_detach, glxsb_detach), 223 224 /* crypto device methods */ 225 DEVMETHOD(cryptodev_probesession, glxsb_crypto_probesession), 226 DEVMETHOD(cryptodev_newsession, glxsb_crypto_newsession), 227 DEVMETHOD(cryptodev_freesession, glxsb_crypto_freesession), 228 DEVMETHOD(cryptodev_process, glxsb_crypto_process), 229 230 {0,0} 231 }; 232 233 static driver_t glxsb_driver = { 234 "glxsb", 235 glxsb_methods, 236 sizeof(struct glxsb_softc) 237 }; 238 239 static devclass_t glxsb_devclass; 240 241 DRIVER_MODULE(glxsb, pci, glxsb_driver, glxsb_devclass, 0, 0); 242 MODULE_VERSION(glxsb, 1); 243 MODULE_DEPEND(glxsb, crypto, 1, 1, 1); 244 245 static int 246 glxsb_probe(device_t dev) 247 { 248 249 if (pci_get_vendor(dev) == PCI_VENDOR_AMD && 250 pci_get_device(dev) == PCI_PRODUCT_AMD_GEODE_LX_CRYPTO) { 251 device_set_desc(dev, 252 "AMD Geode LX Security Block (AES-128-CBC, RNG)"); 253 return (BUS_PROBE_DEFAULT); 254 } 255 256 return (ENXIO); 257 } 258 259 static int 260 glxsb_attach(device_t dev) 261 { 262 struct glxsb_softc *sc = device_get_softc(dev); 263 uint64_t msr; 264 265 sc->sc_dev = dev; 266 msr = rdmsr(SB_GLD_MSR_CAP); 267 268 if ((msr & 0xFFFF00) != 0x130400) { 269 device_printf(dev, "unknown ID 0x%x\n", 270 (int)((msr & 0xFFFF00) >> 16)); 271 return (ENXIO); 272 } 273 274 pci_enable_busmaster(dev); 275 276 /* Map in the security block configuration/control registers */ 277 sc->sc_rid = PCIR_BAR(0); 278 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 279 RF_ACTIVE); 280 if (sc->sc_sr == NULL) { 281 device_printf(dev, "cannot map register space\n"); 282 return (ENXIO); 283 } 284 285 /* 286 * Configure the Security Block. 287 * 288 * We want to enable the noise generator (T_NE), and enable the 289 * linear feedback shift register and whitener post-processing 290 * (T_SEL = 3). Also ensure that test mode (deterministic values) 291 * is disabled. 292 */ 293 msr = rdmsr(SB_GLD_MSR_CTRL); 294 msr &= ~(SB_GMC_T_TM | SB_GMC_T_SEL_MASK); 295 msr |= SB_GMC_T_NE | SB_GMC_T_SEL3; 296 #if 0 297 msr |= SB_GMC_SBI | SB_GMC_SBY; /* for AES, if necessary */ 298 #endif 299 wrmsr(SB_GLD_MSR_CTRL, msr); 300 301 /* Disable interrupts */ 302 bus_write_4(sc->sc_sr, SB_AES_INT, SB_AI_CLEAR_INTR); 303 304 /* Allocate a contiguous DMA-able buffer to work in */ 305 if (glxsb_dma_alloc(sc) != 0) 306 goto fail0; 307 308 /* Initialize our task queue */ 309 sc->sc_tq = taskqueue_create("glxsb_taskq", M_NOWAIT | M_ZERO, 310 taskqueue_thread_enqueue, &sc->sc_tq); 311 if (sc->sc_tq == NULL) { 312 device_printf(dev, "cannot create task queue\n"); 313 goto fail0; 314 } 315 if (taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 316 device_get_nameunit(dev)) != 0) { 317 device_printf(dev, "cannot start task queue\n"); 318 goto fail1; 319 } 320 TASK_INIT(&sc->sc_cryptotask, 0, glxsb_crypto_task, sc); 321 322 /* Initialize crypto */ 323 if (glxsb_crypto_setup(sc) != 0) 324 goto fail1; 325 326 /* Install a periodic collector for the "true" (AMD's word) RNG */ 327 if (hz > 100) 328 sc->sc_rnghz = hz / 100; 329 else 330 sc->sc_rnghz = 1; 331 callout_init(&sc->sc_rngco, 1); 332 glxsb_rnd(sc); 333 334 return (0); 335 336 fail1: 337 taskqueue_free(sc->sc_tq); 338 fail0: 339 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr); 340 return (ENXIO); 341 } 342 343 static int 344 glxsb_detach(device_t dev) 345 { 346 struct glxsb_softc *sc = device_get_softc(dev); 347 348 crypto_unregister_all(sc->sc_cid); 349 350 callout_drain(&sc->sc_rngco); 351 taskqueue_drain(sc->sc_tq, &sc->sc_cryptotask); 352 bus_generic_detach(dev); 353 glxsb_dma_free(sc, &sc->sc_dma); 354 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr); 355 taskqueue_free(sc->sc_tq); 356 mtx_destroy(&sc->sc_task_mtx); 357 return (0); 358 } 359 360 /* 361 * callback for bus_dmamap_load() 362 */ 363 static void 364 glxsb_dmamap_cb(void *arg, bus_dma_segment_t *seg, int nseg, int error) 365 { 366 367 bus_addr_t *paddr = (bus_addr_t*) arg; 368 *paddr = seg[0].ds_addr; 369 } 370 371 static int 372 glxsb_dma_alloc(struct glxsb_softc *sc) 373 { 374 struct glxsb_dma_map *dma = &sc->sc_dma; 375 int rc; 376 377 dma->dma_nsegs = 1; 378 dma->dma_size = GLXSB_MAX_AES_LEN * 2; 379 380 /* Setup DMA descriptor area */ 381 rc = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 382 SB_AES_ALIGN, 0, /* alignments, bounds */ 383 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 384 BUS_SPACE_MAXADDR, /* highaddr */ 385 NULL, NULL, /* filter, filterarg */ 386 dma->dma_size, /* maxsize */ 387 dma->dma_nsegs, /* nsegments */ 388 dma->dma_size, /* maxsegsize */ 389 BUS_DMA_ALLOCNOW, /* flags */ 390 NULL, NULL, /* lockfunc, lockarg */ 391 &sc->sc_dmat); 392 if (rc != 0) { 393 device_printf(sc->sc_dev, 394 "cannot allocate DMA tag (%d)\n", rc); 395 return (rc); 396 } 397 398 rc = bus_dmamem_alloc(sc->sc_dmat, (void **)&dma->dma_vaddr, 399 BUS_DMA_NOWAIT, &dma->dma_map); 400 if (rc != 0) { 401 device_printf(sc->sc_dev, 402 "cannot allocate DMA memory of %d bytes (%d)\n", 403 dma->dma_size, rc); 404 goto fail0; 405 } 406 407 rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 408 dma->dma_size, glxsb_dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT); 409 if (rc != 0) { 410 device_printf(sc->sc_dev, 411 "cannot load DMA memory for %d bytes (%d)\n", 412 dma->dma_size, rc); 413 goto fail1; 414 } 415 416 return (0); 417 418 fail1: 419 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); 420 fail0: 421 bus_dma_tag_destroy(sc->sc_dmat); 422 return (rc); 423 } 424 425 static void 426 glxsb_dma_pre_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 427 { 428 429 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 430 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 431 } 432 433 static void 434 glxsb_dma_post_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 435 { 436 437 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 438 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 439 } 440 441 static void 442 glxsb_dma_free(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 443 { 444 445 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 446 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); 447 bus_dma_tag_destroy(sc->sc_dmat); 448 } 449 450 static void 451 glxsb_rnd(void *v) 452 { 453 struct glxsb_softc *sc = v; 454 uint32_t status, value; 455 456 status = bus_read_4(sc->sc_sr, SB_RANDOM_NUM_STATUS); 457 if (status & SB_RNS_TRNG_VALID) { 458 value = bus_read_4(sc->sc_sr, SB_RANDOM_NUM); 459 /* feed with one uint32 */ 460 /* MarkM: FIX!! Check that this does not swamp the harvester! */ 461 random_harvest_queue(&value, sizeof(value), RANDOM_PURE_GLXSB); 462 } 463 464 callout_reset(&sc->sc_rngco, sc->sc_rnghz, glxsb_rnd, sc); 465 } 466 467 static int 468 glxsb_crypto_setup(struct glxsb_softc *sc) 469 { 470 471 sc->sc_cid = crypto_get_driverid(sc->sc_dev, 472 sizeof(struct glxsb_session), CRYPTOCAP_F_HARDWARE); 473 474 if (sc->sc_cid < 0) { 475 device_printf(sc->sc_dev, "cannot get crypto driver id\n"); 476 return (ENOMEM); 477 } 478 479 mtx_init(&sc->sc_task_mtx, "glxsb_crypto_mtx", NULL, MTX_DEF); 480 481 return (0); 482 } 483 484 static int 485 glxsb_crypto_probesession(device_t dev, const struct crypto_session_params *csp) 486 { 487 488 if (csp->csp_flags != 0) 489 return (EINVAL); 490 491 /* 492 * We only support HMAC algorithms to be able to work with 493 * ipsec(4), so if we are asked only for authentication without 494 * encryption, don't pretend we can accelerate it. 495 */ 496 switch (csp->csp_mode) { 497 case CSP_MODE_ETA: 498 switch (csp->csp_auth_alg) { 499 case CRYPTO_NULL_HMAC: 500 case CRYPTO_SHA1_HMAC: 501 case CRYPTO_RIPEMD160_HMAC: 502 case CRYPTO_SHA2_256_HMAC: 503 case CRYPTO_SHA2_384_HMAC: 504 case CRYPTO_SHA2_512_HMAC: 505 break; 506 default: 507 return (EINVAL); 508 } 509 /* FALLTHROUGH */ 510 case CSP_MODE_CIPHER: 511 switch (csp->csp_cipher_alg) { 512 case CRYPTO_AES_CBC: 513 if (csp->csp_cipher_klen * 8 != 128) 514 return (EINVAL); 515 break; 516 default: 517 return (EINVAL); 518 } 519 default: 520 return (EINVAL); 521 } 522 return (CRYPTODEV_PROBE_HARDWARE); 523 } 524 525 static int 526 glxsb_crypto_newsession(device_t dev, crypto_session_t cses, 527 const struct crypto_session_params *csp) 528 { 529 struct glxsb_softc *sc = device_get_softc(dev); 530 struct glxsb_session *ses; 531 int error; 532 533 ses = crypto_get_driver_session(cses); 534 535 /* Copy the key (Geode LX wants the primary key only) */ 536 if (csp->csp_cipher_key != NULL) 537 bcopy(csp->csp_cipher_key, ses->ses_key, sizeof(ses->ses_key)); 538 539 if (csp->csp_auth_alg != 0) { 540 error = glxsb_hash_setup(ses, csp); 541 if (error != 0) { 542 glxsb_crypto_freesession(sc->sc_dev, cses); 543 return (error); 544 } 545 } 546 547 return (0); 548 } 549 550 static void 551 glxsb_crypto_freesession(device_t dev, crypto_session_t cses) 552 { 553 struct glxsb_session *ses; 554 555 ses = crypto_get_driver_session(cses); 556 glxsb_hash_free(ses); 557 } 558 559 static int 560 glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc, 561 uint32_t pdst, const void *key, int len, const void *iv) 562 { 563 uint32_t status; 564 int i; 565 566 if (len & 0xF) { 567 device_printf(sc->sc_dev, 568 "len must be a multiple of 16 (not %d)\n", len); 569 return (EINVAL); 570 } 571 572 /* Set the source */ 573 bus_write_4(sc->sc_sr, SB_SOURCE_A, psrc); 574 575 /* Set the destination address */ 576 bus_write_4(sc->sc_sr, SB_DEST_A, pdst); 577 578 /* Set the data length */ 579 bus_write_4(sc->sc_sr, SB_LENGTH_A, len); 580 581 /* Set the IV */ 582 if (iv != NULL) { 583 bus_write_region_4(sc->sc_sr, SB_CBC_IV, iv, 4); 584 control |= SB_CTL_CBC; 585 } 586 587 /* Set the key */ 588 bus_write_region_4(sc->sc_sr, SB_WKEY, key, 4); 589 590 /* Ask the security block to do it */ 591 bus_write_4(sc->sc_sr, SB_CTL_A, 592 control | SB_CTL_WK | SB_CTL_DC | SB_CTL_SC | SB_CTL_ST); 593 594 /* 595 * Now wait until it is done. 596 * 597 * We do a busy wait. Obviously the number of iterations of 598 * the loop required to perform the AES operation depends upon 599 * the number of bytes to process. 600 * 601 * On a 500 MHz Geode LX we see 602 * 603 * length (bytes) typical max iterations 604 * 16 12 605 * 64 22 606 * 256 59 607 * 1024 212 608 * 8192 1,537 609 * 610 * Since we have a maximum size of operation defined in 611 * GLXSB_MAX_AES_LEN, we use this constant to decide how long 612 * to wait. Allow an order of magnitude longer than it should 613 * really take, just in case. 614 */ 615 616 for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) { 617 status = bus_read_4(sc->sc_sr, SB_CTL_A); 618 if ((status & SB_CTL_ST) == 0) /* Done */ 619 return (0); 620 } 621 622 device_printf(sc->sc_dev, "operation failed to complete\n"); 623 return (EIO); 624 } 625 626 static int 627 glxsb_crypto_encdec(struct cryptop *crp, struct glxsb_session *ses, 628 struct glxsb_softc *sc) 629 { 630 char *op_src, *op_dst; 631 const void *key; 632 uint32_t op_psrc, op_pdst; 633 uint8_t op_iv[SB_AES_BLOCK_SIZE]; 634 int error; 635 int len, tlen, xlen; 636 int offset; 637 uint32_t control; 638 639 if ((crp->crp_payload_length % SB_AES_BLOCK_SIZE) != 0) 640 return (EINVAL); 641 642 /* How much of our buffer will we need to use? */ 643 xlen = crp->crp_payload_length > GLXSB_MAX_AES_LEN ? 644 GLXSB_MAX_AES_LEN : crp->crp_payload_length; 645 646 /* 647 * XXX Check if we can have input == output on Geode LX. 648 * XXX In the meantime, use two separate (adjacent) buffers. 649 */ 650 op_src = sc->sc_dma.dma_vaddr; 651 op_dst = (char *)sc->sc_dma.dma_vaddr + xlen; 652 653 op_psrc = sc->sc_dma.dma_paddr; 654 op_pdst = sc->sc_dma.dma_paddr + xlen; 655 656 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) 657 control = SB_CTL_ENC; 658 else 659 control = SB_CTL_DEC; 660 661 crypto_read_iv(crp, op_iv); 662 663 offset = 0; 664 tlen = crp->crp_payload_length; 665 666 if (crp->crp_cipher_key != NULL) 667 key = crp->crp_cipher_key; 668 else 669 key = ses->ses_key; 670 671 /* Process the data in GLXSB_MAX_AES_LEN chunks */ 672 while (tlen > 0) { 673 len = (tlen > GLXSB_MAX_AES_LEN) ? GLXSB_MAX_AES_LEN : tlen; 674 crypto_copydata(crp, crp->crp_payload_start + offset, len, 675 op_src); 676 677 glxsb_dma_pre_op(sc, &sc->sc_dma); 678 679 error = glxsb_aes(sc, control, op_psrc, op_pdst, key, len, 680 op_iv); 681 682 glxsb_dma_post_op(sc, &sc->sc_dma); 683 if (error != 0) 684 return (error); 685 686 crypto_copyback(crp, crp->crp_payload_start + offset, len, 687 op_dst); 688 689 offset += len; 690 tlen -= len; 691 692 /* 693 * Copy out last block for use as next iteration IV. 694 */ 695 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) 696 bcopy(op_dst + len - sizeof(op_iv), op_iv, 697 sizeof(op_iv)); 698 else 699 bcopy(op_src + len - sizeof(op_iv), op_iv, 700 sizeof(op_iv)); 701 } /* while */ 702 703 /* All AES processing has now been done. */ 704 bzero(sc->sc_dma.dma_vaddr, xlen * 2); 705 706 return (0); 707 } 708 709 static void 710 glxsb_crypto_task(void *arg, int pending) 711 { 712 struct glxsb_softc *sc = arg; 713 const struct crypto_session_params *csp; 714 struct glxsb_session *ses; 715 struct cryptop *crp; 716 int error; 717 718 crp = sc->sc_to.to_crp; 719 ses = sc->sc_to.to_ses; 720 csp = crypto_get_params(crp->crp_session); 721 722 /* Perform data authentication if requested before encryption */ 723 if (csp->csp_mode == CSP_MODE_ETA && 724 !CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { 725 error = glxsb_hash_process(ses, csp, crp); 726 if (error != 0) 727 goto out; 728 } 729 730 error = glxsb_crypto_encdec(crp, ses, sc); 731 if (error != 0) 732 goto out; 733 734 /* Perform data authentication if requested after encryption */ 735 if (csp->csp_mode == CSP_MODE_ETA && 736 CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { 737 error = glxsb_hash_process(ses, csp, crp); 738 if (error != 0) 739 goto out; 740 } 741 out: 742 mtx_lock(&sc->sc_task_mtx); 743 sc->sc_task_count--; 744 mtx_unlock(&sc->sc_task_mtx); 745 746 crp->crp_etype = error; 747 crypto_unblock(sc->sc_cid, CRYPTO_SYMQ); 748 crypto_done(crp); 749 } 750 751 static int 752 glxsb_crypto_process(device_t dev, struct cryptop *crp, int hint) 753 { 754 struct glxsb_softc *sc = device_get_softc(dev); 755 struct glxsb_session *ses; 756 757 ses = crypto_get_driver_session(crp->crp_session); 758 759 mtx_lock(&sc->sc_task_mtx); 760 if (sc->sc_task_count != 0) { 761 mtx_unlock(&sc->sc_task_mtx); 762 return (ERESTART); 763 } 764 sc->sc_task_count++; 765 766 sc->sc_to.to_crp = crp; 767 sc->sc_to.to_ses = ses; 768 mtx_unlock(&sc->sc_task_mtx); 769 770 taskqueue_enqueue(sc->sc_tq, &sc->sc_cryptotask); 771 return(0); 772 } 773