1 /* $OpenBSD: glxsb.c,v 1.7 2007/02/12 14:31:45 tom Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Tom Cosgrove <tom@openbsd.org> 5 * Copyright (c) 2003, 2004 Theo de Raadt 6 * Copyright (c) 2003 Jason Wright 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for the security block on the AMD Geode LX processors 23 * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234d_lx_ds.pdf 24 */ 25 26 #include <sys/cdefs.h> 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/errno.h> 31 #include <sys/kernel.h> 32 #include <sys/lock.h> 33 #include <sys/malloc.h> 34 #include <sys/mbuf.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 #include <sys/random.h> 39 #include <sys/rman.h> 40 #include <sys/rwlock.h> 41 #include <sys/sysctl.h> 42 #include <sys/taskqueue.h> 43 44 #include <machine/bus.h> 45 #include <machine/cpufunc.h> 46 #include <machine/resource.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 51 #include <opencrypto/cryptodev.h> 52 #include <opencrypto/xform.h> 53 54 #include "cryptodev_if.h" 55 #include "glxsb.h" 56 57 #define PCI_VENDOR_AMD 0x1022 /* AMD */ 58 #define PCI_PRODUCT_AMD_GEODE_LX_CRYPTO 0x2082 /* Geode LX Crypto */ 59 60 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */ 61 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */ 62 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */ 63 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */ 64 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */ 65 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */ 66 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */ 67 68 /* For GLD_MSR_CTRL: */ 69 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */ 70 #define SB_GMC_DIV1 0x0001 71 #define SB_GMC_DIV2 0x0002 72 #define SB_GMC_DIV3 0x0003 73 #define SB_GMC_DIV_MASK 0x0003 74 #define SB_GMC_SBI 0x0004 /* AES swap bits */ 75 #define SB_GMC_SBY 0x0008 /* AES swap bytes */ 76 #define SB_GMC_TW 0x0010 /* Time write (EEPROM) */ 77 #define SB_GMC_T_SEL0 0x0000 /* RNG post-proc: none */ 78 #define SB_GMC_T_SEL1 0x0100 /* RNG post-proc: LFSR */ 79 #define SB_GMC_T_SEL2 0x0200 /* RNG post-proc: whitener */ 80 #define SB_GMC_T_SEL3 0x0300 /* RNG LFSR+whitener */ 81 #define SB_GMC_T_SEL_MASK 0x0300 82 #define SB_GMC_T_NE 0x0400 /* Noise (generator) Enable */ 83 #define SB_GMC_T_TM 0x0800 /* RNG test mode */ 84 /* (deterministic) */ 85 86 /* Security Block configuration/control registers (offsets from base) */ 87 #define SB_CTL_A 0x0000 /* RW - SB Control A */ 88 #define SB_CTL_B 0x0004 /* RW - SB Control B */ 89 #define SB_AES_INT 0x0008 /* RW - SB AES Interrupt */ 90 #define SB_SOURCE_A 0x0010 /* RW - Source A */ 91 #define SB_DEST_A 0x0014 /* RW - Destination A */ 92 #define SB_LENGTH_A 0x0018 /* RW - Length A */ 93 #define SB_SOURCE_B 0x0020 /* RW - Source B */ 94 #define SB_DEST_B 0x0024 /* RW - Destination B */ 95 #define SB_LENGTH_B 0x0028 /* RW - Length B */ 96 #define SB_WKEY 0x0030 /* WO - Writable Key 0-3 */ 97 #define SB_WKEY_0 0x0030 /* WO - Writable Key 0 */ 98 #define SB_WKEY_1 0x0034 /* WO - Writable Key 1 */ 99 #define SB_WKEY_2 0x0038 /* WO - Writable Key 2 */ 100 #define SB_WKEY_3 0x003C /* WO - Writable Key 3 */ 101 #define SB_CBC_IV 0x0040 /* RW - CBC IV 0-3 */ 102 #define SB_CBC_IV_0 0x0040 /* RW - CBC IV 0 */ 103 #define SB_CBC_IV_1 0x0044 /* RW - CBC IV 1 */ 104 #define SB_CBC_IV_2 0x0048 /* RW - CBC IV 2 */ 105 #define SB_CBC_IV_3 0x004C /* RW - CBC IV 3 */ 106 #define SB_RANDOM_NUM 0x0050 /* RW - Random Number */ 107 #define SB_RANDOM_NUM_STATUS 0x0054 /* RW - Random Number Status */ 108 #define SB_EEPROM_COMM 0x0800 /* RW - EEPROM Command */ 109 #define SB_EEPROM_ADDR 0x0804 /* RW - EEPROM Address */ 110 #define SB_EEPROM_DATA 0x0808 /* RW - EEPROM Data */ 111 #define SB_EEPROM_SEC_STATE 0x080C /* RW - EEPROM Security State */ 112 113 /* For SB_CTL_A and _B */ 114 #define SB_CTL_ST 0x0001 /* Start operation (enc/dec) */ 115 #define SB_CTL_ENC 0x0002 /* Encrypt (0 is decrypt) */ 116 #define SB_CTL_DEC 0x0000 /* Decrypt */ 117 #define SB_CTL_WK 0x0004 /* Use writable key (we set) */ 118 #define SB_CTL_DC 0x0008 /* Destination coherent */ 119 #define SB_CTL_SC 0x0010 /* Source coherent */ 120 #define SB_CTL_CBC 0x0020 /* CBC (0 is ECB) */ 121 122 /* For SB_AES_INT */ 123 #define SB_AI_DISABLE_AES_A 0x0001 /* Disable AES A compl int */ 124 #define SB_AI_ENABLE_AES_A 0x0000 /* Enable AES A compl int */ 125 #define SB_AI_DISABLE_AES_B 0x0002 /* Disable AES B compl int */ 126 #define SB_AI_ENABLE_AES_B 0x0000 /* Enable AES B compl int */ 127 #define SB_AI_DISABLE_EEPROM 0x0004 /* Disable EEPROM op comp int */ 128 #define SB_AI_ENABLE_EEPROM 0x0000 /* Enable EEPROM op compl int */ 129 #define SB_AI_AES_A_COMPLETE 0x10000 /* AES A operation complete */ 130 #define SB_AI_AES_B_COMPLETE 0x20000 /* AES B operation complete */ 131 #define SB_AI_EEPROM_COMPLETE 0x40000 /* EEPROM operation complete */ 132 133 #define SB_AI_CLEAR_INTR \ 134 (SB_AI_DISABLE_AES_A | SB_AI_DISABLE_AES_B |\ 135 SB_AI_DISABLE_EEPROM | SB_AI_AES_A_COMPLETE |\ 136 SB_AI_AES_B_COMPLETE | SB_AI_EEPROM_COMPLETE) 137 138 #define SB_RNS_TRNG_VALID 0x0001 /* in SB_RANDOM_NUM_STATUS */ 139 140 #define SB_MEM_SIZE 0x0810 /* Size of memory block */ 141 142 #define SB_AES_ALIGN 0x0010 /* Source and dest buffers */ 143 /* must be 16-byte aligned */ 144 #define SB_AES_BLOCK_SIZE 0x0010 145 146 /* 147 * The Geode LX security block AES acceleration doesn't perform scatter- 148 * gather: it just takes source and destination addresses. Therefore the 149 * plain- and ciphertexts need to be contiguous. To this end, we allocate 150 * a buffer for both, and accept the overhead of copying in and out. If 151 * the number of bytes in one operation is bigger than allowed for by the 152 * buffer (buffer is twice the size of the max length, as it has both input 153 * and output) then we have to perform multiple encryptions/decryptions. 154 */ 155 156 #define GLXSB_MAX_AES_LEN 16384 157 158 MALLOC_DEFINE(M_GLXSB, "glxsb_data", "Glxsb Data"); 159 160 struct glxsb_dma_map { 161 bus_dmamap_t dma_map; /* DMA map */ 162 bus_dma_segment_t dma_seg; /* segments */ 163 int dma_nsegs; /* #segments */ 164 int dma_size; /* size */ 165 caddr_t dma_vaddr; /* virtual address */ 166 bus_addr_t dma_paddr; /* physical address */ 167 }; 168 169 struct glxsb_taskop { 170 struct glxsb_session *to_ses; /* crypto session */ 171 struct cryptop *to_crp; /* cryptop to perfom */ 172 }; 173 174 struct glxsb_softc { 175 device_t sc_dev; /* device backpointer */ 176 struct resource *sc_sr; /* resource */ 177 int sc_rid; /* resource rid */ 178 struct callout sc_rngco; /* RNG callout */ 179 int sc_rnghz; /* RNG callout ticks */ 180 bus_dma_tag_t sc_dmat; /* DMA tag */ 181 struct glxsb_dma_map sc_dma; /* DMA map */ 182 int32_t sc_cid; /* crypto tag */ 183 struct mtx sc_task_mtx; /* task mutex */ 184 struct taskqueue *sc_tq; /* task queue */ 185 struct task sc_cryptotask; /* task */ 186 struct glxsb_taskop sc_to; /* task's crypto operation */ 187 int sc_task_count; /* tasks count */ 188 }; 189 190 static int glxsb_probe(device_t); 191 static int glxsb_attach(device_t); 192 static int glxsb_detach(device_t); 193 194 static void glxsb_dmamap_cb(void *, bus_dma_segment_t *, int, int); 195 static int glxsb_dma_alloc(struct glxsb_softc *); 196 static void glxsb_dma_pre_op(struct glxsb_softc *, struct glxsb_dma_map *); 197 static void glxsb_dma_post_op(struct glxsb_softc *, struct glxsb_dma_map *); 198 static void glxsb_dma_free(struct glxsb_softc *, struct glxsb_dma_map *); 199 200 static void glxsb_rnd(void *); 201 static int glxsb_crypto_setup(struct glxsb_softc *); 202 static int glxsb_crypto_probesession(device_t, 203 const struct crypto_session_params *); 204 static int glxsb_crypto_newsession(device_t, crypto_session_t, 205 const struct crypto_session_params *); 206 static void glxsb_crypto_freesession(device_t, crypto_session_t); 207 static int glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t, 208 uint32_t, const void *, int, const void *); 209 210 static int glxsb_crypto_encdec(struct cryptop *, struct glxsb_session *, 211 struct glxsb_softc *); 212 213 static void glxsb_crypto_task(void *, int); 214 static int glxsb_crypto_process(device_t, struct cryptop *, int); 215 216 static device_method_t glxsb_methods[] = { 217 /* device interface */ 218 DEVMETHOD(device_probe, glxsb_probe), 219 DEVMETHOD(device_attach, glxsb_attach), 220 DEVMETHOD(device_detach, glxsb_detach), 221 222 /* crypto device methods */ 223 DEVMETHOD(cryptodev_probesession, glxsb_crypto_probesession), 224 DEVMETHOD(cryptodev_newsession, glxsb_crypto_newsession), 225 DEVMETHOD(cryptodev_freesession, glxsb_crypto_freesession), 226 DEVMETHOD(cryptodev_process, glxsb_crypto_process), 227 228 {0,0} 229 }; 230 231 static driver_t glxsb_driver = { 232 "glxsb", 233 glxsb_methods, 234 sizeof(struct glxsb_softc) 235 }; 236 237 DRIVER_MODULE(glxsb, pci, glxsb_driver, 0, 0); 238 MODULE_VERSION(glxsb, 1); 239 MODULE_DEPEND(glxsb, crypto, 1, 1, 1); 240 241 static int 242 glxsb_probe(device_t dev) 243 { 244 245 if (pci_get_vendor(dev) == PCI_VENDOR_AMD && 246 pci_get_device(dev) == PCI_PRODUCT_AMD_GEODE_LX_CRYPTO) { 247 device_set_desc(dev, 248 "AMD Geode LX Security Block (AES-128-CBC, RNG)"); 249 return (BUS_PROBE_DEFAULT); 250 } 251 252 return (ENXIO); 253 } 254 255 static int 256 glxsb_attach(device_t dev) 257 { 258 struct glxsb_softc *sc = device_get_softc(dev); 259 uint64_t msr; 260 261 sc->sc_dev = dev; 262 msr = rdmsr(SB_GLD_MSR_CAP); 263 264 if ((msr & 0xFFFF00) != 0x130400) { 265 device_printf(dev, "unknown ID 0x%x\n", 266 (int)((msr & 0xFFFF00) >> 16)); 267 return (ENXIO); 268 } 269 270 pci_enable_busmaster(dev); 271 272 /* Map in the security block configuration/control registers */ 273 sc->sc_rid = PCIR_BAR(0); 274 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 275 RF_ACTIVE); 276 if (sc->sc_sr == NULL) { 277 device_printf(dev, "cannot map register space\n"); 278 return (ENXIO); 279 } 280 281 /* 282 * Configure the Security Block. 283 * 284 * We want to enable the noise generator (T_NE), and enable the 285 * linear feedback shift register and whitener post-processing 286 * (T_SEL = 3). Also ensure that test mode (deterministic values) 287 * is disabled. 288 */ 289 msr = rdmsr(SB_GLD_MSR_CTRL); 290 msr &= ~(SB_GMC_T_TM | SB_GMC_T_SEL_MASK); 291 msr |= SB_GMC_T_NE | SB_GMC_T_SEL3; 292 #if 0 293 msr |= SB_GMC_SBI | SB_GMC_SBY; /* for AES, if necessary */ 294 #endif 295 wrmsr(SB_GLD_MSR_CTRL, msr); 296 297 /* Disable interrupts */ 298 bus_write_4(sc->sc_sr, SB_AES_INT, SB_AI_CLEAR_INTR); 299 300 /* Allocate a contiguous DMA-able buffer to work in */ 301 if (glxsb_dma_alloc(sc) != 0) 302 goto fail0; 303 304 /* Initialize our task queue */ 305 sc->sc_tq = taskqueue_create("glxsb_taskq", M_NOWAIT | M_ZERO, 306 taskqueue_thread_enqueue, &sc->sc_tq); 307 if (sc->sc_tq == NULL) { 308 device_printf(dev, "cannot create task queue\n"); 309 goto fail0; 310 } 311 if (taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 312 device_get_nameunit(dev)) != 0) { 313 device_printf(dev, "cannot start task queue\n"); 314 goto fail1; 315 } 316 TASK_INIT(&sc->sc_cryptotask, 0, glxsb_crypto_task, sc); 317 318 /* Initialize crypto */ 319 if (glxsb_crypto_setup(sc) != 0) 320 goto fail1; 321 322 /* Install a periodic collector for the "true" (AMD's word) RNG */ 323 if (hz > 100) 324 sc->sc_rnghz = hz / 100; 325 else 326 sc->sc_rnghz = 1; 327 callout_init(&sc->sc_rngco, 1); 328 glxsb_rnd(sc); 329 330 return (0); 331 332 fail1: 333 taskqueue_free(sc->sc_tq); 334 fail0: 335 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr); 336 return (ENXIO); 337 } 338 339 static int 340 glxsb_detach(device_t dev) 341 { 342 struct glxsb_softc *sc = device_get_softc(dev); 343 344 crypto_unregister_all(sc->sc_cid); 345 346 callout_drain(&sc->sc_rngco); 347 taskqueue_drain(sc->sc_tq, &sc->sc_cryptotask); 348 bus_generic_detach(dev); 349 glxsb_dma_free(sc, &sc->sc_dma); 350 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr); 351 taskqueue_free(sc->sc_tq); 352 mtx_destroy(&sc->sc_task_mtx); 353 return (0); 354 } 355 356 /* 357 * callback for bus_dmamap_load() 358 */ 359 static void 360 glxsb_dmamap_cb(void *arg, bus_dma_segment_t *seg, int nseg, int error) 361 { 362 363 bus_addr_t *paddr = (bus_addr_t*) arg; 364 *paddr = seg[0].ds_addr; 365 } 366 367 static int 368 glxsb_dma_alloc(struct glxsb_softc *sc) 369 { 370 struct glxsb_dma_map *dma = &sc->sc_dma; 371 int rc; 372 373 dma->dma_nsegs = 1; 374 dma->dma_size = GLXSB_MAX_AES_LEN * 2; 375 376 /* Setup DMA descriptor area */ 377 rc = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 378 SB_AES_ALIGN, 0, /* alignments, bounds */ 379 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 380 BUS_SPACE_MAXADDR, /* highaddr */ 381 NULL, NULL, /* filter, filterarg */ 382 dma->dma_size, /* maxsize */ 383 dma->dma_nsegs, /* nsegments */ 384 dma->dma_size, /* maxsegsize */ 385 BUS_DMA_ALLOCNOW, /* flags */ 386 NULL, NULL, /* lockfunc, lockarg */ 387 &sc->sc_dmat); 388 if (rc != 0) { 389 device_printf(sc->sc_dev, 390 "cannot allocate DMA tag (%d)\n", rc); 391 return (rc); 392 } 393 394 rc = bus_dmamem_alloc(sc->sc_dmat, (void **)&dma->dma_vaddr, 395 BUS_DMA_NOWAIT, &dma->dma_map); 396 if (rc != 0) { 397 device_printf(sc->sc_dev, 398 "cannot allocate DMA memory of %d bytes (%d)\n", 399 dma->dma_size, rc); 400 goto fail0; 401 } 402 403 rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 404 dma->dma_size, glxsb_dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT); 405 if (rc != 0) { 406 device_printf(sc->sc_dev, 407 "cannot load DMA memory for %d bytes (%d)\n", 408 dma->dma_size, rc); 409 goto fail1; 410 } 411 412 return (0); 413 414 fail1: 415 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); 416 fail0: 417 bus_dma_tag_destroy(sc->sc_dmat); 418 return (rc); 419 } 420 421 static void 422 glxsb_dma_pre_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 423 { 424 425 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 426 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 427 } 428 429 static void 430 glxsb_dma_post_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 431 { 432 433 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 435 } 436 437 static void 438 glxsb_dma_free(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 439 { 440 441 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 442 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); 443 bus_dma_tag_destroy(sc->sc_dmat); 444 } 445 446 static void 447 glxsb_rnd(void *v) 448 { 449 struct glxsb_softc *sc = v; 450 uint32_t status, value; 451 452 status = bus_read_4(sc->sc_sr, SB_RANDOM_NUM_STATUS); 453 if (status & SB_RNS_TRNG_VALID) { 454 value = bus_read_4(sc->sc_sr, SB_RANDOM_NUM); 455 /* feed with one uint32 */ 456 /* MarkM: FIX!! Check that this does not swamp the harvester! */ 457 random_harvest_queue(&value, sizeof(value), RANDOM_PURE_GLXSB); 458 } 459 460 callout_reset(&sc->sc_rngco, sc->sc_rnghz, glxsb_rnd, sc); 461 } 462 463 static int 464 glxsb_crypto_setup(struct glxsb_softc *sc) 465 { 466 467 sc->sc_cid = crypto_get_driverid(sc->sc_dev, 468 sizeof(struct glxsb_session), CRYPTOCAP_F_HARDWARE); 469 470 if (sc->sc_cid < 0) { 471 device_printf(sc->sc_dev, "cannot get crypto driver id\n"); 472 return (ENOMEM); 473 } 474 475 mtx_init(&sc->sc_task_mtx, "glxsb_crypto_mtx", NULL, MTX_DEF); 476 477 return (0); 478 } 479 480 static int 481 glxsb_crypto_probesession(device_t dev, const struct crypto_session_params *csp) 482 { 483 484 if (csp->csp_flags != 0) 485 return (EINVAL); 486 487 /* 488 * We only support HMAC algorithms to be able to work with 489 * ipsec(4), so if we are asked only for authentication without 490 * encryption, don't pretend we can accelerate it. 491 */ 492 switch (csp->csp_mode) { 493 case CSP_MODE_ETA: 494 switch (csp->csp_auth_alg) { 495 case CRYPTO_NULL_HMAC: 496 case CRYPTO_SHA1_HMAC: 497 case CRYPTO_RIPEMD160_HMAC: 498 case CRYPTO_SHA2_256_HMAC: 499 case CRYPTO_SHA2_384_HMAC: 500 case CRYPTO_SHA2_512_HMAC: 501 break; 502 default: 503 return (EINVAL); 504 } 505 /* FALLTHROUGH */ 506 case CSP_MODE_CIPHER: 507 switch (csp->csp_cipher_alg) { 508 case CRYPTO_AES_CBC: 509 if (csp->csp_cipher_klen * 8 != 128) 510 return (EINVAL); 511 break; 512 default: 513 return (EINVAL); 514 } 515 default: 516 return (EINVAL); 517 } 518 return (CRYPTODEV_PROBE_HARDWARE); 519 } 520 521 static int 522 glxsb_crypto_newsession(device_t dev, crypto_session_t cses, 523 const struct crypto_session_params *csp) 524 { 525 struct glxsb_softc *sc = device_get_softc(dev); 526 struct glxsb_session *ses; 527 int error; 528 529 ses = crypto_get_driver_session(cses); 530 531 /* Copy the key (Geode LX wants the primary key only) */ 532 if (csp->csp_cipher_key != NULL) 533 bcopy(csp->csp_cipher_key, ses->ses_key, sizeof(ses->ses_key)); 534 535 if (csp->csp_auth_alg != 0) { 536 error = glxsb_hash_setup(ses, csp); 537 if (error != 0) { 538 glxsb_crypto_freesession(sc->sc_dev, cses); 539 return (error); 540 } 541 } 542 543 return (0); 544 } 545 546 static void 547 glxsb_crypto_freesession(device_t dev, crypto_session_t cses) 548 { 549 struct glxsb_session *ses; 550 551 ses = crypto_get_driver_session(cses); 552 glxsb_hash_free(ses); 553 } 554 555 static int 556 glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc, 557 uint32_t pdst, const void *key, int len, const void *iv) 558 { 559 uint32_t status; 560 int i; 561 562 if (len & 0xF) { 563 device_printf(sc->sc_dev, 564 "len must be a multiple of 16 (not %d)\n", len); 565 return (EINVAL); 566 } 567 568 /* Set the source */ 569 bus_write_4(sc->sc_sr, SB_SOURCE_A, psrc); 570 571 /* Set the destination address */ 572 bus_write_4(sc->sc_sr, SB_DEST_A, pdst); 573 574 /* Set the data length */ 575 bus_write_4(sc->sc_sr, SB_LENGTH_A, len); 576 577 /* Set the IV */ 578 if (iv != NULL) { 579 bus_write_region_4(sc->sc_sr, SB_CBC_IV, iv, 4); 580 control |= SB_CTL_CBC; 581 } 582 583 /* Set the key */ 584 bus_write_region_4(sc->sc_sr, SB_WKEY, key, 4); 585 586 /* Ask the security block to do it */ 587 bus_write_4(sc->sc_sr, SB_CTL_A, 588 control | SB_CTL_WK | SB_CTL_DC | SB_CTL_SC | SB_CTL_ST); 589 590 /* 591 * Now wait until it is done. 592 * 593 * We do a busy wait. Obviously the number of iterations of 594 * the loop required to perform the AES operation depends upon 595 * the number of bytes to process. 596 * 597 * On a 500 MHz Geode LX we see 598 * 599 * length (bytes) typical max iterations 600 * 16 12 601 * 64 22 602 * 256 59 603 * 1024 212 604 * 8192 1,537 605 * 606 * Since we have a maximum size of operation defined in 607 * GLXSB_MAX_AES_LEN, we use this constant to decide how long 608 * to wait. Allow an order of magnitude longer than it should 609 * really take, just in case. 610 */ 611 612 for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) { 613 status = bus_read_4(sc->sc_sr, SB_CTL_A); 614 if ((status & SB_CTL_ST) == 0) /* Done */ 615 return (0); 616 } 617 618 device_printf(sc->sc_dev, "operation failed to complete\n"); 619 return (EIO); 620 } 621 622 static int 623 glxsb_crypto_encdec(struct cryptop *crp, struct glxsb_session *ses, 624 struct glxsb_softc *sc) 625 { 626 char *op_src, *op_dst; 627 const void *key; 628 uint32_t op_psrc, op_pdst; 629 uint8_t op_iv[SB_AES_BLOCK_SIZE]; 630 int error; 631 int len, tlen, xlen; 632 int offset; 633 uint32_t control; 634 635 if ((crp->crp_payload_length % SB_AES_BLOCK_SIZE) != 0) 636 return (EINVAL); 637 638 /* How much of our buffer will we need to use? */ 639 xlen = crp->crp_payload_length > GLXSB_MAX_AES_LEN ? 640 GLXSB_MAX_AES_LEN : crp->crp_payload_length; 641 642 /* 643 * XXX Check if we can have input == output on Geode LX. 644 * XXX In the meantime, use two separate (adjacent) buffers. 645 */ 646 op_src = sc->sc_dma.dma_vaddr; 647 op_dst = (char *)sc->sc_dma.dma_vaddr + xlen; 648 649 op_psrc = sc->sc_dma.dma_paddr; 650 op_pdst = sc->sc_dma.dma_paddr + xlen; 651 652 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) 653 control = SB_CTL_ENC; 654 else 655 control = SB_CTL_DEC; 656 657 crypto_read_iv(crp, op_iv); 658 659 offset = 0; 660 tlen = crp->crp_payload_length; 661 662 if (crp->crp_cipher_key != NULL) 663 key = crp->crp_cipher_key; 664 else 665 key = ses->ses_key; 666 667 /* Process the data in GLXSB_MAX_AES_LEN chunks */ 668 while (tlen > 0) { 669 len = (tlen > GLXSB_MAX_AES_LEN) ? GLXSB_MAX_AES_LEN : tlen; 670 crypto_copydata(crp, crp->crp_payload_start + offset, len, 671 op_src); 672 673 glxsb_dma_pre_op(sc, &sc->sc_dma); 674 675 error = glxsb_aes(sc, control, op_psrc, op_pdst, key, len, 676 op_iv); 677 678 glxsb_dma_post_op(sc, &sc->sc_dma); 679 if (error != 0) 680 return (error); 681 682 crypto_copyback(crp, crp->crp_payload_start + offset, len, 683 op_dst); 684 685 offset += len; 686 tlen -= len; 687 688 /* 689 * Copy out last block for use as next iteration IV. 690 */ 691 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) 692 bcopy(op_dst + len - sizeof(op_iv), op_iv, 693 sizeof(op_iv)); 694 else 695 bcopy(op_src + len - sizeof(op_iv), op_iv, 696 sizeof(op_iv)); 697 } /* while */ 698 699 /* All AES processing has now been done. */ 700 bzero(sc->sc_dma.dma_vaddr, xlen * 2); 701 702 return (0); 703 } 704 705 static void 706 glxsb_crypto_task(void *arg, int pending) 707 { 708 struct glxsb_softc *sc = arg; 709 const struct crypto_session_params *csp; 710 struct glxsb_session *ses; 711 struct cryptop *crp; 712 int error; 713 714 crp = sc->sc_to.to_crp; 715 ses = sc->sc_to.to_ses; 716 csp = crypto_get_params(crp->crp_session); 717 718 /* Perform data authentication if requested before encryption */ 719 if (csp->csp_mode == CSP_MODE_ETA && 720 !CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { 721 error = glxsb_hash_process(ses, csp, crp); 722 if (error != 0) 723 goto out; 724 } 725 726 error = glxsb_crypto_encdec(crp, ses, sc); 727 if (error != 0) 728 goto out; 729 730 /* Perform data authentication if requested after encryption */ 731 if (csp->csp_mode == CSP_MODE_ETA && 732 CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { 733 error = glxsb_hash_process(ses, csp, crp); 734 if (error != 0) 735 goto out; 736 } 737 out: 738 mtx_lock(&sc->sc_task_mtx); 739 sc->sc_task_count--; 740 mtx_unlock(&sc->sc_task_mtx); 741 742 crp->crp_etype = error; 743 crypto_unblock(sc->sc_cid, CRYPTO_SYMQ); 744 crypto_done(crp); 745 } 746 747 static int 748 glxsb_crypto_process(device_t dev, struct cryptop *crp, int hint) 749 { 750 struct glxsb_softc *sc = device_get_softc(dev); 751 struct glxsb_session *ses; 752 753 ses = crypto_get_driver_session(crp->crp_session); 754 755 mtx_lock(&sc->sc_task_mtx); 756 if (sc->sc_task_count != 0) { 757 mtx_unlock(&sc->sc_task_mtx); 758 return (ERESTART); 759 } 760 sc->sc_task_count++; 761 762 sc->sc_to.to_crp = crp; 763 sc->sc_to.to_ses = ses; 764 mtx_unlock(&sc->sc_task_mtx); 765 766 taskqueue_enqueue(sc->sc_tq, &sc->sc_cryptotask); 767 return(0); 768 } 769