1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 /* 30 * AMD Geode LX CS5536 System Management Bus controller. 31 * 32 * Although AMD refers to this device as an SMBus controller, it 33 * really is an I2C controller (It lacks SMBus ALERT# and Alert 34 * Response support). 35 * 36 * The driver is implemented as an interrupt-driven state machine, 37 * supporting both master and slave mode. 38 */ 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/sysctl.h> 47 #ifdef GLXIIC_DEBUG 48 #include <sys/syslog.h> 49 #endif 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <dev/iicbus/iiconf.h> 59 #include <dev/iicbus/iicbus.h> 60 61 #include "iicbus_if.h" 62 63 /* CS5536 PCI-ISA ID. */ 64 #define GLXIIC_CS5536_DEV_ID 0x20901022 65 66 /* MSRs. */ 67 #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021 68 69 /* Bus speeds. */ 70 #define GLXIIC_SLOW 0x0258 /* 10 kHz. */ 71 #define GLXIIC_FAST 0x0078 /* 50 kHz. */ 72 #define GLXIIC_FASTEST 0x003c /* 100 kHz. */ 73 74 /* Default bus activity timeout in milliseconds. */ 75 #define GLXIIC_DEFAULT_TIMEOUT 35 76 77 /* GPIO register offsets. */ 78 #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10 79 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34 80 81 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */ 82 #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000 83 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000 84 85 /* SMB register offsets. */ 86 #define GLXIIC_SMB_SDA 0x00 87 #define GLXIIC_SMB_STS 0x01 88 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7) 89 #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6) 90 #define GLXIIC_SMB_STS_BER_BIT (1 << 5) 91 #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4) 92 #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3) 93 #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2) 94 #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1) 95 #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0) 96 #define GLXIIC_SMB_CTRL_STS 0x02 97 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5) 98 #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4) 99 #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3) 100 #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2) 101 #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1) 102 #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0) 103 #define GLXIIC_SMB_CTRL1 0x03 104 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7) 105 #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6) 106 #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5) 107 #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4) 108 #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2) 109 #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1) 110 #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0) 111 #define GLXIIC_SMB_ADDR 0x04 112 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7) 113 #define GLXIIC_SMB_CTRL2 0x05 114 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0) 115 #define GLXIIC_SMB_CTRL3 0x06 116 117 typedef enum { 118 GLXIIC_STATE_IDLE, 119 GLXIIC_STATE_SLAVE_TX, 120 GLXIIC_STATE_SLAVE_RX, 121 GLXIIC_STATE_MASTER_ADDR, 122 GLXIIC_STATE_MASTER_TX, 123 GLXIIC_STATE_MASTER_RX, 124 GLXIIC_STATE_MASTER_STOP, 125 GLXIIC_STATE_MAX, 126 } glxiic_state_t; 127 128 struct glxiic_softc { 129 device_t dev; /* Myself. */ 130 device_t iicbus; /* IIC bus. */ 131 struct mtx mtx; /* Lock. */ 132 glxiic_state_t state; /* Driver state. */ 133 struct callout callout; /* Driver state timeout callout. */ 134 int timeout; /* Driver state timeout (ms). */ 135 136 int smb_rid; /* SMB controller resource ID. */ 137 struct resource *smb_res; /* SMB controller resource. */ 138 int gpio_rid; /* GPIO resource ID. */ 139 struct resource *gpio_res; /* GPIO resource. */ 140 141 int irq_rid; /* IRQ resource ID. */ 142 struct resource *irq_res; /* IRQ resource. */ 143 void *irq_handler; /* IRQ handler cookie. */ 144 int old_irq; /* IRQ mapped by board firmware. */ 145 146 struct iic_msg *msg; /* Current master mode message. */ 147 uint32_t nmsgs; /* Number of messages remaining. */ 148 uint8_t *data; /* Current master mode data byte. */ 149 uint16_t ndata; /* Number of data bytes remaining. */ 150 int error; /* Last master mode error. */ 151 152 uint8_t addr; /* Own address. */ 153 uint16_t sclfrq; /* Bus frequency. */ 154 }; 155 156 #ifdef GLXIIC_DEBUG 157 #define GLXIIC_DEBUG_LOG(fmt, args...) \ 158 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args) 159 #else 160 #define GLXIIC_DEBUG_LOG(fmt, args...) 161 #endif 162 163 #define GLXIIC_SCLFRQ(n) ((n << 1)) 164 #define GLXIIC_SMBADDR(n) ((n >> 1)) 165 #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16)) 166 #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf) 167 168 #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx) 169 #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx) 170 #define GLXIIC_LOCK_INIT(_sc) \ 171 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF) 172 #define GLXIIC_SLEEP(_sc) \ 173 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0) 174 #define GLXIIC_WAKEUP(_sc) wakeup(_sc); 175 #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 176 #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 177 178 typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc, 179 uint8_t status); 180 181 static glxiic_state_callback_t glxiic_state_idle_callback; 182 static glxiic_state_callback_t glxiic_state_slave_tx_callback; 183 static glxiic_state_callback_t glxiic_state_slave_rx_callback; 184 static glxiic_state_callback_t glxiic_state_master_addr_callback; 185 static glxiic_state_callback_t glxiic_state_master_tx_callback; 186 static glxiic_state_callback_t glxiic_state_master_rx_callback; 187 static glxiic_state_callback_t glxiic_state_master_stop_callback; 188 189 struct glxiic_state_table_entry { 190 glxiic_state_callback_t *callback; 191 boolean_t master; 192 }; 193 typedef struct glxiic_state_table_entry glxiic_state_table_entry_t; 194 195 static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = { 196 [GLXIIC_STATE_IDLE] = { 197 .callback = &glxiic_state_idle_callback, 198 .master = FALSE, 199 }, 200 201 [GLXIIC_STATE_SLAVE_TX] = { 202 .callback = &glxiic_state_slave_tx_callback, 203 .master = FALSE, 204 }, 205 206 [GLXIIC_STATE_SLAVE_RX] = { 207 .callback = &glxiic_state_slave_rx_callback, 208 .master = FALSE, 209 }, 210 211 [GLXIIC_STATE_MASTER_ADDR] = { 212 .callback = &glxiic_state_master_addr_callback, 213 .master = TRUE, 214 }, 215 216 [GLXIIC_STATE_MASTER_TX] = { 217 .callback = &glxiic_state_master_tx_callback, 218 .master = TRUE, 219 }, 220 221 [GLXIIC_STATE_MASTER_RX] = { 222 .callback = &glxiic_state_master_rx_callback, 223 .master = TRUE, 224 }, 225 226 [GLXIIC_STATE_MASTER_STOP] = { 227 .callback = &glxiic_state_master_stop_callback, 228 .master = TRUE, 229 }, 230 }; 231 232 static void glxiic_identify(driver_t *driver, device_t parent); 233 static int glxiic_probe(device_t dev); 234 static int glxiic_attach(device_t dev); 235 static int glxiic_detach(device_t dev); 236 237 static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc); 238 static void glxiic_stop_locked(struct glxiic_softc *sc); 239 static void glxiic_timeout(void *arg); 240 static void glxiic_start_timeout_locked(struct glxiic_softc *sc); 241 static void glxiic_set_state_locked(struct glxiic_softc *sc, 242 glxiic_state_t state); 243 static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc, 244 uint8_t status); 245 static void glxiic_intr(void *arg); 246 247 static int glxiic_reset(device_t dev, u_char speed, u_char addr, 248 u_char *oldaddr); 249 static int glxiic_transfer(device_t dev, struct iic_msg *msgs, 250 uint32_t nmsgs); 251 252 static void glxiic_smb_map_interrupt(int irq); 253 static void glxiic_gpio_enable(struct glxiic_softc *sc); 254 static void glxiic_gpio_disable(struct glxiic_softc *sc); 255 static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, 256 uint8_t addr); 257 static void glxiic_smb_disable(struct glxiic_softc *sc); 258 259 static device_method_t glxiic_methods[] = { 260 DEVMETHOD(device_identify, glxiic_identify), 261 DEVMETHOD(device_probe, glxiic_probe), 262 DEVMETHOD(device_attach, glxiic_attach), 263 DEVMETHOD(device_detach, glxiic_detach), 264 265 DEVMETHOD(iicbus_reset, glxiic_reset), 266 DEVMETHOD(iicbus_transfer, glxiic_transfer), 267 DEVMETHOD(iicbus_callback, iicbus_null_callback), 268 269 { 0, 0 } 270 }; 271 272 static driver_t glxiic_driver = { 273 "glxiic", 274 glxiic_methods, 275 sizeof(struct glxiic_softc), 276 }; 277 278 DRIVER_MODULE(glxiic, isab, glxiic_driver, 0, 0); 279 DRIVER_MODULE(iicbus, glxiic, iicbus_driver, 0, 0); 280 MODULE_DEPEND(glxiic, iicbus, 1, 1, 1); 281 282 static void 283 glxiic_identify(driver_t *driver, device_t parent) 284 { 285 286 /* Prevent child from being added more than once. */ 287 if (device_find_child(parent, driver->name, -1) != NULL) 288 return; 289 290 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) { 291 if (device_add_child(parent, driver->name, -1) == NULL) 292 device_printf(parent, "Could not add glxiic child\n"); 293 } 294 } 295 296 static int 297 glxiic_probe(device_t dev) 298 { 299 300 if (resource_disabled("glxiic", device_get_unit(dev))) 301 return (ENXIO); 302 303 device_set_desc(dev, "AMD Geode CS5536 SMBus controller"); 304 305 return (BUS_PROBE_DEFAULT); 306 } 307 308 static int 309 glxiic_attach(device_t dev) 310 { 311 struct glxiic_softc *sc; 312 struct sysctl_ctx_list *ctx; 313 struct sysctl_oid *tree; 314 int error, irq, unit; 315 uint32_t irq_map; 316 317 sc = device_get_softc(dev); 318 sc->dev = dev; 319 sc->state = GLXIIC_STATE_IDLE; 320 error = 0; 321 322 GLXIIC_LOCK_INIT(sc); 323 callout_init_mtx(&sc->callout, &sc->mtx, 0); 324 325 sc->smb_rid = PCIR_BAR(0); 326 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid, 327 RF_ACTIVE); 328 if (sc->smb_res == NULL) { 329 device_printf(dev, "Could not allocate SMBus I/O port\n"); 330 error = ENXIO; 331 goto out; 332 } 333 334 sc->gpio_rid = PCIR_BAR(1); 335 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 336 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE); 337 if (sc->gpio_res == NULL) { 338 device_printf(dev, "Could not allocate GPIO I/O port\n"); 339 error = ENXIO; 340 goto out; 341 } 342 343 /* Ensure the controller is not enabled by firmware. */ 344 glxiic_smb_disable(sc); 345 346 /* Read the existing IRQ map. */ 347 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 348 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 349 350 unit = device_get_unit(dev); 351 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) { 352 if (irq < 1 || irq > 15) { 353 device_printf(dev, "Bad value %d for glxiic.%d.irq\n", 354 irq, unit); 355 error = ENXIO; 356 goto out; 357 } 358 359 if (bootverbose) 360 device_printf(dev, "Using irq %d set by hint\n", irq); 361 } else if (sc->old_irq != 0) { 362 if (bootverbose) 363 device_printf(dev, "Using irq %d set by firmware\n", 364 irq); 365 irq = sc->old_irq; 366 } else { 367 device_printf(dev, "No irq mapped by firmware"); 368 printf(" and no glxiic.%d.irq hint provided\n", unit); 369 error = ENXIO; 370 goto out; 371 } 372 373 /* Map the SMBus interrupt to the requested legacy IRQ. */ 374 glxiic_smb_map_interrupt(irq); 375 376 sc->irq_rid = 0; 377 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 378 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE); 379 if (sc->irq_res == NULL) { 380 device_printf(dev, "Could not allocate IRQ %d\n", irq); 381 error = ENXIO; 382 goto out; 383 } 384 385 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 386 NULL, glxiic_intr, sc, &(sc->irq_handler)); 387 if (error != 0) { 388 device_printf(dev, "Could not setup IRQ handler\n"); 389 error = ENXIO; 390 goto out; 391 } 392 393 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 394 device_printf(dev, "Could not allocate iicbus instance\n"); 395 error = ENXIO; 396 goto out; 397 } 398 399 ctx = device_get_sysctl_ctx(dev); 400 tree = device_get_sysctl_tree(dev); 401 402 sc->timeout = GLXIIC_DEFAULT_TIMEOUT; 403 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 404 "timeout", CTLFLAG_RWTUN, &sc->timeout, 0, 405 "activity timeout in ms"); 406 407 glxiic_gpio_enable(sc); 408 glxiic_smb_enable(sc, IIC_FASTEST, 0); 409 410 /* Probe and attach the iicbus when interrupts are available. */ 411 bus_delayed_attach_children(dev); 412 413 out: 414 if (error != 0) { 415 callout_drain(&sc->callout); 416 417 if (sc->iicbus != NULL) 418 device_delete_child(dev, sc->iicbus); 419 if (sc->smb_res != NULL) { 420 glxiic_smb_disable(sc); 421 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 422 sc->smb_res); 423 } 424 if (sc->gpio_res != NULL) { 425 glxiic_gpio_disable(sc); 426 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 427 sc->gpio_res); 428 } 429 if (sc->irq_handler != NULL) 430 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 431 if (sc->irq_res != NULL) 432 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 433 sc->irq_res); 434 435 /* Restore the old SMBus interrupt mapping. */ 436 glxiic_smb_map_interrupt(sc->old_irq); 437 438 GLXIIC_LOCK_DESTROY(sc); 439 } 440 441 return (error); 442 } 443 444 static int 445 glxiic_detach(device_t dev) 446 { 447 struct glxiic_softc *sc; 448 int error; 449 450 sc = device_get_softc(dev); 451 452 error = bus_generic_detach(dev); 453 if (error != 0) 454 return (error); 455 456 callout_drain(&sc->callout); 457 458 if (sc->smb_res != NULL) { 459 glxiic_smb_disable(sc); 460 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 461 sc->smb_res); 462 } 463 if (sc->gpio_res != NULL) { 464 glxiic_gpio_disable(sc); 465 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 466 sc->gpio_res); 467 } 468 if (sc->irq_handler != NULL) 469 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 470 if (sc->irq_res != NULL) 471 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 472 sc->irq_res); 473 474 /* Restore the old SMBus interrupt mapping. */ 475 glxiic_smb_map_interrupt(sc->old_irq); 476 477 GLXIIC_LOCK_DESTROY(sc); 478 479 return (0); 480 } 481 482 static uint8_t 483 glxiic_read_status_locked(struct glxiic_softc *sc) 484 { 485 uint8_t status; 486 487 GLXIIC_ASSERT_LOCKED(sc); 488 489 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS); 490 491 /* Clear all status flags except SDAST and STASTR after reading. */ 492 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT | 493 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT | 494 GLXIIC_SMB_STS_NMATCH_BIT)); 495 496 return (status); 497 } 498 499 static void 500 glxiic_stop_locked(struct glxiic_softc *sc) 501 { 502 uint8_t status, ctrl1; 503 504 GLXIIC_ASSERT_LOCKED(sc); 505 506 status = glxiic_read_status_locked(sc); 507 508 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 509 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 510 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT); 511 512 /* 513 * Perform a dummy read of SDA in master receive mode to clear 514 * SDAST if set. 515 */ 516 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 && 517 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0) 518 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 519 520 /* Check stall after start bit and clear if needed */ 521 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 522 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 523 GLXIIC_SMB_STS_STASTR_BIT); 524 } 525 } 526 527 static void 528 glxiic_timeout(void *arg) 529 { 530 struct glxiic_softc *sc; 531 uint8_t error; 532 533 sc = (struct glxiic_softc *)arg; 534 535 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state); 536 537 if (glxiic_state_table[sc->state].master) { 538 sc->error = IIC_ETIMEOUT; 539 GLXIIC_WAKEUP(sc); 540 } else { 541 error = IIC_ETIMEOUT; 542 iicbus_intr(sc->iicbus, INTR_ERROR, &error); 543 } 544 545 glxiic_smb_disable(sc); 546 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr); 547 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 548 } 549 550 static void 551 glxiic_start_timeout_locked(struct glxiic_softc *sc) 552 { 553 554 GLXIIC_ASSERT_LOCKED(sc); 555 556 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0, 557 glxiic_timeout, sc, 0); 558 } 559 560 static void 561 glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state) 562 { 563 564 GLXIIC_ASSERT_LOCKED(sc); 565 566 if (state == GLXIIC_STATE_IDLE) 567 callout_stop(&sc->callout); 568 else if (sc->timeout > 0) 569 glxiic_start_timeout_locked(sc); 570 571 sc->state = state; 572 } 573 574 static int 575 glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status) 576 { 577 uint8_t ctrl_sts, addr; 578 579 GLXIIC_ASSERT_LOCKED(sc); 580 581 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS); 582 583 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) { 584 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) { 585 addr = sc->addr | LSB; 586 glxiic_set_state_locked(sc, 587 GLXIIC_STATE_SLAVE_TX); 588 } else { 589 addr = sc->addr & ~LSB; 590 glxiic_set_state_locked(sc, 591 GLXIIC_STATE_SLAVE_RX); 592 } 593 iicbus_intr(sc->iicbus, INTR_START, &addr); 594 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) { 595 addr = 0; 596 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX); 597 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr); 598 } else { 599 GLXIIC_DEBUG_LOG("unknown slave match"); 600 return (IIC_ESTATUS); 601 } 602 603 return (IIC_NOERR); 604 } 605 606 static int 607 glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status) 608 { 609 610 GLXIIC_ASSERT_LOCKED(sc); 611 612 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 613 GLXIIC_DEBUG_LOG("bus error in idle"); 614 return (IIC_EBUSERR); 615 } 616 617 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 618 return (glxiic_handle_slave_match_locked(sc, status)); 619 } 620 621 return (IIC_NOERR); 622 } 623 624 static int 625 glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status) 626 { 627 uint8_t data; 628 629 GLXIIC_ASSERT_LOCKED(sc); 630 631 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 632 GLXIIC_DEBUG_LOG("bus error in slave tx"); 633 return (IIC_EBUSERR); 634 } 635 636 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 637 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 638 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 639 return (IIC_NOERR); 640 } 641 642 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 643 iicbus_intr(sc->iicbus, INTR_NOACK, NULL); 644 return (IIC_NOERR); 645 } 646 647 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 648 /* Handle repeated start in slave mode. */ 649 return (glxiic_handle_slave_match_locked(sc, status)); 650 } 651 652 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 653 GLXIIC_DEBUG_LOG("not awaiting data in slave tx"); 654 return (IIC_ESTATUS); 655 } 656 657 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); 658 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data); 659 660 glxiic_start_timeout_locked(sc); 661 662 return (IIC_NOERR); 663 } 664 665 static int 666 glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status) 667 { 668 uint8_t data; 669 670 GLXIIC_ASSERT_LOCKED(sc); 671 672 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 673 GLXIIC_DEBUG_LOG("bus error in slave rx"); 674 return (IIC_EBUSERR); 675 } 676 677 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 678 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 679 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 680 return (IIC_NOERR); 681 } 682 683 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 684 /* Handle repeated start in slave mode. */ 685 return (glxiic_handle_slave_match_locked(sc, status)); 686 } 687 688 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 689 GLXIIC_DEBUG_LOG("no pending data in slave rx"); 690 return (IIC_ESTATUS); 691 } 692 693 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 694 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data); 695 696 glxiic_start_timeout_locked(sc); 697 698 return (IIC_NOERR); 699 } 700 701 static int 702 glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status) 703 { 704 uint8_t slave; 705 uint8_t ctrl1; 706 707 GLXIIC_ASSERT_LOCKED(sc); 708 709 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 710 GLXIIC_DEBUG_LOG("bus error after master start"); 711 return (IIC_EBUSERR); 712 } 713 714 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 715 GLXIIC_DEBUG_LOG("not bus master after master start"); 716 return (IIC_ESTATUS); 717 } 718 719 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 720 GLXIIC_DEBUG_LOG("not awaiting address in master addr"); 721 return (IIC_ESTATUS); 722 } 723 724 if ((sc->msg->flags & IIC_M_RD) != 0) { 725 slave = sc->msg->slave | LSB; 726 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX); 727 } else { 728 slave = sc->msg->slave & ~LSB; 729 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX); 730 } 731 732 sc->data = sc->msg->buf; 733 sc->ndata = sc->msg->len; 734 735 /* Handle address-only transfer. */ 736 if (sc->ndata == 0) 737 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 738 739 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave); 740 741 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) { 742 /* Last byte from slave, set NACK. */ 743 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 744 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 745 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 746 } 747 748 return (IIC_NOERR); 749 } 750 751 static int 752 glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status) 753 { 754 755 GLXIIC_ASSERT_LOCKED(sc); 756 757 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 758 GLXIIC_DEBUG_LOG("bus error in master tx"); 759 return (IIC_EBUSERR); 760 } 761 762 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 763 GLXIIC_DEBUG_LOG("not bus master in master tx"); 764 return (IIC_ESTATUS); 765 } 766 767 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 768 GLXIIC_DEBUG_LOG("slave nack in master tx"); 769 return (IIC_ENOACK); 770 } 771 772 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 773 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 774 GLXIIC_SMB_STS_STASTR_BIT); 775 } 776 777 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 778 GLXIIC_DEBUG_LOG("not awaiting data in master tx"); 779 return (IIC_ESTATUS); 780 } 781 782 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++); 783 if (--sc->ndata == 0) 784 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 785 else 786 glxiic_start_timeout_locked(sc); 787 788 return (IIC_NOERR); 789 } 790 791 static int 792 glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status) 793 { 794 uint8_t ctrl1; 795 796 GLXIIC_ASSERT_LOCKED(sc); 797 798 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 799 GLXIIC_DEBUG_LOG("bus error in master rx"); 800 return (IIC_EBUSERR); 801 } 802 803 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 804 GLXIIC_DEBUG_LOG("not bus master in master rx"); 805 return (IIC_ESTATUS); 806 } 807 808 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 809 GLXIIC_DEBUG_LOG("slave nack in rx"); 810 return (IIC_ENOACK); 811 } 812 813 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 814 /* Bus is stalled, clear and wait for data. */ 815 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 816 GLXIIC_SMB_STS_STASTR_BIT); 817 return (IIC_NOERR); 818 } 819 820 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 821 GLXIIC_DEBUG_LOG("no pending data in master rx"); 822 return (IIC_ESTATUS); 823 } 824 825 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 826 if (--sc->ndata == 0) { 827 /* Proceed with stop on reading last byte. */ 828 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 829 return (glxiic_state_table[sc->state].callback(sc, status)); 830 } 831 832 if (sc->ndata == 1) { 833 /* Last byte from slave, set NACK. */ 834 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 835 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 836 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 837 } 838 839 glxiic_start_timeout_locked(sc); 840 841 return (IIC_NOERR); 842 } 843 844 static int 845 glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status) 846 { 847 uint8_t ctrl1; 848 849 GLXIIC_ASSERT_LOCKED(sc); 850 851 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 852 GLXIIC_DEBUG_LOG("bus error in master stop"); 853 return (IIC_EBUSERR); 854 } 855 856 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 857 GLXIIC_DEBUG_LOG("not bus master in master stop"); 858 return (IIC_ESTATUS); 859 } 860 861 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 862 GLXIIC_DEBUG_LOG("slave nack in master stop"); 863 return (IIC_ENOACK); 864 } 865 866 if (--sc->nmsgs > 0) { 867 /* Start transfer of next message. */ 868 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) { 869 glxiic_stop_locked(sc); 870 } 871 872 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 873 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 874 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 875 876 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 877 sc->msg++; 878 } else { 879 /* Last message. */ 880 glxiic_stop_locked(sc); 881 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 882 sc->error = IIC_NOERR; 883 GLXIIC_WAKEUP(sc); 884 } 885 886 return (IIC_NOERR); 887 } 888 889 static void 890 glxiic_intr(void *arg) 891 { 892 struct glxiic_softc *sc; 893 int error; 894 uint8_t status, data; 895 896 sc = (struct glxiic_softc *)arg; 897 898 GLXIIC_LOCK(sc); 899 900 status = glxiic_read_status_locked(sc); 901 902 /* Check if this interrupt originated from the SMBus. */ 903 if ((status & 904 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) { 905 906 error = glxiic_state_table[sc->state].callback(sc, status); 907 908 if (error != IIC_NOERR) { 909 if (glxiic_state_table[sc->state].master) { 910 glxiic_stop_locked(sc); 911 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 912 sc->error = error; 913 GLXIIC_WAKEUP(sc); 914 } else { 915 data = error & 0xff; 916 iicbus_intr(sc->iicbus, INTR_ERROR, &data); 917 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 918 } 919 } 920 } 921 922 GLXIIC_UNLOCK(sc); 923 } 924 925 static int 926 glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 927 { 928 struct glxiic_softc *sc; 929 930 sc = device_get_softc(dev); 931 932 GLXIIC_LOCK(sc); 933 934 if (oldaddr != NULL) 935 *oldaddr = sc->addr; 936 sc->addr = addr; 937 938 /* A disable/enable cycle resets the controller. */ 939 glxiic_smb_disable(sc); 940 glxiic_smb_enable(sc, speed, addr); 941 942 if (glxiic_state_table[sc->state].master) { 943 sc->error = IIC_ESTATUS; 944 GLXIIC_WAKEUP(sc); 945 } 946 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 947 948 GLXIIC_UNLOCK(sc); 949 950 return (IIC_NOERR); 951 } 952 953 static int 954 glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 955 { 956 struct glxiic_softc *sc; 957 int error; 958 uint8_t ctrl1; 959 960 sc = device_get_softc(dev); 961 962 GLXIIC_LOCK(sc); 963 964 if (sc->state != GLXIIC_STATE_IDLE) { 965 error = IIC_EBUSBSY; 966 goto out; 967 } 968 969 sc->msg = msgs; 970 sc->nmsgs = nmsgs; 971 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 972 973 /* Set start bit and let glxiic_intr() handle the transfer. */ 974 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 975 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 976 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 977 978 GLXIIC_SLEEP(sc); 979 error = sc->error; 980 out: 981 GLXIIC_UNLOCK(sc); 982 983 return (error); 984 } 985 986 static void 987 glxiic_smb_map_interrupt(int irq) 988 { 989 uint32_t irq_map; 990 int old_irq; 991 992 /* Protect the read-modify-write operation. */ 993 critical_enter(); 994 995 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 996 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 997 998 if (irq != old_irq) { 999 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq); 1000 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq); 1001 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map); 1002 } 1003 1004 critical_exit(); 1005 } 1006 1007 static void 1008 glxiic_gpio_enable(struct glxiic_softc *sc) 1009 { 1010 1011 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1012 GLXIIC_GPIO_14_15_ENABLE); 1013 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1014 GLXIIC_GPIO_14_15_ENABLE); 1015 } 1016 1017 static void 1018 glxiic_gpio_disable(struct glxiic_softc *sc) 1019 { 1020 1021 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1022 GLXIIC_GPIO_14_15_DISABLE); 1023 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1024 GLXIIC_GPIO_14_15_DISABLE); 1025 } 1026 1027 static void 1028 glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr) 1029 { 1030 uint8_t ctrl1; 1031 1032 ctrl1 = 0; 1033 1034 switch (speed) { 1035 case IIC_SLOW: 1036 sc->sclfrq = GLXIIC_SLOW; 1037 break; 1038 case IIC_FAST: 1039 sc->sclfrq = GLXIIC_FAST; 1040 break; 1041 case IIC_FASTEST: 1042 sc->sclfrq = GLXIIC_FASTEST; 1043 break; 1044 case IIC_UNKNOWN: 1045 default: 1046 /* Reuse last frequency. */ 1047 break; 1048 } 1049 1050 /* Set bus speed and enable controller. */ 1051 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1052 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT); 1053 1054 if (addr != 0) { 1055 /* Enable new match and global call match interrupts. */ 1056 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT | 1057 GLXIIC_SMB_CTRL1_GCMEN_BIT; 1058 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 1059 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr)); 1060 } else { 1061 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0); 1062 } 1063 1064 /* Enable stall after start and interrupt. */ 1065 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 1066 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT); 1067 } 1068 1069 static void 1070 glxiic_smb_disable(struct glxiic_softc *sc) 1071 { 1072 uint16_t sclfrq; 1073 1074 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2); 1075 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1076 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT); 1077 } 1078