1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 /* 31 * AMD Geode LX CS5536 System Management Bus controller. 32 * 33 * Although AMD refers to this device as an SMBus controller, it 34 * really is an I2C controller (It lacks SMBus ALERT# and Alert 35 * Response support). 36 * 37 * The driver is implemented as an interrupt-driven state machine, 38 * supporting both master and slave mode. 39 */ 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 #include <sys/sysctl.h> 48 #ifdef GLXIIC_DEBUG 49 #include <sys/syslog.h> 50 #endif 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 55 #include <machine/bus.h> 56 #include <sys/rman.h> 57 #include <machine/resource.h> 58 59 #include <dev/iicbus/iiconf.h> 60 #include <dev/iicbus/iicbus.h> 61 62 #include "iicbus_if.h" 63 64 /* CS5536 PCI-ISA ID. */ 65 #define GLXIIC_CS5536_DEV_ID 0x20901022 66 67 /* MSRs. */ 68 #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021 69 70 /* Bus speeds. */ 71 #define GLXIIC_SLOW 0x0258 /* 10 kHz. */ 72 #define GLXIIC_FAST 0x0078 /* 50 kHz. */ 73 #define GLXIIC_FASTEST 0x003c /* 100 kHz. */ 74 75 /* Default bus activity timeout in milliseconds. */ 76 #define GLXIIC_DEFAULT_TIMEOUT 35 77 78 /* GPIO register offsets. */ 79 #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10 80 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34 81 82 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */ 83 #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000 84 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000 85 86 /* SMB register offsets. */ 87 #define GLXIIC_SMB_SDA 0x00 88 #define GLXIIC_SMB_STS 0x01 89 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7) 90 #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6) 91 #define GLXIIC_SMB_STS_BER_BIT (1 << 5) 92 #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4) 93 #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3) 94 #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2) 95 #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1) 96 #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0) 97 #define GLXIIC_SMB_CTRL_STS 0x02 98 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5) 99 #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4) 100 #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3) 101 #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2) 102 #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1) 103 #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0) 104 #define GLXIIC_SMB_CTRL1 0x03 105 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7) 106 #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6) 107 #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5) 108 #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4) 109 #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2) 110 #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1) 111 #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0) 112 #define GLXIIC_SMB_ADDR 0x04 113 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7) 114 #define GLXIIC_SMB_CTRL2 0x05 115 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0) 116 #define GLXIIC_SMB_CTRL3 0x06 117 118 typedef enum { 119 GLXIIC_STATE_IDLE, 120 GLXIIC_STATE_SLAVE_TX, 121 GLXIIC_STATE_SLAVE_RX, 122 GLXIIC_STATE_MASTER_ADDR, 123 GLXIIC_STATE_MASTER_TX, 124 GLXIIC_STATE_MASTER_RX, 125 GLXIIC_STATE_MASTER_STOP, 126 GLXIIC_STATE_MAX, 127 } glxiic_state_t; 128 129 struct glxiic_softc { 130 device_t dev; /* Myself. */ 131 device_t iicbus; /* IIC bus. */ 132 struct mtx mtx; /* Lock. */ 133 glxiic_state_t state; /* Driver state. */ 134 struct callout callout; /* Driver state timeout callout. */ 135 int timeout; /* Driver state timeout (ms). */ 136 137 int smb_rid; /* SMB controller resource ID. */ 138 struct resource *smb_res; /* SMB controller resource. */ 139 int gpio_rid; /* GPIO resource ID. */ 140 struct resource *gpio_res; /* GPIO resource. */ 141 142 int irq_rid; /* IRQ resource ID. */ 143 struct resource *irq_res; /* IRQ resource. */ 144 void *irq_handler; /* IRQ handler cookie. */ 145 int old_irq; /* IRQ mapped by board firmware. */ 146 147 struct iic_msg *msg; /* Current master mode message. */ 148 uint32_t nmsgs; /* Number of messages remaining. */ 149 uint8_t *data; /* Current master mode data byte. */ 150 uint16_t ndata; /* Number of data bytes remaining. */ 151 int error; /* Last master mode error. */ 152 153 uint8_t addr; /* Own address. */ 154 uint16_t sclfrq; /* Bus frequency. */ 155 }; 156 157 #ifdef GLXIIC_DEBUG 158 #define GLXIIC_DEBUG_LOG(fmt, args...) \ 159 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args) 160 #else 161 #define GLXIIC_DEBUG_LOG(fmt, args...) 162 #endif 163 164 #define GLXIIC_SCLFRQ(n) ((n << 1)) 165 #define GLXIIC_SMBADDR(n) ((n >> 1)) 166 #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16)) 167 #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf) 168 169 #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx) 170 #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx) 171 #define GLXIIC_LOCK_INIT(_sc) \ 172 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF) 173 #define GLXIIC_SLEEP(_sc) \ 174 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0) 175 #define GLXIIC_WAKEUP(_sc) wakeup(_sc); 176 #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 177 #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 178 179 typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc, 180 uint8_t status); 181 182 static glxiic_state_callback_t glxiic_state_idle_callback; 183 static glxiic_state_callback_t glxiic_state_slave_tx_callback; 184 static glxiic_state_callback_t glxiic_state_slave_rx_callback; 185 static glxiic_state_callback_t glxiic_state_master_addr_callback; 186 static glxiic_state_callback_t glxiic_state_master_tx_callback; 187 static glxiic_state_callback_t glxiic_state_master_rx_callback; 188 static glxiic_state_callback_t glxiic_state_master_stop_callback; 189 190 struct glxiic_state_table_entry { 191 glxiic_state_callback_t *callback; 192 boolean_t master; 193 }; 194 typedef struct glxiic_state_table_entry glxiic_state_table_entry_t; 195 196 static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = { 197 [GLXIIC_STATE_IDLE] = { 198 .callback = &glxiic_state_idle_callback, 199 .master = FALSE, 200 }, 201 202 [GLXIIC_STATE_SLAVE_TX] = { 203 .callback = &glxiic_state_slave_tx_callback, 204 .master = FALSE, 205 }, 206 207 [GLXIIC_STATE_SLAVE_RX] = { 208 .callback = &glxiic_state_slave_rx_callback, 209 .master = FALSE, 210 }, 211 212 [GLXIIC_STATE_MASTER_ADDR] = { 213 .callback = &glxiic_state_master_addr_callback, 214 .master = TRUE, 215 }, 216 217 [GLXIIC_STATE_MASTER_TX] = { 218 .callback = &glxiic_state_master_tx_callback, 219 .master = TRUE, 220 }, 221 222 [GLXIIC_STATE_MASTER_RX] = { 223 .callback = &glxiic_state_master_rx_callback, 224 .master = TRUE, 225 }, 226 227 [GLXIIC_STATE_MASTER_STOP] = { 228 .callback = &glxiic_state_master_stop_callback, 229 .master = TRUE, 230 }, 231 }; 232 233 static void glxiic_identify(driver_t *driver, device_t parent); 234 static int glxiic_probe(device_t dev); 235 static int glxiic_attach(device_t dev); 236 static int glxiic_detach(device_t dev); 237 238 static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc); 239 static void glxiic_stop_locked(struct glxiic_softc *sc); 240 static void glxiic_timeout(void *arg); 241 static void glxiic_start_timeout_locked(struct glxiic_softc *sc); 242 static void glxiic_set_state_locked(struct glxiic_softc *sc, 243 glxiic_state_t state); 244 static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc, 245 uint8_t status); 246 static void glxiic_intr(void *arg); 247 248 static int glxiic_reset(device_t dev, u_char speed, u_char addr, 249 u_char *oldaddr); 250 static int glxiic_transfer(device_t dev, struct iic_msg *msgs, 251 uint32_t nmsgs); 252 253 static void glxiic_smb_map_interrupt(int irq); 254 static void glxiic_gpio_enable(struct glxiic_softc *sc); 255 static void glxiic_gpio_disable(struct glxiic_softc *sc); 256 static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, 257 uint8_t addr); 258 static void glxiic_smb_disable(struct glxiic_softc *sc); 259 260 static device_method_t glxiic_methods[] = { 261 DEVMETHOD(device_identify, glxiic_identify), 262 DEVMETHOD(device_probe, glxiic_probe), 263 DEVMETHOD(device_attach, glxiic_attach), 264 DEVMETHOD(device_detach, glxiic_detach), 265 266 DEVMETHOD(iicbus_reset, glxiic_reset), 267 DEVMETHOD(iicbus_transfer, glxiic_transfer), 268 DEVMETHOD(iicbus_callback, iicbus_null_callback), 269 270 { 0, 0 } 271 }; 272 273 static driver_t glxiic_driver = { 274 "glxiic", 275 glxiic_methods, 276 sizeof(struct glxiic_softc), 277 }; 278 279 static devclass_t glxiic_devclass; 280 281 DRIVER_MODULE(glxiic, isab, glxiic_driver, glxiic_devclass, 0, 0); 282 DRIVER_MODULE(iicbus, glxiic, iicbus_driver, iicbus_devclass, 0, 0); 283 MODULE_DEPEND(glxiic, iicbus, 1, 1, 1); 284 285 static void 286 glxiic_identify(driver_t *driver, device_t parent) 287 { 288 289 /* Prevent child from being added more than once. */ 290 if (device_find_child(parent, driver->name, -1) != NULL) 291 return; 292 293 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) { 294 if (device_add_child(parent, driver->name, -1) == NULL) 295 device_printf(parent, "Could not add glxiic child\n"); 296 } 297 } 298 299 static int 300 glxiic_probe(device_t dev) 301 { 302 303 if (resource_disabled("glxiic", device_get_unit(dev))) 304 return (ENXIO); 305 306 device_set_desc(dev, "AMD Geode CS5536 SMBus controller"); 307 308 return (BUS_PROBE_DEFAULT); 309 } 310 311 static int 312 glxiic_attach(device_t dev) 313 { 314 struct glxiic_softc *sc; 315 struct sysctl_ctx_list *ctx; 316 struct sysctl_oid *tree; 317 int error, irq, unit; 318 uint32_t irq_map; 319 320 sc = device_get_softc(dev); 321 sc->dev = dev; 322 sc->state = GLXIIC_STATE_IDLE; 323 error = 0; 324 325 GLXIIC_LOCK_INIT(sc); 326 callout_init_mtx(&sc->callout, &sc->mtx, 0); 327 328 sc->smb_rid = PCIR_BAR(0); 329 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid, 330 RF_ACTIVE); 331 if (sc->smb_res == NULL) { 332 device_printf(dev, "Could not allocate SMBus I/O port\n"); 333 error = ENXIO; 334 goto out; 335 } 336 337 sc->gpio_rid = PCIR_BAR(1); 338 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 339 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE); 340 if (sc->gpio_res == NULL) { 341 device_printf(dev, "Could not allocate GPIO I/O port\n"); 342 error = ENXIO; 343 goto out; 344 } 345 346 /* Ensure the controller is not enabled by firmware. */ 347 glxiic_smb_disable(sc); 348 349 /* Read the existing IRQ map. */ 350 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 351 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 352 353 unit = device_get_unit(dev); 354 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) { 355 if (irq < 1 || irq > 15) { 356 device_printf(dev, "Bad value %d for glxiic.%d.irq\n", 357 irq, unit); 358 error = ENXIO; 359 goto out; 360 } 361 362 if (bootverbose) 363 device_printf(dev, "Using irq %d set by hint\n", irq); 364 } else if (sc->old_irq != 0) { 365 if (bootverbose) 366 device_printf(dev, "Using irq %d set by firmware\n", 367 irq); 368 irq = sc->old_irq; 369 } else { 370 device_printf(dev, "No irq mapped by firmware"); 371 printf(" and no glxiic.%d.irq hint provided\n", unit); 372 error = ENXIO; 373 goto out; 374 } 375 376 /* Map the SMBus interrupt to the requested legacy IRQ. */ 377 glxiic_smb_map_interrupt(irq); 378 379 sc->irq_rid = 0; 380 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 381 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE); 382 if (sc->irq_res == NULL) { 383 device_printf(dev, "Could not allocate IRQ %d\n", irq); 384 error = ENXIO; 385 goto out; 386 } 387 388 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 389 NULL, glxiic_intr, sc, &(sc->irq_handler)); 390 if (error != 0) { 391 device_printf(dev, "Could not setup IRQ handler\n"); 392 error = ENXIO; 393 goto out; 394 } 395 396 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 397 device_printf(dev, "Could not allocate iicbus instance\n"); 398 error = ENXIO; 399 goto out; 400 } 401 402 ctx = device_get_sysctl_ctx(dev); 403 tree = device_get_sysctl_tree(dev); 404 405 sc->timeout = GLXIIC_DEFAULT_TIMEOUT; 406 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 407 "timeout", CTLFLAG_RWTUN, &sc->timeout, 0, 408 "activity timeout in ms"); 409 410 glxiic_gpio_enable(sc); 411 glxiic_smb_enable(sc, IIC_FASTEST, 0); 412 413 /* Probe and attach the iicbus when interrupts are available. */ 414 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 415 error = 0; 416 417 out: 418 if (error != 0) { 419 callout_drain(&sc->callout); 420 421 if (sc->iicbus != NULL) 422 device_delete_child(dev, sc->iicbus); 423 if (sc->smb_res != NULL) { 424 glxiic_smb_disable(sc); 425 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 426 sc->smb_res); 427 } 428 if (sc->gpio_res != NULL) { 429 glxiic_gpio_disable(sc); 430 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 431 sc->gpio_res); 432 } 433 if (sc->irq_handler != NULL) 434 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 435 if (sc->irq_res != NULL) 436 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 437 sc->irq_res); 438 439 /* Restore the old SMBus interrupt mapping. */ 440 glxiic_smb_map_interrupt(sc->old_irq); 441 442 GLXIIC_LOCK_DESTROY(sc); 443 } 444 445 return (error); 446 } 447 448 static int 449 glxiic_detach(device_t dev) 450 { 451 struct glxiic_softc *sc; 452 int error; 453 454 sc = device_get_softc(dev); 455 456 error = bus_generic_detach(dev); 457 if (error != 0) 458 goto out; 459 if (sc->iicbus != NULL) 460 error = device_delete_child(dev, sc->iicbus); 461 462 out: 463 callout_drain(&sc->callout); 464 465 if (sc->smb_res != NULL) { 466 glxiic_smb_disable(sc); 467 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 468 sc->smb_res); 469 } 470 if (sc->gpio_res != NULL) { 471 glxiic_gpio_disable(sc); 472 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 473 sc->gpio_res); 474 } 475 if (sc->irq_handler != NULL) 476 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 477 if (sc->irq_res != NULL) 478 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 479 sc->irq_res); 480 481 /* Restore the old SMBus interrupt mapping. */ 482 glxiic_smb_map_interrupt(sc->old_irq); 483 484 GLXIIC_LOCK_DESTROY(sc); 485 486 return (error); 487 } 488 489 static uint8_t 490 glxiic_read_status_locked(struct glxiic_softc *sc) 491 { 492 uint8_t status; 493 494 GLXIIC_ASSERT_LOCKED(sc); 495 496 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS); 497 498 /* Clear all status flags except SDAST and STASTR after reading. */ 499 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT | 500 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT | 501 GLXIIC_SMB_STS_NMATCH_BIT)); 502 503 return (status); 504 } 505 506 static void 507 glxiic_stop_locked(struct glxiic_softc *sc) 508 { 509 uint8_t status, ctrl1; 510 511 GLXIIC_ASSERT_LOCKED(sc); 512 513 status = glxiic_read_status_locked(sc); 514 515 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 516 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 517 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT); 518 519 /* 520 * Perform a dummy read of SDA in master receive mode to clear 521 * SDAST if set. 522 */ 523 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 && 524 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0) 525 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 526 527 /* Check stall after start bit and clear if needed */ 528 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 529 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 530 GLXIIC_SMB_STS_STASTR_BIT); 531 } 532 } 533 534 static void 535 glxiic_timeout(void *arg) 536 { 537 struct glxiic_softc *sc; 538 uint8_t error; 539 540 sc = (struct glxiic_softc *)arg; 541 542 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state); 543 544 if (glxiic_state_table[sc->state].master) { 545 sc->error = IIC_ETIMEOUT; 546 GLXIIC_WAKEUP(sc); 547 } else { 548 error = IIC_ETIMEOUT; 549 iicbus_intr(sc->iicbus, INTR_ERROR, &error); 550 } 551 552 glxiic_smb_disable(sc); 553 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr); 554 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 555 } 556 557 static void 558 glxiic_start_timeout_locked(struct glxiic_softc *sc) 559 { 560 561 GLXIIC_ASSERT_LOCKED(sc); 562 563 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0, 564 glxiic_timeout, sc, 0); 565 } 566 567 static void 568 glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state) 569 { 570 571 GLXIIC_ASSERT_LOCKED(sc); 572 573 if (state == GLXIIC_STATE_IDLE) 574 callout_stop(&sc->callout); 575 else if (sc->timeout > 0) 576 glxiic_start_timeout_locked(sc); 577 578 sc->state = state; 579 } 580 581 static int 582 glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status) 583 { 584 uint8_t ctrl_sts, addr; 585 586 GLXIIC_ASSERT_LOCKED(sc); 587 588 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS); 589 590 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) { 591 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) { 592 addr = sc->addr | LSB; 593 glxiic_set_state_locked(sc, 594 GLXIIC_STATE_SLAVE_TX); 595 } else { 596 addr = sc->addr & ~LSB; 597 glxiic_set_state_locked(sc, 598 GLXIIC_STATE_SLAVE_RX); 599 } 600 iicbus_intr(sc->iicbus, INTR_START, &addr); 601 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) { 602 addr = 0; 603 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX); 604 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr); 605 } else { 606 GLXIIC_DEBUG_LOG("unknown slave match"); 607 return (IIC_ESTATUS); 608 } 609 610 return (IIC_NOERR); 611 } 612 613 static int 614 glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status) 615 { 616 617 GLXIIC_ASSERT_LOCKED(sc); 618 619 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 620 GLXIIC_DEBUG_LOG("bus error in idle"); 621 return (IIC_EBUSERR); 622 } 623 624 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 625 return (glxiic_handle_slave_match_locked(sc, status)); 626 } 627 628 return (IIC_NOERR); 629 } 630 631 static int 632 glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status) 633 { 634 uint8_t data; 635 636 GLXIIC_ASSERT_LOCKED(sc); 637 638 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 639 GLXIIC_DEBUG_LOG("bus error in slave tx"); 640 return (IIC_EBUSERR); 641 } 642 643 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 644 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 645 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 646 return (IIC_NOERR); 647 } 648 649 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 650 iicbus_intr(sc->iicbus, INTR_NOACK, NULL); 651 return (IIC_NOERR); 652 } 653 654 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 655 /* Handle repeated start in slave mode. */ 656 return (glxiic_handle_slave_match_locked(sc, status)); 657 } 658 659 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 660 GLXIIC_DEBUG_LOG("not awaiting data in slave tx"); 661 return (IIC_ESTATUS); 662 } 663 664 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); 665 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data); 666 667 glxiic_start_timeout_locked(sc); 668 669 return (IIC_NOERR); 670 } 671 672 static int 673 glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status) 674 { 675 uint8_t data; 676 677 GLXIIC_ASSERT_LOCKED(sc); 678 679 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 680 GLXIIC_DEBUG_LOG("bus error in slave rx"); 681 return (IIC_EBUSERR); 682 } 683 684 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 685 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 686 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 687 return (IIC_NOERR); 688 } 689 690 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 691 /* Handle repeated start in slave mode. */ 692 return (glxiic_handle_slave_match_locked(sc, status)); 693 } 694 695 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 696 GLXIIC_DEBUG_LOG("no pending data in slave rx"); 697 return (IIC_ESTATUS); 698 } 699 700 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 701 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data); 702 703 glxiic_start_timeout_locked(sc); 704 705 return (IIC_NOERR); 706 } 707 708 static int 709 glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status) 710 { 711 uint8_t slave; 712 uint8_t ctrl1; 713 714 GLXIIC_ASSERT_LOCKED(sc); 715 716 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 717 GLXIIC_DEBUG_LOG("bus error after master start"); 718 return (IIC_EBUSERR); 719 } 720 721 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 722 GLXIIC_DEBUG_LOG("not bus master after master start"); 723 return (IIC_ESTATUS); 724 } 725 726 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 727 GLXIIC_DEBUG_LOG("not awaiting address in master addr"); 728 return (IIC_ESTATUS); 729 } 730 731 if ((sc->msg->flags & IIC_M_RD) != 0) { 732 slave = sc->msg->slave | LSB; 733 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX); 734 } else { 735 slave = sc->msg->slave & ~LSB; 736 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX); 737 } 738 739 sc->data = sc->msg->buf; 740 sc->ndata = sc->msg->len; 741 742 /* Handle address-only transfer. */ 743 if (sc->ndata == 0) 744 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 745 746 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave); 747 748 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) { 749 /* Last byte from slave, set NACK. */ 750 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 751 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 752 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 753 } 754 755 return (IIC_NOERR); 756 } 757 758 static int 759 glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status) 760 { 761 762 GLXIIC_ASSERT_LOCKED(sc); 763 764 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 765 GLXIIC_DEBUG_LOG("bus error in master tx"); 766 return (IIC_EBUSERR); 767 } 768 769 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 770 GLXIIC_DEBUG_LOG("not bus master in master tx"); 771 return (IIC_ESTATUS); 772 } 773 774 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 775 GLXIIC_DEBUG_LOG("slave nack in master tx"); 776 return (IIC_ENOACK); 777 } 778 779 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 780 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 781 GLXIIC_SMB_STS_STASTR_BIT); 782 } 783 784 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 785 GLXIIC_DEBUG_LOG("not awaiting data in master tx"); 786 return (IIC_ESTATUS); 787 } 788 789 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++); 790 if (--sc->ndata == 0) 791 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 792 else 793 glxiic_start_timeout_locked(sc); 794 795 return (IIC_NOERR); 796 } 797 798 static int 799 glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status) 800 { 801 uint8_t ctrl1; 802 803 GLXIIC_ASSERT_LOCKED(sc); 804 805 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 806 GLXIIC_DEBUG_LOG("bus error in master rx"); 807 return (IIC_EBUSERR); 808 } 809 810 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 811 GLXIIC_DEBUG_LOG("not bus master in master rx"); 812 return (IIC_ESTATUS); 813 } 814 815 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 816 GLXIIC_DEBUG_LOG("slave nack in rx"); 817 return (IIC_ENOACK); 818 } 819 820 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 821 /* Bus is stalled, clear and wait for data. */ 822 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 823 GLXIIC_SMB_STS_STASTR_BIT); 824 return (IIC_NOERR); 825 } 826 827 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 828 GLXIIC_DEBUG_LOG("no pending data in master rx"); 829 return (IIC_ESTATUS); 830 } 831 832 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 833 if (--sc->ndata == 0) { 834 /* Proceed with stop on reading last byte. */ 835 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 836 return (glxiic_state_table[sc->state].callback(sc, status)); 837 } 838 839 if (sc->ndata == 1) { 840 /* Last byte from slave, set NACK. */ 841 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 842 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 843 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 844 } 845 846 glxiic_start_timeout_locked(sc); 847 848 return (IIC_NOERR); 849 } 850 851 static int 852 glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status) 853 { 854 uint8_t ctrl1; 855 856 GLXIIC_ASSERT_LOCKED(sc); 857 858 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 859 GLXIIC_DEBUG_LOG("bus error in master stop"); 860 return (IIC_EBUSERR); 861 } 862 863 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 864 GLXIIC_DEBUG_LOG("not bus master in master stop"); 865 return (IIC_ESTATUS); 866 } 867 868 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 869 GLXIIC_DEBUG_LOG("slave nack in master stop"); 870 return (IIC_ENOACK); 871 } 872 873 if (--sc->nmsgs > 0) { 874 /* Start transfer of next message. */ 875 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) { 876 glxiic_stop_locked(sc); 877 } 878 879 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 880 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 881 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 882 883 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 884 sc->msg++; 885 } else { 886 /* Last message. */ 887 glxiic_stop_locked(sc); 888 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 889 sc->error = IIC_NOERR; 890 GLXIIC_WAKEUP(sc); 891 } 892 893 return (IIC_NOERR); 894 } 895 896 static void 897 glxiic_intr(void *arg) 898 { 899 struct glxiic_softc *sc; 900 int error; 901 uint8_t status, data; 902 903 sc = (struct glxiic_softc *)arg; 904 905 GLXIIC_LOCK(sc); 906 907 status = glxiic_read_status_locked(sc); 908 909 /* Check if this interrupt originated from the SMBus. */ 910 if ((status & 911 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) { 912 913 error = glxiic_state_table[sc->state].callback(sc, status); 914 915 if (error != IIC_NOERR) { 916 if (glxiic_state_table[sc->state].master) { 917 glxiic_stop_locked(sc); 918 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 919 sc->error = error; 920 GLXIIC_WAKEUP(sc); 921 } else { 922 data = error & 0xff; 923 iicbus_intr(sc->iicbus, INTR_ERROR, &data); 924 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 925 } 926 } 927 } 928 929 GLXIIC_UNLOCK(sc); 930 } 931 932 static int 933 glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 934 { 935 struct glxiic_softc *sc; 936 937 sc = device_get_softc(dev); 938 939 GLXIIC_LOCK(sc); 940 941 if (oldaddr != NULL) 942 *oldaddr = sc->addr; 943 sc->addr = addr; 944 945 /* A disable/enable cycle resets the controller. */ 946 glxiic_smb_disable(sc); 947 glxiic_smb_enable(sc, speed, addr); 948 949 if (glxiic_state_table[sc->state].master) { 950 sc->error = IIC_ESTATUS; 951 GLXIIC_WAKEUP(sc); 952 } 953 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 954 955 GLXIIC_UNLOCK(sc); 956 957 return (IIC_NOERR); 958 } 959 960 static int 961 glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 962 { 963 struct glxiic_softc *sc; 964 int error; 965 uint8_t ctrl1; 966 967 sc = device_get_softc(dev); 968 969 GLXIIC_LOCK(sc); 970 971 if (sc->state != GLXIIC_STATE_IDLE) { 972 error = IIC_EBUSBSY; 973 goto out; 974 } 975 976 sc->msg = msgs; 977 sc->nmsgs = nmsgs; 978 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 979 980 /* Set start bit and let glxiic_intr() handle the transfer. */ 981 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 982 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 983 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 984 985 GLXIIC_SLEEP(sc); 986 error = sc->error; 987 out: 988 GLXIIC_UNLOCK(sc); 989 990 return (error); 991 } 992 993 static void 994 glxiic_smb_map_interrupt(int irq) 995 { 996 uint32_t irq_map; 997 int old_irq; 998 999 /* Protect the read-modify-write operation. */ 1000 critical_enter(); 1001 1002 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 1003 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 1004 1005 if (irq != old_irq) { 1006 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq); 1007 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq); 1008 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map); 1009 } 1010 1011 critical_exit(); 1012 } 1013 1014 static void 1015 glxiic_gpio_enable(struct glxiic_softc *sc) 1016 { 1017 1018 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1019 GLXIIC_GPIO_14_15_ENABLE); 1020 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1021 GLXIIC_GPIO_14_15_ENABLE); 1022 } 1023 1024 static void 1025 glxiic_gpio_disable(struct glxiic_softc *sc) 1026 { 1027 1028 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1029 GLXIIC_GPIO_14_15_DISABLE); 1030 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1031 GLXIIC_GPIO_14_15_DISABLE); 1032 } 1033 1034 static void 1035 glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr) 1036 { 1037 uint8_t ctrl1; 1038 1039 ctrl1 = 0; 1040 1041 switch (speed) { 1042 case IIC_SLOW: 1043 sc->sclfrq = GLXIIC_SLOW; 1044 break; 1045 case IIC_FAST: 1046 sc->sclfrq = GLXIIC_FAST; 1047 break; 1048 case IIC_FASTEST: 1049 sc->sclfrq = GLXIIC_FASTEST; 1050 break; 1051 case IIC_UNKNOWN: 1052 default: 1053 /* Reuse last frequency. */ 1054 break; 1055 } 1056 1057 /* Set bus speed and enable controller. */ 1058 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1059 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT); 1060 1061 if (addr != 0) { 1062 /* Enable new match and global call match interrupts. */ 1063 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT | 1064 GLXIIC_SMB_CTRL1_GCMEN_BIT; 1065 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 1066 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr)); 1067 } else { 1068 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0); 1069 } 1070 1071 /* Enable stall after start and interrupt. */ 1072 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 1073 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT); 1074 } 1075 1076 static void 1077 glxiic_smb_disable(struct glxiic_softc *sc) 1078 { 1079 uint16_t sclfrq; 1080 1081 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2); 1082 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1083 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT); 1084 } 1085