1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 /* 30 * AMD Geode LX CS5536 System Management Bus controller. 31 * 32 * Although AMD refers to this device as an SMBus controller, it 33 * really is an I2C controller (It lacks SMBus ALERT# and Alert 34 * Response support). 35 * 36 * The driver is implemented as an interrupt-driven state machine, 37 * supporting both master and slave mode. 38 */ 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/sysctl.h> 47 #ifdef GLXIIC_DEBUG 48 #include <sys/syslog.h> 49 #endif 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <dev/iicbus/iiconf.h> 59 #include <dev/iicbus/iicbus.h> 60 61 #include "iicbus_if.h" 62 63 /* CS5536 PCI-ISA ID. */ 64 #define GLXIIC_CS5536_DEV_ID 0x20901022 65 66 /* MSRs. */ 67 #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021 68 69 /* Bus speeds. */ 70 #define GLXIIC_SLOW 0x0258 /* 10 kHz. */ 71 #define GLXIIC_FAST 0x0078 /* 50 kHz. */ 72 #define GLXIIC_FASTEST 0x003c /* 100 kHz. */ 73 74 /* Default bus activity timeout in milliseconds. */ 75 #define GLXIIC_DEFAULT_TIMEOUT 35 76 77 /* GPIO register offsets. */ 78 #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10 79 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34 80 81 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */ 82 #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000 83 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000 84 85 /* SMB register offsets. */ 86 #define GLXIIC_SMB_SDA 0x00 87 #define GLXIIC_SMB_STS 0x01 88 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7) 89 #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6) 90 #define GLXIIC_SMB_STS_BER_BIT (1 << 5) 91 #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4) 92 #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3) 93 #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2) 94 #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1) 95 #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0) 96 #define GLXIIC_SMB_CTRL_STS 0x02 97 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5) 98 #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4) 99 #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3) 100 #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2) 101 #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1) 102 #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0) 103 #define GLXIIC_SMB_CTRL1 0x03 104 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7) 105 #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6) 106 #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5) 107 #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4) 108 #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2) 109 #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1) 110 #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0) 111 #define GLXIIC_SMB_ADDR 0x04 112 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7) 113 #define GLXIIC_SMB_CTRL2 0x05 114 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0) 115 #define GLXIIC_SMB_CTRL3 0x06 116 117 typedef enum { 118 GLXIIC_STATE_IDLE, 119 GLXIIC_STATE_SLAVE_TX, 120 GLXIIC_STATE_SLAVE_RX, 121 GLXIIC_STATE_MASTER_ADDR, 122 GLXIIC_STATE_MASTER_TX, 123 GLXIIC_STATE_MASTER_RX, 124 GLXIIC_STATE_MASTER_STOP, 125 GLXIIC_STATE_MAX, 126 } glxiic_state_t; 127 128 struct glxiic_softc { 129 device_t dev; /* Myself. */ 130 device_t iicbus; /* IIC bus. */ 131 struct mtx mtx; /* Lock. */ 132 glxiic_state_t state; /* Driver state. */ 133 struct callout callout; /* Driver state timeout callout. */ 134 int timeout; /* Driver state timeout (ms). */ 135 136 int smb_rid; /* SMB controller resource ID. */ 137 struct resource *smb_res; /* SMB controller resource. */ 138 int gpio_rid; /* GPIO resource ID. */ 139 struct resource *gpio_res; /* GPIO resource. */ 140 141 int irq_rid; /* IRQ resource ID. */ 142 struct resource *irq_res; /* IRQ resource. */ 143 void *irq_handler; /* IRQ handler cookie. */ 144 int old_irq; /* IRQ mapped by board firmware. */ 145 146 struct iic_msg *msg; /* Current master mode message. */ 147 uint32_t nmsgs; /* Number of messages remaining. */ 148 uint8_t *data; /* Current master mode data byte. */ 149 uint16_t ndata; /* Number of data bytes remaining. */ 150 int error; /* Last master mode error. */ 151 152 uint8_t addr; /* Own address. */ 153 uint16_t sclfrq; /* Bus frequency. */ 154 }; 155 156 #ifdef GLXIIC_DEBUG 157 #define GLXIIC_DEBUG_LOG(fmt, args...) \ 158 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args) 159 #else 160 #define GLXIIC_DEBUG_LOG(fmt, args...) 161 #endif 162 163 #define GLXIIC_SCLFRQ(n) ((n << 1)) 164 #define GLXIIC_SMBADDR(n) ((n >> 1)) 165 #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16)) 166 #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf) 167 168 #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx) 169 #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx) 170 #define GLXIIC_LOCK_INIT(_sc) \ 171 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF) 172 #define GLXIIC_SLEEP(_sc) \ 173 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0) 174 #define GLXIIC_WAKEUP(_sc) wakeup(_sc); 175 #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 176 #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 177 178 typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc, 179 uint8_t status); 180 181 static glxiic_state_callback_t glxiic_state_idle_callback; 182 static glxiic_state_callback_t glxiic_state_slave_tx_callback; 183 static glxiic_state_callback_t glxiic_state_slave_rx_callback; 184 static glxiic_state_callback_t glxiic_state_master_addr_callback; 185 static glxiic_state_callback_t glxiic_state_master_tx_callback; 186 static glxiic_state_callback_t glxiic_state_master_rx_callback; 187 static glxiic_state_callback_t glxiic_state_master_stop_callback; 188 189 struct glxiic_state_table_entry { 190 glxiic_state_callback_t *callback; 191 boolean_t master; 192 }; 193 typedef struct glxiic_state_table_entry glxiic_state_table_entry_t; 194 195 static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = { 196 [GLXIIC_STATE_IDLE] = { 197 .callback = &glxiic_state_idle_callback, 198 .master = FALSE, 199 }, 200 201 [GLXIIC_STATE_SLAVE_TX] = { 202 .callback = &glxiic_state_slave_tx_callback, 203 .master = FALSE, 204 }, 205 206 [GLXIIC_STATE_SLAVE_RX] = { 207 .callback = &glxiic_state_slave_rx_callback, 208 .master = FALSE, 209 }, 210 211 [GLXIIC_STATE_MASTER_ADDR] = { 212 .callback = &glxiic_state_master_addr_callback, 213 .master = TRUE, 214 }, 215 216 [GLXIIC_STATE_MASTER_TX] = { 217 .callback = &glxiic_state_master_tx_callback, 218 .master = TRUE, 219 }, 220 221 [GLXIIC_STATE_MASTER_RX] = { 222 .callback = &glxiic_state_master_rx_callback, 223 .master = TRUE, 224 }, 225 226 [GLXIIC_STATE_MASTER_STOP] = { 227 .callback = &glxiic_state_master_stop_callback, 228 .master = TRUE, 229 }, 230 }; 231 232 static void glxiic_identify(driver_t *driver, device_t parent); 233 static int glxiic_probe(device_t dev); 234 static int glxiic_attach(device_t dev); 235 static int glxiic_detach(device_t dev); 236 237 static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc); 238 static void glxiic_stop_locked(struct glxiic_softc *sc); 239 static void glxiic_timeout(void *arg); 240 static void glxiic_start_timeout_locked(struct glxiic_softc *sc); 241 static void glxiic_set_state_locked(struct glxiic_softc *sc, 242 glxiic_state_t state); 243 static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc, 244 uint8_t status); 245 static void glxiic_intr(void *arg); 246 247 static int glxiic_reset(device_t dev, u_char speed, u_char addr, 248 u_char *oldaddr); 249 static int glxiic_transfer(device_t dev, struct iic_msg *msgs, 250 uint32_t nmsgs); 251 252 static void glxiic_smb_map_interrupt(int irq); 253 static void glxiic_gpio_enable(struct glxiic_softc *sc); 254 static void glxiic_gpio_disable(struct glxiic_softc *sc); 255 static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, 256 uint8_t addr); 257 static void glxiic_smb_disable(struct glxiic_softc *sc); 258 259 static device_method_t glxiic_methods[] = { 260 DEVMETHOD(device_identify, glxiic_identify), 261 DEVMETHOD(device_probe, glxiic_probe), 262 DEVMETHOD(device_attach, glxiic_attach), 263 DEVMETHOD(device_detach, glxiic_detach), 264 265 DEVMETHOD(iicbus_reset, glxiic_reset), 266 DEVMETHOD(iicbus_transfer, glxiic_transfer), 267 DEVMETHOD(iicbus_callback, iicbus_null_callback), 268 269 { 0, 0 } 270 }; 271 272 static driver_t glxiic_driver = { 273 "glxiic", 274 glxiic_methods, 275 sizeof(struct glxiic_softc), 276 }; 277 278 DRIVER_MODULE(glxiic, isab, glxiic_driver, 0, 0); 279 DRIVER_MODULE(iicbus, glxiic, iicbus_driver, 0, 0); 280 MODULE_DEPEND(glxiic, iicbus, 1, 1, 1); 281 282 static void 283 glxiic_identify(driver_t *driver, device_t parent) 284 { 285 286 /* Prevent child from being added more than once. */ 287 if (device_find_child(parent, driver->name, DEVICE_UNIT_ANY) != NULL) 288 return; 289 290 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) { 291 if (device_add_child(parent, driver->name, DEVICE_UNIT_ANY) == NULL) 292 device_printf(parent, "Could not add glxiic child\n"); 293 } 294 } 295 296 static int 297 glxiic_probe(device_t dev) 298 { 299 300 if (resource_disabled("glxiic", device_get_unit(dev))) 301 return (ENXIO); 302 303 device_set_desc(dev, "AMD Geode CS5536 SMBus controller"); 304 305 return (BUS_PROBE_DEFAULT); 306 } 307 308 static int 309 glxiic_attach(device_t dev) 310 { 311 struct glxiic_softc *sc; 312 struct sysctl_ctx_list *ctx; 313 struct sysctl_oid *tree; 314 int error, irq, unit; 315 uint32_t irq_map; 316 317 sc = device_get_softc(dev); 318 sc->dev = dev; 319 sc->state = GLXIIC_STATE_IDLE; 320 error = 0; 321 322 GLXIIC_LOCK_INIT(sc); 323 callout_init_mtx(&sc->callout, &sc->mtx, 0); 324 325 sc->smb_rid = PCIR_BAR(0); 326 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid, 327 RF_ACTIVE); 328 if (sc->smb_res == NULL) { 329 device_printf(dev, "Could not allocate SMBus I/O port\n"); 330 error = ENXIO; 331 goto out; 332 } 333 334 sc->gpio_rid = PCIR_BAR(1); 335 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 336 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE); 337 if (sc->gpio_res == NULL) { 338 device_printf(dev, "Could not allocate GPIO I/O port\n"); 339 error = ENXIO; 340 goto out; 341 } 342 343 /* Ensure the controller is not enabled by firmware. */ 344 glxiic_smb_disable(sc); 345 346 /* Read the existing IRQ map. */ 347 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 348 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 349 350 unit = device_get_unit(dev); 351 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) { 352 if (irq < 1 || irq > 15) { 353 device_printf(dev, "Bad value %d for glxiic.%d.irq\n", 354 irq, unit); 355 error = ENXIO; 356 goto out; 357 } 358 359 if (bootverbose) 360 device_printf(dev, "Using irq %d set by hint\n", irq); 361 } else if (sc->old_irq != 0) { 362 if (bootverbose) 363 device_printf(dev, "Using irq %d set by firmware\n", 364 irq); 365 irq = sc->old_irq; 366 } else { 367 device_printf(dev, "No irq mapped by firmware"); 368 printf(" and no glxiic.%d.irq hint provided\n", unit); 369 error = ENXIO; 370 goto out; 371 } 372 373 /* Map the SMBus interrupt to the requested legacy IRQ. */ 374 glxiic_smb_map_interrupt(irq); 375 376 sc->irq_rid = 0; 377 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 378 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE); 379 if (sc->irq_res == NULL) { 380 device_printf(dev, "Could not allocate IRQ %d\n", irq); 381 error = ENXIO; 382 goto out; 383 } 384 385 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 386 NULL, glxiic_intr, sc, &(sc->irq_handler)); 387 if (error != 0) { 388 device_printf(dev, "Could not setup IRQ handler\n"); 389 error = ENXIO; 390 goto out; 391 } 392 393 if ((sc->iicbus = device_add_child(dev, "iicbus", 394 DEVICE_UNIT_ANY)) == NULL) { 395 device_printf(dev, "Could not allocate iicbus instance\n"); 396 error = ENXIO; 397 goto out; 398 } 399 400 ctx = device_get_sysctl_ctx(dev); 401 tree = device_get_sysctl_tree(dev); 402 403 sc->timeout = GLXIIC_DEFAULT_TIMEOUT; 404 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 405 "timeout", CTLFLAG_RWTUN, &sc->timeout, 0, 406 "activity timeout in ms"); 407 408 glxiic_gpio_enable(sc); 409 glxiic_smb_enable(sc, IIC_FASTEST, 0); 410 411 /* Probe and attach the iicbus when interrupts are available. */ 412 bus_delayed_attach_children(dev); 413 414 out: 415 if (error != 0) { 416 callout_drain(&sc->callout); 417 418 if (sc->iicbus != NULL) 419 device_delete_child(dev, sc->iicbus); 420 if (sc->smb_res != NULL) { 421 glxiic_smb_disable(sc); 422 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 423 sc->smb_res); 424 } 425 if (sc->gpio_res != NULL) { 426 glxiic_gpio_disable(sc); 427 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 428 sc->gpio_res); 429 } 430 if (sc->irq_handler != NULL) 431 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 432 if (sc->irq_res != NULL) 433 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 434 sc->irq_res); 435 436 /* Restore the old SMBus interrupt mapping. */ 437 glxiic_smb_map_interrupt(sc->old_irq); 438 439 GLXIIC_LOCK_DESTROY(sc); 440 } 441 442 return (error); 443 } 444 445 static int 446 glxiic_detach(device_t dev) 447 { 448 struct glxiic_softc *sc; 449 int error; 450 451 sc = device_get_softc(dev); 452 453 error = bus_generic_detach(dev); 454 if (error != 0) 455 return (error); 456 457 callout_drain(&sc->callout); 458 459 if (sc->smb_res != NULL) { 460 glxiic_smb_disable(sc); 461 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 462 sc->smb_res); 463 } 464 if (sc->gpio_res != NULL) { 465 glxiic_gpio_disable(sc); 466 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 467 sc->gpio_res); 468 } 469 if (sc->irq_handler != NULL) 470 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 471 if (sc->irq_res != NULL) 472 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 473 sc->irq_res); 474 475 /* Restore the old SMBus interrupt mapping. */ 476 glxiic_smb_map_interrupt(sc->old_irq); 477 478 GLXIIC_LOCK_DESTROY(sc); 479 480 return (0); 481 } 482 483 static uint8_t 484 glxiic_read_status_locked(struct glxiic_softc *sc) 485 { 486 uint8_t status; 487 488 GLXIIC_ASSERT_LOCKED(sc); 489 490 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS); 491 492 /* Clear all status flags except SDAST and STASTR after reading. */ 493 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT | 494 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT | 495 GLXIIC_SMB_STS_NMATCH_BIT)); 496 497 return (status); 498 } 499 500 static void 501 glxiic_stop_locked(struct glxiic_softc *sc) 502 { 503 uint8_t status, ctrl1; 504 505 GLXIIC_ASSERT_LOCKED(sc); 506 507 status = glxiic_read_status_locked(sc); 508 509 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 510 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 511 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT); 512 513 /* 514 * Perform a dummy read of SDA in master receive mode to clear 515 * SDAST if set. 516 */ 517 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 && 518 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0) 519 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 520 521 /* Check stall after start bit and clear if needed */ 522 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 523 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 524 GLXIIC_SMB_STS_STASTR_BIT); 525 } 526 } 527 528 static void 529 glxiic_timeout(void *arg) 530 { 531 struct glxiic_softc *sc; 532 uint8_t error; 533 534 sc = (struct glxiic_softc *)arg; 535 536 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state); 537 538 if (glxiic_state_table[sc->state].master) { 539 sc->error = IIC_ETIMEOUT; 540 GLXIIC_WAKEUP(sc); 541 } else { 542 error = IIC_ETIMEOUT; 543 iicbus_intr(sc->iicbus, INTR_ERROR, &error); 544 } 545 546 glxiic_smb_disable(sc); 547 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr); 548 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 549 } 550 551 static void 552 glxiic_start_timeout_locked(struct glxiic_softc *sc) 553 { 554 555 GLXIIC_ASSERT_LOCKED(sc); 556 557 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0, 558 glxiic_timeout, sc, 0); 559 } 560 561 static void 562 glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state) 563 { 564 565 GLXIIC_ASSERT_LOCKED(sc); 566 567 if (state == GLXIIC_STATE_IDLE) 568 callout_stop(&sc->callout); 569 else if (sc->timeout > 0) 570 glxiic_start_timeout_locked(sc); 571 572 sc->state = state; 573 } 574 575 static int 576 glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status) 577 { 578 uint8_t ctrl_sts, addr; 579 580 GLXIIC_ASSERT_LOCKED(sc); 581 582 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS); 583 584 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) { 585 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) { 586 addr = sc->addr | LSB; 587 glxiic_set_state_locked(sc, 588 GLXIIC_STATE_SLAVE_TX); 589 } else { 590 addr = sc->addr & ~LSB; 591 glxiic_set_state_locked(sc, 592 GLXIIC_STATE_SLAVE_RX); 593 } 594 iicbus_intr(sc->iicbus, INTR_START, &addr); 595 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) { 596 addr = 0; 597 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX); 598 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr); 599 } else { 600 GLXIIC_DEBUG_LOG("unknown slave match"); 601 return (IIC_ESTATUS); 602 } 603 604 return (IIC_NOERR); 605 } 606 607 static int 608 glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status) 609 { 610 611 GLXIIC_ASSERT_LOCKED(sc); 612 613 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 614 GLXIIC_DEBUG_LOG("bus error in idle"); 615 return (IIC_EBUSERR); 616 } 617 618 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 619 return (glxiic_handle_slave_match_locked(sc, status)); 620 } 621 622 return (IIC_NOERR); 623 } 624 625 static int 626 glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status) 627 { 628 uint8_t data; 629 630 GLXIIC_ASSERT_LOCKED(sc); 631 632 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 633 GLXIIC_DEBUG_LOG("bus error in slave tx"); 634 return (IIC_EBUSERR); 635 } 636 637 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 638 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 639 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 640 return (IIC_NOERR); 641 } 642 643 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 644 iicbus_intr(sc->iicbus, INTR_NOACK, NULL); 645 return (IIC_NOERR); 646 } 647 648 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 649 /* Handle repeated start in slave mode. */ 650 return (glxiic_handle_slave_match_locked(sc, status)); 651 } 652 653 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 654 GLXIIC_DEBUG_LOG("not awaiting data in slave tx"); 655 return (IIC_ESTATUS); 656 } 657 658 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); 659 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data); 660 661 glxiic_start_timeout_locked(sc); 662 663 return (IIC_NOERR); 664 } 665 666 static int 667 glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status) 668 { 669 uint8_t data; 670 671 GLXIIC_ASSERT_LOCKED(sc); 672 673 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 674 GLXIIC_DEBUG_LOG("bus error in slave rx"); 675 return (IIC_EBUSERR); 676 } 677 678 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 679 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 680 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 681 return (IIC_NOERR); 682 } 683 684 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 685 /* Handle repeated start in slave mode. */ 686 return (glxiic_handle_slave_match_locked(sc, status)); 687 } 688 689 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 690 GLXIIC_DEBUG_LOG("no pending data in slave rx"); 691 return (IIC_ESTATUS); 692 } 693 694 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 695 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data); 696 697 glxiic_start_timeout_locked(sc); 698 699 return (IIC_NOERR); 700 } 701 702 static int 703 glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status) 704 { 705 uint8_t slave; 706 uint8_t ctrl1; 707 708 GLXIIC_ASSERT_LOCKED(sc); 709 710 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 711 GLXIIC_DEBUG_LOG("bus error after master start"); 712 return (IIC_EBUSERR); 713 } 714 715 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 716 GLXIIC_DEBUG_LOG("not bus master after master start"); 717 return (IIC_ESTATUS); 718 } 719 720 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 721 GLXIIC_DEBUG_LOG("not awaiting address in master addr"); 722 return (IIC_ESTATUS); 723 } 724 725 if ((sc->msg->flags & IIC_M_RD) != 0) { 726 slave = sc->msg->slave | LSB; 727 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX); 728 } else { 729 slave = sc->msg->slave & ~LSB; 730 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX); 731 } 732 733 sc->data = sc->msg->buf; 734 sc->ndata = sc->msg->len; 735 736 /* Handle address-only transfer. */ 737 if (sc->ndata == 0) 738 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 739 740 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave); 741 742 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) { 743 /* Last byte from slave, set NACK. */ 744 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 745 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 746 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 747 } 748 749 return (IIC_NOERR); 750 } 751 752 static int 753 glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status) 754 { 755 756 GLXIIC_ASSERT_LOCKED(sc); 757 758 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 759 GLXIIC_DEBUG_LOG("bus error in master tx"); 760 return (IIC_EBUSERR); 761 } 762 763 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 764 GLXIIC_DEBUG_LOG("not bus master in master tx"); 765 return (IIC_ESTATUS); 766 } 767 768 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 769 GLXIIC_DEBUG_LOG("slave nack in master tx"); 770 return (IIC_ENOACK); 771 } 772 773 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 774 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 775 GLXIIC_SMB_STS_STASTR_BIT); 776 } 777 778 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 779 GLXIIC_DEBUG_LOG("not awaiting data in master tx"); 780 return (IIC_ESTATUS); 781 } 782 783 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++); 784 if (--sc->ndata == 0) 785 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 786 else 787 glxiic_start_timeout_locked(sc); 788 789 return (IIC_NOERR); 790 } 791 792 static int 793 glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status) 794 { 795 uint8_t ctrl1; 796 797 GLXIIC_ASSERT_LOCKED(sc); 798 799 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 800 GLXIIC_DEBUG_LOG("bus error in master rx"); 801 return (IIC_EBUSERR); 802 } 803 804 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 805 GLXIIC_DEBUG_LOG("not bus master in master rx"); 806 return (IIC_ESTATUS); 807 } 808 809 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 810 GLXIIC_DEBUG_LOG("slave nack in rx"); 811 return (IIC_ENOACK); 812 } 813 814 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 815 /* Bus is stalled, clear and wait for data. */ 816 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 817 GLXIIC_SMB_STS_STASTR_BIT); 818 return (IIC_NOERR); 819 } 820 821 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 822 GLXIIC_DEBUG_LOG("no pending data in master rx"); 823 return (IIC_ESTATUS); 824 } 825 826 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 827 if (--sc->ndata == 0) { 828 /* Proceed with stop on reading last byte. */ 829 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 830 return (glxiic_state_table[sc->state].callback(sc, status)); 831 } 832 833 if (sc->ndata == 1) { 834 /* Last byte from slave, set NACK. */ 835 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 836 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 837 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 838 } 839 840 glxiic_start_timeout_locked(sc); 841 842 return (IIC_NOERR); 843 } 844 845 static int 846 glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status) 847 { 848 uint8_t ctrl1; 849 850 GLXIIC_ASSERT_LOCKED(sc); 851 852 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 853 GLXIIC_DEBUG_LOG("bus error in master stop"); 854 return (IIC_EBUSERR); 855 } 856 857 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 858 GLXIIC_DEBUG_LOG("not bus master in master stop"); 859 return (IIC_ESTATUS); 860 } 861 862 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 863 GLXIIC_DEBUG_LOG("slave nack in master stop"); 864 return (IIC_ENOACK); 865 } 866 867 if (--sc->nmsgs > 0) { 868 /* Start transfer of next message. */ 869 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) { 870 glxiic_stop_locked(sc); 871 } 872 873 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 874 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 875 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 876 877 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 878 sc->msg++; 879 } else { 880 /* Last message. */ 881 glxiic_stop_locked(sc); 882 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 883 sc->error = IIC_NOERR; 884 GLXIIC_WAKEUP(sc); 885 } 886 887 return (IIC_NOERR); 888 } 889 890 static void 891 glxiic_intr(void *arg) 892 { 893 struct glxiic_softc *sc; 894 int error; 895 uint8_t status, data; 896 897 sc = (struct glxiic_softc *)arg; 898 899 GLXIIC_LOCK(sc); 900 901 status = glxiic_read_status_locked(sc); 902 903 /* Check if this interrupt originated from the SMBus. */ 904 if ((status & 905 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) { 906 907 error = glxiic_state_table[sc->state].callback(sc, status); 908 909 if (error != IIC_NOERR) { 910 if (glxiic_state_table[sc->state].master) { 911 glxiic_stop_locked(sc); 912 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 913 sc->error = error; 914 GLXIIC_WAKEUP(sc); 915 } else { 916 data = error & 0xff; 917 iicbus_intr(sc->iicbus, INTR_ERROR, &data); 918 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 919 } 920 } 921 } 922 923 GLXIIC_UNLOCK(sc); 924 } 925 926 static int 927 glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 928 { 929 struct glxiic_softc *sc; 930 931 sc = device_get_softc(dev); 932 933 GLXIIC_LOCK(sc); 934 935 if (oldaddr != NULL) 936 *oldaddr = sc->addr; 937 sc->addr = addr; 938 939 /* A disable/enable cycle resets the controller. */ 940 glxiic_smb_disable(sc); 941 glxiic_smb_enable(sc, speed, addr); 942 943 if (glxiic_state_table[sc->state].master) { 944 sc->error = IIC_ESTATUS; 945 GLXIIC_WAKEUP(sc); 946 } 947 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 948 949 GLXIIC_UNLOCK(sc); 950 951 return (IIC_NOERR); 952 } 953 954 static int 955 glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 956 { 957 struct glxiic_softc *sc; 958 int error; 959 uint8_t ctrl1; 960 961 sc = device_get_softc(dev); 962 963 GLXIIC_LOCK(sc); 964 965 if (sc->state != GLXIIC_STATE_IDLE) { 966 error = IIC_EBUSBSY; 967 goto out; 968 } 969 970 sc->msg = msgs; 971 sc->nmsgs = nmsgs; 972 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 973 974 /* Set start bit and let glxiic_intr() handle the transfer. */ 975 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 976 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 977 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 978 979 GLXIIC_SLEEP(sc); 980 error = sc->error; 981 out: 982 GLXIIC_UNLOCK(sc); 983 984 return (error); 985 } 986 987 static void 988 glxiic_smb_map_interrupt(int irq) 989 { 990 uint32_t irq_map; 991 int old_irq; 992 993 /* Protect the read-modify-write operation. */ 994 critical_enter(); 995 996 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 997 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 998 999 if (irq != old_irq) { 1000 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq); 1001 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq); 1002 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map); 1003 } 1004 1005 critical_exit(); 1006 } 1007 1008 static void 1009 glxiic_gpio_enable(struct glxiic_softc *sc) 1010 { 1011 1012 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1013 GLXIIC_GPIO_14_15_ENABLE); 1014 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1015 GLXIIC_GPIO_14_15_ENABLE); 1016 } 1017 1018 static void 1019 glxiic_gpio_disable(struct glxiic_softc *sc) 1020 { 1021 1022 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1023 GLXIIC_GPIO_14_15_DISABLE); 1024 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1025 GLXIIC_GPIO_14_15_DISABLE); 1026 } 1027 1028 static void 1029 glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr) 1030 { 1031 uint8_t ctrl1; 1032 1033 ctrl1 = 0; 1034 1035 switch (speed) { 1036 case IIC_SLOW: 1037 sc->sclfrq = GLXIIC_SLOW; 1038 break; 1039 case IIC_FAST: 1040 sc->sclfrq = GLXIIC_FAST; 1041 break; 1042 case IIC_FASTEST: 1043 sc->sclfrq = GLXIIC_FASTEST; 1044 break; 1045 case IIC_UNKNOWN: 1046 default: 1047 /* Reuse last frequency. */ 1048 break; 1049 } 1050 1051 /* Set bus speed and enable controller. */ 1052 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1053 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT); 1054 1055 if (addr != 0) { 1056 /* Enable new match and global call match interrupts. */ 1057 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT | 1058 GLXIIC_SMB_CTRL1_GCMEN_BIT; 1059 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 1060 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr)); 1061 } else { 1062 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0); 1063 } 1064 1065 /* Enable stall after start and interrupt. */ 1066 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 1067 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT); 1068 } 1069 1070 static void 1071 glxiic_smb_disable(struct glxiic_softc *sc) 1072 { 1073 uint16_t sclfrq; 1074 1075 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2); 1076 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1077 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT); 1078 } 1079