1 /* 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _IF_GEMVAR_H 32 #define _IF_GEMVAR_H 33 34 35 #include <sys/queue.h> 36 #include <sys/callout.h> 37 38 /* 39 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 40 */ 41 42 /* 43 * Transmit descriptor list size. This is arbitrary, but allocate 44 * enough descriptors for 64 pending transmissions and 16 segments 45 * per packet. 46 */ 47 #define GEM_NTXSEGS 16 48 49 #define GEM_TXQUEUELEN 64 50 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 51 #define GEM_MAXTXFREE (GEM_NTXDESC - 1) 52 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 53 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 54 55 /* 56 * Receive descriptor list size. We have one Rx buffer per incoming 57 * packet, so this logic is a little simpler. 58 */ 59 #define GEM_NRXDESC 128 60 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 61 #define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK) 62 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 63 64 /* 65 * How many ticks to wait until to retry on a RX descriptor that is still owned 66 * by the hardware. 67 */ 68 #define GEM_RXOWN_TICKS (hz / 50) 69 70 /* 71 * Control structures are DMA'd to the GEM chip. We allocate them in 72 * a single clump that maps to a single DMA segment to make several things 73 * easier. 74 */ 75 struct gem_control_data { 76 /* 77 * The transmit descriptors. 78 */ 79 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 80 81 /* 82 * The receive descriptors. 83 */ 84 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 85 }; 86 87 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 88 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 89 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 90 91 /* 92 * Software state for transmit job mbufs (may be elements of mbuf chains). 93 */ 94 struct gem_txsoft { 95 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 96 bus_dmamap_t txs_dmamap; /* our DMA map */ 97 int txs_firstdesc; /* first descriptor in packet */ 98 int txs_lastdesc; /* last descriptor in packet */ 99 int txs_ndescs; /* number of descriptors */ 100 STAILQ_ENTRY(gem_txsoft) txs_q; 101 }; 102 103 STAILQ_HEAD(gem_txsq, gem_txsoft); 104 105 /* Argument structure for busdma callback */ 106 struct gem_txdma { 107 struct gem_softc *txd_sc; 108 struct gem_txsoft *txd_txs; 109 }; 110 111 /* 112 * Software state for receive jobs. 113 */ 114 struct gem_rxsoft { 115 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 116 bus_dmamap_t rxs_dmamap; /* our DMA map */ 117 bus_addr_t rxs_paddr; /* physical address of the segment */ 118 }; 119 120 /* 121 * Software state per device. 122 */ 123 struct gem_softc { 124 struct arpcom sc_arpcom; /* arp common data */ 125 device_t sc_miibus; 126 struct mii_data *sc_mii; /* MII media control */ 127 device_t sc_dev; /* generic device information */ 128 struct callout sc_tick_ch; /* tick callout */ 129 struct callout sc_rx_ch; /* delayed rx callout */ 130 131 /* The following bus handles are to be provided by the bus front-end */ 132 bus_space_tag_t sc_bustag; /* bus tag */ 133 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */ 134 bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */ 135 bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */ 136 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */ 137 bus_dmamap_t sc_dmamap; /* bus dma handle */ 138 bus_space_handle_t sc_h; /* bus space handle for all regs */ 139 140 int sc_phys[2]; /* MII instance -> PHY map */ 141 142 int sc_mif_config; /* Selected MII reg setting */ 143 144 int sc_pci; /* XXXXX -- PCI buses are LE. */ 145 u_int sc_variant; /* which GEM are we dealing with? */ 146 #define GEM_UNKNOWN 0 /* don't know */ 147 #define GEM_SUN_GEM 1 /* Sun GEM variant */ 148 #define GEM_APPLE_GMAC 2 /* Apple GMAC variant */ 149 150 u_int sc_flags; /* */ 151 #define GEM_GIGABIT 0x0001 /* has a gigabit PHY */ 152 153 /* 154 * Ring buffer DMA stuff. 155 */ 156 bus_dma_segment_t sc_cdseg; /* control data memory */ 157 int sc_cdnseg; /* number of segments */ 158 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 159 bus_addr_t sc_cddma; 160 161 /* 162 * Software state for transmit and receive descriptors. 163 */ 164 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 165 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 166 167 /* 168 * Control data structures. 169 */ 170 struct gem_control_data *sc_control_data; 171 #define sc_txdescs sc_control_data->gcd_txdescs 172 #define sc_rxdescs sc_control_data->gcd_rxdescs 173 174 int sc_txfree; /* number of free Tx descriptors */ 175 int sc_txnext; /* next ready Tx descriptor */ 176 int sc_txwin; /* Tx descriptors since last Tx int */ 177 178 struct gem_txsq sc_txfreeq; /* free Tx descsofts */ 179 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ 180 181 int sc_rxptr; /* next ready RX descriptor/descsoft */ 182 int sc_rxfifosize; /* Rx FIFO size (bytes) */ 183 184 /* ========== */ 185 int sc_inited; 186 int sc_debug; 187 int sc_ifflags; 188 }; 189 190 #define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v)) 191 #define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v)) 192 193 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 194 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 195 196 #define GEM_CDSYNC(sc, ops) \ 197 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops)); \ 198 199 #define GEM_INIT_RXDESC(sc, x) \ 200 do { \ 201 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 202 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 203 struct mbuf *__m = __rxs->rxs_mbuf; \ 204 \ 205 __m->m_data = __m->m_ext.ext_buf; \ 206 __rxd->gd_addr = \ 207 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \ 208 __rxd->gd_flags = \ 209 GEM_DMA_WRITE((sc), \ 210 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 211 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 212 } while (0) 213 214 #ifdef _KERNEL 215 extern devclass_t gem_devclass; 216 217 int gem_attach(struct gem_softc *); 218 void gem_detach(struct gem_softc *); 219 void gem_suspend(struct gem_softc *); 220 void gem_resume(struct gem_softc *); 221 void gem_intr(void *); 222 223 int gem_mediachange(struct ifnet *); 224 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 225 226 void gem_reset(struct gem_softc *); 227 228 /* MII methods & callbacks */ 229 int gem_mii_readreg(device_t, int, int); 230 int gem_mii_writereg(device_t, int, int, int); 231 void gem_mii_statchg(device_t); 232 233 #endif /* _KERNEL */ 234 235 236 #endif 237