1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 3 * 4 * Copyright (C) 2001 Eduardo Horvath. 5 * All rights reserved. 6 * 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _IF_GEMREG_H 35 #define _IF_GEMREG_H 36 37 /* register definitions for Apple GMAC, Sun ERI and Sun GEM */ 38 39 /* 40 * First bank: these registers live at the start of the PCI 41 * mapping, and at the start of the second bank of the SBus 42 * version. 43 */ 44 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 45 #define GEM_CONFIG 0x0004 /* config reg */ 46 #define GEM_STATUS 0x000c /* status reg */ 47 /* Note: Reading the status reg clears bits 0-6. */ 48 #define GEM_INTMASK 0x0010 49 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 50 #define GEM_STATUS_ALIAS 0x001c 51 52 /* Bits in GEM_SEB register */ 53 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */ 54 #define GEM_SEB_RXWON 0x00000004 55 56 /* Bits in GEM_CONFIG register */ 57 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */ 58 #define GEM_CONFIG_BURST_INF 0x00000001 /* infinite for entire packet */ 59 #define GEM_CONFIG_TXDMA_LIMIT 0x0000003e 60 #define GEM_CONFIG_RXDMA_LIMIT 0x000007c0 61 /* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 62 #define GEM_CONFIG_RONPAULBIT 0x00000800 /* after infinite burst use */ 63 /* memory read multiple for */ 64 /* PCI commands */ 65 #define GEM_CONFIG_BUG2FIX 0x00001000 /* fix RX hang after overflow */ 66 67 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 68 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 69 70 /* Top part of GEM_STATUS has TX completion information */ 71 #define GEM_STATUS_TX_COMPLETION_MASK 0xfff80000 /* TX completion reg. */ 72 #define GEM_STATUS_TX_COMPLETION_SHFT 19 73 74 /* 75 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs 76 * Bits 0-6 auto-clear when read. 77 */ 78 #define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */ 79 #define GEM_INTR_TX_EMPTY 0x00000002 /* TX ring empty */ 80 #define GEM_INTR_TX_DONE 0x00000004 /* TX complete */ 81 #define GEM_INTR_RX_DONE 0x00000010 /* Got a packet */ 82 #define GEM_INTR_RX_NOBUF 0x00000020 83 #define GEM_INTR_RX_TAG_ERR 0x00000040 84 #define GEM_INTR_PERR 0x00000080 /* Parity error */ 85 #define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */ 86 #define GEM_INTR_TX_MAC 0x00004000 87 #define GEM_INTR_RX_MAC 0x00008000 88 #define GEM_INTR_MAC_CONTROL 0x00010000 /* MAC control interrupt */ 89 #define GEM_INTR_MIF 0x00020000 90 #define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */ 91 #define GEM_INTR_BITS "\177\020" \ 92 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 93 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 94 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 95 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 96 97 /* 98 * Second bank: these registers live at offset 0x1000 of the PCI 99 * mapping, and at the start of the first bank of the SBus 100 * version. 101 */ 102 #define GEM_PCI_BANK2_OFFSET 0x1000 103 #define GEM_PCI_BANK2_SIZE 0x14 104 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 105 #define GEM_PCI_ERROR_STATUS 0x0000 /* PCI error status */ 106 #define GEM_PCI_ERROR_MASK 0x0004 /* PCI error mask */ 107 #define GEM_PCI_BIF_CONFIG 0x0008 /* PCI BIF configuration */ 108 #define GEM_PCI_BIF_DIAG 0x000c /* PCI BIF diagnostic */ 109 110 #define GEM_SBUS_BIF_RESET 0x0000 /* SBus BIF only software reset */ 111 #define GEM_SBUS_CONFIG 0x0004 /* SBus IO configuration */ 112 #define GEM_SBUS_STATUS 0x0008 /* SBus IO status */ 113 #define GEM_SBUS_REVISION 0x000c /* SBus revision ID */ 114 115 #define GEM_RESET 0x0010 /* software reset */ 116 117 /* GEM_PCI_ERROR_STATUS and GEM_PCI_ERROR_MASK error bits */ 118 #define GEM_PCI_ERR_STAT_BADACK 0x00000001 /* No ACK64# */ 119 #define GEM_PCI_ERR_STAT_DTRTO 0x00000002 /* Delayed xaction timeout */ 120 #define GEM_PCI_ERR_STAT_OTHERS 0x00000004 121 #define GEM_PCI_ERR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 122 123 /* GEM_PCI_BIF_CONFIG register bits */ 124 #define GEM_PCI_BIF_CNF_SLOWCLK 0x00000001 /* Parity error timing */ 125 #define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */ 126 #define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */ 127 #define GEM_PCI_BIF_CNF_M66EN 0x00000008 128 #define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 129 "b\2B64DIS\0b\3M66EN\0\0" 130 131 /* GEM_PCI_BIF_DIAG register bits */ 132 #define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */ 133 #define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */ 134 135 /* Bits in GEM_SBUS_CONFIG register */ 136 #define GEM_SBUS_CFG_BURST_32 0x00000001 /* 32 byte bursts */ 137 #define GEM_SBUS_CFG_BURST_64 0x00000002 /* 64 byte bursts */ 138 #define GEM_SBUS_CFG_BURST_128 0x00000004 /* 128 byte bursts */ 139 #define GEM_SBUS_CFG_64BIT 0x00000008 /* extended transfer mode */ 140 #define GEM_SBUS_CFG_PARITY 0x00000200 /* enable parity checking */ 141 142 /* GEM_SBUS_STATUS register bits */ 143 #define GEM_SBUS_STATUS_LERR 0x00000001 /* LERR from SBus slave */ 144 #define GEM_SBUS_STATUS_SACK 0x00000002 /* size ack. error */ 145 #define GEM_SBUS_STATUS_EACK 0x00000004 /* SBus ctrl. or slave error */ 146 #define GEM_SBUS_STATUS_MPARITY 0x00000008 /* SBus master parity error */ 147 148 /* GEM_RESET register bits -- TX and RX self clear when complete. */ 149 #define GEM_RESET_TX 0x00000001 /* Reset TX half. */ 150 #define GEM_RESET_RX 0x00000002 /* Reset RX half. */ 151 #define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ 152 #define GEM_RESET_CLSZ_MASK 0x00ff0000 /* ERI cache line size */ 153 #define GEM_RESET_CLSZ_SHFT 16 154 155 /* The rest of the registers live in the first bank again. */ 156 157 /* TX DMA registers */ 158 #define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 159 #define GEM_TX_CONFIG 0x2004 160 #define GEM_TX_RING_PTR_LO 0x2008 161 #define GEM_TX_RING_PTR_HI 0x200c 162 163 #define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 164 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 165 #define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 166 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 167 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 168 169 #define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 170 #define GEM_TX_DATA_PTR_LO 0x2030 171 #define GEM_TX_DATA_PTR_HI 0x2034 172 173 #define GEM_TX_COMPLETION 0x2100 174 #define GEM_TX_FIFO_ADDRESS 0x2104 175 #define GEM_TX_FIFO_TAG 0x2108 176 #define GEM_TX_FIFO_DATA_LO 0x210c 177 #define GEM_TX_FIFO_DATA_HI_T1 0x2110 178 #define GEM_TX_FIFO_DATA_HI_T0 0x2114 179 #define GEM_TX_FIFO_SIZE 0x2118 180 #define GEM_TX_DEBUG 0x3028 181 182 /* GEM_TX_CONFIG register bits */ 183 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 184 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 185 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 186 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 187 188 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 189 #define GEM_RING_SZ_64 (1<<1) 190 #define GEM_RING_SZ_128 (2<<1) 191 #define GEM_RING_SZ_256 (3<<1) 192 #define GEM_RING_SZ_512 (4<<1) 193 #define GEM_RING_SZ_1024 (5<<1) 194 #define GEM_RING_SZ_2048 (6<<1) 195 #define GEM_RING_SZ_4096 (7<<1) 196 #define GEM_RING_SZ_8192 (8<<1) 197 198 /* GEM_TX_COMPLETION register bits */ 199 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 200 201 /* RX DMA registers */ 202 #define GEM_RX_CONFIG 0x4000 203 #define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 204 #define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 205 206 #define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 207 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 208 #define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 209 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 210 211 #define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 212 #define GEM_RX_PAUSE_THRESH 0x4020 213 214 #define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 215 #define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 216 217 #define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 218 #define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 219 #define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 220 221 #define GEM_RX_FIFO_ADDRESS 0x410c 222 #define GEM_RX_FIFO_TAG 0x4110 223 #define GEM_RX_FIFO_DATA_LO 0x4114 224 #define GEM_RX_FIFO_DATA_HI_T1 0x4118 225 #define GEM_RX_FIFO_DATA_HI_T0 0x411c 226 #define GEM_RX_FIFO_SIZE 0x4120 227 228 /* GEM_RX_CONFIG register bits */ 229 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 230 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 231 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 232 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 233 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 234 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 235 236 #define GEM_THRSH_64 0 237 #define GEM_THRSH_128 1 238 #define GEM_THRSH_256 2 239 #define GEM_THRSH_512 3 240 #define GEM_THRSH_1024 4 241 #define GEM_THRSH_2048 5 242 243 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 244 #define GEM_RX_CONFIG_FBOFF_SHFT 10 245 #define GEM_RX_CONFIG_CXM_START_SHFT 13 246 247 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 248 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff 249 #define GEM_RX_PTH_XON_THRESH 0x001ff000 250 251 /* GEM_RX_BLANKING register bits */ 252 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 253 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 254 #define GEM_RX_BLANKING_TIME_SHIFT 12 255 /* One tick is 2048 PCI clocks, or 16us at 66MHz */ 256 257 /* GEM_MAC registers */ 258 #define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 259 #define GEM_MAC_RXRESET 0x6004 /* ditto */ 260 #define GEM_MAC_SEND_PAUSE_CMD 0x6008 261 #define GEM_MAC_TX_STATUS 0x6010 262 #define GEM_MAC_RX_STATUS 0x6014 263 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 264 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 265 #define GEM_MAC_RX_MASK 0x6024 266 #define GEM_MAC_CONTROL_MASK 0x6028 267 #define GEM_MAC_TX_CONFIG 0x6030 268 #define GEM_MAC_RX_CONFIG 0x6034 269 #define GEM_MAC_CONTROL_CONFIG 0x6038 270 #define GEM_MAC_XIF_CONFIG 0x603c 271 #define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 272 #define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 273 #define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 274 #define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ 275 #define GEM_MAC_MAC_MIN_FRAME 0x6050 276 #define GEM_MAC_MAC_MAX_FRAME 0x6054 277 #define GEM_MAC_PREAMBLE_LEN 0x6058 278 #define GEM_MAC_JAM_SIZE 0x605c 279 #define GEM_MAC_ATTEMPT_LIMIT 0x6060 280 #define GEM_MAC_CONTROL_TYPE 0x6064 281 282 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 283 #define GEM_MAC_ADDR1 0x6084 284 #define GEM_MAC_ADDR2 0x6088 285 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 286 #define GEM_MAC_ADDR4 0x6090 287 #define GEM_MAC_ADDR5 0x6094 288 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 289 #define GEM_MAC_ADDR7 0x609c 290 #define GEM_MAC_ADDR8 0x60a0 291 292 #define GEM_MAC_ADDR_FILTER0 0x60a4 293 #define GEM_MAC_ADDR_FILTER1 0x60a8 294 #define GEM_MAC_ADDR_FILTER2 0x60ac 295 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 296 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 297 298 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 299 #define GEM_MAC_HASH1 0x60c4 300 #define GEM_MAC_HASH2 0x60c8 301 #define GEM_MAC_HASH3 0x60cc 302 #define GEM_MAC_HASH4 0x60d0 303 #define GEM_MAC_HASH5 0x60d4 304 #define GEM_MAC_HASH6 0x60d8 305 #define GEM_MAC_HASH7 0x60dc 306 #define GEM_MAC_HASH8 0x60e0 307 #define GEM_MAC_HASH9 0x60e4 308 #define GEM_MAC_HASH10 0x60e8 309 #define GEM_MAC_HASH11 0x60ec 310 #define GEM_MAC_HASH12 0x60f0 311 #define GEM_MAC_HASH13 0x60f4 312 #define GEM_MAC_HASH14 0x60f8 313 #define GEM_MAC_HASH15 0x60fc 314 315 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 316 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 317 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 318 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 319 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 320 #define GEM_MAC_PEAK_ATTEMPTS 0x6114 321 #define GEM_MAC_RX_FRAME_COUNT 0x6118 322 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c 323 #define GEM_MAC_RX_ALIGN_ERR 0x6120 324 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124 325 #define GEM_MAC_RX_CODE_VIOL 0x6128 326 #define GEM_MAC_RANDOM_SEED 0x6130 327 #define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */ 328 329 /* GEM_MAC_SEND_PAUSE_CMD register bits */ 330 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 331 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000 332 333 /* GEM_MAC_TX_STATUS and _MASK register bits */ 334 #define GEM_MAC_TX_XMIT_DONE 0x00000001 335 #define GEM_MAC_TX_UNDERRUN 0x00000002 336 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 337 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 338 #define GEM_MAC_TX_ECC_EXP 0x00000010 339 #define GEM_MAC_TX_LCC_EXP 0x00000020 340 #define GEM_MAC_TX_FCC_EXP 0x00000040 341 #define GEM_MAC_TX_DEFER_EXP 0x00000080 342 #define GEM_MAC_TX_PEAK_EXP 0x00000100 343 344 /* GEM_MAC_RX_STATUS and _MASK register bits */ 345 #define GEM_MAC_RX_DONE 0x00000001 346 #define GEM_MAC_RX_OVERFLOW 0x00000002 347 #define GEM_MAC_RX_FRAME_CNT 0x00000004 348 #define GEM_MAC_RX_ALIGN_EXP 0x00000008 349 #define GEM_MAC_RX_CRC_EXP 0x00000010 350 #define GEM_MAC_RX_LEN_EXP 0x00000020 351 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 352 353 /* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 354 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 355 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 356 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 357 #define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */ 358 #define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 359 360 #define GEM_MAC_PAUSE_TIME_SHFT 16 361 #define GEM_MAC_PAUSE_TIME(x) \ 362 (((x) & GEM_MAC_PAUSE_TIME_SLTS) >> GEM_MAC_PAUSE_TIME_SHFT) 363 364 /* GEM_MAC_XIF_CONFIG register bits */ 365 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 366 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 367 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 368 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 369 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 370 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 371 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 372 #define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 373 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 374 "b\6FDLED\0\0" 375 376 /* 377 * GEM_MAC_SLOT_TIME register 378 * The slot time is used as PAUSE time unit, value depends on whether carrier 379 * extension is enabled. 380 */ 381 #define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 382 #define GEM_MAC_SLOT_TIME_NORMAL 0x40 383 384 /* GEM_MAC_TX_CONFIG register bits */ 385 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 386 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 387 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 388 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */ 389 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 390 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 391 #define GEM_MAC_TX_NO_BACKOFF 0x00000040 392 #define GEM_MAC_TX_SLOWDOWN 0x00000080 393 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 394 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 395 /* Carrier Extension is required for half duplex Gbps operation. */ 396 #define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 397 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 398 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 399 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 400 "b\x9TXCARREXT\0\0" 401 402 /* GEM_MAC_RX_CONFIG register bits */ 403 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 404 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 405 #define GEM_MAC_RX_STRIP_CRC 0x00000004 406 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 407 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 408 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 409 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 410 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 411 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 412 /* 413 * Carrier Extension enables reception of packet bursts generated by 414 * senders with carrier extension enabled. 415 */ 416 #define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 417 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 418 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 419 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 420 421 /* GEM_MAC_CONTROL_CONFIG bits */ 422 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 423 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 424 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 425 #define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 426 427 /* 428 * MIF registers 429 * Bit bang registers use low bit only. 430 */ 431 #define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 432 #define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 433 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208 434 #define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 435 #define GEM_MIF_CONFIG 0x6210 436 #define GEM_MIF_MASK 0x6214 437 #define GEM_MIF_STATUS 0x6218 438 #define GEM_MIF_STATE_MACHINE 0x621c 439 440 /* GEM_MIF_FRAME bits */ 441 #define GEM_MIF_FRAME_DATA 0x0000ffff 442 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA LSB, 1 for completion */ 443 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA MSB, 1 for instruction */ 444 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000 445 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address */ 446 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 447 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 448 449 #define GEM_MIF_FRAME_READ 0x60020000 450 #define GEM_MIF_FRAME_WRITE 0x50020000 451 452 #define GEM_MIF_REG_SHIFT 18 453 #define GEM_MIF_PHY_SHIFT 23 454 455 /* GEM_MIF_CONFIG register bits */ 456 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0: MDIO_0 */ 457 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 458 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 459 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 460 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 attached/data */ 461 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 attached/data */ 462 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 463 /* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */ 464 #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 465 "b\x8MDIO0\0b\x9MDIO1\0\0" 466 467 /* GEM_MIF_STATUS and GEM_MIF_MASK bits */ 468 #define GEM_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */ 469 #define GEM_MIF_POLL_STATUS_SHFT 0 470 #define GEM_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */ 471 #define GEM_MIF_POLL_DATA_SHFT 8 472 /* 473 * The Basic part is the last value read in the POLL field of the config 474 * register. 475 * The status part indicates the bits that have changed. 476 */ 477 478 /* GEM PCS/Serial link registers */ 479 /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 480 #define GEM_MII_CONTROL 0x9000 481 #define GEM_MII_STATUS 0x9004 482 #define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 483 #define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 484 #define GEM_MII_CONFIG 0x9010 485 #define GEM_MII_STATE_MACHINE 0x9014 486 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ 487 #define GEM_MII_DATAPATH_MODE 0x9050 488 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 489 #define GEM_MII_OUTPUT_SELECT 0x9058 490 #define GEM_MII_SLINK_STATUS 0x905c /* Serialink status */ 491 492 /* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */ 493 #define GEM_MII_CONTROL_1000M 0x00000040 /* 1000Mbps speed select */ 494 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 495 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full-duplex, always 0 */ 496 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto-negotiation */ 497 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY from MII */ 498 #define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down */ 499 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto-negotiation enable */ 500 #define GEM_MII_CONTROL_10_100M 0x00002000 /* 10/100Mbps speed select */ 501 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 502 #define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS. */ 503 #define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 504 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 505 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 506 507 /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ 508 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability */ 509 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 510 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 511 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto-negotiate */ 512 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 513 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */ 514 #define GEM_MII_STATUS_EXTENDED 0x00000100 /* extended status */ 515 #define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 516 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0\0" 517 518 /* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ 519 #define GEM_MII_ANEG_FDUPLX 0x00000020 /* full-duplex */ 520 #define GEM_MII_ANEG_HDUPLX 0x00000040 /* half-duplex */ 521 #define GEM_MII_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */ 522 #define GEM_MII_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */ 523 #define GEM_MII_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */ 524 #define GEM_MII_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */ 525 #define GEM_MII_ANEG_RFLT_MASK \ 526 (CAS_PCS_ANEG_RFLT_FAIL | CAS_PCS_ANEG_RFLT_OFF) 527 #define GEM_MII_ANEG_ACK 0x00004000 /* acknowledge */ 528 #define GEM_MII_ANEG_NP 0x00008000 /* next page */ 529 #define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 530 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 531 "\b\xfNPBIT\0\0" 532 533 /* GEM_MII_CONFIG reg */ 534 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS. */ 535 #define GEM_MII_CONFIG_SDO 0x00000002 /* signal detect override */ 536 #define GEM_MII_CONFIG_SDL 0x00000004 /* signal detect active-low */ 537 #define GEM_MII_CONFIG_JS_NORM 0x00000000 /* jitter study - normal op. */ 538 #define GEM_MII_CONFIG_JS_HF 0x00000008 /* jitter study - HF test */ 539 #define GEM_MII_CONFIG_JS_LF 0x00000010 /* jitter study - LF test */ 540 #define GEM_MII_CONFIG_JS_MASK \ 541 (GEM_MII_CONFIG_JS_HF | GEM_MII_CONFIG_JS_LF) 542 #define GEM_MII_CONFIG_ANTO 0x00000020 /* auto-neg. timer override */ 543 #define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 544 545 /* 546 * GEM_MII_INTERRUP_STATUS reg 547 * No mask register; mask with the global interrupt mask register. 548 */ 549 #define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */ 550 551 /* GEM_MII_DATAPATH_MODE reg */ 552 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serialink */ 553 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */ 554 #define GEM_MII_DATAPATH_MII 0x00000004 /* GMII/MII */ 555 #define GEM_MII_DATAPATH_GMIIOE 0x00000008 /* serial output on GMII en. */ 556 #define GEM_MII_DATAPATH_BITS "\177\020" \ 557 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3GMIIOE\0\0" 558 559 /* GEM_MII_SLINK_CONTROL reg */ 560 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at SL, logic 561 * reversed for SERDES */ 562 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 563 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock to reference clock */ 564 #define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */ 565 #define GEM_MII_SLINK_SELFTEST 0x000001c0 /* self-test */ 566 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink. */ 567 #define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink. */ 568 #define GEM_MII_SLINK_RX_POLE 0x00003000 /* PLL input to Serialink. */ 569 #define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink. */ 570 #define GEM_MII_SLINK_TX_POLE 0x00030000 /* PLL input to Serialink. */ 571 #define GEM_MII_SLINK_CONTROL_BITS \ 572 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 573 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0" 574 575 /* GEM_MII_SLINK_STATUS reg */ 576 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 577 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us w/ lockrefn */ 578 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 579 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 580 581 /* 582 * PCI Expansion ROM runtime access 583 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half 584 * of the first register bank, although they only support up to 64KB ROMs. 585 */ 586 #define GEM_PCI_ROM_OFFSET 0x100000 587 #define GEM_PCI_ROM_SIZE 0x10000 588 589 /* Wired PHY addresses */ 590 #define GEM_PHYAD_INTERNAL 1 591 #define GEM_PHYAD_EXTERNAL 0 592 593 /* Miscellaneous */ 594 #define GEM_ERI_CACHE_LINE_SIZE 16 595 #define GEM_ERI_LATENCY_TIMER 64 596 597 /* 598 * descriptor table structures 599 */ 600 struct gem_desc { 601 uint64_t gd_flags; 602 uint64_t gd_addr; 603 }; 604 605 /* 606 * Transmit flags 607 * GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_START, GEM_TD_CXSUM_STUFF and 608 * GEM_TD_INTERRUPT_ME only need to be set in the first descriptor of a group. 609 */ 610 #define GEM_TD_BUFSIZE 0x0000000000007fffULL 611 #define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */ 612 #define GEM_TD_CXSUM_STARTSHFT 15 613 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */ 614 #define GEM_TD_CXSUM_STUFFSHFT 21 615 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */ 616 #define GEM_TD_END_OF_PACKET 0x0000000040000000ULL 617 #define GEM_TD_START_OF_PACKET 0x0000000080000000ULL 618 #define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */ 619 #define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */ 620 621 /* Receive flags */ 622 #define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */ 623 #define GEM_RD_BUFSIZE 0x000000007fff0000ULL 624 #define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */ 625 #define GEM_RD_HASHVAL 0x0ffff00000000000ULL 626 #define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 627 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */ 628 #define GEM_RD_BAD_CRC 0x4000000000000000ULL 629 #define GEM_RD_BUFSHIFT 16 630 #define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT) 631 632 #endif 633