1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 36 */ 37 38 #if 0 39 #define GEM_DEBUG 40 #endif 41 42 #if 0 /* XXX: In case of emergency, re-enable this. */ 43 #define GEM_RINT_TIMEOUT 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/callout.h> 50 #include <sys/endian.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/lock.h> 55 #include <sys/module.h> 56 #include <sys/mutex.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/rman.h> 60 61 #include <net/bpf.h> 62 #include <net/ethernet.h> 63 #include <net/if.h> 64 #include <net/if_arp.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/ip.h> 73 #include <netinet/tcp.h> 74 #include <netinet/udp.h> 75 76 #include <machine/bus.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <dev/gem/if_gemreg.h> 82 #include <dev/gem/if_gemvar.h> 83 84 CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85 CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86 87 #define GEM_TRIES 10000 88 89 /* 90 * The hardware supports basic TCP/UDP checksum offloading. However, 91 * the hardware doesn't compensate the checksum for UDP datagram which 92 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93 * by default. It can be reactivated by setting special link option 94 * link0 with ifconfig(8). 95 */ 96 #define GEM_CSUM_FEATURES (CSUM_TCP) 97 98 static int gem_add_rxbuf(struct gem_softc *sc, int idx); 99 static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 100 uint32_t clr, uint32_t set); 101 static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 102 int nsegs, int error); 103 static int gem_disable_rx(struct gem_softc *sc); 104 static int gem_disable_tx(struct gem_softc *sc); 105 static void gem_eint(struct gem_softc *sc, u_int status); 106 static void gem_init(void *xsc); 107 static void gem_init_locked(struct gem_softc *sc); 108 static void gem_init_regs(struct gem_softc *sc); 109 static int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 110 static int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 111 static int gem_meminit(struct gem_softc *sc); 112 static void gem_mifinit(struct gem_softc *sc); 113 static void gem_reset(struct gem_softc *sc); 114 static int gem_reset_rx(struct gem_softc *sc); 115 static void gem_reset_rxdma(struct gem_softc *sc); 116 static int gem_reset_tx(struct gem_softc *sc); 117 static u_int gem_ringsize(u_int sz); 118 static void gem_rint(struct gem_softc *sc); 119 #ifdef GEM_RINT_TIMEOUT 120 static void gem_rint_timeout(void *arg); 121 #endif 122 static inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 123 static void gem_rxdrain(struct gem_softc *sc); 124 static void gem_setladrf(struct gem_softc *sc); 125 static void gem_start(struct ifnet *ifp); 126 static void gem_start_locked(struct ifnet *ifp); 127 static void gem_stop(struct ifnet *ifp, int disable); 128 static void gem_tick(void *arg); 129 static void gem_tint(struct gem_softc *sc); 130 static inline void gem_txkick(struct gem_softc *sc); 131 static int gem_watchdog(struct gem_softc *sc); 132 133 devclass_t gem_devclass; 134 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 135 MODULE_DEPEND(gem, miibus, 1, 1, 1); 136 137 #ifdef GEM_DEBUG 138 #include <sys/ktr.h> 139 #define KTR_GEM KTR_SPARE2 140 #endif 141 142 #define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 143 gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 144 #define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 145 gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 146 147 int 148 gem_attach(struct gem_softc *sc) 149 { 150 struct gem_txsoft *txs; 151 struct ifnet *ifp; 152 int error, i, phy; 153 uint32_t v; 154 155 if (bootverbose) 156 device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 157 158 /* Set up ifnet structure. */ 159 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160 if (ifp == NULL) 161 return (ENOSPC); 162 sc->sc_csum_features = GEM_CSUM_FEATURES; 163 ifp->if_softc = sc; 164 if_initname(ifp, device_get_name(sc->sc_dev), 165 device_get_unit(sc->sc_dev)); 166 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 167 ifp->if_start = gem_start; 168 ifp->if_ioctl = gem_ioctl; 169 ifp->if_init = gem_init; 170 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 171 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 172 IFQ_SET_READY(&ifp->if_snd); 173 174 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 175 #ifdef GEM_RINT_TIMEOUT 176 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 177 #endif 178 179 /* Make sure the chip is stopped. */ 180 gem_reset(sc); 181 182 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 184 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 185 NULL, &sc->sc_pdmatag); 186 if (error != 0) 187 goto fail_ifnet; 188 189 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 190 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 191 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 192 if (error != 0) 193 goto fail_ptag; 194 195 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 196 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 197 MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 199 if (error != 0) 200 goto fail_rtag; 201 202 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 203 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 204 sizeof(struct gem_control_data), 1, 205 sizeof(struct gem_control_data), 0, 206 NULL, NULL, &sc->sc_cdmatag); 207 if (error != 0) 208 goto fail_ttag; 209 210 /* 211 * Allocate the control data structures, create and load the 212 * DMA map for it. 213 */ 214 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 215 (void **)&sc->sc_control_data, 216 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 217 &sc->sc_cddmamap)) != 0) { 218 device_printf(sc->sc_dev, 219 "unable to allocate control data, error = %d\n", error); 220 goto fail_ctag; 221 } 222 223 sc->sc_cddma = 0; 224 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 225 sc->sc_control_data, sizeof(struct gem_control_data), 226 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 227 device_printf(sc->sc_dev, 228 "unable to load control data DMA map, error = %d\n", 229 error); 230 goto fail_cmem; 231 } 232 233 /* 234 * Initialize the transmit job descriptors. 235 */ 236 STAILQ_INIT(&sc->sc_txfreeq); 237 STAILQ_INIT(&sc->sc_txdirtyq); 238 239 /* 240 * Create the transmit buffer DMA maps. 241 */ 242 error = ENOMEM; 243 for (i = 0; i < GEM_TXQUEUELEN; i++) { 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 txs->txs_ndescs = 0; 247 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 248 &txs->txs_dmamap)) != 0) { 249 device_printf(sc->sc_dev, 250 "unable to create TX DMA map %d, error = %d\n", 251 i, error); 252 goto fail_txd; 253 } 254 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 262 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 device_printf(sc->sc_dev, 264 "unable to create RX DMA map %d, error = %d\n", 265 i, error); 266 goto fail_rxd; 267 } 268 sc->sc_rxsoft[i].rxs_mbuf = NULL; 269 } 270 271 /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 272 if ((sc->sc_flags & GEM_SERDES) != 0) 273 goto serdes; 274 275 /* Bad things will happen when touching this register on ERI. */ 276 if (sc->sc_variant != GEM_SUN_ERI) { 277 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 278 GEM_MII_DATAPATH_MII); 279 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 280 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 281 } 282 283 gem_mifinit(sc); 284 285 /* 286 * Look for an external PHY. 287 */ 288 error = ENXIO; 289 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 290 if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 291 v |= GEM_MIF_CONFIG_PHY_SEL; 292 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 293 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 294 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 295 switch (sc->sc_variant) { 296 case GEM_SUN_ERI: 297 phy = GEM_PHYAD_EXTERNAL; 298 break; 299 default: 300 phy = MII_PHY_ANY; 301 break; 302 } 303 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 304 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 305 MII_OFFSET_ANY, 0); 306 } 307 308 /* 309 * Fall back on an internal PHY if no external PHY was found. 310 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 311 * trusted when the firmware has powered down the chip. 312 */ 313 if (error != 0 && 314 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 315 v &= ~GEM_MIF_CONFIG_PHY_SEL; 316 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 317 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 318 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 319 switch (sc->sc_variant) { 320 case GEM_SUN_ERI: 321 case GEM_APPLE_K2_GMAC: 322 phy = GEM_PHYAD_INTERNAL; 323 break; 324 case GEM_APPLE_GMAC: 325 phy = GEM_PHYAD_EXTERNAL; 326 break; 327 default: 328 phy = MII_PHY_ANY; 329 break; 330 } 331 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 332 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 333 MII_OFFSET_ANY, 0); 334 } 335 336 /* 337 * Try the external PCS SERDES if we didn't find any PHYs. 338 */ 339 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 340 serdes: 341 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 342 GEM_MII_DATAPATH_SERDES); 343 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 344 BUS_SPACE_BARRIER_WRITE); 345 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 346 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 347 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 348 BUS_SPACE_BARRIER_WRITE); 349 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 350 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 351 BUS_SPACE_BARRIER_WRITE); 352 sc->sc_flags |= GEM_SERDES; 353 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 354 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, 355 GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, 0); 356 } 357 if (error != 0) { 358 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 359 goto fail_rxd; 360 } 361 sc->sc_mii = device_get_softc(sc->sc_miibus); 362 363 /* 364 * From this point forward, the attachment cannot fail. A failure 365 * before this point releases all resources that may have been 366 * allocated. 367 */ 368 369 /* Get RX FIFO size. */ 370 sc->sc_rxfifosize = 64 * 371 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 372 373 /* Get TX FIFO size. */ 374 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 375 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 376 sc->sc_rxfifosize / 1024, v / 16); 377 378 /* Attach the interface. */ 379 ether_ifattach(ifp, sc->sc_enaddr); 380 381 /* 382 * Tell the upper layer(s) we support long frames/checksum offloads. 383 */ 384 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 385 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 386 ifp->if_hwassist |= sc->sc_csum_features; 387 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 388 389 return (0); 390 391 /* 392 * Free any resources we've allocated during the failed attach 393 * attempt. Do this in reverse order and fall through. 394 */ 395 fail_rxd: 396 for (i = 0; i < GEM_NRXDESC; i++) 397 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 398 bus_dmamap_destroy(sc->sc_rdmatag, 399 sc->sc_rxsoft[i].rxs_dmamap); 400 fail_txd: 401 for (i = 0; i < GEM_TXQUEUELEN; i++) 402 if (sc->sc_txsoft[i].txs_dmamap != NULL) 403 bus_dmamap_destroy(sc->sc_tdmatag, 404 sc->sc_txsoft[i].txs_dmamap); 405 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 406 fail_cmem: 407 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 408 sc->sc_cddmamap); 409 fail_ctag: 410 bus_dma_tag_destroy(sc->sc_cdmatag); 411 fail_ttag: 412 bus_dma_tag_destroy(sc->sc_tdmatag); 413 fail_rtag: 414 bus_dma_tag_destroy(sc->sc_rdmatag); 415 fail_ptag: 416 bus_dma_tag_destroy(sc->sc_pdmatag); 417 fail_ifnet: 418 if_free(ifp); 419 return (error); 420 } 421 422 void 423 gem_detach(struct gem_softc *sc) 424 { 425 struct ifnet *ifp = sc->sc_ifp; 426 int i; 427 428 ether_ifdetach(ifp); 429 GEM_LOCK(sc); 430 gem_stop(ifp, 1); 431 GEM_UNLOCK(sc); 432 callout_drain(&sc->sc_tick_ch); 433 #ifdef GEM_RINT_TIMEOUT 434 callout_drain(&sc->sc_rx_ch); 435 #endif 436 if_free(ifp); 437 device_delete_child(sc->sc_dev, sc->sc_miibus); 438 439 for (i = 0; i < GEM_NRXDESC; i++) 440 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 441 bus_dmamap_destroy(sc->sc_rdmatag, 442 sc->sc_rxsoft[i].rxs_dmamap); 443 for (i = 0; i < GEM_TXQUEUELEN; i++) 444 if (sc->sc_txsoft[i].txs_dmamap != NULL) 445 bus_dmamap_destroy(sc->sc_tdmatag, 446 sc->sc_txsoft[i].txs_dmamap); 447 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 448 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 449 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 450 sc->sc_cddmamap); 451 bus_dma_tag_destroy(sc->sc_cdmatag); 452 bus_dma_tag_destroy(sc->sc_tdmatag); 453 bus_dma_tag_destroy(sc->sc_rdmatag); 454 bus_dma_tag_destroy(sc->sc_pdmatag); 455 } 456 457 void 458 gem_suspend(struct gem_softc *sc) 459 { 460 struct ifnet *ifp = sc->sc_ifp; 461 462 GEM_LOCK(sc); 463 gem_stop(ifp, 0); 464 GEM_UNLOCK(sc); 465 } 466 467 void 468 gem_resume(struct gem_softc *sc) 469 { 470 struct ifnet *ifp = sc->sc_ifp; 471 472 GEM_LOCK(sc); 473 /* 474 * On resume all registers have to be initialized again like 475 * after power-on. 476 */ 477 sc->sc_flags &= ~GEM_INITED; 478 if (ifp->if_flags & IFF_UP) 479 gem_init_locked(sc); 480 GEM_UNLOCK(sc); 481 } 482 483 static inline void 484 gem_rxcksum(struct mbuf *m, uint64_t flags) 485 { 486 struct ether_header *eh; 487 struct ip *ip; 488 struct udphdr *uh; 489 uint16_t *opts; 490 int32_t hlen, len, pktlen; 491 uint32_t temp32; 492 uint16_t cksum; 493 494 pktlen = m->m_pkthdr.len; 495 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 496 return; 497 eh = mtod(m, struct ether_header *); 498 if (eh->ether_type != htons(ETHERTYPE_IP)) 499 return; 500 ip = (struct ip *)(eh + 1); 501 if (ip->ip_v != IPVERSION) 502 return; 503 504 hlen = ip->ip_hl << 2; 505 pktlen -= sizeof(struct ether_header); 506 if (hlen < sizeof(struct ip)) 507 return; 508 if (ntohs(ip->ip_len) < hlen) 509 return; 510 if (ntohs(ip->ip_len) != pktlen) 511 return; 512 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 513 return; /* Cannot handle fragmented packet. */ 514 515 switch (ip->ip_p) { 516 case IPPROTO_TCP: 517 if (pktlen < (hlen + sizeof(struct tcphdr))) 518 return; 519 break; 520 case IPPROTO_UDP: 521 if (pktlen < (hlen + sizeof(struct udphdr))) 522 return; 523 uh = (struct udphdr *)((uint8_t *)ip + hlen); 524 if (uh->uh_sum == 0) 525 return; /* no checksum */ 526 break; 527 default: 528 return; 529 } 530 531 cksum = ~(flags & GEM_RD_CHECKSUM); 532 /* checksum fixup for IP options */ 533 len = hlen - sizeof(struct ip); 534 if (len > 0) { 535 opts = (uint16_t *)(ip + 1); 536 for (; len > 0; len -= sizeof(uint16_t), opts++) { 537 temp32 = cksum - *opts; 538 temp32 = (temp32 >> 16) + (temp32 & 65535); 539 cksum = temp32 & 65535; 540 } 541 } 542 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 543 m->m_pkthdr.csum_data = cksum; 544 } 545 546 static void 547 gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 548 { 549 struct gem_softc *sc = xsc; 550 551 if (error != 0) 552 return; 553 if (nsegs != 1) 554 panic("%s: bad control buffer segment count", __func__); 555 sc->sc_cddma = segs[0].ds_addr; 556 } 557 558 static void 559 gem_tick(void *arg) 560 { 561 struct gem_softc *sc = arg; 562 struct ifnet *ifp = sc->sc_ifp; 563 uint32_t v; 564 565 GEM_LOCK_ASSERT(sc, MA_OWNED); 566 567 /* 568 * Unload collision and error counters. 569 */ 570 ifp->if_collisions += 571 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 572 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 573 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 574 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 575 ifp->if_collisions += v; 576 ifp->if_oerrors += v; 577 ifp->if_ierrors += 578 GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 579 GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 580 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 581 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 582 583 /* 584 * Then clear the hardware counters. 585 */ 586 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 587 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 588 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 589 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 590 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 591 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 592 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 593 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 594 595 mii_tick(sc->sc_mii); 596 597 if (gem_watchdog(sc) == EJUSTRETURN) 598 return; 599 600 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 601 } 602 603 static int 604 gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 605 uint32_t set) 606 { 607 int i; 608 uint32_t reg; 609 610 for (i = GEM_TRIES; i--; DELAY(100)) { 611 reg = GEM_BANKN_READ_M(bank, 4, sc, r); 612 if ((reg & clr) == 0 && (reg & set) == set) 613 return (1); 614 } 615 return (0); 616 } 617 618 static void 619 gem_reset(struct gem_softc *sc) 620 { 621 622 #ifdef GEM_DEBUG 623 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 624 #endif 625 gem_reset_rx(sc); 626 gem_reset_tx(sc); 627 628 /* Do a full reset. */ 629 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 630 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 631 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 632 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 633 device_printf(sc->sc_dev, "cannot reset device\n"); 634 } 635 636 static void 637 gem_rxdrain(struct gem_softc *sc) 638 { 639 struct gem_rxsoft *rxs; 640 int i; 641 642 for (i = 0; i < GEM_NRXDESC; i++) { 643 rxs = &sc->sc_rxsoft[i]; 644 if (rxs->rxs_mbuf != NULL) { 645 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 646 BUS_DMASYNC_POSTREAD); 647 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 648 m_freem(rxs->rxs_mbuf); 649 rxs->rxs_mbuf = NULL; 650 } 651 } 652 } 653 654 static void 655 gem_stop(struct ifnet *ifp, int disable) 656 { 657 struct gem_softc *sc = ifp->if_softc; 658 struct gem_txsoft *txs; 659 660 #ifdef GEM_DEBUG 661 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 662 #endif 663 664 callout_stop(&sc->sc_tick_ch); 665 #ifdef GEM_RINT_TIMEOUT 666 callout_stop(&sc->sc_rx_ch); 667 #endif 668 669 gem_reset_tx(sc); 670 gem_reset_rx(sc); 671 672 /* 673 * Release any queued transmit buffers. 674 */ 675 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 676 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 677 if (txs->txs_ndescs != 0) { 678 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 679 BUS_DMASYNC_POSTWRITE); 680 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 681 if (txs->txs_mbuf != NULL) { 682 m_freem(txs->txs_mbuf); 683 txs->txs_mbuf = NULL; 684 } 685 } 686 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 687 } 688 689 if (disable) 690 gem_rxdrain(sc); 691 692 /* 693 * Mark the interface down and cancel the watchdog timer. 694 */ 695 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 696 sc->sc_flags &= ~GEM_LINK; 697 sc->sc_wdog_timer = 0; 698 } 699 700 static int 701 gem_reset_rx(struct gem_softc *sc) 702 { 703 704 /* 705 * Resetting while DMA is in progress can cause a bus hang, so we 706 * disable DMA first. 707 */ 708 gem_disable_rx(sc); 709 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 710 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 711 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 712 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 713 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 714 715 /* Finally, reset the ERX. */ 716 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX); 717 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 718 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 719 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 720 0)) { 721 device_printf(sc->sc_dev, "cannot reset receiver\n"); 722 return (1); 723 } 724 return (0); 725 } 726 727 /* 728 * Reset the receiver DMA engine. 729 * 730 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 731 * etc in order to reset the receiver DMA engine only and not do a full 732 * reset which amongst others also downs the link and clears the FIFOs. 733 */ 734 static void 735 gem_reset_rxdma(struct gem_softc *sc) 736 { 737 int i; 738 739 if (gem_reset_rx(sc) != 0) 740 return (gem_init_locked(sc)); 741 for (i = 0; i < GEM_NRXDESC; i++) 742 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 743 GEM_UPDATE_RXDESC(sc, i); 744 sc->sc_rxptr = 0; 745 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 747 /* NOTE: we use only 32-bit DMA addresses here. */ 748 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 749 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 750 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 751 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 752 gem_ringsize(GEM_NRXDESC /* XXX */) | 753 ((ETHER_HDR_LEN + sizeof(struct ip)) << 754 GEM_RX_CONFIG_CXM_START_SHFT) | 755 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 756 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 757 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 758 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 759 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 760 GEM_RX_BLANKING_TIME_SHIFT) | 6); 761 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 762 (3 * sc->sc_rxfifosize / 256) | 763 ((sc->sc_rxfifosize / 256) << 12)); 764 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 765 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 766 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 767 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 768 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 769 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE); 770 } 771 772 static int 773 gem_reset_tx(struct gem_softc *sc) 774 { 775 776 /* 777 * Resetting while DMA is in progress can cause a bus hang, so we 778 * disable DMA first. 779 */ 780 gem_disable_tx(sc); 781 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 782 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 783 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 784 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 785 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 786 787 /* Finally, reset the ETX. */ 788 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX); 789 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 790 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 791 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 792 0)) { 793 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 794 return (1); 795 } 796 return (0); 797 } 798 799 static int 800 gem_disable_rx(struct gem_softc *sc) 801 { 802 803 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 804 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 805 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 806 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 807 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 808 0)); 809 } 810 811 static int 812 gem_disable_tx(struct gem_softc *sc) 813 { 814 815 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 816 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 817 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 818 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 819 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 820 0)); 821 } 822 823 static int 824 gem_meminit(struct gem_softc *sc) 825 { 826 struct gem_rxsoft *rxs; 827 int error, i; 828 829 GEM_LOCK_ASSERT(sc, MA_OWNED); 830 831 /* 832 * Initialize the transmit descriptor ring. 833 */ 834 for (i = 0; i < GEM_NTXDESC; i++) { 835 sc->sc_txdescs[i].gd_flags = 0; 836 sc->sc_txdescs[i].gd_addr = 0; 837 } 838 sc->sc_txfree = GEM_MAXTXFREE; 839 sc->sc_txnext = 0; 840 sc->sc_txwin = 0; 841 842 /* 843 * Initialize the receive descriptor and receive job 844 * descriptor rings. 845 */ 846 for (i = 0; i < GEM_NRXDESC; i++) { 847 rxs = &sc->sc_rxsoft[i]; 848 if (rxs->rxs_mbuf == NULL) { 849 if ((error = gem_add_rxbuf(sc, i)) != 0) { 850 device_printf(sc->sc_dev, 851 "unable to allocate or map RX buffer %d, " 852 "error = %d\n", i, error); 853 /* 854 * XXX we should attempt to run with fewer 855 * receive buffers instead of just failing. 856 */ 857 gem_rxdrain(sc); 858 return (1); 859 } 860 } else 861 GEM_INIT_RXDESC(sc, i); 862 } 863 sc->sc_rxptr = 0; 864 865 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 866 867 return (0); 868 } 869 870 static u_int 871 gem_ringsize(u_int sz) 872 { 873 874 switch (sz) { 875 case 32: 876 return (GEM_RING_SZ_32); 877 case 64: 878 return (GEM_RING_SZ_64); 879 case 128: 880 return (GEM_RING_SZ_128); 881 case 256: 882 return (GEM_RING_SZ_256); 883 case 512: 884 return (GEM_RING_SZ_512); 885 case 1024: 886 return (GEM_RING_SZ_1024); 887 case 2048: 888 return (GEM_RING_SZ_2048); 889 case 4096: 890 return (GEM_RING_SZ_4096); 891 case 8192: 892 return (GEM_RING_SZ_8192); 893 default: 894 printf("%s: invalid ring size %d\n", __func__, sz); 895 return (GEM_RING_SZ_32); 896 } 897 } 898 899 static void 900 gem_init(void *xsc) 901 { 902 struct gem_softc *sc = xsc; 903 904 GEM_LOCK(sc); 905 gem_init_locked(sc); 906 GEM_UNLOCK(sc); 907 } 908 909 /* 910 * Initialization of interface; set up initialization block 911 * and transmit/receive descriptor rings. 912 */ 913 static void 914 gem_init_locked(struct gem_softc *sc) 915 { 916 struct ifnet *ifp = sc->sc_ifp; 917 uint32_t v; 918 919 GEM_LOCK_ASSERT(sc, MA_OWNED); 920 921 #ifdef GEM_DEBUG 922 CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 923 __func__); 924 #endif 925 /* 926 * Initialization sequence. The numbered steps below correspond 927 * to the sequence outlined in section 6.3.5.1 in the Ethernet 928 * Channel Engine manual (part of the PCIO manual). 929 * See also the STP2002-STQ document from Sun Microsystems. 930 */ 931 932 /* step 1 & 2. Reset the Ethernet Channel. */ 933 gem_stop(ifp, 0); 934 gem_reset(sc); 935 #ifdef GEM_DEBUG 936 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 937 __func__); 938 #endif 939 940 if ((sc->sc_flags & GEM_SERDES) == 0) 941 /* Re-initialize the MIF. */ 942 gem_mifinit(sc); 943 944 /* step 3. Setup data structures in host memory. */ 945 if (gem_meminit(sc) != 0) 946 return; 947 948 /* step 4. TX MAC registers & counters */ 949 gem_init_regs(sc); 950 951 /* step 5. RX MAC registers & counters */ 952 gem_setladrf(sc); 953 954 /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 955 /* NOTE: we use only 32-bit DMA addresses here. */ 956 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 957 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 958 959 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 960 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 961 #ifdef GEM_DEBUG 962 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 963 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 964 #endif 965 966 /* step 8. Global Configuration & Interrupt Mask */ 967 968 /* 969 * Set the internal arbitration to "infinite" bursts of the 970 * maximum length of 31 * 64 bytes so DMA transfers aren't 971 * split up in cache line size chunks. This greatly improves 972 * RX performance. 973 * Enable silicon bug workarounds for the Apple variants. 974 */ 975 GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 976 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 977 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 978 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 979 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 980 981 GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 982 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 983 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 984 GEM_INTR_BERR 985 #ifdef GEM_DEBUG 986 | GEM_INTR_PCS | GEM_INTR_MIF 987 #endif 988 )); 989 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 990 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 991 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 992 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 993 GEM_MAC_TX_PEAK_EXP); 994 #ifdef GEM_DEBUG 995 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 996 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 997 #else 998 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 999 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1000 #endif 1001 1002 /* step 9. ETX Configuration: use mostly default values. */ 1003 1004 /* Enable DMA. */ 1005 v = gem_ringsize(GEM_NTXDESC); 1006 /* Set TX FIFO threshold and enable DMA. */ 1007 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1008 GEM_TX_CONFIG_TXFIFO_TH; 1009 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 1010 1011 /* step 10. ERX Configuration */ 1012 1013 /* Encode Receive Descriptor ring size. */ 1014 v = gem_ringsize(GEM_NRXDESC /* XXX */); 1015 /* RX TCP/UDP checksum offset */ 1016 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 1017 GEM_RX_CONFIG_CXM_START_SHFT); 1018 /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1019 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1020 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1021 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1022 GEM_RX_CONFIG_RXDMA_EN); 1023 1024 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1025 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1026 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1027 GEM_RX_BLANKING_TIME_SHIFT) | 6); 1028 1029 /* 1030 * The following value is for an OFF Threshold of about 3/4 full 1031 * and an ON Threshold of 1/4 full. 1032 */ 1033 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 1034 (3 * sc->sc_rxfifosize / 256) | 1035 ((sc->sc_rxfifosize / 256) << 12)); 1036 1037 /* step 11. Configure Media. */ 1038 1039 /* step 12. RX_MAC Configuration Register */ 1040 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1041 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1042 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 1043 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1044 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1045 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1046 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1047 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 1048 1049 /* step 13. TX_MAC Configuration Register */ 1050 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1051 v |= GEM_MAC_TX_ENABLE; 1052 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1053 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1054 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1055 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1056 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1057 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1058 1059 /* step 14. Issue Transmit Pending command. */ 1060 1061 /* step 15. Give the reciever a swift kick. */ 1062 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 1063 1064 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1065 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1066 1067 mii_mediachg(sc->sc_mii); 1068 1069 /* Start the one second timer. */ 1070 sc->sc_wdog_timer = 0; 1071 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1072 } 1073 1074 static int 1075 gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 1076 { 1077 bus_dma_segment_t txsegs[GEM_NTXSEGS]; 1078 struct gem_txsoft *txs; 1079 struct ip *ip; 1080 struct mbuf *m; 1081 uint64_t cflags, flags; 1082 int error, nexttx, nsegs, offset, seg; 1083 1084 GEM_LOCK_ASSERT(sc, MA_OWNED); 1085 1086 /* Get a work queue entry. */ 1087 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1088 /* Ran out of descriptors. */ 1089 return (ENOBUFS); 1090 } 1091 1092 cflags = 0; 1093 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1094 if (M_WRITABLE(*m_head) == 0) { 1095 m = m_dup(*m_head, M_DONTWAIT); 1096 m_freem(*m_head); 1097 *m_head = m; 1098 if (m == NULL) 1099 return (ENOBUFS); 1100 } 1101 offset = sizeof(struct ether_header); 1102 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1103 if (m == NULL) { 1104 *m_head = NULL; 1105 return (ENOBUFS); 1106 } 1107 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1108 offset += (ip->ip_hl << 2); 1109 cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1110 ((offset + m->m_pkthdr.csum_data) << 1111 GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1112 *m_head = m; 1113 } 1114 1115 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1116 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1117 if (error == EFBIG) { 1118 m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 1119 if (m == NULL) { 1120 m_freem(*m_head); 1121 *m_head = NULL; 1122 return (ENOBUFS); 1123 } 1124 *m_head = m; 1125 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1126 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1127 BUS_DMA_NOWAIT); 1128 if (error != 0) { 1129 m_freem(*m_head); 1130 *m_head = NULL; 1131 return (error); 1132 } 1133 } else if (error != 0) 1134 return (error); 1135 /* If nsegs is wrong then the stack is corrupt. */ 1136 KASSERT(nsegs <= GEM_NTXSEGS, 1137 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1138 if (nsegs == 0) { 1139 m_freem(*m_head); 1140 *m_head = NULL; 1141 return (EIO); 1142 } 1143 1144 /* 1145 * Ensure we have enough descriptors free to describe 1146 * the packet. Note, we always reserve one descriptor 1147 * at the end of the ring as a termination point, in 1148 * order to prevent wrap-around. 1149 */ 1150 if (nsegs > sc->sc_txfree - 1) { 1151 txs->txs_ndescs = 0; 1152 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1153 return (ENOBUFS); 1154 } 1155 1156 txs->txs_ndescs = nsegs; 1157 txs->txs_firstdesc = sc->sc_txnext; 1158 nexttx = txs->txs_firstdesc; 1159 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1160 #ifdef GEM_DEBUG 1161 CTR6(KTR_GEM, 1162 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1163 __func__, seg, nexttx, txsegs[seg].ds_len, 1164 txsegs[seg].ds_addr, 1165 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1166 #endif 1167 sc->sc_txdescs[nexttx].gd_addr = 1168 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1169 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1170 ("%s: segment size too large!", __func__)); 1171 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1172 sc->sc_txdescs[nexttx].gd_flags = 1173 GEM_DMA_WRITE(sc, flags | cflags); 1174 txs->txs_lastdesc = nexttx; 1175 } 1176 1177 /* Set EOP on the last descriptor. */ 1178 #ifdef GEM_DEBUG 1179 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1180 __func__, seg, nexttx); 1181 #endif 1182 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1183 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1184 1185 /* Lastly set SOP on the first descriptor. */ 1186 #ifdef GEM_DEBUG 1187 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1188 __func__, seg, nexttx); 1189 #endif 1190 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1191 sc->sc_txwin = 0; 1192 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1193 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1194 GEM_TD_START_OF_PACKET); 1195 } else 1196 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1197 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1198 1199 /* Sync the DMA map. */ 1200 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1201 BUS_DMASYNC_PREWRITE); 1202 1203 #ifdef GEM_DEBUG 1204 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1205 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1206 txs->txs_ndescs); 1207 #endif 1208 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1209 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1210 txs->txs_mbuf = *m_head; 1211 1212 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1213 sc->sc_txfree -= txs->txs_ndescs; 1214 1215 return (0); 1216 } 1217 1218 static void 1219 gem_init_regs(struct gem_softc *sc) 1220 { 1221 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1222 1223 GEM_LOCK_ASSERT(sc, MA_OWNED); 1224 1225 /* These registers are not cleared on reset. */ 1226 if ((sc->sc_flags & GEM_INITED) == 0) { 1227 /* magic values */ 1228 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1229 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1230 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 1231 1232 /* min frame length */ 1233 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1234 /* max frame length and max burst size */ 1235 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1236 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1237 1238 /* more magic values */ 1239 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1240 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1241 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1242 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088); 1243 1244 /* random number seed */ 1245 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1246 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1247 1248 /* secondary MAC address: 0:0:0:0:0:0 */ 1249 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1250 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1251 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1252 1253 /* MAC control address: 01:80:c2:00:00:01 */ 1254 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1255 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1256 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 1257 1258 /* MAC filter address: 0:0:0:0:0:0 */ 1259 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1260 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1261 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1262 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1263 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 1264 1265 sc->sc_flags |= GEM_INITED; 1266 } 1267 1268 /* Counters need to be zeroed. */ 1269 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1270 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1271 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1272 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1273 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1274 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1275 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1276 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1277 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1278 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1279 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 1280 1281 /* Set XOFF PAUSE time. */ 1282 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1283 1284 /* Set the station address. */ 1285 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1286 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1287 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1288 1289 /* Enable MII outputs. */ 1290 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 1291 } 1292 1293 static void 1294 gem_start(struct ifnet *ifp) 1295 { 1296 struct gem_softc *sc = ifp->if_softc; 1297 1298 GEM_LOCK(sc); 1299 gem_start_locked(ifp); 1300 GEM_UNLOCK(sc); 1301 } 1302 1303 static inline void 1304 gem_txkick(struct gem_softc *sc) 1305 { 1306 1307 /* 1308 * Update the TX kick register. This register has to point to the 1309 * descriptor after the last valid one and for optimum performance 1310 * should be incremented in multiples of 4 (the DMA engine fetches/ 1311 * updates descriptors in batches of 4). 1312 */ 1313 #ifdef GEM_DEBUG 1314 CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1315 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1316 #endif 1317 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1318 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1319 } 1320 1321 static void 1322 gem_start_locked(struct ifnet *ifp) 1323 { 1324 struct gem_softc *sc = ifp->if_softc; 1325 struct mbuf *m; 1326 int kicked, ntx; 1327 1328 GEM_LOCK_ASSERT(sc, MA_OWNED); 1329 1330 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1331 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 1332 return; 1333 1334 #ifdef GEM_DEBUG 1335 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1336 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1337 sc->sc_txnext); 1338 #endif 1339 ntx = 0; 1340 kicked = 0; 1341 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1342 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1343 if (m == NULL) 1344 break; 1345 if (gem_load_txmbuf(sc, &m) != 0) { 1346 if (m == NULL) 1347 break; 1348 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1349 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1350 break; 1351 } 1352 if ((sc->sc_txnext % 4) == 0) { 1353 gem_txkick(sc); 1354 kicked = 1; 1355 } else 1356 kicked = 0; 1357 ntx++; 1358 BPF_MTAP(ifp, m); 1359 } 1360 1361 if (ntx > 0) { 1362 if (kicked == 0) 1363 gem_txkick(sc); 1364 #ifdef GEM_DEBUG 1365 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1366 device_get_name(sc->sc_dev), sc->sc_txnext); 1367 #endif 1368 1369 /* Set a watchdog timer in case the chip flakes out. */ 1370 sc->sc_wdog_timer = 5; 1371 #ifdef GEM_DEBUG 1372 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1373 device_get_name(sc->sc_dev), __func__, 1374 sc->sc_wdog_timer); 1375 #endif 1376 } 1377 } 1378 1379 static void 1380 gem_tint(struct gem_softc *sc) 1381 { 1382 struct ifnet *ifp = sc->sc_ifp; 1383 struct gem_txsoft *txs; 1384 int progress; 1385 uint32_t txlast; 1386 #ifdef GEM_DEBUG 1387 int i; 1388 1389 GEM_LOCK_ASSERT(sc, MA_OWNED); 1390 1391 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1392 #endif 1393 1394 /* 1395 * Go through our TX list and free mbufs for those 1396 * frames that have been transmitted. 1397 */ 1398 progress = 0; 1399 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1400 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1401 #ifdef GEM_DEBUG 1402 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1403 printf(" txsoft %p transmit chain:\n", txs); 1404 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1405 printf("descriptor %d: ", i); 1406 printf("gd_flags: 0x%016llx\t", 1407 (long long)GEM_DMA_READ(sc, 1408 sc->sc_txdescs[i].gd_flags)); 1409 printf("gd_addr: 0x%016llx\n", 1410 (long long)GEM_DMA_READ(sc, 1411 sc->sc_txdescs[i].gd_addr)); 1412 if (i == txs->txs_lastdesc) 1413 break; 1414 } 1415 } 1416 #endif 1417 1418 /* 1419 * In theory, we could harvest some descriptors before 1420 * the ring is empty, but that's a bit complicated. 1421 * 1422 * GEM_TX_COMPLETION points to the last descriptor 1423 * processed + 1. 1424 */ 1425 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1426 #ifdef GEM_DEBUG 1427 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 1428 "txs->txs_lastdesc = %d, txlast = %d", 1429 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1430 #endif 1431 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1432 if ((txlast >= txs->txs_firstdesc) && 1433 (txlast <= txs->txs_lastdesc)) 1434 break; 1435 } else { 1436 /* Ick -- this command wraps. */ 1437 if ((txlast >= txs->txs_firstdesc) || 1438 (txlast <= txs->txs_lastdesc)) 1439 break; 1440 } 1441 1442 #ifdef GEM_DEBUG 1443 CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1444 #endif 1445 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1446 1447 sc->sc_txfree += txs->txs_ndescs; 1448 1449 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1450 BUS_DMASYNC_POSTWRITE); 1451 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1452 if (txs->txs_mbuf != NULL) { 1453 m_freem(txs->txs_mbuf); 1454 txs->txs_mbuf = NULL; 1455 } 1456 1457 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1458 1459 ifp->if_opackets++; 1460 progress = 1; 1461 } 1462 1463 #ifdef GEM_DEBUG 1464 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1465 "GEM_TX_COMPLETION %x", 1466 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1467 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1468 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1469 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1470 #endif 1471 1472 if (progress) { 1473 if (sc->sc_txfree == GEM_NTXDESC - 1) 1474 sc->sc_txwin = 0; 1475 1476 /* 1477 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1478 * and restart. 1479 */ 1480 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1481 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1482 sc->sc_wdog_timer = 0; 1483 gem_start_locked(ifp); 1484 } 1485 1486 #ifdef GEM_DEBUG 1487 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1488 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1489 #endif 1490 } 1491 1492 #ifdef GEM_RINT_TIMEOUT 1493 static void 1494 gem_rint_timeout(void *arg) 1495 { 1496 struct gem_softc *sc = arg; 1497 1498 GEM_LOCK_ASSERT(sc, MA_OWNED); 1499 1500 gem_rint(sc); 1501 } 1502 #endif 1503 1504 static void 1505 gem_rint(struct gem_softc *sc) 1506 { 1507 struct ifnet *ifp = sc->sc_ifp; 1508 struct mbuf *m; 1509 uint64_t rxstat; 1510 uint32_t rxcomp; 1511 1512 GEM_LOCK_ASSERT(sc, MA_OWNED); 1513 1514 #ifdef GEM_RINT_TIMEOUT 1515 callout_stop(&sc->sc_rx_ch); 1516 #endif 1517 #ifdef GEM_DEBUG 1518 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1519 #endif 1520 1521 /* 1522 * Read the completion register once. This limits 1523 * how long the following loop can execute. 1524 */ 1525 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1526 #ifdef GEM_DEBUG 1527 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1528 __func__, sc->sc_rxptr, rxcomp); 1529 #endif 1530 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1531 for (; sc->sc_rxptr != rxcomp;) { 1532 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1533 rxstat = GEM_DMA_READ(sc, 1534 sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 1535 1536 if (rxstat & GEM_RD_OWN) { 1537 #ifdef GEM_RINT_TIMEOUT 1538 /* 1539 * The descriptor is still marked as owned, although 1540 * it is supposed to have completed. This has been 1541 * observed on some machines. Just exiting here 1542 * might leave the packet sitting around until another 1543 * one arrives to trigger a new interrupt, which is 1544 * generally undesirable, so set up a timeout. 1545 */ 1546 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1547 gem_rint_timeout, sc); 1548 #endif 1549 m = NULL; 1550 goto kickit; 1551 } 1552 1553 if (rxstat & GEM_RD_BAD_CRC) { 1554 ifp->if_ierrors++; 1555 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1556 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1557 m = NULL; 1558 goto kickit; 1559 } 1560 1561 #ifdef GEM_DEBUG 1562 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1563 printf(" rxsoft %p descriptor %d: ", 1564 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1565 printf("gd_flags: 0x%016llx\t", 1566 (long long)GEM_DMA_READ(sc, 1567 sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1568 printf("gd_addr: 0x%016llx\n", 1569 (long long)GEM_DMA_READ(sc, 1570 sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 1571 } 1572 #endif 1573 1574 /* 1575 * Allocate a new mbuf cluster. If that fails, we are 1576 * out of memory, and must drop the packet and recycle 1577 * the buffer that's already attached to this descriptor. 1578 */ 1579 if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 1580 ifp->if_ierrors++; 1581 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1582 m = NULL; 1583 } 1584 1585 kickit: 1586 /* 1587 * Update the RX kick register. This register has to point 1588 * to the descriptor after the last valid one (before the 1589 * current batch) and for optimum performance should be 1590 * incremented in multiples of 4 (the DMA engine fetches/ 1591 * updates descriptors in batches of 4). 1592 */ 1593 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1594 if ((sc->sc_rxptr % 4) == 0) { 1595 GEM_CDSYNC(sc, 1596 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1597 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1598 (sc->sc_rxptr + GEM_NRXDESC - 4) & 1599 GEM_NRXDESC_MASK); 1600 } 1601 1602 if (m == NULL) { 1603 if (rxstat & GEM_RD_OWN) 1604 break; 1605 continue; 1606 } 1607 1608 ifp->if_ipackets++; 1609 m->m_data += ETHER_ALIGN; /* first byte offset */ 1610 m->m_pkthdr.rcvif = ifp; 1611 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 1612 1613 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1614 gem_rxcksum(m, rxstat); 1615 1616 /* Pass it on. */ 1617 GEM_UNLOCK(sc); 1618 (*ifp->if_input)(ifp, m); 1619 GEM_LOCK(sc); 1620 } 1621 1622 #ifdef GEM_DEBUG 1623 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1624 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1625 #endif 1626 } 1627 1628 static int 1629 gem_add_rxbuf(struct gem_softc *sc, int idx) 1630 { 1631 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1632 struct mbuf *m; 1633 bus_dma_segment_t segs[1]; 1634 int error, nsegs; 1635 1636 GEM_LOCK_ASSERT(sc, MA_OWNED); 1637 1638 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1639 if (m == NULL) 1640 return (ENOBUFS); 1641 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1642 1643 #ifdef GEM_DEBUG 1644 /* Bzero the packet to check DMA. */ 1645 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1646 #endif 1647 1648 if (rxs->rxs_mbuf != NULL) { 1649 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1650 BUS_DMASYNC_POSTREAD); 1651 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1652 } 1653 1654 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1655 m, segs, &nsegs, BUS_DMA_NOWAIT); 1656 if (error != 0) { 1657 device_printf(sc->sc_dev, 1658 "cannot load RS DMA map %d, error = %d\n", idx, error); 1659 m_freem(m); 1660 return (error); 1661 } 1662 /* If nsegs is wrong then the stack is corrupt. */ 1663 KASSERT(nsegs == 1, 1664 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1665 rxs->rxs_mbuf = m; 1666 rxs->rxs_paddr = segs[0].ds_addr; 1667 1668 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1669 BUS_DMASYNC_PREREAD); 1670 1671 GEM_INIT_RXDESC(sc, idx); 1672 1673 return (0); 1674 } 1675 1676 static void 1677 gem_eint(struct gem_softc *sc, u_int status) 1678 { 1679 1680 sc->sc_ifp->if_ierrors++; 1681 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1682 gem_reset_rxdma(sc); 1683 return; 1684 } 1685 1686 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1687 if ((status & GEM_INTR_BERR) != 0) { 1688 if ((sc->sc_flags & GEM_PCI) != 0) 1689 printf(", PCI bus error 0x%x\n", 1690 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1691 else 1692 printf(", SBus error 0x%x\n", 1693 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1694 } 1695 } 1696 1697 void 1698 gem_intr(void *v) 1699 { 1700 struct gem_softc *sc = v; 1701 uint32_t status, status2; 1702 1703 GEM_LOCK(sc); 1704 status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1705 1706 #ifdef GEM_DEBUG 1707 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1708 device_get_name(sc->sc_dev), __func__, 1709 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1710 1711 /* 1712 * PCS interrupts must be cleared, otherwise no traffic is passed! 1713 */ 1714 if ((status & GEM_INTR_PCS) != 0) { 1715 status2 = 1716 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1717 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1718 if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1719 device_printf(sc->sc_dev, 1720 "%s: PCS link status changed\n", __func__); 1721 } 1722 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1723 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1724 if ((status2 & GEM_MAC_PAUSED) != 0) 1725 device_printf(sc->sc_dev, 1726 "%s: PAUSE received (PAUSE time %d slots)\n", 1727 __func__, GEM_MAC_PAUSE_TIME(status2)); 1728 if ((status2 & GEM_MAC_PAUSE) != 0) 1729 device_printf(sc->sc_dev, 1730 "%s: transited to PAUSE state\n", __func__); 1731 if ((status2 & GEM_MAC_RESUME) != 0) 1732 device_printf(sc->sc_dev, 1733 "%s: transited to non-PAUSE state\n", __func__); 1734 } 1735 if ((status & GEM_INTR_MIF) != 0) 1736 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1737 #endif 1738 1739 if (__predict_false(status & 1740 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 1741 gem_eint(sc, status); 1742 1743 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1744 gem_rint(sc); 1745 1746 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1747 gem_tint(sc); 1748 1749 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1750 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1751 if ((status2 & 1752 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1753 GEM_MAC_TX_PEAK_EXP)) != 0) 1754 device_printf(sc->sc_dev, 1755 "MAC TX fault, status %x\n", status2); 1756 if ((status2 & 1757 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1758 sc->sc_ifp->if_oerrors++; 1759 gem_init_locked(sc); 1760 } 1761 } 1762 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1763 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1764 /* 1765 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1766 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1767 * silicon bug so handle them silently. Moreover, it's 1768 * likely that the receiver has hung so we reset it. 1769 */ 1770 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1771 sc->sc_ifp->if_ierrors++; 1772 gem_reset_rxdma(sc); 1773 } else if ((status2 & 1774 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1775 device_printf(sc->sc_dev, 1776 "MAC RX fault, status %x\n", status2); 1777 } 1778 GEM_UNLOCK(sc); 1779 } 1780 1781 static int 1782 gem_watchdog(struct gem_softc *sc) 1783 { 1784 struct ifnet *ifp = sc->sc_ifp; 1785 1786 GEM_LOCK_ASSERT(sc, MA_OWNED); 1787 1788 #ifdef GEM_DEBUG 1789 CTR4(KTR_GEM, 1790 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1791 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1792 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1793 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1794 CTR4(KTR_GEM, 1795 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1796 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1797 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1798 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1799 #endif 1800 1801 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1802 return (0); 1803 1804 if ((sc->sc_flags & GEM_LINK) != 0) 1805 device_printf(sc->sc_dev, "device timeout\n"); 1806 else if (bootverbose) 1807 device_printf(sc->sc_dev, "device timeout (no link)\n"); 1808 ++ifp->if_oerrors; 1809 1810 /* Try to get more packets going. */ 1811 gem_init_locked(sc); 1812 gem_start_locked(ifp); 1813 return (EJUSTRETURN); 1814 } 1815 1816 static void 1817 gem_mifinit(struct gem_softc *sc) 1818 { 1819 1820 /* Configure the MIF in frame mode. */ 1821 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1822 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1823 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 1824 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1825 } 1826 1827 /* 1828 * MII interface 1829 * 1830 * The MII interface supports at least three different operating modes: 1831 * 1832 * Bitbang mode is implemented using data, clock and output enable registers. 1833 * 1834 * Frame mode is implemented by loading a complete frame into the frame 1835 * register and polling the valid bit for completion. 1836 * 1837 * Polling mode uses the frame register but completion is indicated by 1838 * an interrupt. 1839 * 1840 */ 1841 int 1842 gem_mii_readreg(device_t dev, int phy, int reg) 1843 { 1844 struct gem_softc *sc; 1845 int n; 1846 uint32_t v; 1847 1848 #ifdef GEM_DEBUG_PHY 1849 printf("%s: phy %d reg %d\n", __func__, phy, reg); 1850 #endif 1851 1852 sc = device_get_softc(dev); 1853 if ((sc->sc_flags & GEM_SERDES) != 0) { 1854 switch (reg) { 1855 case MII_BMCR: 1856 reg = GEM_MII_CONTROL; 1857 break; 1858 case MII_BMSR: 1859 reg = GEM_MII_STATUS; 1860 break; 1861 case MII_PHYIDR1: 1862 case MII_PHYIDR2: 1863 return (0); 1864 case MII_ANAR: 1865 reg = GEM_MII_ANAR; 1866 break; 1867 case MII_ANLPAR: 1868 reg = GEM_MII_ANLPAR; 1869 break; 1870 case MII_EXTSR: 1871 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1872 default: 1873 device_printf(sc->sc_dev, 1874 "%s: unhandled register %d\n", __func__, reg); 1875 return (0); 1876 } 1877 return (GEM_BANK1_READ_4(sc, reg)); 1878 } 1879 1880 /* Construct the frame command. */ 1881 v = GEM_MIF_FRAME_READ | 1882 (phy << GEM_MIF_PHY_SHIFT) | 1883 (reg << GEM_MIF_REG_SHIFT); 1884 1885 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1886 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1887 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1888 for (n = 0; n < 100; n++) { 1889 DELAY(1); 1890 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1891 if (v & GEM_MIF_FRAME_TA0) 1892 return (v & GEM_MIF_FRAME_DATA); 1893 } 1894 1895 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1896 return (0); 1897 } 1898 1899 int 1900 gem_mii_writereg(device_t dev, int phy, int reg, int val) 1901 { 1902 struct gem_softc *sc; 1903 int n; 1904 uint32_t v; 1905 1906 #ifdef GEM_DEBUG_PHY 1907 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 1908 #endif 1909 1910 sc = device_get_softc(dev); 1911 if ((sc->sc_flags & GEM_SERDES) != 0) { 1912 switch (reg) { 1913 case MII_BMSR: 1914 reg = GEM_MII_STATUS; 1915 break; 1916 case MII_BMCR: 1917 reg = GEM_MII_CONTROL; 1918 if ((val & GEM_MII_CONTROL_RESET) == 0) 1919 break; 1920 GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1921 GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1922 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1923 if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1924 GEM_MII_CONTROL_RESET, 0)) 1925 device_printf(sc->sc_dev, 1926 "cannot reset PCS\n"); 1927 /* FALLTHROUGH */ 1928 case MII_ANAR: 1929 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1930 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1931 BUS_SPACE_BARRIER_WRITE); 1932 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1933 GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 1934 BUS_SPACE_BARRIER_WRITE); 1935 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1936 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1937 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 1938 BUS_SPACE_BARRIER_WRITE); 1939 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1940 GEM_MII_CONFIG_ENABLE); 1941 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1942 BUS_SPACE_BARRIER_WRITE); 1943 return (0); 1944 case MII_ANLPAR: 1945 reg = GEM_MII_ANLPAR; 1946 break; 1947 default: 1948 device_printf(sc->sc_dev, 1949 "%s: unhandled register %d\n", __func__, reg); 1950 return (0); 1951 } 1952 GEM_BANK1_WRITE_4(sc, reg, val); 1953 GEM_BANK1_BARRIER(sc, reg, 4, 1954 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1955 return (0); 1956 } 1957 1958 /* Construct the frame command. */ 1959 v = GEM_MIF_FRAME_WRITE | 1960 (phy << GEM_MIF_PHY_SHIFT) | 1961 (reg << GEM_MIF_REG_SHIFT) | 1962 (val & GEM_MIF_FRAME_DATA); 1963 1964 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1965 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1966 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1967 for (n = 0; n < 100; n++) { 1968 DELAY(1); 1969 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1970 if (v & GEM_MIF_FRAME_TA0) 1971 return (1); 1972 } 1973 1974 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1975 return (0); 1976 } 1977 1978 void 1979 gem_mii_statchg(device_t dev) 1980 { 1981 struct gem_softc *sc; 1982 int gigabit; 1983 uint32_t rxcfg, txcfg, v; 1984 1985 sc = device_get_softc(dev); 1986 1987 GEM_LOCK_ASSERT(sc, MA_OWNED); 1988 1989 #ifdef GEM_DEBUG 1990 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1991 device_printf(sc->sc_dev, "%s: status change\n", __func__); 1992 #endif 1993 1994 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 1995 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 1996 sc->sc_flags |= GEM_LINK; 1997 else 1998 sc->sc_flags &= ~GEM_LINK; 1999 2000 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2001 case IFM_1000_SX: 2002 case IFM_1000_LX: 2003 case IFM_1000_CX: 2004 case IFM_1000_T: 2005 gigabit = 1; 2006 break; 2007 default: 2008 gigabit = 0; 2009 } 2010 2011 /* 2012 * The configuration done here corresponds to the steps F) and 2013 * G) and as far as enabling of RX and TX MAC goes also step H) 2014 * of the initialization sequence outlined in section 3.2.1 of 2015 * the GEM Gigabit Ethernet ASIC Specification. 2016 */ 2017 2018 rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2019 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2020 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2021 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2022 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2023 else if (gigabit != 0) { 2024 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2025 txcfg |= GEM_MAC_TX_CARR_EXTEND; 2026 } 2027 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 2028 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 2029 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2030 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2031 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2032 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2033 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 2034 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2035 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2036 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2037 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2038 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2039 2040 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2041 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2042 #ifdef notyet 2043 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2044 IFM_ETH_RXPAUSE) != 0) 2045 v |= GEM_MAC_CC_RX_PAUSE; 2046 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2047 IFM_ETH_TXPAUSE) != 0) 2048 v |= GEM_MAC_CC_TX_PAUSE; 2049 #endif 2050 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2051 2052 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2053 gigabit != 0) 2054 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2055 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2056 else 2057 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2058 GEM_MAC_SLOT_TIME_NORMAL); 2059 2060 /* XIF Configuration */ 2061 v = GEM_MAC_XIF_LINK_LED; 2062 v |= GEM_MAC_XIF_TX_MII_ENA; 2063 if ((sc->sc_flags & GEM_SERDES) == 0) { 2064 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2065 GEM_MIF_CONFIG_PHY_SEL) != 0) { 2066 /* External MII needs echo disable if half duplex. */ 2067 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2068 IFM_FDX) == 0) 2069 v |= GEM_MAC_XIF_ECHO_DISABL; 2070 } else 2071 /* 2072 * Internal MII needs buffer enable. 2073 * XXX buffer enable makes only sense for an 2074 * external PHY. 2075 */ 2076 v |= GEM_MAC_XIF_MII_BUF_ENA; 2077 } 2078 if (gigabit != 0) 2079 v |= GEM_MAC_XIF_GMII_MODE; 2080 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2081 v |= GEM_MAC_XIF_FDPLX_LED; 2082 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 2083 2084 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2085 (sc->sc_flags & GEM_LINK) != 0) { 2086 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2087 txcfg | GEM_MAC_TX_ENABLE); 2088 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2089 rxcfg | GEM_MAC_RX_ENABLE); 2090 } 2091 } 2092 2093 int 2094 gem_mediachange(struct ifnet *ifp) 2095 { 2096 struct gem_softc *sc = ifp->if_softc; 2097 int error; 2098 2099 /* XXX add support for serial media. */ 2100 2101 GEM_LOCK(sc); 2102 error = mii_mediachg(sc->sc_mii); 2103 GEM_UNLOCK(sc); 2104 return (error); 2105 } 2106 2107 void 2108 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2109 { 2110 struct gem_softc *sc = ifp->if_softc; 2111 2112 GEM_LOCK(sc); 2113 if ((ifp->if_flags & IFF_UP) == 0) { 2114 GEM_UNLOCK(sc); 2115 return; 2116 } 2117 2118 mii_pollstat(sc->sc_mii); 2119 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2120 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2121 GEM_UNLOCK(sc); 2122 } 2123 2124 static int 2125 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2126 { 2127 struct gem_softc *sc = ifp->if_softc; 2128 struct ifreq *ifr = (struct ifreq *)data; 2129 int error; 2130 2131 error = 0; 2132 switch (cmd) { 2133 case SIOCSIFFLAGS: 2134 GEM_LOCK(sc); 2135 if ((ifp->if_flags & IFF_UP) != 0) { 2136 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2137 ((ifp->if_flags ^ sc->sc_ifflags) & 2138 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2139 gem_setladrf(sc); 2140 else 2141 gem_init_locked(sc); 2142 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2143 gem_stop(ifp, 0); 2144 if ((ifp->if_flags & IFF_LINK0) != 0) 2145 sc->sc_csum_features |= CSUM_UDP; 2146 else 2147 sc->sc_csum_features &= ~CSUM_UDP; 2148 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2149 ifp->if_hwassist = sc->sc_csum_features; 2150 sc->sc_ifflags = ifp->if_flags; 2151 GEM_UNLOCK(sc); 2152 break; 2153 case SIOCADDMULTI: 2154 case SIOCDELMULTI: 2155 GEM_LOCK(sc); 2156 gem_setladrf(sc); 2157 GEM_UNLOCK(sc); 2158 break; 2159 case SIOCGIFMEDIA: 2160 case SIOCSIFMEDIA: 2161 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2162 break; 2163 case SIOCSIFCAP: 2164 GEM_LOCK(sc); 2165 ifp->if_capenable = ifr->ifr_reqcap; 2166 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2167 ifp->if_hwassist = sc->sc_csum_features; 2168 else 2169 ifp->if_hwassist = 0; 2170 GEM_UNLOCK(sc); 2171 break; 2172 default: 2173 error = ether_ioctl(ifp, cmd, data); 2174 break; 2175 } 2176 2177 return (error); 2178 } 2179 2180 static void 2181 gem_setladrf(struct gem_softc *sc) 2182 { 2183 struct ifnet *ifp = sc->sc_ifp; 2184 struct ifmultiaddr *inm; 2185 int i; 2186 uint32_t hash[16]; 2187 uint32_t crc, v; 2188 2189 GEM_LOCK_ASSERT(sc, MA_OWNED); 2190 2191 /* Get the current RX configuration. */ 2192 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2193 2194 /* 2195 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2196 * and hash filter. Depending on the case, the right bit will be 2197 * enabled. 2198 */ 2199 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2200 GEM_MAC_RX_PROMISC_GRP); 2201 2202 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2203 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2204 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2205 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 2206 0)) 2207 device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2208 2209 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2210 v |= GEM_MAC_RX_PROMISCUOUS; 2211 goto chipit; 2212 } 2213 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2214 v |= GEM_MAC_RX_PROMISC_GRP; 2215 goto chipit; 2216 } 2217 2218 /* 2219 * Set up multicast address filter by passing all multicast 2220 * addresses through a crc generator, and then using the high 2221 * order 8 bits as an index into the 256 bit logical address 2222 * filter. The high order 4 bits selects the word, while the 2223 * other 4 bits select the bit within the word (where bit 0 2224 * is the MSB). 2225 */ 2226 2227 /* Clear the hash table. */ 2228 memset(hash, 0, sizeof(hash)); 2229 2230 if_maddr_rlock(ifp); 2231 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2232 if (inm->ifma_addr->sa_family != AF_LINK) 2233 continue; 2234 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2235 inm->ifma_addr), ETHER_ADDR_LEN); 2236 2237 /* We just want the 8 most significant bits. */ 2238 crc >>= 24; 2239 2240 /* Set the corresponding bit in the filter. */ 2241 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2242 } 2243 if_maddr_runlock(ifp); 2244 2245 v |= GEM_MAC_RX_HASH_FILTER; 2246 2247 /* Now load the hash table into the chip (if we are using it). */ 2248 for (i = 0; i < 16; i++) 2249 GEM_BANK1_WRITE_4(sc, 2250 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 2251 hash[i]); 2252 2253 chipit: 2254 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2255 } 2256