1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #if 0 38 #define GEM_DEBUG 39 #endif 40 41 #if 0 /* XXX: In case of emergency, re-enable this. */ 42 #define GEM_RINT_TIMEOUT 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/bus.h> 48 #include <sys/callout.h> 49 #include <sys/endian.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/lock.h> 54 #include <sys/module.h> 55 #include <sys/mutex.h> 56 #include <sys/socket.h> 57 #include <sys/sockio.h> 58 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/if.h> 62 #include <net/if_arp.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <machine/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/gem/if_gemreg.h> 73 #include <dev/gem/if_gemvar.h> 74 75 #define TRIES 10000 76 77 static void gem_start(struct ifnet *); 78 static void gem_start_locked(struct ifnet *); 79 static void gem_stop(struct ifnet *, int); 80 static int gem_ioctl(struct ifnet *, u_long, caddr_t); 81 static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); 82 static void gem_txdma_callback(void *, bus_dma_segment_t *, int, 83 bus_size_t, int); 84 static void gem_tick(void *); 85 static void gem_watchdog(struct ifnet *); 86 static void gem_init(void *); 87 static void gem_init_locked(struct gem_softc *sc); 88 static void gem_init_regs(struct gem_softc *sc); 89 static int gem_ringsize(int sz); 90 static int gem_meminit(struct gem_softc *); 91 static int gem_load_txmbuf(struct gem_softc *, struct mbuf *); 92 static void gem_mifinit(struct gem_softc *); 93 static int gem_bitwait(struct gem_softc *sc, bus_addr_t r, 94 u_int32_t clr, u_int32_t set); 95 static int gem_reset_rx(struct gem_softc *); 96 static int gem_reset_tx(struct gem_softc *); 97 static int gem_disable_rx(struct gem_softc *); 98 static int gem_disable_tx(struct gem_softc *); 99 static void gem_rxdrain(struct gem_softc *); 100 static int gem_add_rxbuf(struct gem_softc *, int); 101 static void gem_setladrf(struct gem_softc *); 102 103 struct mbuf *gem_get(struct gem_softc *, int, int); 104 static void gem_eint(struct gem_softc *, u_int); 105 static void gem_rint(struct gem_softc *); 106 #ifdef GEM_RINT_TIMEOUT 107 static void gem_rint_timeout(void *); 108 #endif 109 static void gem_tint(struct gem_softc *); 110 #ifdef notyet 111 static void gem_power(int, void *); 112 #endif 113 114 devclass_t gem_devclass; 115 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 116 MODULE_DEPEND(gem, miibus, 1, 1, 1); 117 118 #ifdef GEM_DEBUG 119 #include <sys/ktr.h> 120 #define KTR_GEM KTR_CT2 121 #endif 122 123 #define GEM_NSEGS GEM_NTXDESC 124 125 /* 126 * gem_attach: 127 * 128 * Attach a Gem interface to the system. 129 */ 130 int 131 gem_attach(sc) 132 struct gem_softc *sc; 133 { 134 struct ifnet *ifp; 135 struct mii_softc *child; 136 int i, error; 137 u_int32_t v; 138 139 GEM_LOCK_ASSERT(sc, MA_NOTOWNED); 140 141 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 142 if (ifp == NULL) 143 return (ENOSPC); 144 145 /* Make sure the chip is stopped. */ 146 ifp->if_softc = sc; 147 GEM_LOCK(sc); 148 gem_reset(sc); 149 GEM_UNLOCK(sc); 150 151 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 152 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS, 153 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->sc_pdmatag); 154 if (error) 155 goto fail_ifnet; 156 157 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 158 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE, 159 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL, 160 &sc->sc_rdmatag); 161 if (error) 162 goto fail_ptag; 163 164 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 165 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 166 GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT, 167 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 168 if (error) 169 goto fail_rtag; 170 171 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 172 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 173 sizeof(struct gem_control_data), 1, 174 sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW, 175 busdma_lock_mutex, &Giant, &sc->sc_cdmatag); 176 if (error) 177 goto fail_ttag; 178 179 /* 180 * Allocate the control data structures, and create and load the 181 * DMA map for it. 182 */ 183 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 184 (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) { 185 device_printf(sc->sc_dev, "unable to allocate control data," 186 " error = %d\n", error); 187 goto fail_ctag; 188 } 189 190 sc->sc_cddma = 0; 191 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 192 sc->sc_control_data, sizeof(struct gem_control_data), 193 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 194 device_printf(sc->sc_dev, "unable to load control data DMA " 195 "map, error = %d\n", error); 196 goto fail_cmem; 197 } 198 199 /* 200 * Initialize the transmit job descriptors. 201 */ 202 STAILQ_INIT(&sc->sc_txfreeq); 203 STAILQ_INIT(&sc->sc_txdirtyq); 204 205 /* 206 * Create the transmit buffer DMA maps. 207 */ 208 error = ENOMEM; 209 for (i = 0; i < GEM_TXQUEUELEN; i++) { 210 struct gem_txsoft *txs; 211 212 txs = &sc->sc_txsoft[i]; 213 txs->txs_mbuf = NULL; 214 txs->txs_ndescs = 0; 215 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 216 &txs->txs_dmamap)) != 0) { 217 device_printf(sc->sc_dev, "unable to create tx DMA map " 218 "%d, error = %d\n", i, error); 219 goto fail_txd; 220 } 221 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 222 } 223 224 /* 225 * Create the receive buffer DMA maps. 226 */ 227 for (i = 0; i < GEM_NRXDESC; i++) { 228 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 229 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 230 device_printf(sc->sc_dev, "unable to create rx DMA map " 231 "%d, error = %d\n", i, error); 232 goto fail_rxd; 233 } 234 sc->sc_rxsoft[i].rxs_mbuf = NULL; 235 } 236 237 GEM_LOCK(sc); 238 gem_mifinit(sc); 239 GEM_UNLOCK(sc); 240 241 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange, 242 gem_mediastatus)) != 0) { 243 device_printf(sc->sc_dev, "phy probe failed: %d\n", error); 244 goto fail_rxd; 245 } 246 sc->sc_mii = device_get_softc(sc->sc_miibus); 247 248 /* 249 * From this point forward, the attachment cannot fail. A failure 250 * before this point releases all resources that may have been 251 * allocated. 252 */ 253 254 /* Get RX FIFO size */ 255 sc->sc_rxfifosize = 64 * 256 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 257 258 /* Get TX FIFO size */ 259 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 260 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 261 sc->sc_rxfifosize / 1024, v / 16); 262 263 /* Initialize ifnet structure. */ 264 ifp->if_softc = sc; 265 if_initname(ifp, device_get_name(sc->sc_dev), 266 device_get_unit(sc->sc_dev)); 267 ifp->if_mtu = ETHERMTU; 268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 269 ifp->if_start = gem_start; 270 ifp->if_ioctl = gem_ioctl; 271 ifp->if_watchdog = gem_watchdog; 272 ifp->if_init = gem_init; 273 ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN; 274 /* 275 * Walk along the list of attached MII devices and 276 * establish an `MII instance' to `phy number' 277 * mapping. We'll use this mapping in media change 278 * requests to determine which phy to use to program 279 * the MIF configuration register. 280 */ 281 for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL; 282 child = LIST_NEXT(child, mii_list)) { 283 /* 284 * Note: we support just two PHYs: the built-in 285 * internal device and an external on the MII 286 * connector. 287 */ 288 if (child->mii_phy > 1 || child->mii_inst > 1) { 289 device_printf(sc->sc_dev, "cannot accomodate " 290 "MII device %s at phy %d, instance %d\n", 291 device_get_name(child->mii_dev), 292 child->mii_phy, child->mii_inst); 293 continue; 294 } 295 296 sc->sc_phys[child->mii_inst] = child->mii_phy; 297 } 298 299 /* 300 * Now select and activate the PHY we will use. 301 * 302 * The order of preference is External (MDI1), 303 * Internal (MDI0), Serial Link (no MII). 304 */ 305 if (sc->sc_phys[1]) { 306 #ifdef GEM_DEBUG 307 printf("using external phy\n"); 308 #endif 309 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 310 } else { 311 #ifdef GEM_DEBUG 312 printf("using internal phy\n"); 313 #endif 314 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 315 } 316 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 317 sc->sc_mif_config); 318 /* Attach the interface. */ 319 ether_ifattach(ifp, sc->sc_enaddr); 320 321 #if notyet 322 /* 323 * Add a suspend hook to make sure we come back up after a 324 * resume. 325 */ 326 sc->sc_powerhook = powerhook_establish(gem_power, sc); 327 if (sc->sc_powerhook == NULL) 328 device_printf(sc->sc_dev, "WARNING: unable to establish power " 329 "hook\n"); 330 #endif 331 332 callout_init(&sc->sc_tick_ch, CALLOUT_MPSAFE); 333 #ifdef GEM_RINT_TIMEOUT 334 callout_init(&sc->sc_rx_ch, CALLOUT_MPSAFE); 335 #endif 336 return (0); 337 338 /* 339 * Free any resources we've allocated during the failed attach 340 * attempt. Do this in reverse order and fall through. 341 */ 342 fail_rxd: 343 for (i = 0; i < GEM_NRXDESC; i++) { 344 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 345 bus_dmamap_destroy(sc->sc_rdmatag, 346 sc->sc_rxsoft[i].rxs_dmamap); 347 } 348 fail_txd: 349 for (i = 0; i < GEM_TXQUEUELEN; i++) { 350 if (sc->sc_txsoft[i].txs_dmamap != NULL) 351 bus_dmamap_destroy(sc->sc_tdmatag, 352 sc->sc_txsoft[i].txs_dmamap); 353 } 354 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 355 fail_cmem: 356 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 357 sc->sc_cddmamap); 358 fail_ctag: 359 bus_dma_tag_destroy(sc->sc_cdmatag); 360 fail_ttag: 361 bus_dma_tag_destroy(sc->sc_tdmatag); 362 fail_rtag: 363 bus_dma_tag_destroy(sc->sc_rdmatag); 364 fail_ptag: 365 bus_dma_tag_destroy(sc->sc_pdmatag); 366 fail_ifnet: 367 if_free(ifp); 368 return (error); 369 } 370 371 void 372 gem_detach(sc) 373 struct gem_softc *sc; 374 { 375 struct ifnet *ifp = sc->sc_ifp; 376 int i; 377 378 GEM_LOCK_ASSERT(sc, MA_NOTOWNED); 379 380 GEM_LOCK(sc); 381 gem_stop(ifp, 1); 382 GEM_UNLOCK(sc); 383 ether_ifdetach(ifp); 384 if_free(ifp); 385 device_delete_child(sc->sc_dev, sc->sc_miibus); 386 387 for (i = 0; i < GEM_NRXDESC; i++) { 388 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 389 bus_dmamap_destroy(sc->sc_rdmatag, 390 sc->sc_rxsoft[i].rxs_dmamap); 391 } 392 for (i = 0; i < GEM_TXQUEUELEN; i++) { 393 if (sc->sc_txsoft[i].txs_dmamap != NULL) 394 bus_dmamap_destroy(sc->sc_tdmatag, 395 sc->sc_txsoft[i].txs_dmamap); 396 } 397 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 398 GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE); 399 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 400 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 401 sc->sc_cddmamap); 402 bus_dma_tag_destroy(sc->sc_cdmatag); 403 bus_dma_tag_destroy(sc->sc_tdmatag); 404 bus_dma_tag_destroy(sc->sc_rdmatag); 405 bus_dma_tag_destroy(sc->sc_pdmatag); 406 } 407 408 void 409 gem_suspend(sc) 410 struct gem_softc *sc; 411 { 412 struct ifnet *ifp = sc->sc_ifp; 413 414 GEM_LOCK(sc); 415 gem_stop(ifp, 0); 416 GEM_UNLOCK(sc); 417 } 418 419 void 420 gem_resume(sc) 421 struct gem_softc *sc; 422 { 423 struct ifnet *ifp = sc->sc_ifp; 424 425 GEM_LOCK(sc); 426 if (ifp->if_flags & IFF_UP) 427 gem_init_locked(sc); 428 GEM_UNLOCK(sc); 429 } 430 431 static void 432 gem_cddma_callback(xsc, segs, nsegs, error) 433 void *xsc; 434 bus_dma_segment_t *segs; 435 int nsegs; 436 int error; 437 { 438 struct gem_softc *sc = (struct gem_softc *)xsc; 439 440 if (error != 0) 441 return; 442 if (nsegs != 1) { 443 /* can't happen... */ 444 panic("gem_cddma_callback: bad control buffer segment count"); 445 } 446 sc->sc_cddma = segs[0].ds_addr; 447 } 448 449 static void 450 gem_txdma_callback(xsc, segs, nsegs, totsz, error) 451 void *xsc; 452 bus_dma_segment_t *segs; 453 int nsegs; 454 bus_size_t totsz; 455 int error; 456 { 457 struct gem_txdma *txd = (struct gem_txdma *)xsc; 458 struct gem_softc *sc = txd->txd_sc; 459 struct gem_txsoft *txs = txd->txd_txs; 460 bus_size_t len = 0; 461 uint64_t flags = 0; 462 int seg, nexttx; 463 464 if (error != 0) 465 return; 466 /* 467 * Ensure we have enough descriptors free to describe 468 * the packet. Note, we always reserve one descriptor 469 * at the end of the ring as a termination point, to 470 * prevent wrap-around. 471 */ 472 if (nsegs > sc->sc_txfree - 1) { 473 txs->txs_ndescs = -1; 474 return; 475 } 476 txs->txs_ndescs = nsegs; 477 478 nexttx = txs->txs_firstdesc; 479 /* 480 * Initialize the transmit descriptors. 481 */ 482 for (seg = 0; seg < nsegs; 483 seg++, nexttx = GEM_NEXTTX(nexttx)) { 484 #ifdef GEM_DEBUG 485 CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len " 486 "%lx, addr %#lx (%#lx)", seg, nexttx, 487 segs[seg].ds_len, segs[seg].ds_addr, 488 GEM_DMA_WRITE(sc, segs[seg].ds_addr)); 489 #endif 490 491 if (segs[seg].ds_len == 0) 492 continue; 493 sc->sc_txdescs[nexttx].gd_addr = 494 GEM_DMA_WRITE(sc, segs[seg].ds_addr); 495 KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE, 496 ("gem_txdma_callback: segment size too large!")); 497 flags = segs[seg].ds_len & GEM_TD_BUFSIZE; 498 if (len == 0) { 499 #ifdef GEM_DEBUG 500 CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, " 501 "tx %d", seg, nexttx); 502 #endif 503 flags |= GEM_TD_START_OF_PACKET; 504 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 505 sc->sc_txwin = 0; 506 flags |= GEM_TD_INTERRUPT_ME; 507 } 508 } 509 if (len + segs[seg].ds_len == totsz) { 510 #ifdef GEM_DEBUG 511 CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, " 512 "tx %d", seg, nexttx); 513 #endif 514 flags |= GEM_TD_END_OF_PACKET; 515 } 516 sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags); 517 txs->txs_lastdesc = nexttx; 518 len += segs[seg].ds_len; 519 } 520 KASSERT((flags & GEM_TD_END_OF_PACKET) != 0, 521 ("gem_txdma_callback: missed end of packet!")); 522 } 523 524 static void 525 gem_tick(arg) 526 void *arg; 527 { 528 struct gem_softc *sc = arg; 529 530 mii_tick(sc->sc_mii); 531 532 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 533 } 534 535 static int 536 gem_bitwait(sc, r, clr, set) 537 struct gem_softc *sc; 538 bus_addr_t r; 539 u_int32_t clr; 540 u_int32_t set; 541 { 542 int i; 543 u_int32_t reg; 544 545 for (i = TRIES; i--; DELAY(100)) { 546 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 547 if ((r & clr) == 0 && (r & set) == set) 548 return (1); 549 } 550 return (0); 551 } 552 553 void 554 gem_reset(sc) 555 struct gem_softc *sc; 556 { 557 bus_space_tag_t t = sc->sc_bustag; 558 bus_space_handle_t h = sc->sc_h; 559 560 #ifdef GEM_DEBUG 561 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 562 #endif 563 gem_reset_rx(sc); 564 gem_reset_tx(sc); 565 566 /* Do a full reset */ 567 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 568 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 569 device_printf(sc->sc_dev, "cannot reset device\n"); 570 } 571 572 573 /* 574 * gem_rxdrain: 575 * 576 * Drain the receive queue. 577 */ 578 static void 579 gem_rxdrain(sc) 580 struct gem_softc *sc; 581 { 582 struct gem_rxsoft *rxs; 583 int i; 584 585 for (i = 0; i < GEM_NRXDESC; i++) { 586 rxs = &sc->sc_rxsoft[i]; 587 if (rxs->rxs_mbuf != NULL) { 588 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 589 BUS_DMASYNC_POSTREAD); 590 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 591 m_freem(rxs->rxs_mbuf); 592 rxs->rxs_mbuf = NULL; 593 } 594 } 595 } 596 597 /* 598 * Reset the whole thing. 599 */ 600 static void 601 gem_stop(ifp, disable) 602 struct ifnet *ifp; 603 int disable; 604 { 605 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 606 struct gem_txsoft *txs; 607 608 #ifdef GEM_DEBUG 609 CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev)); 610 #endif 611 612 callout_stop(&sc->sc_tick_ch); 613 614 /* XXX - Should we reset these instead? */ 615 gem_disable_tx(sc); 616 gem_disable_rx(sc); 617 618 /* 619 * Release any queued transmit buffers. 620 */ 621 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 622 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 623 if (txs->txs_ndescs != 0) { 624 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 625 BUS_DMASYNC_POSTWRITE); 626 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 627 if (txs->txs_mbuf != NULL) { 628 m_freem(txs->txs_mbuf); 629 txs->txs_mbuf = NULL; 630 } 631 } 632 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 633 } 634 635 if (disable) 636 gem_rxdrain(sc); 637 638 /* 639 * Mark the interface down and cancel the watchdog timer. 640 */ 641 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 642 ifp->if_timer = 0; 643 } 644 645 /* 646 * Reset the receiver 647 */ 648 int 649 gem_reset_rx(sc) 650 struct gem_softc *sc; 651 { 652 bus_space_tag_t t = sc->sc_bustag; 653 bus_space_handle_t h = sc->sc_h; 654 655 /* 656 * Resetting while DMA is in progress can cause a bus hang, so we 657 * disable DMA first. 658 */ 659 gem_disable_rx(sc); 660 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 661 /* Wait till it finishes */ 662 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 663 device_printf(sc->sc_dev, "cannot disable read dma\n"); 664 665 /* Wait 5ms extra. */ 666 DELAY(5000); 667 668 /* Finally, reset the ERX */ 669 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 670 /* Wait till it finishes */ 671 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 672 device_printf(sc->sc_dev, "cannot reset receiver\n"); 673 return (1); 674 } 675 return (0); 676 } 677 678 679 /* 680 * Reset the transmitter 681 */ 682 static int 683 gem_reset_tx(sc) 684 struct gem_softc *sc; 685 { 686 bus_space_tag_t t = sc->sc_bustag; 687 bus_space_handle_t h = sc->sc_h; 688 int i; 689 690 /* 691 * Resetting while DMA is in progress can cause a bus hang, so we 692 * disable DMA first. 693 */ 694 gem_disable_tx(sc); 695 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 696 /* Wait till it finishes */ 697 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 698 device_printf(sc->sc_dev, "cannot disable read dma\n"); 699 700 /* Wait 5ms extra. */ 701 DELAY(5000); 702 703 /* Finally, reset the ETX */ 704 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 705 /* Wait till it finishes */ 706 for (i = TRIES; i--; DELAY(100)) 707 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 708 break; 709 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 710 device_printf(sc->sc_dev, "cannot reset receiver\n"); 711 return (1); 712 } 713 return (0); 714 } 715 716 /* 717 * disable receiver. 718 */ 719 static int 720 gem_disable_rx(sc) 721 struct gem_softc *sc; 722 { 723 bus_space_tag_t t = sc->sc_bustag; 724 bus_space_handle_t h = sc->sc_h; 725 u_int32_t cfg; 726 727 /* Flip the enable bit */ 728 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 729 cfg &= ~GEM_MAC_RX_ENABLE; 730 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 731 732 /* Wait for it to finish */ 733 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 734 } 735 736 /* 737 * disable transmitter. 738 */ 739 static int 740 gem_disable_tx(sc) 741 struct gem_softc *sc; 742 { 743 bus_space_tag_t t = sc->sc_bustag; 744 bus_space_handle_t h = sc->sc_h; 745 u_int32_t cfg; 746 747 /* Flip the enable bit */ 748 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 749 cfg &= ~GEM_MAC_TX_ENABLE; 750 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 751 752 /* Wait for it to finish */ 753 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 754 } 755 756 /* 757 * Initialize interface. 758 */ 759 static int 760 gem_meminit(sc) 761 struct gem_softc *sc; 762 { 763 struct gem_rxsoft *rxs; 764 int i, error; 765 766 /* 767 * Initialize the transmit descriptor ring. 768 */ 769 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 770 for (i = 0; i < GEM_NTXDESC; i++) { 771 sc->sc_txdescs[i].gd_flags = 0; 772 sc->sc_txdescs[i].gd_addr = 0; 773 } 774 sc->sc_txfree = GEM_MAXTXFREE; 775 sc->sc_txnext = 0; 776 sc->sc_txwin = 0; 777 778 /* 779 * Initialize the receive descriptor and receive job 780 * descriptor rings. 781 */ 782 for (i = 0; i < GEM_NRXDESC; i++) { 783 rxs = &sc->sc_rxsoft[i]; 784 if (rxs->rxs_mbuf == NULL) { 785 if ((error = gem_add_rxbuf(sc, i)) != 0) { 786 device_printf(sc->sc_dev, "unable to " 787 "allocate or map rx buffer %d, error = " 788 "%d\n", i, error); 789 /* 790 * XXX Should attempt to run with fewer receive 791 * XXX buffers instead of just failing. 792 */ 793 gem_rxdrain(sc); 794 return (1); 795 } 796 } else 797 GEM_INIT_RXDESC(sc, i); 798 } 799 sc->sc_rxptr = 0; 800 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 801 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 802 803 return (0); 804 } 805 806 static int 807 gem_ringsize(sz) 808 int sz; 809 { 810 int v = 0; 811 812 switch (sz) { 813 case 32: 814 v = GEM_RING_SZ_32; 815 break; 816 case 64: 817 v = GEM_RING_SZ_64; 818 break; 819 case 128: 820 v = GEM_RING_SZ_128; 821 break; 822 case 256: 823 v = GEM_RING_SZ_256; 824 break; 825 case 512: 826 v = GEM_RING_SZ_512; 827 break; 828 case 1024: 829 v = GEM_RING_SZ_1024; 830 break; 831 case 2048: 832 v = GEM_RING_SZ_2048; 833 break; 834 case 4096: 835 v = GEM_RING_SZ_4096; 836 break; 837 case 8192: 838 v = GEM_RING_SZ_8192; 839 break; 840 default: 841 printf("gem: invalid Receive Descriptor ring size\n"); 842 break; 843 } 844 return (v); 845 } 846 847 static void 848 gem_init(xsc) 849 void *xsc; 850 { 851 struct gem_softc *sc = (struct gem_softc *)xsc; 852 853 GEM_LOCK(sc); 854 gem_init_locked(sc); 855 GEM_UNLOCK(sc); 856 } 857 858 /* 859 * Initialization of interface; set up initialization block 860 * and transmit/receive descriptor rings. 861 */ 862 static void 863 gem_init_locked(sc) 864 struct gem_softc *sc; 865 { 866 struct ifnet *ifp = sc->sc_ifp; 867 bus_space_tag_t t = sc->sc_bustag; 868 bus_space_handle_t h = sc->sc_h; 869 u_int32_t v; 870 871 GEM_LOCK_ASSERT(sc, MA_OWNED); 872 873 #ifdef GEM_DEBUG 874 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 875 #endif 876 /* 877 * Initialization sequence. The numbered steps below correspond 878 * to the sequence outlined in section 6.3.5.1 in the Ethernet 879 * Channel Engine manual (part of the PCIO manual). 880 * See also the STP2002-STQ document from Sun Microsystems. 881 */ 882 883 /* step 1 & 2. Reset the Ethernet Channel */ 884 gem_stop(sc->sc_ifp, 0); 885 gem_reset(sc); 886 #ifdef GEM_DEBUG 887 CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev)); 888 #endif 889 890 /* Re-initialize the MIF */ 891 gem_mifinit(sc); 892 893 /* step 3. Setup data structures in host memory */ 894 gem_meminit(sc); 895 896 /* step 4. TX MAC registers & counters */ 897 gem_init_regs(sc); 898 /* XXX: VLAN code from NetBSD temporarily removed. */ 899 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 900 (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 901 902 /* step 5. RX MAC registers & counters */ 903 gem_setladrf(sc); 904 905 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 906 /* NOTE: we use only 32-bit DMA addresses here. */ 907 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 908 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 909 910 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 911 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 912 #ifdef GEM_DEBUG 913 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 914 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 915 #endif 916 917 /* step 8. Global Configuration & Interrupt Mask */ 918 bus_space_write_4(t, h, GEM_INTMASK, 919 ~(GEM_INTR_TX_INTME| 920 GEM_INTR_TX_EMPTY| 921 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 922 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 923 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 924 GEM_INTR_BERR)); 925 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 926 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 927 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 928 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 929 930 /* step 9. ETX Configuration: use mostly default values */ 931 932 /* Enable DMA */ 933 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 934 bus_space_write_4(t, h, GEM_TX_CONFIG, 935 v|GEM_TX_CONFIG_TXDMA_EN| 936 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 937 938 /* step 10. ERX Configuration */ 939 940 /* Encode Receive Descriptor ring size: four possible values */ 941 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 942 943 /* Enable DMA */ 944 bus_space_write_4(t, h, GEM_RX_CONFIG, 945 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 946 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 947 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 948 /* 949 * The following value is for an OFF Threshold of about 3/4 full 950 * and an ON Threshold of 1/4 full. 951 */ 952 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 953 (3 * sc->sc_rxfifosize / 256) | 954 ( (sc->sc_rxfifosize / 256) << 12)); 955 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 956 957 /* step 11. Configure Media */ 958 GEM_UNLOCK(sc); 959 mii_mediachg(sc->sc_mii); 960 GEM_LOCK(sc); 961 962 /* step 12. RX_MAC Configuration Register */ 963 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 964 v |= GEM_MAC_RX_ENABLE; 965 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 966 967 /* step 14. Issue Transmit Pending command */ 968 969 /* step 15. Give the reciever a swift kick */ 970 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 971 972 /* Start the one second timer. */ 973 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 974 975 ifp->if_drv_flags |= IFF_DRV_RUNNING; 976 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 977 ifp->if_timer = 0; 978 sc->sc_ifflags = ifp->if_flags; 979 } 980 981 static int 982 gem_load_txmbuf(sc, m0) 983 struct gem_softc *sc; 984 struct mbuf *m0; 985 { 986 struct gem_txdma txd; 987 struct gem_txsoft *txs; 988 int error; 989 990 /* Get a work queue entry. */ 991 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 992 /* Ran out of descriptors. */ 993 return (-1); 994 } 995 txd.txd_sc = sc; 996 txd.txd_txs = txs; 997 txs->txs_firstdesc = sc->sc_txnext; 998 error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0, 999 gem_txdma_callback, &txd, BUS_DMA_NOWAIT); 1000 if (error != 0) 1001 goto fail; 1002 if (txs->txs_ndescs == -1) { 1003 error = -1; 1004 goto fail; 1005 } 1006 1007 /* Sync the DMA map. */ 1008 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1009 BUS_DMASYNC_PREWRITE); 1010 1011 #ifdef GEM_DEBUG 1012 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, " 1013 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc, 1014 txs->txs_ndescs); 1015 #endif 1016 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1017 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1018 txs->txs_mbuf = m0; 1019 1020 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1021 sc->sc_txfree -= txs->txs_ndescs; 1022 return (0); 1023 1024 fail: 1025 #ifdef GEM_DEBUG 1026 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error); 1027 #endif 1028 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1029 return (error); 1030 } 1031 1032 static void 1033 gem_init_regs(sc) 1034 struct gem_softc *sc; 1035 { 1036 bus_space_tag_t t = sc->sc_bustag; 1037 bus_space_handle_t h = sc->sc_h; 1038 const u_char *laddr = IFP2ENADDR(sc->sc_ifp); 1039 u_int32_t v; 1040 1041 /* These regs are not cleared on reset */ 1042 if (!sc->sc_inited) { 1043 1044 /* Wooo. Magic values. */ 1045 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 1046 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 1047 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 1048 1049 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1050 /* Max frame and max burst size */ 1051 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1052 ETHER_MAX_LEN | (0x2000<<16)); 1053 1054 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 1055 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 1056 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1057 /* Dunno.... */ 1058 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1059 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1060 ((laddr[5]<<8)|laddr[4])&0x3ff); 1061 1062 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1063 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1064 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1065 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1066 1067 /* MAC control addr set to 01:80:c2:00:00:01 */ 1068 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1069 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1070 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1071 1072 /* MAC filter addr set to 0:0:0:0:0:0 */ 1073 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1074 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1075 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1076 1077 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1078 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1079 1080 sc->sc_inited = 1; 1081 } 1082 1083 /* Counters need to be zeroed */ 1084 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1085 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1086 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1087 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1088 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1089 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1090 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1091 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1092 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1093 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1094 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1095 1096 /* Un-pause stuff */ 1097 #if 0 1098 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1099 #else 1100 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 1101 #endif 1102 1103 /* 1104 * Set the station address. 1105 */ 1106 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1107 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1108 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1109 1110 /* 1111 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1112 */ 1113 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1114 v = GEM_MAC_XIF_TX_MII_ENA; 1115 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1116 v |= GEM_MAC_XIF_FDPLX_LED; 1117 if (sc->sc_flags & GEM_GIGABIT) 1118 v |= GEM_MAC_XIF_GMII_MODE; 1119 } 1120 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1121 } 1122 1123 static void 1124 gem_start(ifp) 1125 struct ifnet *ifp; 1126 { 1127 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1128 1129 GEM_LOCK(sc); 1130 gem_start_locked(ifp); 1131 GEM_UNLOCK(sc); 1132 } 1133 1134 static void 1135 gem_start_locked(ifp) 1136 struct ifnet *ifp; 1137 { 1138 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1139 struct mbuf *m0 = NULL; 1140 int firsttx, ntx = 0, ofree, txmfail; 1141 1142 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1143 IFF_DRV_RUNNING) 1144 return; 1145 1146 /* 1147 * Remember the previous number of free descriptors and 1148 * the first descriptor we'll use. 1149 */ 1150 ofree = sc->sc_txfree; 1151 firsttx = sc->sc_txnext; 1152 1153 #ifdef GEM_DEBUG 1154 CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d", 1155 device_get_name(sc->sc_dev), ofree, firsttx); 1156 #endif 1157 1158 /* 1159 * Loop through the send queue, setting up transmit descriptors 1160 * until we drain the queue, or use up all available transmit 1161 * descriptors. 1162 */ 1163 txmfail = 0; 1164 do { 1165 /* 1166 * Grab a packet off the queue. 1167 */ 1168 IF_DEQUEUE(&ifp->if_snd, m0); 1169 if (m0 == NULL) 1170 break; 1171 1172 txmfail = gem_load_txmbuf(sc, m0); 1173 if (txmfail > 0) { 1174 /* Drop the mbuf and complain. */ 1175 printf("gem_start: error %d while loading mbuf dma " 1176 "map\n", txmfail); 1177 continue; 1178 } 1179 /* Not enough descriptors. */ 1180 if (txmfail == -1) { 1181 if (sc->sc_txfree == GEM_MAXTXFREE) 1182 panic("gem_start: mbuf chain too long!"); 1183 IF_PREPEND(&ifp->if_snd, m0); 1184 break; 1185 } 1186 1187 ntx++; 1188 /* Kick the transmitter. */ 1189 #ifdef GEM_DEBUG 1190 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d", 1191 device_get_name(sc->sc_dev), sc->sc_txnext); 1192 #endif 1193 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1194 sc->sc_txnext); 1195 1196 if (ifp->if_bpf != NULL) 1197 bpf_mtap(ifp->if_bpf, m0); 1198 } while (1); 1199 1200 if (txmfail == -1 || sc->sc_txfree == 0) { 1201 /* No more slots left; notify upper layer. */ 1202 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1203 } 1204 1205 if (ntx > 0) { 1206 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1207 1208 #ifdef GEM_DEBUG 1209 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1210 device_get_name(sc->sc_dev), firsttx); 1211 #endif 1212 1213 /* Set a watchdog timer in case the chip flakes out. */ 1214 ifp->if_timer = 5; 1215 #ifdef GEM_DEBUG 1216 CTR2(KTR_GEM, "%s: gem_start: watchdog %d", 1217 device_get_name(sc->sc_dev), ifp->if_timer); 1218 #endif 1219 } 1220 } 1221 1222 /* 1223 * Transmit interrupt. 1224 */ 1225 static void 1226 gem_tint(sc) 1227 struct gem_softc *sc; 1228 { 1229 struct ifnet *ifp = sc->sc_ifp; 1230 bus_space_tag_t t = sc->sc_bustag; 1231 bus_space_handle_t mac = sc->sc_h; 1232 struct gem_txsoft *txs; 1233 int txlast; 1234 int progress = 0; 1235 1236 1237 #ifdef GEM_DEBUG 1238 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 1239 #endif 1240 1241 /* 1242 * Unload collision counters 1243 */ 1244 ifp->if_collisions += 1245 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1246 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1247 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1248 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1249 1250 /* 1251 * then clear the hardware counters. 1252 */ 1253 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1254 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1255 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1256 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1257 1258 /* 1259 * Go through our Tx list and free mbufs for those 1260 * frames that have been transmitted. 1261 */ 1262 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1263 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1264 1265 #ifdef GEM_DEBUG 1266 if (ifp->if_flags & IFF_DEBUG) { 1267 int i; 1268 printf(" txsoft %p transmit chain:\n", txs); 1269 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1270 printf("descriptor %d: ", i); 1271 printf("gd_flags: 0x%016llx\t", (long long) 1272 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1273 printf("gd_addr: 0x%016llx\n", (long long) 1274 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1275 if (i == txs->txs_lastdesc) 1276 break; 1277 } 1278 } 1279 #endif 1280 1281 /* 1282 * In theory, we could harveast some descriptors before 1283 * the ring is empty, but that's a bit complicated. 1284 * 1285 * GEM_TX_COMPLETION points to the last descriptor 1286 * processed +1. 1287 */ 1288 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1289 #ifdef GEM_DEBUG 1290 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 1291 "txs->txs_lastdesc = %d, txlast = %d", 1292 txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1293 #endif 1294 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1295 if ((txlast >= txs->txs_firstdesc) && 1296 (txlast <= txs->txs_lastdesc)) 1297 break; 1298 } else { 1299 /* Ick -- this command wraps */ 1300 if ((txlast >= txs->txs_firstdesc) || 1301 (txlast <= txs->txs_lastdesc)) 1302 break; 1303 } 1304 1305 #ifdef GEM_DEBUG 1306 CTR0(KTR_GEM, "gem_tint: releasing a desc"); 1307 #endif 1308 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1309 1310 sc->sc_txfree += txs->txs_ndescs; 1311 1312 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1313 BUS_DMASYNC_POSTWRITE); 1314 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1315 if (txs->txs_mbuf != NULL) { 1316 m_freem(txs->txs_mbuf); 1317 txs->txs_mbuf = NULL; 1318 } 1319 1320 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1321 1322 ifp->if_opackets++; 1323 progress = 1; 1324 } 1325 1326 #ifdef GEM_DEBUG 1327 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 1328 "GEM_TX_DATA_PTR %llx " 1329 "GEM_TX_COMPLETION %x", 1330 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1331 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1332 GEM_TX_DATA_PTR_HI) << 32) | 1333 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1334 GEM_TX_DATA_PTR_LO), 1335 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION)); 1336 #endif 1337 1338 if (progress) { 1339 if (sc->sc_txfree == GEM_NTXDESC - 1) 1340 sc->sc_txwin = 0; 1341 1342 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */ 1343 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1344 gem_start_locked(ifp); 1345 1346 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1347 ifp->if_timer = 0; 1348 } 1349 1350 #ifdef GEM_DEBUG 1351 CTR2(KTR_GEM, "%s: gem_tint: watchdog %d", 1352 device_get_name(sc->sc_dev), ifp->if_timer); 1353 #endif 1354 } 1355 1356 #ifdef GEM_RINT_TIMEOUT 1357 static void 1358 gem_rint_timeout(arg) 1359 void *arg; 1360 { 1361 struct gem_softc *sc = (struct gem_softc *)arg; 1362 1363 GEM_LOCK(sc); 1364 gem_rint(sc); 1365 GEM_UNLOCK(sc); 1366 } 1367 #endif 1368 1369 /* 1370 * Receive interrupt. 1371 */ 1372 static void 1373 gem_rint(sc) 1374 struct gem_softc *sc; 1375 { 1376 struct ifnet *ifp = sc->sc_ifp; 1377 bus_space_tag_t t = sc->sc_bustag; 1378 bus_space_handle_t h = sc->sc_h; 1379 struct gem_rxsoft *rxs; 1380 struct mbuf *m; 1381 u_int64_t rxstat; 1382 u_int32_t rxcomp; 1383 int i, len, progress = 0; 1384 1385 #ifdef GEM_RINT_TIMEOUT 1386 callout_stop(&sc->sc_rx_ch); 1387 #endif 1388 #ifdef GEM_DEBUG 1389 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 1390 #endif 1391 1392 /* 1393 * Read the completion register once. This limits 1394 * how long the following loop can execute. 1395 */ 1396 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1397 1398 #ifdef GEM_DEBUG 1399 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 1400 sc->sc_rxptr, rxcomp); 1401 #endif 1402 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1403 for (i = sc->sc_rxptr; i != rxcomp; 1404 i = GEM_NEXTRX(i)) { 1405 rxs = &sc->sc_rxsoft[i]; 1406 1407 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1408 1409 if (rxstat & GEM_RD_OWN) { 1410 #ifdef GEM_RINT_TIMEOUT 1411 /* 1412 * The descriptor is still marked as owned, although 1413 * it is supposed to have completed. This has been 1414 * observed on some machines. Just exiting here 1415 * might leave the packet sitting around until another 1416 * one arrives to trigger a new interrupt, which is 1417 * generally undesirable, so set up a timeout. 1418 */ 1419 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1420 gem_rint_timeout, sc); 1421 #endif 1422 break; 1423 } 1424 1425 progress++; 1426 ifp->if_ipackets++; 1427 1428 if (rxstat & GEM_RD_BAD_CRC) { 1429 ifp->if_ierrors++; 1430 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1431 GEM_INIT_RXDESC(sc, i); 1432 continue; 1433 } 1434 1435 #ifdef GEM_DEBUG 1436 if (ifp->if_flags & IFF_DEBUG) { 1437 printf(" rxsoft %p descriptor %d: ", rxs, i); 1438 printf("gd_flags: 0x%016llx\t", (long long) 1439 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1440 printf("gd_addr: 0x%016llx\n", (long long) 1441 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1442 } 1443 #endif 1444 1445 /* 1446 * No errors; receive the packet. Note the Gem 1447 * includes the CRC with every packet. 1448 */ 1449 len = GEM_RD_BUFLEN(rxstat); 1450 1451 /* 1452 * Allocate a new mbuf cluster. If that fails, we are 1453 * out of memory, and must drop the packet and recycle 1454 * the buffer that's already attached to this descriptor. 1455 */ 1456 m = rxs->rxs_mbuf; 1457 if (gem_add_rxbuf(sc, i) != 0) { 1458 ifp->if_ierrors++; 1459 GEM_INIT_RXDESC(sc, i); 1460 continue; 1461 } 1462 m->m_data += 2; /* We're already off by two */ 1463 1464 m->m_pkthdr.rcvif = ifp; 1465 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN; 1466 1467 /* Pass it on. */ 1468 GEM_UNLOCK(sc); 1469 (*ifp->if_input)(ifp, m); 1470 GEM_LOCK(sc); 1471 } 1472 1473 if (progress) { 1474 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1475 /* Update the receive pointer. */ 1476 if (i == sc->sc_rxptr) { 1477 device_printf(sc->sc_dev, "rint: ring wrap\n"); 1478 } 1479 sc->sc_rxptr = i; 1480 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1481 } 1482 1483 #ifdef GEM_DEBUG 1484 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", 1485 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 1486 #endif 1487 } 1488 1489 1490 /* 1491 * gem_add_rxbuf: 1492 * 1493 * Add a receive buffer to the indicated descriptor. 1494 */ 1495 static int 1496 gem_add_rxbuf(sc, idx) 1497 struct gem_softc *sc; 1498 int idx; 1499 { 1500 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1501 struct mbuf *m; 1502 bus_dma_segment_t segs[1]; 1503 int error, nsegs; 1504 1505 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1506 if (m == NULL) 1507 return (ENOBUFS); 1508 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1509 1510 #ifdef GEM_DEBUG 1511 /* bzero the packet to check dma */ 1512 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1513 #endif 1514 1515 if (rxs->rxs_mbuf != NULL) { 1516 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1517 BUS_DMASYNC_POSTREAD); 1518 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1519 } 1520 1521 rxs->rxs_mbuf = m; 1522 1523 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1524 m, segs, &nsegs, BUS_DMA_NOWAIT); 1525 /* If nsegs is wrong then the stack is corrupt. */ 1526 KASSERT(nsegs == 1, ("Too many segments returned!")); 1527 if (error != 0) { 1528 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " 1529 "%d\n", idx, error); 1530 m_freem(m); 1531 return (ENOBUFS); 1532 } 1533 rxs->rxs_paddr = segs[0].ds_addr; 1534 1535 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1536 1537 GEM_INIT_RXDESC(sc, idx); 1538 1539 return (0); 1540 } 1541 1542 1543 static void 1544 gem_eint(sc, status) 1545 struct gem_softc *sc; 1546 u_int status; 1547 { 1548 1549 if ((status & GEM_INTR_MIF) != 0) { 1550 device_printf(sc->sc_dev, "XXXlink status changed\n"); 1551 return; 1552 } 1553 1554 device_printf(sc->sc_dev, "status=%x\n", status); 1555 } 1556 1557 1558 void 1559 gem_intr(v) 1560 void *v; 1561 { 1562 struct gem_softc *sc = (struct gem_softc *)v; 1563 bus_space_tag_t t = sc->sc_bustag; 1564 bus_space_handle_t seb = sc->sc_h; 1565 u_int32_t status; 1566 1567 GEM_LOCK(sc); 1568 status = bus_space_read_4(t, seb, GEM_STATUS); 1569 #ifdef GEM_DEBUG 1570 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 1571 device_get_name(sc->sc_dev), (status>>19), 1572 (u_int)status); 1573 #endif 1574 1575 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1576 gem_eint(sc, status); 1577 1578 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1579 gem_tint(sc); 1580 1581 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1582 gem_rint(sc); 1583 1584 /* We should eventually do more than just print out error stats. */ 1585 if (status & GEM_INTR_TX_MAC) { 1586 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1587 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1588 device_printf(sc->sc_dev, "MAC tx fault, status %x\n", 1589 txstat); 1590 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1591 gem_init_locked(sc); 1592 } 1593 if (status & GEM_INTR_RX_MAC) { 1594 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1595 if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1596 device_printf(sc->sc_dev, "MAC rx fault, status %x\n", 1597 rxstat); 1598 if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0) 1599 gem_init_locked(sc); 1600 } 1601 GEM_UNLOCK(sc); 1602 } 1603 1604 1605 static void 1606 gem_watchdog(ifp) 1607 struct ifnet *ifp; 1608 { 1609 struct gem_softc *sc = ifp->if_softc; 1610 1611 GEM_LOCK(sc); 1612 #ifdef GEM_DEBUG 1613 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1614 "GEM_MAC_RX_CONFIG %x", 1615 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1616 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1617 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)); 1618 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 1619 "GEM_MAC_TX_CONFIG %x", 1620 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 1621 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS), 1622 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 1623 #endif 1624 1625 device_printf(sc->sc_dev, "device timeout\n"); 1626 ++ifp->if_oerrors; 1627 1628 /* Try to get more packets going. */ 1629 gem_init_locked(sc); 1630 GEM_UNLOCK(sc); 1631 } 1632 1633 /* 1634 * Initialize the MII Management Interface 1635 */ 1636 static void 1637 gem_mifinit(sc) 1638 struct gem_softc *sc; 1639 { 1640 bus_space_tag_t t = sc->sc_bustag; 1641 bus_space_handle_t mif = sc->sc_h; 1642 1643 GEM_LOCK_ASSERT(sc, MA_OWNED); 1644 1645 /* Configure the MIF in frame mode */ 1646 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1647 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1648 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1649 } 1650 1651 /* 1652 * MII interface 1653 * 1654 * The GEM MII interface supports at least three different operating modes: 1655 * 1656 * Bitbang mode is implemented using data, clock and output enable registers. 1657 * 1658 * Frame mode is implemented by loading a complete frame into the frame 1659 * register and polling the valid bit for completion. 1660 * 1661 * Polling mode uses the frame register but completion is indicated by 1662 * an interrupt. 1663 * 1664 */ 1665 int 1666 gem_mii_readreg(dev, phy, reg) 1667 device_t dev; 1668 int phy, reg; 1669 { 1670 struct gem_softc *sc = device_get_softc(dev); 1671 bus_space_tag_t t = sc->sc_bustag; 1672 bus_space_handle_t mif = sc->sc_h; 1673 int n; 1674 u_int32_t v; 1675 1676 GEM_LOCK(sc); 1677 #ifdef GEM_DEBUG_PHY 1678 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1679 #endif 1680 1681 #if 0 1682 /* Select the desired PHY in the MIF configuration register */ 1683 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1684 /* Clear PHY select bit */ 1685 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1686 if (phy == GEM_PHYAD_EXTERNAL) 1687 /* Set PHY select bit to get at external device */ 1688 v |= GEM_MIF_CONFIG_PHY_SEL; 1689 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1690 #endif 1691 1692 /* Construct the frame command */ 1693 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1694 GEM_MIF_FRAME_READ; 1695 1696 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1697 for (n = 0; n < 100; n++) { 1698 DELAY(1); 1699 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1700 if (v & GEM_MIF_FRAME_TA0) { 1701 GEM_UNLOCK(sc); 1702 return (v & GEM_MIF_FRAME_DATA); 1703 } 1704 } 1705 1706 device_printf(sc->sc_dev, "mii_read timeout\n"); 1707 GEM_UNLOCK(sc); 1708 return (0); 1709 } 1710 1711 int 1712 gem_mii_writereg(dev, phy, reg, val) 1713 device_t dev; 1714 int phy, reg, val; 1715 { 1716 struct gem_softc *sc = device_get_softc(dev); 1717 bus_space_tag_t t = sc->sc_bustag; 1718 bus_space_handle_t mif = sc->sc_h; 1719 int n; 1720 u_int32_t v; 1721 1722 GEM_LOCK(sc); 1723 #ifdef GEM_DEBUG_PHY 1724 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 1725 #endif 1726 1727 #if 0 1728 /* Select the desired PHY in the MIF configuration register */ 1729 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1730 /* Clear PHY select bit */ 1731 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1732 if (phy == GEM_PHYAD_EXTERNAL) 1733 /* Set PHY select bit to get at external device */ 1734 v |= GEM_MIF_CONFIG_PHY_SEL; 1735 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1736 #endif 1737 /* Construct the frame command */ 1738 v = GEM_MIF_FRAME_WRITE | 1739 (phy << GEM_MIF_PHY_SHIFT) | 1740 (reg << GEM_MIF_REG_SHIFT) | 1741 (val & GEM_MIF_FRAME_DATA); 1742 1743 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1744 for (n = 0; n < 100; n++) { 1745 DELAY(1); 1746 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1747 if (v & GEM_MIF_FRAME_TA0) { 1748 GEM_UNLOCK(sc); 1749 return (1); 1750 } 1751 } 1752 1753 device_printf(sc->sc_dev, "mii_write timeout\n"); 1754 GEM_UNLOCK(sc); 1755 return (0); 1756 } 1757 1758 void 1759 gem_mii_statchg(dev) 1760 device_t dev; 1761 { 1762 struct gem_softc *sc = device_get_softc(dev); 1763 #ifdef GEM_DEBUG 1764 int instance; 1765 #endif 1766 bus_space_tag_t t = sc->sc_bustag; 1767 bus_space_handle_t mac = sc->sc_h; 1768 u_int32_t v; 1769 1770 GEM_LOCK(sc); 1771 #ifdef GEM_DEBUG 1772 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 1773 if (sc->sc_debug) 1774 printf("gem_mii_statchg: status change: phy = %d\n", 1775 sc->sc_phys[instance]); 1776 #endif 1777 1778 /* Set tx full duplex options */ 1779 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1780 DELAY(10000); /* reg must be cleared and delay before changing. */ 1781 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1782 GEM_MAC_TX_ENABLE; 1783 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 1784 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1785 } 1786 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1787 1788 /* XIF Configuration */ 1789 v = GEM_MAC_XIF_LINK_LED; 1790 v |= GEM_MAC_XIF_TX_MII_ENA; 1791 1792 /* If an external transceiver is connected, enable its MII drivers */ 1793 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1794 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1795 /* External MII needs echo disable if half duplex. */ 1796 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 1797 /* turn on full duplex LED */ 1798 v |= GEM_MAC_XIF_FDPLX_LED; 1799 else 1800 /* half duplex -- disable echo */ 1801 v |= GEM_MAC_XIF_ECHO_DISABL; 1802 1803 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T) 1804 v |= GEM_MAC_XIF_GMII_MODE; 1805 else 1806 v &= ~GEM_MAC_XIF_GMII_MODE; 1807 } else { 1808 /* Internal MII needs buf enable */ 1809 v |= GEM_MAC_XIF_MII_BUF_ENA; 1810 } 1811 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1812 GEM_UNLOCK(sc); 1813 } 1814 1815 int 1816 gem_mediachange(ifp) 1817 struct ifnet *ifp; 1818 { 1819 struct gem_softc *sc = ifp->if_softc; 1820 1821 /* XXX Add support for serial media. */ 1822 1823 return (mii_mediachg(sc->sc_mii)); 1824 } 1825 1826 void 1827 gem_mediastatus(ifp, ifmr) 1828 struct ifnet *ifp; 1829 struct ifmediareq *ifmr; 1830 { 1831 struct gem_softc *sc = ifp->if_softc; 1832 1833 GEM_LOCK(sc); 1834 if ((ifp->if_flags & IFF_UP) == 0) { 1835 GEM_UNLOCK(sc); 1836 return; 1837 } 1838 1839 GEM_UNLOCK(sc); 1840 mii_pollstat(sc->sc_mii); 1841 GEM_LOCK(sc); 1842 ifmr->ifm_active = sc->sc_mii->mii_media_active; 1843 ifmr->ifm_status = sc->sc_mii->mii_media_status; 1844 GEM_UNLOCK(sc); 1845 } 1846 1847 /* 1848 * Process an ioctl request. 1849 */ 1850 static int 1851 gem_ioctl(ifp, cmd, data) 1852 struct ifnet *ifp; 1853 u_long cmd; 1854 caddr_t data; 1855 { 1856 struct gem_softc *sc = ifp->if_softc; 1857 struct ifreq *ifr = (struct ifreq *)data; 1858 int error = 0; 1859 1860 GEM_LOCK(sc); 1861 1862 switch (cmd) { 1863 case SIOCSIFADDR: 1864 case SIOCGIFADDR: 1865 case SIOCSIFMTU: 1866 GEM_UNLOCK(sc); 1867 error = ether_ioctl(ifp, cmd, data); 1868 GEM_LOCK(sc); 1869 break; 1870 case SIOCSIFFLAGS: 1871 if (ifp->if_flags & IFF_UP) { 1872 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC) 1873 gem_setladrf(sc); 1874 else 1875 gem_init_locked(sc); 1876 } else { 1877 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1878 gem_stop(ifp, 0); 1879 } 1880 sc->sc_ifflags = ifp->if_flags; 1881 error = 0; 1882 break; 1883 case SIOCADDMULTI: 1884 case SIOCDELMULTI: 1885 gem_setladrf(sc); 1886 error = 0; 1887 break; 1888 case SIOCGIFMEDIA: 1889 case SIOCSIFMEDIA: 1890 GEM_UNLOCK(sc); 1891 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 1892 GEM_LOCK(sc); 1893 break; 1894 default: 1895 error = ENOTTY; 1896 break; 1897 } 1898 1899 /* Try to get things going again */ 1900 if (ifp->if_flags & IFF_UP) 1901 gem_start_locked(ifp); 1902 GEM_UNLOCK(sc); 1903 return (error); 1904 } 1905 1906 /* 1907 * Set up the logical address filter. 1908 */ 1909 static void 1910 gem_setladrf(sc) 1911 struct gem_softc *sc; 1912 { 1913 struct ifnet *ifp = sc->sc_ifp; 1914 struct ifmultiaddr *inm; 1915 bus_space_tag_t t = sc->sc_bustag; 1916 bus_space_handle_t h = sc->sc_h; 1917 u_int32_t crc; 1918 u_int32_t hash[16]; 1919 u_int32_t v; 1920 int i; 1921 1922 GEM_LOCK_ASSERT(sc, MA_OWNED); 1923 1924 /* Get current RX configuration */ 1925 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1926 1927 /* 1928 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1929 * and hash filter. Depending on the case, the right bit will be 1930 * enabled. 1931 */ 1932 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1933 GEM_MAC_RX_PROMISC_GRP); 1934 1935 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1936 /* Turn on promiscuous mode */ 1937 v |= GEM_MAC_RX_PROMISCUOUS; 1938 goto chipit; 1939 } 1940 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 1941 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1942 ifp->if_flags |= IFF_ALLMULTI; 1943 v |= GEM_MAC_RX_PROMISC_GRP; 1944 goto chipit; 1945 } 1946 1947 /* 1948 * Set up multicast address filter by passing all multicast addresses 1949 * through a crc generator, and then using the high order 8 bits as an 1950 * index into the 256 bit logical address filter. The high order 4 1951 * bits selects the word, while the other 4 bits select the bit within 1952 * the word (where bit 0 is the MSB). 1953 */ 1954 1955 /* Clear hash table */ 1956 memset(hash, 0, sizeof(hash)); 1957 1958 IF_ADDR_LOCK(ifp); 1959 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 1960 if (inm->ifma_addr->sa_family != AF_LINK) 1961 continue; 1962 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1963 inm->ifma_addr), ETHER_ADDR_LEN); 1964 1965 /* Just want the 8 most significant bits. */ 1966 crc >>= 24; 1967 1968 /* Set the corresponding bit in the filter. */ 1969 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1970 } 1971 IF_ADDR_UNLOCK(ifp); 1972 1973 v |= GEM_MAC_RX_HASH_FILTER; 1974 ifp->if_flags &= ~IFF_ALLMULTI; 1975 1976 /* Now load the hash table into the chip (if we are using it) */ 1977 for (i = 0; i < 16; i++) { 1978 bus_space_write_4(t, h, 1979 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1980 hash[i]); 1981 } 1982 1983 chipit: 1984 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1985 } 1986