1 /* 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #if 0 37 #define GEM_DEBUG 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/callout.h> 44 #include <sys/endian.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #include <machine/bus.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/mii/miivar.h> 62 63 #include <gem/if_gemreg.h> 64 #include <gem/if_gemvar.h> 65 66 #define TRIES 10000 67 68 static void gem_start(struct ifnet *); 69 static void gem_stop(struct ifnet *, int); 70 static int gem_ioctl(struct ifnet *, u_long, caddr_t); 71 static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); 72 static void gem_rxdma_callback(void *, bus_dma_segment_t *, int, 73 bus_size_t, int); 74 static void gem_txdma_callback(void *, bus_dma_segment_t *, int, 75 bus_size_t, int); 76 static void gem_tick(void *); 77 static void gem_watchdog(struct ifnet *); 78 static void gem_init(void *); 79 static void gem_init_regs(struct gem_softc *sc); 80 static int gem_ringsize(int sz); 81 static int gem_meminit(struct gem_softc *); 82 static int gem_load_txmbuf(struct gem_softc *, struct mbuf *); 83 static void gem_mifinit(struct gem_softc *); 84 static int gem_bitwait(struct gem_softc *sc, bus_addr_t r, 85 u_int32_t clr, u_int32_t set); 86 static int gem_reset_rx(struct gem_softc *); 87 static int gem_reset_tx(struct gem_softc *); 88 static int gem_disable_rx(struct gem_softc *); 89 static int gem_disable_tx(struct gem_softc *); 90 static void gem_rxdrain(struct gem_softc *); 91 static int gem_add_rxbuf(struct gem_softc *, int); 92 static void gem_setladrf(struct gem_softc *); 93 94 struct mbuf *gem_get(struct gem_softc *, int, int); 95 static void gem_eint(struct gem_softc *, u_int); 96 static void gem_rint(struct gem_softc *); 97 #if 0 98 static void gem_rint_timeout(void *); 99 #endif 100 static void gem_tint(struct gem_softc *); 101 #ifdef notyet 102 static void gem_power(int, void *); 103 #endif 104 105 devclass_t gem_devclass; 106 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 107 MODULE_DEPEND(gem, miibus, 1, 1, 1); 108 109 #ifdef GEM_DEBUG 110 #include <sys/ktr.h> 111 #define KTR_GEM KTR_CT2 112 #endif 113 114 #define GEM_NSEGS GEM_NTXDESC 115 116 /* 117 * gem_attach: 118 * 119 * Attach a Gem interface to the system. 120 */ 121 int 122 gem_attach(sc) 123 struct gem_softc *sc; 124 { 125 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 126 struct mii_softc *child; 127 int i, error; 128 u_int32_t v; 129 130 /* Make sure the chip is stopped. */ 131 ifp->if_softc = sc; 132 gem_reset(sc); 133 134 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 135 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS, 136 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->sc_pdmatag); 137 if (error) 138 return (error); 139 140 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 141 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE, 142 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL, 143 &sc->sc_rdmatag); 144 if (error) 145 goto fail_ptag; 146 147 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 148 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 149 GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT, 150 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 151 if (error) 152 goto fail_rtag; 153 154 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 155 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 156 sizeof(struct gem_control_data), 1, 157 sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW, 158 busdma_lock_mutex, &Giant, &sc->sc_cdmatag); 159 if (error) 160 goto fail_ttag; 161 162 /* 163 * Allocate the control data structures, and create and load the 164 * DMA map for it. 165 */ 166 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 167 (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) { 168 device_printf(sc->sc_dev, "unable to allocate control data," 169 " error = %d\n", error); 170 goto fail_ctag; 171 } 172 173 sc->sc_cddma = 0; 174 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 175 sc->sc_control_data, sizeof(struct gem_control_data), 176 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 177 device_printf(sc->sc_dev, "unable to load control data DMA " 178 "map, error = %d\n", error); 179 goto fail_cmem; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 STAILQ_INIT(&sc->sc_txfreeq); 186 STAILQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 error = ENOMEM; 192 for (i = 0; i < GEM_TXQUEUELEN; i++) { 193 struct gem_txsoft *txs; 194 195 txs = &sc->sc_txsoft[i]; 196 txs->txs_mbuf = NULL; 197 txs->txs_ndescs = 0; 198 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 199 &txs->txs_dmamap)) != 0) { 200 device_printf(sc->sc_dev, "unable to create tx DMA map " 201 "%d, error = %d\n", i, error); 202 goto fail_txd; 203 } 204 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 205 } 206 207 /* 208 * Create the receive buffer DMA maps. 209 */ 210 for (i = 0; i < GEM_NRXDESC; i++) { 211 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 212 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 213 device_printf(sc->sc_dev, "unable to create rx DMA map " 214 "%d, error = %d\n", i, error); 215 goto fail_rxd; 216 } 217 sc->sc_rxsoft[i].rxs_mbuf = NULL; 218 } 219 220 221 gem_mifinit(sc); 222 223 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange, 224 gem_mediastatus)) != 0) { 225 device_printf(sc->sc_dev, "phy probe failed: %d\n", error); 226 goto fail_rxd; 227 } 228 sc->sc_mii = device_get_softc(sc->sc_miibus); 229 230 /* 231 * From this point forward, the attachment cannot fail. A failure 232 * before this point releases all resources that may have been 233 * allocated. 234 */ 235 236 /* Announce ourselves. */ 237 device_printf(sc->sc_dev, "Ethernet address:"); 238 for (i = 0; i < 6; i++) 239 printf("%c%02x", i > 0 ? ':' : ' ', sc->sc_arpcom.ac_enaddr[i]); 240 241 /* Get RX FIFO size */ 242 sc->sc_rxfifosize = 64 * 243 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 244 printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 245 246 /* Get TX FIFO size */ 247 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 248 printf(", %uKB TX fifo\n", v / 16); 249 250 /* Initialize ifnet structure. */ 251 ifp->if_softc = sc; 252 ifp->if_unit = device_get_unit(sc->sc_dev); 253 ifp->if_name = "gem"; 254 ifp->if_mtu = ETHERMTU; 255 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 256 ifp->if_start = gem_start; 257 ifp->if_ioctl = gem_ioctl; 258 ifp->if_watchdog = gem_watchdog; 259 ifp->if_init = gem_init; 260 ifp->if_output = ether_output; 261 ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN; 262 /* 263 * Walk along the list of attached MII devices and 264 * establish an `MII instance' to `phy number' 265 * mapping. We'll use this mapping in media change 266 * requests to determine which phy to use to program 267 * the MIF configuration register. 268 */ 269 for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL; 270 child = LIST_NEXT(child, mii_list)) { 271 /* 272 * Note: we support just two PHYs: the built-in 273 * internal device and an external on the MII 274 * connector. 275 */ 276 if (child->mii_phy > 1 || child->mii_inst > 1) { 277 device_printf(sc->sc_dev, "cannot accomodate " 278 "MII device %s at phy %d, instance %d\n", 279 device_get_name(child->mii_dev), 280 child->mii_phy, child->mii_inst); 281 continue; 282 } 283 284 sc->sc_phys[child->mii_inst] = child->mii_phy; 285 } 286 287 /* 288 * Now select and activate the PHY we will use. 289 * 290 * The order of preference is External (MDI1), 291 * Internal (MDI0), Serial Link (no MII). 292 */ 293 if (sc->sc_phys[1]) { 294 #ifdef GEM_DEBUG 295 printf("using external phy\n"); 296 #endif 297 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 298 } else { 299 #ifdef GEM_DEBUG 300 printf("using internal phy\n"); 301 #endif 302 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 303 } 304 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 305 sc->sc_mif_config); 306 /* Attach the interface. */ 307 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr); 308 309 #if notyet 310 /* 311 * Add a suspend hook to make sure we come back up after a 312 * resume. 313 */ 314 sc->sc_powerhook = powerhook_establish(gem_power, sc); 315 if (sc->sc_powerhook == NULL) 316 device_printf(sc->sc_dev, "WARNING: unable to establish power " 317 "hook\n"); 318 #endif 319 320 callout_init(&sc->sc_tick_ch, 0); 321 callout_init(&sc->sc_rx_ch, 0); 322 return (0); 323 324 /* 325 * Free any resources we've allocated during the failed attach 326 * attempt. Do this in reverse order and fall through. 327 */ 328 fail_rxd: 329 for (i = 0; i < GEM_NRXDESC; i++) { 330 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 331 bus_dmamap_destroy(sc->sc_rdmatag, 332 sc->sc_rxsoft[i].rxs_dmamap); 333 } 334 fail_txd: 335 for (i = 0; i < GEM_TXQUEUELEN; i++) { 336 if (sc->sc_txsoft[i].txs_dmamap != NULL) 337 bus_dmamap_destroy(sc->sc_tdmatag, 338 sc->sc_txsoft[i].txs_dmamap); 339 } 340 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 341 fail_cmem: 342 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 343 sc->sc_cddmamap); 344 fail_ctag: 345 bus_dma_tag_destroy(sc->sc_cdmatag); 346 fail_ttag: 347 bus_dma_tag_destroy(sc->sc_tdmatag); 348 fail_rtag: 349 bus_dma_tag_destroy(sc->sc_rdmatag); 350 fail_ptag: 351 bus_dma_tag_destroy(sc->sc_pdmatag); 352 return (error); 353 } 354 355 void 356 gem_detach(sc) 357 struct gem_softc *sc; 358 { 359 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 360 int i; 361 362 ether_ifdetach(ifp); 363 gem_stop(ifp, 1); 364 device_delete_child(sc->sc_dev, sc->sc_miibus); 365 366 for (i = 0; i < GEM_NRXDESC; i++) { 367 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 368 bus_dmamap_destroy(sc->sc_rdmatag, 369 sc->sc_rxsoft[i].rxs_dmamap); 370 } 371 for (i = 0; i < GEM_TXQUEUELEN; i++) { 372 if (sc->sc_txsoft[i].txs_dmamap != NULL) 373 bus_dmamap_destroy(sc->sc_tdmatag, 374 sc->sc_txsoft[i].txs_dmamap); 375 } 376 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 377 GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE); 378 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 379 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 380 sc->sc_cddmamap); 381 bus_dma_tag_destroy(sc->sc_cdmatag); 382 bus_dma_tag_destroy(sc->sc_tdmatag); 383 bus_dma_tag_destroy(sc->sc_rdmatag); 384 bus_dma_tag_destroy(sc->sc_pdmatag); 385 } 386 387 void 388 gem_suspend(sc) 389 struct gem_softc *sc; 390 { 391 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 392 393 gem_stop(ifp, 0); 394 } 395 396 void 397 gem_resume(sc) 398 struct gem_softc *sc; 399 { 400 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 401 402 if (ifp->if_flags & IFF_UP) 403 gem_init(ifp); 404 } 405 406 static void 407 gem_cddma_callback(xsc, segs, nsegs, error) 408 void *xsc; 409 bus_dma_segment_t *segs; 410 int nsegs; 411 int error; 412 { 413 struct gem_softc *sc = (struct gem_softc *)xsc; 414 415 if (error != 0) 416 return; 417 if (nsegs != 1) { 418 /* can't happen... */ 419 panic("gem_cddma_callback: bad control buffer segment count"); 420 } 421 sc->sc_cddma = segs[0].ds_addr; 422 } 423 424 static void 425 gem_rxdma_callback(xsc, segs, nsegs, totsz, error) 426 void *xsc; 427 bus_dma_segment_t *segs; 428 int nsegs; 429 bus_size_t totsz; 430 int error; 431 { 432 struct gem_rxsoft *rxs = (struct gem_rxsoft *)xsc; 433 434 if (error != 0) 435 return; 436 KASSERT(nsegs == 1, ("gem_rxdma_callback: bad dma segment count")); 437 rxs->rxs_paddr = segs[0].ds_addr; 438 } 439 440 static void 441 gem_txdma_callback(xsc, segs, nsegs, totsz, error) 442 void *xsc; 443 bus_dma_segment_t *segs; 444 int nsegs; 445 bus_size_t totsz; 446 int error; 447 { 448 struct gem_txdma *txd = (struct gem_txdma *)xsc; 449 struct gem_softc *sc = txd->txd_sc; 450 struct gem_txsoft *txs = txd->txd_txs; 451 bus_size_t len = 0; 452 uint64_t flags = 0; 453 int seg, nexttx; 454 455 if (error != 0) 456 return; 457 /* 458 * Ensure we have enough descriptors free to describe 459 * the packet. Note, we always reserve one descriptor 460 * at the end of the ring as a termination point, to 461 * prevent wrap-around. 462 */ 463 if (nsegs > sc->sc_txfree - 1) { 464 txs->txs_ndescs = -1; 465 return; 466 } 467 txs->txs_ndescs = nsegs; 468 469 nexttx = txs->txs_firstdesc; 470 /* 471 * Initialize the transmit descriptors. 472 */ 473 for (seg = 0; seg < nsegs; 474 seg++, nexttx = GEM_NEXTTX(nexttx)) { 475 #ifdef GEM_DEBUG 476 CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len " 477 "%lx, addr %#lx (%#lx)", seg, nexttx, 478 segs[seg].ds_len, segs[seg].ds_addr, 479 GEM_DMA_WRITE(sc, segs[seg].ds_addr)); 480 #endif 481 482 if (segs[seg].ds_len == 0) 483 continue; 484 sc->sc_txdescs[nexttx].gd_addr = 485 GEM_DMA_WRITE(sc, segs[seg].ds_addr); 486 KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE, 487 ("gem_txdma_callback: segment size too large!")); 488 flags = segs[seg].ds_len & GEM_TD_BUFSIZE; 489 if (len == 0) { 490 #ifdef GEM_DEBUG 491 CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, " 492 "tx %d", seg, nexttx); 493 #endif 494 flags |= GEM_TD_START_OF_PACKET; 495 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 496 sc->sc_txwin = 0; 497 flags |= GEM_TD_INTERRUPT_ME; 498 } 499 } 500 if (len + segs[seg].ds_len == totsz) { 501 #ifdef GEM_DEBUG 502 CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, " 503 "tx %d", seg, nexttx); 504 #endif 505 flags |= GEM_TD_END_OF_PACKET; 506 } 507 sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags); 508 txs->txs_lastdesc = nexttx; 509 len += segs[seg].ds_len; 510 } 511 KASSERT((flags & GEM_TD_END_OF_PACKET) != 0, 512 ("gem_txdma_callback: missed end of packet!")); 513 } 514 515 static void 516 gem_tick(arg) 517 void *arg; 518 { 519 struct gem_softc *sc = arg; 520 int s; 521 522 s = splnet(); 523 mii_tick(sc->sc_mii); 524 splx(s); 525 526 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 527 } 528 529 static int 530 gem_bitwait(sc, r, clr, set) 531 struct gem_softc *sc; 532 bus_addr_t r; 533 u_int32_t clr; 534 u_int32_t set; 535 { 536 int i; 537 u_int32_t reg; 538 539 for (i = TRIES; i--; DELAY(100)) { 540 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 541 if ((r & clr) == 0 && (r & set) == set) 542 return (1); 543 } 544 return (0); 545 } 546 547 void 548 gem_reset(sc) 549 struct gem_softc *sc; 550 { 551 bus_space_tag_t t = sc->sc_bustag; 552 bus_space_handle_t h = sc->sc_h; 553 int s; 554 555 s = splnet(); 556 #ifdef GEM_DEBUG 557 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 558 #endif 559 gem_reset_rx(sc); 560 gem_reset_tx(sc); 561 562 /* Do a full reset */ 563 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 564 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 565 device_printf(sc->sc_dev, "cannot reset device\n"); 566 splx(s); 567 } 568 569 570 /* 571 * gem_rxdrain: 572 * 573 * Drain the receive queue. 574 */ 575 static void 576 gem_rxdrain(sc) 577 struct gem_softc *sc; 578 { 579 struct gem_rxsoft *rxs; 580 int i; 581 582 for (i = 0; i < GEM_NRXDESC; i++) { 583 rxs = &sc->sc_rxsoft[i]; 584 if (rxs->rxs_mbuf != NULL) { 585 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 586 BUS_DMASYNC_POSTREAD); 587 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 588 m_freem(rxs->rxs_mbuf); 589 rxs->rxs_mbuf = NULL; 590 } 591 } 592 } 593 594 /* 595 * Reset the whole thing. 596 */ 597 static void 598 gem_stop(ifp, disable) 599 struct ifnet *ifp; 600 int disable; 601 { 602 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 603 struct gem_txsoft *txs; 604 605 #ifdef GEM_DEBUG 606 CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev)); 607 #endif 608 609 callout_stop(&sc->sc_tick_ch); 610 611 /* XXX - Should we reset these instead? */ 612 gem_disable_tx(sc); 613 gem_disable_rx(sc); 614 615 /* 616 * Release any queued transmit buffers. 617 */ 618 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 619 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 620 if (txs->txs_ndescs != 0) { 621 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 622 BUS_DMASYNC_POSTWRITE); 623 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 624 if (txs->txs_mbuf != NULL) { 625 m_freem(txs->txs_mbuf); 626 txs->txs_mbuf = NULL; 627 } 628 } 629 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 630 } 631 632 if (disable) 633 gem_rxdrain(sc); 634 635 /* 636 * Mark the interface down and cancel the watchdog timer. 637 */ 638 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 639 ifp->if_timer = 0; 640 } 641 642 /* 643 * Reset the receiver 644 */ 645 int 646 gem_reset_rx(sc) 647 struct gem_softc *sc; 648 { 649 bus_space_tag_t t = sc->sc_bustag; 650 bus_space_handle_t h = sc->sc_h; 651 652 /* 653 * Resetting while DMA is in progress can cause a bus hang, so we 654 * disable DMA first. 655 */ 656 gem_disable_rx(sc); 657 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 658 /* Wait till it finishes */ 659 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 660 device_printf(sc->sc_dev, "cannot disable read dma\n"); 661 662 /* Wait 5ms extra. */ 663 DELAY(5000); 664 665 /* Finally, reset the ERX */ 666 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 667 /* Wait till it finishes */ 668 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 669 device_printf(sc->sc_dev, "cannot reset receiver\n"); 670 return (1); 671 } 672 return (0); 673 } 674 675 676 /* 677 * Reset the transmitter 678 */ 679 static int 680 gem_reset_tx(sc) 681 struct gem_softc *sc; 682 { 683 bus_space_tag_t t = sc->sc_bustag; 684 bus_space_handle_t h = sc->sc_h; 685 int i; 686 687 /* 688 * Resetting while DMA is in progress can cause a bus hang, so we 689 * disable DMA first. 690 */ 691 gem_disable_tx(sc); 692 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 693 /* Wait till it finishes */ 694 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 695 device_printf(sc->sc_dev, "cannot disable read dma\n"); 696 697 /* Wait 5ms extra. */ 698 DELAY(5000); 699 700 /* Finally, reset the ETX */ 701 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 702 /* Wait till it finishes */ 703 for (i = TRIES; i--; DELAY(100)) 704 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 705 break; 706 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 707 device_printf(sc->sc_dev, "cannot reset receiver\n"); 708 return (1); 709 } 710 return (0); 711 } 712 713 /* 714 * disable receiver. 715 */ 716 static int 717 gem_disable_rx(sc) 718 struct gem_softc *sc; 719 { 720 bus_space_tag_t t = sc->sc_bustag; 721 bus_space_handle_t h = sc->sc_h; 722 u_int32_t cfg; 723 724 /* Flip the enable bit */ 725 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 726 cfg &= ~GEM_MAC_RX_ENABLE; 727 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 728 729 /* Wait for it to finish */ 730 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 731 } 732 733 /* 734 * disable transmitter. 735 */ 736 static int 737 gem_disable_tx(sc) 738 struct gem_softc *sc; 739 { 740 bus_space_tag_t t = sc->sc_bustag; 741 bus_space_handle_t h = sc->sc_h; 742 u_int32_t cfg; 743 744 /* Flip the enable bit */ 745 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 746 cfg &= ~GEM_MAC_TX_ENABLE; 747 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 748 749 /* Wait for it to finish */ 750 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 751 } 752 753 /* 754 * Initialize interface. 755 */ 756 static int 757 gem_meminit(sc) 758 struct gem_softc *sc; 759 { 760 struct gem_rxsoft *rxs; 761 int i, error; 762 763 /* 764 * Initialize the transmit descriptor ring. 765 */ 766 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 767 for (i = 0; i < GEM_NTXDESC; i++) { 768 sc->sc_txdescs[i].gd_flags = 0; 769 sc->sc_txdescs[i].gd_addr = 0; 770 } 771 sc->sc_txfree = GEM_MAXTXFREE; 772 sc->sc_txnext = 0; 773 sc->sc_txwin = 0; 774 775 /* 776 * Initialize the receive descriptor and receive job 777 * descriptor rings. 778 */ 779 for (i = 0; i < GEM_NRXDESC; i++) { 780 rxs = &sc->sc_rxsoft[i]; 781 if (rxs->rxs_mbuf == NULL) { 782 if ((error = gem_add_rxbuf(sc, i)) != 0) { 783 device_printf(sc->sc_dev, "unable to " 784 "allocate or map rx buffer %d, error = " 785 "%d\n", i, error); 786 /* 787 * XXX Should attempt to run with fewer receive 788 * XXX buffers instead of just failing. 789 */ 790 gem_rxdrain(sc); 791 return (1); 792 } 793 } else 794 GEM_INIT_RXDESC(sc, i); 795 } 796 sc->sc_rxptr = 0; 797 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 798 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 799 800 return (0); 801 } 802 803 static int 804 gem_ringsize(sz) 805 int sz; 806 { 807 int v = 0; 808 809 switch (sz) { 810 case 32: 811 v = GEM_RING_SZ_32; 812 break; 813 case 64: 814 v = GEM_RING_SZ_64; 815 break; 816 case 128: 817 v = GEM_RING_SZ_128; 818 break; 819 case 256: 820 v = GEM_RING_SZ_256; 821 break; 822 case 512: 823 v = GEM_RING_SZ_512; 824 break; 825 case 1024: 826 v = GEM_RING_SZ_1024; 827 break; 828 case 2048: 829 v = GEM_RING_SZ_2048; 830 break; 831 case 4096: 832 v = GEM_RING_SZ_4096; 833 break; 834 case 8192: 835 v = GEM_RING_SZ_8192; 836 break; 837 default: 838 printf("gem: invalid Receive Descriptor ring size\n"); 839 break; 840 } 841 return (v); 842 } 843 844 /* 845 * Initialization of interface; set up initialization block 846 * and transmit/receive descriptor rings. 847 */ 848 static void 849 gem_init(xsc) 850 void *xsc; 851 { 852 struct gem_softc *sc = (struct gem_softc *)xsc; 853 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 854 bus_space_tag_t t = sc->sc_bustag; 855 bus_space_handle_t h = sc->sc_h; 856 int s; 857 u_int32_t v; 858 859 s = splnet(); 860 861 #ifdef GEM_DEBUG 862 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 863 #endif 864 /* 865 * Initialization sequence. The numbered steps below correspond 866 * to the sequence outlined in section 6.3.5.1 in the Ethernet 867 * Channel Engine manual (part of the PCIO manual). 868 * See also the STP2002-STQ document from Sun Microsystems. 869 */ 870 871 /* step 1 & 2. Reset the Ethernet Channel */ 872 gem_stop(&sc->sc_arpcom.ac_if, 0); 873 gem_reset(sc); 874 #ifdef GEM_DEBUG 875 CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev)); 876 #endif 877 878 /* Re-initialize the MIF */ 879 gem_mifinit(sc); 880 881 /* step 3. Setup data structures in host memory */ 882 gem_meminit(sc); 883 884 /* step 4. TX MAC registers & counters */ 885 gem_init_regs(sc); 886 /* XXX: VLAN code from NetBSD temporarily removed. */ 887 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 888 (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 889 890 /* step 5. RX MAC registers & counters */ 891 gem_setladrf(sc); 892 893 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 894 /* NOTE: we use only 32-bit DMA addresses here. */ 895 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 896 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 897 898 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 899 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 900 #ifdef GEM_DEBUG 901 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 902 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 903 #endif 904 905 /* step 8. Global Configuration & Interrupt Mask */ 906 bus_space_write_4(t, h, GEM_INTMASK, 907 ~(GEM_INTR_TX_INTME| 908 GEM_INTR_TX_EMPTY| 909 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 910 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 911 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 912 GEM_INTR_BERR)); 913 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 914 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 915 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 916 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 917 918 /* step 9. ETX Configuration: use mostly default values */ 919 920 /* Enable DMA */ 921 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 922 bus_space_write_4(t, h, GEM_TX_CONFIG, 923 v|GEM_TX_CONFIG_TXDMA_EN| 924 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 925 926 /* step 10. ERX Configuration */ 927 928 /* Encode Receive Descriptor ring size: four possible values */ 929 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 930 931 /* Enable DMA */ 932 bus_space_write_4(t, h, GEM_RX_CONFIG, 933 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 934 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 935 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 936 /* 937 * The following value is for an OFF Threshold of about 3/4 full 938 * and an ON Threshold of 1/4 full. 939 */ 940 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 941 (3 * sc->sc_rxfifosize / 256) | 942 ( (sc->sc_rxfifosize / 256) << 12)); 943 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 944 945 /* step 11. Configure Media */ 946 mii_mediachg(sc->sc_mii); 947 948 /* step 12. RX_MAC Configuration Register */ 949 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 950 v |= GEM_MAC_RX_ENABLE; 951 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 952 953 /* step 14. Issue Transmit Pending command */ 954 955 /* step 15. Give the reciever a swift kick */ 956 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 957 958 /* Start the one second timer. */ 959 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 960 961 ifp->if_flags |= IFF_RUNNING; 962 ifp->if_flags &= ~IFF_OACTIVE; 963 ifp->if_timer = 0; 964 sc->sc_ifflags = ifp->if_flags; 965 splx(s); 966 } 967 968 static int 969 gem_load_txmbuf(sc, m0) 970 struct gem_softc *sc; 971 struct mbuf *m0; 972 { 973 struct gem_txdma txd; 974 struct gem_txsoft *txs; 975 int error; 976 977 /* Get a work queue entry. */ 978 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 979 /* Ran out of descriptors. */ 980 return (-1); 981 } 982 txd.txd_sc = sc; 983 txd.txd_txs = txs; 984 txs->txs_mbuf = m0; 985 txs->txs_firstdesc = sc->sc_txnext; 986 error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0, 987 gem_txdma_callback, &txd, BUS_DMA_NOWAIT); 988 if (error != 0) 989 goto fail; 990 if (txs->txs_ndescs == -1) { 991 error = -1; 992 goto fail; 993 } 994 995 /* Sync the DMA map. */ 996 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 997 BUS_DMASYNC_PREWRITE); 998 999 #ifdef GEM_DEBUG 1000 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, " 1001 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc, 1002 txs->txs_ndescs); 1003 #endif 1004 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1005 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1006 1007 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1008 sc->sc_txfree -= txs->txs_ndescs; 1009 return (0); 1010 1011 fail: 1012 #ifdef GEM_DEBUG 1013 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error); 1014 #endif 1015 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1016 return (error); 1017 } 1018 1019 static void 1020 gem_init_regs(sc) 1021 struct gem_softc *sc; 1022 { 1023 bus_space_tag_t t = sc->sc_bustag; 1024 bus_space_handle_t h = sc->sc_h; 1025 const u_char *laddr = sc->sc_arpcom.ac_enaddr; 1026 u_int32_t v; 1027 1028 /* These regs are not cleared on reset */ 1029 if (!sc->sc_inited) { 1030 1031 /* Wooo. Magic values. */ 1032 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 1033 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 1034 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 1035 1036 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1037 /* Max frame and max burst size */ 1038 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1039 ETHER_MAX_LEN | (0x2000<<16)); 1040 1041 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 1042 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 1043 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1044 /* Dunno.... */ 1045 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1046 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1047 ((laddr[5]<<8)|laddr[4])&0x3ff); 1048 1049 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1050 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1051 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1052 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1053 1054 /* MAC control addr set to 01:80:c2:00:00:01 */ 1055 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1056 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1057 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1058 1059 /* MAC filter addr set to 0:0:0:0:0:0 */ 1060 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1061 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1062 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1063 1064 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1065 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1066 1067 sc->sc_inited = 1; 1068 } 1069 1070 /* Counters need to be zeroed */ 1071 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1072 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1073 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1074 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1075 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1076 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1077 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1078 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1079 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1080 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1081 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1082 1083 /* Un-pause stuff */ 1084 #if 0 1085 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1086 #else 1087 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 1088 #endif 1089 1090 /* 1091 * Set the station address. 1092 */ 1093 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1094 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1095 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1096 1097 /* 1098 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1099 */ 1100 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1101 v = GEM_MAC_XIF_TX_MII_ENA; 1102 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1103 v |= GEM_MAC_XIF_FDPLX_LED; 1104 if (sc->sc_flags & GEM_GIGABIT) 1105 v |= GEM_MAC_XIF_GMII_MODE; 1106 } 1107 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1108 } 1109 1110 static void 1111 gem_start(ifp) 1112 struct ifnet *ifp; 1113 { 1114 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1115 struct mbuf *m0 = NULL; 1116 int firsttx, ntx = 0, ofree, txmfail; 1117 1118 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1119 return; 1120 1121 /* 1122 * Remember the previous number of free descriptors and 1123 * the first descriptor we'll use. 1124 */ 1125 ofree = sc->sc_txfree; 1126 firsttx = sc->sc_txnext; 1127 1128 #ifdef GEM_DEBUG 1129 CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d", 1130 device_get_name(sc->sc_dev), ofree, firsttx); 1131 #endif 1132 1133 /* 1134 * Loop through the send queue, setting up transmit descriptors 1135 * until we drain the queue, or use up all available transmit 1136 * descriptors. 1137 */ 1138 txmfail = 0; 1139 do { 1140 /* 1141 * Grab a packet off the queue. 1142 */ 1143 IF_DEQUEUE(&ifp->if_snd, m0); 1144 if (m0 == NULL) 1145 break; 1146 1147 txmfail = gem_load_txmbuf(sc, m0); 1148 if (txmfail > 0) { 1149 /* Drop the mbuf and complain. */ 1150 printf("gem_start: error %d while loading mbuf dma " 1151 "map\n", txmfail); 1152 continue; 1153 } 1154 /* Not enough descriptors. */ 1155 if (txmfail == -1) { 1156 if (sc->sc_txfree == GEM_MAXTXFREE) 1157 panic("gem_start: mbuf chain too long!"); 1158 IF_PREPEND(&ifp->if_snd, m0); 1159 break; 1160 } 1161 1162 ntx++; 1163 /* Kick the transmitter. */ 1164 #ifdef GEM_DEBUG 1165 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d", 1166 device_get_name(sc->sc_dev), sc->sc_txnext); 1167 #endif 1168 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1169 sc->sc_txnext); 1170 1171 if (ifp->if_bpf != NULL) 1172 bpf_mtap(ifp->if_bpf, m0); 1173 } while (1); 1174 1175 if (txmfail == -1 || sc->sc_txfree == 0) { 1176 /* No more slots left; notify upper layer. */ 1177 ifp->if_flags |= IFF_OACTIVE; 1178 } 1179 1180 if (ntx > 0) { 1181 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1182 1183 #ifdef GEM_DEBUG 1184 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1185 device_get_name(sc->sc_dev), firsttx); 1186 #endif 1187 1188 /* Set a watchdog timer in case the chip flakes out. */ 1189 ifp->if_timer = 5; 1190 #ifdef GEM_DEBUG 1191 CTR2(KTR_GEM, "%s: gem_start: watchdog %d", 1192 device_get_name(sc->sc_dev), ifp->if_timer); 1193 #endif 1194 } 1195 } 1196 1197 /* 1198 * Transmit interrupt. 1199 */ 1200 static void 1201 gem_tint(sc) 1202 struct gem_softc *sc; 1203 { 1204 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1205 bus_space_tag_t t = sc->sc_bustag; 1206 bus_space_handle_t mac = sc->sc_h; 1207 struct gem_txsoft *txs; 1208 int txlast; 1209 int progress = 0; 1210 1211 1212 #ifdef GEM_DEBUG 1213 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 1214 #endif 1215 1216 /* 1217 * Unload collision counters 1218 */ 1219 ifp->if_collisions += 1220 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1221 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1222 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1223 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1224 1225 /* 1226 * then clear the hardware counters. 1227 */ 1228 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1229 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1230 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1231 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1232 1233 /* 1234 * Go through our Tx list and free mbufs for those 1235 * frames that have been transmitted. 1236 */ 1237 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1238 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1239 1240 #ifdef GEM_DEBUG 1241 if (ifp->if_flags & IFF_DEBUG) { 1242 int i; 1243 printf(" txsoft %p transmit chain:\n", txs); 1244 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1245 printf("descriptor %d: ", i); 1246 printf("gd_flags: 0x%016llx\t", (long long) 1247 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1248 printf("gd_addr: 0x%016llx\n", (long long) 1249 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1250 if (i == txs->txs_lastdesc) 1251 break; 1252 } 1253 } 1254 #endif 1255 1256 /* 1257 * In theory, we could harveast some descriptors before 1258 * the ring is empty, but that's a bit complicated. 1259 * 1260 * GEM_TX_COMPLETION points to the last descriptor 1261 * processed +1. 1262 */ 1263 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1264 #ifdef GEM_DEBUG 1265 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 1266 "txs->txs_lastdesc = %d, txlast = %d", 1267 txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1268 #endif 1269 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1270 if ((txlast >= txs->txs_firstdesc) && 1271 (txlast <= txs->txs_lastdesc)) 1272 break; 1273 } else { 1274 /* Ick -- this command wraps */ 1275 if ((txlast >= txs->txs_firstdesc) || 1276 (txlast <= txs->txs_lastdesc)) 1277 break; 1278 } 1279 1280 #ifdef GEM_DEBUG 1281 CTR0(KTR_GEM, "gem_tint: releasing a desc"); 1282 #endif 1283 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1284 1285 sc->sc_txfree += txs->txs_ndescs; 1286 1287 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1288 BUS_DMASYNC_POSTWRITE); 1289 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1290 if (txs->txs_mbuf != NULL) { 1291 m_freem(txs->txs_mbuf); 1292 txs->txs_mbuf = NULL; 1293 } 1294 1295 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1296 1297 ifp->if_opackets++; 1298 progress = 1; 1299 } 1300 1301 #ifdef GEM_DEBUG 1302 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 1303 "GEM_TX_DATA_PTR %llx " 1304 "GEM_TX_COMPLETION %x", 1305 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1306 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1307 GEM_TX_DATA_PTR_HI) << 32) | 1308 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1309 GEM_TX_DATA_PTR_LO), 1310 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION)); 1311 #endif 1312 1313 if (progress) { 1314 if (sc->sc_txfree == GEM_NTXDESC - 1) 1315 sc->sc_txwin = 0; 1316 1317 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1318 ifp->if_flags &= ~IFF_OACTIVE; 1319 gem_start(ifp); 1320 1321 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1322 ifp->if_timer = 0; 1323 } 1324 1325 #ifdef GEM_DEBUG 1326 CTR2(KTR_GEM, "%s: gem_tint: watchdog %d", 1327 device_get_name(sc->sc_dev), ifp->if_timer); 1328 #endif 1329 } 1330 1331 #if 0 1332 static void 1333 gem_rint_timeout(arg) 1334 void *arg; 1335 { 1336 1337 gem_rint((struct gem_softc *)arg); 1338 } 1339 #endif 1340 1341 /* 1342 * Receive interrupt. 1343 */ 1344 static void 1345 gem_rint(sc) 1346 struct gem_softc *sc; 1347 { 1348 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1349 bus_space_tag_t t = sc->sc_bustag; 1350 bus_space_handle_t h = sc->sc_h; 1351 struct gem_rxsoft *rxs; 1352 struct mbuf *m; 1353 u_int64_t rxstat; 1354 u_int32_t rxcomp; 1355 int i, len, progress = 0; 1356 1357 callout_stop(&sc->sc_rx_ch); 1358 #ifdef GEM_DEBUG 1359 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 1360 #endif 1361 1362 /* 1363 * Read the completion register once. This limits 1364 * how long the following loop can execute. 1365 */ 1366 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1367 1368 #ifdef GEM_DEBUG 1369 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 1370 sc->sc_rxptr, rxcomp); 1371 #endif 1372 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1373 for (i = sc->sc_rxptr; i != rxcomp; 1374 i = GEM_NEXTRX(i)) { 1375 rxs = &sc->sc_rxsoft[i]; 1376 1377 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1378 1379 if (rxstat & GEM_RD_OWN) { 1380 #if 0 /* XXX: In case of emergency, re-enable this. */ 1381 /* 1382 * The descriptor is still marked as owned, although 1383 * it is supposed to have completed. This has been 1384 * observed on some machines. Just exiting here 1385 * might leave the packet sitting around until another 1386 * one arrives to trigger a new interrupt, which is 1387 * generally undesirable, so set up a timeout. 1388 */ 1389 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1390 gem_rint_timeout, sc); 1391 #endif 1392 break; 1393 } 1394 1395 progress++; 1396 ifp->if_ipackets++; 1397 1398 if (rxstat & GEM_RD_BAD_CRC) { 1399 ifp->if_ierrors++; 1400 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1401 GEM_INIT_RXDESC(sc, i); 1402 continue; 1403 } 1404 1405 #ifdef GEM_DEBUG 1406 if (ifp->if_flags & IFF_DEBUG) { 1407 printf(" rxsoft %p descriptor %d: ", rxs, i); 1408 printf("gd_flags: 0x%016llx\t", (long long) 1409 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1410 printf("gd_addr: 0x%016llx\n", (long long) 1411 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1412 } 1413 #endif 1414 1415 /* 1416 * No errors; receive the packet. Note the Gem 1417 * includes the CRC with every packet. 1418 */ 1419 len = GEM_RD_BUFLEN(rxstat); 1420 1421 /* 1422 * Allocate a new mbuf cluster. If that fails, we are 1423 * out of memory, and must drop the packet and recycle 1424 * the buffer that's already attached to this descriptor. 1425 */ 1426 m = rxs->rxs_mbuf; 1427 if (gem_add_rxbuf(sc, i) != 0) { 1428 ifp->if_ierrors++; 1429 GEM_INIT_RXDESC(sc, i); 1430 continue; 1431 } 1432 m->m_data += 2; /* We're already off by two */ 1433 1434 m->m_pkthdr.rcvif = ifp; 1435 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN; 1436 1437 /* Pass it on. */ 1438 (*ifp->if_input)(ifp, m); 1439 } 1440 1441 if (progress) { 1442 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1443 /* Update the receive pointer. */ 1444 if (i == sc->sc_rxptr) { 1445 device_printf(sc->sc_dev, "rint: ring wrap\n"); 1446 } 1447 sc->sc_rxptr = i; 1448 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1449 } 1450 1451 #ifdef GEM_DEBUG 1452 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", 1453 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 1454 #endif 1455 } 1456 1457 1458 /* 1459 * gem_add_rxbuf: 1460 * 1461 * Add a receive buffer to the indicated descriptor. 1462 */ 1463 static int 1464 gem_add_rxbuf(sc, idx) 1465 struct gem_softc *sc; 1466 int idx; 1467 { 1468 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1469 struct mbuf *m; 1470 int error; 1471 1472 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1473 if (m == NULL) 1474 return (ENOBUFS); 1475 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1476 1477 #ifdef GEM_DEBUG 1478 /* bzero the packet to check dma */ 1479 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1480 #endif 1481 1482 if (rxs->rxs_mbuf != NULL) { 1483 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1484 BUS_DMASYNC_POSTREAD); 1485 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1486 } 1487 1488 rxs->rxs_mbuf = m; 1489 1490 error = bus_dmamap_load_mbuf(sc->sc_rdmatag, rxs->rxs_dmamap, 1491 m, gem_rxdma_callback, rxs, BUS_DMA_NOWAIT); 1492 if (error != 0 || rxs->rxs_paddr == 0) { 1493 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " 1494 "%d\n", idx, error); 1495 panic("gem_add_rxbuf"); /* XXX */ 1496 } 1497 1498 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1499 1500 GEM_INIT_RXDESC(sc, idx); 1501 1502 return (0); 1503 } 1504 1505 1506 static void 1507 gem_eint(sc, status) 1508 struct gem_softc *sc; 1509 u_int status; 1510 { 1511 1512 if ((status & GEM_INTR_MIF) != 0) { 1513 device_printf(sc->sc_dev, "XXXlink status changed\n"); 1514 return; 1515 } 1516 1517 device_printf(sc->sc_dev, "status=%x\n", status); 1518 } 1519 1520 1521 void 1522 gem_intr(v) 1523 void *v; 1524 { 1525 struct gem_softc *sc = (struct gem_softc *)v; 1526 bus_space_tag_t t = sc->sc_bustag; 1527 bus_space_handle_t seb = sc->sc_h; 1528 u_int32_t status; 1529 1530 status = bus_space_read_4(t, seb, GEM_STATUS); 1531 #ifdef GEM_DEBUG 1532 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 1533 device_get_name(sc->sc_dev), (status>>19), 1534 (u_int)status); 1535 #endif 1536 1537 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1538 gem_eint(sc, status); 1539 1540 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1541 gem_tint(sc); 1542 1543 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1544 gem_rint(sc); 1545 1546 /* We should eventually do more than just print out error stats. */ 1547 if (status & GEM_INTR_TX_MAC) { 1548 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1549 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1550 device_printf(sc->sc_dev, "MAC tx fault, status %x\n", 1551 txstat); 1552 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1553 gem_init(sc); 1554 } 1555 if (status & GEM_INTR_RX_MAC) { 1556 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1557 if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1558 device_printf(sc->sc_dev, "MAC rx fault, status %x\n", 1559 rxstat); 1560 if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0) 1561 gem_init(sc); 1562 } 1563 } 1564 1565 1566 static void 1567 gem_watchdog(ifp) 1568 struct ifnet *ifp; 1569 { 1570 struct gem_softc *sc = ifp->if_softc; 1571 1572 #ifdef GEM_DEBUG 1573 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1574 "GEM_MAC_RX_CONFIG %x", 1575 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1576 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1577 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)); 1578 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 1579 "GEM_MAC_TX_CONFIG %x", 1580 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 1581 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS), 1582 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 1583 #endif 1584 1585 device_printf(sc->sc_dev, "device timeout\n"); 1586 ++ifp->if_oerrors; 1587 1588 /* Try to get more packets going. */ 1589 gem_start(ifp); 1590 } 1591 1592 /* 1593 * Initialize the MII Management Interface 1594 */ 1595 static void 1596 gem_mifinit(sc) 1597 struct gem_softc *sc; 1598 { 1599 bus_space_tag_t t = sc->sc_bustag; 1600 bus_space_handle_t mif = sc->sc_h; 1601 1602 /* Configure the MIF in frame mode */ 1603 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1604 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1605 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1606 } 1607 1608 /* 1609 * MII interface 1610 * 1611 * The GEM MII interface supports at least three different operating modes: 1612 * 1613 * Bitbang mode is implemented using data, clock and output enable registers. 1614 * 1615 * Frame mode is implemented by loading a complete frame into the frame 1616 * register and polling the valid bit for completion. 1617 * 1618 * Polling mode uses the frame register but completion is indicated by 1619 * an interrupt. 1620 * 1621 */ 1622 int 1623 gem_mii_readreg(dev, phy, reg) 1624 device_t dev; 1625 int phy, reg; 1626 { 1627 struct gem_softc *sc = device_get_softc(dev); 1628 bus_space_tag_t t = sc->sc_bustag; 1629 bus_space_handle_t mif = sc->sc_h; 1630 int n; 1631 u_int32_t v; 1632 1633 #ifdef GEM_DEBUG_PHY 1634 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1635 #endif 1636 1637 #if 0 1638 /* Select the desired PHY in the MIF configuration register */ 1639 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1640 /* Clear PHY select bit */ 1641 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1642 if (phy == GEM_PHYAD_EXTERNAL) 1643 /* Set PHY select bit to get at external device */ 1644 v |= GEM_MIF_CONFIG_PHY_SEL; 1645 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1646 #endif 1647 1648 /* Construct the frame command */ 1649 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1650 GEM_MIF_FRAME_READ; 1651 1652 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1653 for (n = 0; n < 100; n++) { 1654 DELAY(1); 1655 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1656 if (v & GEM_MIF_FRAME_TA0) 1657 return (v & GEM_MIF_FRAME_DATA); 1658 } 1659 1660 device_printf(sc->sc_dev, "mii_read timeout\n"); 1661 return (0); 1662 } 1663 1664 int 1665 gem_mii_writereg(dev, phy, reg, val) 1666 device_t dev; 1667 int phy, reg, val; 1668 { 1669 struct gem_softc *sc = device_get_softc(dev); 1670 bus_space_tag_t t = sc->sc_bustag; 1671 bus_space_handle_t mif = sc->sc_h; 1672 int n; 1673 u_int32_t v; 1674 1675 #ifdef GEM_DEBUG_PHY 1676 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 1677 #endif 1678 1679 #if 0 1680 /* Select the desired PHY in the MIF configuration register */ 1681 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1682 /* Clear PHY select bit */ 1683 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1684 if (phy == GEM_PHYAD_EXTERNAL) 1685 /* Set PHY select bit to get at external device */ 1686 v |= GEM_MIF_CONFIG_PHY_SEL; 1687 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1688 #endif 1689 /* Construct the frame command */ 1690 v = GEM_MIF_FRAME_WRITE | 1691 (phy << GEM_MIF_PHY_SHIFT) | 1692 (reg << GEM_MIF_REG_SHIFT) | 1693 (val & GEM_MIF_FRAME_DATA); 1694 1695 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1696 for (n = 0; n < 100; n++) { 1697 DELAY(1); 1698 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1699 if (v & GEM_MIF_FRAME_TA0) 1700 return (1); 1701 } 1702 1703 device_printf(sc->sc_dev, "mii_write timeout\n"); 1704 return (0); 1705 } 1706 1707 void 1708 gem_mii_statchg(dev) 1709 device_t dev; 1710 { 1711 struct gem_softc *sc = device_get_softc(dev); 1712 #ifdef GEM_DEBUG 1713 int instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 1714 #endif 1715 bus_space_tag_t t = sc->sc_bustag; 1716 bus_space_handle_t mac = sc->sc_h; 1717 u_int32_t v; 1718 1719 #ifdef GEM_DEBUG 1720 if (sc->sc_debug) 1721 printf("gem_mii_statchg: status change: phy = %d\n", 1722 sc->sc_phys[instance]); 1723 #endif 1724 1725 /* Set tx full duplex options */ 1726 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1727 DELAY(10000); /* reg must be cleared and delay before changing. */ 1728 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1729 GEM_MAC_TX_ENABLE; 1730 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 1731 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1732 } 1733 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1734 1735 /* XIF Configuration */ 1736 /* We should really calculate all this rather than rely on defaults */ 1737 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1738 v = GEM_MAC_XIF_LINK_LED; 1739 v |= GEM_MAC_XIF_TX_MII_ENA; 1740 1741 /* If an external transceiver is connected, enable its MII drivers */ 1742 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1743 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1744 /* External MII needs echo disable if half duplex. */ 1745 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 1746 /* turn on full duplex LED */ 1747 v |= GEM_MAC_XIF_FDPLX_LED; 1748 else 1749 /* half duplex -- disable echo */ 1750 v |= GEM_MAC_XIF_ECHO_DISABL; 1751 1752 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T) 1753 v |= GEM_MAC_XIF_GMII_MODE; 1754 else 1755 v &= ~GEM_MAC_XIF_GMII_MODE; 1756 } else { 1757 /* Internal MII needs buf enable */ 1758 v |= GEM_MAC_XIF_MII_BUF_ENA; 1759 } 1760 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1761 } 1762 1763 int 1764 gem_mediachange(ifp) 1765 struct ifnet *ifp; 1766 { 1767 struct gem_softc *sc = ifp->if_softc; 1768 1769 /* XXX Add support for serial media. */ 1770 1771 return (mii_mediachg(sc->sc_mii)); 1772 } 1773 1774 void 1775 gem_mediastatus(ifp, ifmr) 1776 struct ifnet *ifp; 1777 struct ifmediareq *ifmr; 1778 { 1779 struct gem_softc *sc = ifp->if_softc; 1780 1781 if ((ifp->if_flags & IFF_UP) == 0) 1782 return; 1783 1784 mii_pollstat(sc->sc_mii); 1785 ifmr->ifm_active = sc->sc_mii->mii_media_active; 1786 ifmr->ifm_status = sc->sc_mii->mii_media_status; 1787 } 1788 1789 /* 1790 * Process an ioctl request. 1791 */ 1792 static int 1793 gem_ioctl(ifp, cmd, data) 1794 struct ifnet *ifp; 1795 u_long cmd; 1796 caddr_t data; 1797 { 1798 struct gem_softc *sc = ifp->if_softc; 1799 struct ifreq *ifr = (struct ifreq *)data; 1800 int s, error = 0; 1801 1802 switch (cmd) { 1803 case SIOCSIFADDR: 1804 case SIOCGIFADDR: 1805 case SIOCSIFMTU: 1806 error = ether_ioctl(ifp, cmd, data); 1807 break; 1808 case SIOCSIFFLAGS: 1809 if (ifp->if_flags & IFF_UP) { 1810 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC) 1811 gem_setladrf(sc); 1812 else 1813 gem_init(sc); 1814 } else { 1815 if (ifp->if_flags & IFF_RUNNING) 1816 gem_stop(ifp, 0); 1817 } 1818 sc->sc_ifflags = ifp->if_flags; 1819 error = 0; 1820 break; 1821 case SIOCADDMULTI: 1822 case SIOCDELMULTI: 1823 gem_setladrf(sc); 1824 error = 0; 1825 break; 1826 case SIOCGIFMEDIA: 1827 case SIOCSIFMEDIA: 1828 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 1829 break; 1830 default: 1831 error = ENOTTY; 1832 break; 1833 } 1834 1835 /* Try to get things going again */ 1836 if (ifp->if_flags & IFF_UP) 1837 gem_start(ifp); 1838 splx(s); 1839 return (error); 1840 } 1841 1842 /* 1843 * Set up the logical address filter. 1844 */ 1845 static void 1846 gem_setladrf(sc) 1847 struct gem_softc *sc; 1848 { 1849 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1850 struct ifmultiaddr *inm; 1851 struct sockaddr_dl *sdl; 1852 bus_space_tag_t t = sc->sc_bustag; 1853 bus_space_handle_t h = sc->sc_h; 1854 u_char *cp; 1855 u_int32_t crc; 1856 u_int32_t hash[16]; 1857 u_int32_t v; 1858 int len; 1859 int i; 1860 1861 /* Get current RX configuration */ 1862 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1863 1864 /* 1865 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1866 * and hash filter. Depending on the case, the right bit will be 1867 * enabled. 1868 */ 1869 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1870 GEM_MAC_RX_PROMISC_GRP); 1871 1872 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1873 /* Turn on promiscuous mode */ 1874 v |= GEM_MAC_RX_PROMISCUOUS; 1875 goto chipit; 1876 } 1877 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 1878 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1879 ifp->if_flags |= IFF_ALLMULTI; 1880 v |= GEM_MAC_RX_PROMISC_GRP; 1881 goto chipit; 1882 } 1883 1884 /* 1885 * Set up multicast address filter by passing all multicast addresses 1886 * through a crc generator, and then using the high order 8 bits as an 1887 * index into the 256 bit logical address filter. The high order 4 1888 * bits selects the word, while the other 4 bits select the bit within 1889 * the word (where bit 0 is the MSB). 1890 */ 1891 1892 /* Clear hash table */ 1893 memset(hash, 0, sizeof(hash)); 1894 1895 TAILQ_FOREACH(inm, &sc->sc_arpcom.ac_if.if_multiaddrs, ifma_link) { 1896 if (inm->ifma_addr->sa_family != AF_LINK) 1897 continue; 1898 sdl = (struct sockaddr_dl *)inm->ifma_addr; 1899 cp = LLADDR(sdl); 1900 crc = 0xffffffff; 1901 for (len = sdl->sdl_alen; --len >= 0;) { 1902 int octet = *cp++; 1903 int i; 1904 1905 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1906 for (i = 0; i < 8; i++) { 1907 if ((crc & 1) ^ (octet & 1)) { 1908 crc >>= 1; 1909 crc ^= MC_POLY_LE; 1910 } else { 1911 crc >>= 1; 1912 } 1913 octet >>= 1; 1914 } 1915 } 1916 /* Just want the 8 most significant bits. */ 1917 crc >>= 24; 1918 1919 /* Set the corresponding bit in the filter. */ 1920 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1921 } 1922 1923 v |= GEM_MAC_RX_HASH_FILTER; 1924 ifp->if_flags &= ~IFF_ALLMULTI; 1925 1926 /* Now load the hash table into the chip (if we are using it) */ 1927 for (i = 0; i < 16; i++) { 1928 bus_space_write_4(t, h, 1929 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1930 hash[i]); 1931 } 1932 1933 chipit: 1934 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1935 } 1936