1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #if 0 38 #define GEM_DEBUG 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/callout.h> 45 #include <sys/endian.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 53 #include <net/bpf.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_arp.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #include <machine/bus.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/gem/if_gemreg.h> 67 #include <dev/gem/if_gemvar.h> 68 69 #define TRIES 10000 70 71 static void gem_start(struct ifnet *); 72 static void gem_stop(struct ifnet *, int); 73 static int gem_ioctl(struct ifnet *, u_long, caddr_t); 74 static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); 75 static void gem_rxdma_callback(void *, bus_dma_segment_t *, int, 76 bus_size_t, int); 77 static void gem_txdma_callback(void *, bus_dma_segment_t *, int, 78 bus_size_t, int); 79 static void gem_tick(void *); 80 static void gem_watchdog(struct ifnet *); 81 static void gem_init(void *); 82 static void gem_init_regs(struct gem_softc *sc); 83 static int gem_ringsize(int sz); 84 static int gem_meminit(struct gem_softc *); 85 static int gem_load_txmbuf(struct gem_softc *, struct mbuf *); 86 static void gem_mifinit(struct gem_softc *); 87 static int gem_bitwait(struct gem_softc *sc, bus_addr_t r, 88 u_int32_t clr, u_int32_t set); 89 static int gem_reset_rx(struct gem_softc *); 90 static int gem_reset_tx(struct gem_softc *); 91 static int gem_disable_rx(struct gem_softc *); 92 static int gem_disable_tx(struct gem_softc *); 93 static void gem_rxdrain(struct gem_softc *); 94 static int gem_add_rxbuf(struct gem_softc *, int); 95 static void gem_setladrf(struct gem_softc *); 96 97 struct mbuf *gem_get(struct gem_softc *, int, int); 98 static void gem_eint(struct gem_softc *, u_int); 99 static void gem_rint(struct gem_softc *); 100 #if 0 101 static void gem_rint_timeout(void *); 102 #endif 103 static void gem_tint(struct gem_softc *); 104 #ifdef notyet 105 static void gem_power(int, void *); 106 #endif 107 108 devclass_t gem_devclass; 109 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 110 MODULE_DEPEND(gem, miibus, 1, 1, 1); 111 112 #ifdef GEM_DEBUG 113 #include <sys/ktr.h> 114 #define KTR_GEM KTR_CT2 115 #endif 116 117 #define GEM_NSEGS GEM_NTXDESC 118 119 /* 120 * gem_attach: 121 * 122 * Attach a Gem interface to the system. 123 */ 124 int 125 gem_attach(sc) 126 struct gem_softc *sc; 127 { 128 struct ifnet *ifp; 129 struct mii_softc *child; 130 int i, error; 131 u_int32_t v; 132 133 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 134 if (ifp == NULL) 135 return (ENOSPC); 136 137 /* Make sure the chip is stopped. */ 138 ifp->if_softc = sc; 139 gem_reset(sc); 140 141 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 142 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS, 143 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->sc_pdmatag); 144 if (error) 145 goto fail_ifnet; 146 147 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 148 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE, 149 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL, 150 &sc->sc_rdmatag); 151 if (error) 152 goto fail_ptag; 153 154 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 155 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 156 GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT, 157 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 158 if (error) 159 goto fail_rtag; 160 161 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 162 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 163 sizeof(struct gem_control_data), 1, 164 sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW, 165 busdma_lock_mutex, &Giant, &sc->sc_cdmatag); 166 if (error) 167 goto fail_ttag; 168 169 /* 170 * Allocate the control data structures, and create and load the 171 * DMA map for it. 172 */ 173 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 174 (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) { 175 device_printf(sc->sc_dev, "unable to allocate control data," 176 " error = %d\n", error); 177 goto fail_ctag; 178 } 179 180 sc->sc_cddma = 0; 181 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 182 sc->sc_control_data, sizeof(struct gem_control_data), 183 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 184 device_printf(sc->sc_dev, "unable to load control data DMA " 185 "map, error = %d\n", error); 186 goto fail_cmem; 187 } 188 189 /* 190 * Initialize the transmit job descriptors. 191 */ 192 STAILQ_INIT(&sc->sc_txfreeq); 193 STAILQ_INIT(&sc->sc_txdirtyq); 194 195 /* 196 * Create the transmit buffer DMA maps. 197 */ 198 error = ENOMEM; 199 for (i = 0; i < GEM_TXQUEUELEN; i++) { 200 struct gem_txsoft *txs; 201 202 txs = &sc->sc_txsoft[i]; 203 txs->txs_mbuf = NULL; 204 txs->txs_ndescs = 0; 205 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 206 &txs->txs_dmamap)) != 0) { 207 device_printf(sc->sc_dev, "unable to create tx DMA map " 208 "%d, error = %d\n", i, error); 209 goto fail_txd; 210 } 211 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 212 } 213 214 /* 215 * Create the receive buffer DMA maps. 216 */ 217 for (i = 0; i < GEM_NRXDESC; i++) { 218 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 219 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 220 device_printf(sc->sc_dev, "unable to create rx DMA map " 221 "%d, error = %d\n", i, error); 222 goto fail_rxd; 223 } 224 sc->sc_rxsoft[i].rxs_mbuf = NULL; 225 } 226 227 228 gem_mifinit(sc); 229 230 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange, 231 gem_mediastatus)) != 0) { 232 device_printf(sc->sc_dev, "phy probe failed: %d\n", error); 233 goto fail_rxd; 234 } 235 sc->sc_mii = device_get_softc(sc->sc_miibus); 236 237 /* 238 * From this point forward, the attachment cannot fail. A failure 239 * before this point releases all resources that may have been 240 * allocated. 241 */ 242 243 /* Get RX FIFO size */ 244 sc->sc_rxfifosize = 64 * 245 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 246 247 /* Get TX FIFO size */ 248 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 249 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 250 sc->sc_rxfifosize / 1024, v / 16); 251 252 /* Initialize ifnet structure. */ 253 ifp->if_softc = sc; 254 if_initname(ifp, device_get_name(sc->sc_dev), 255 device_get_unit(sc->sc_dev)); 256 ifp->if_mtu = ETHERMTU; 257 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 258 IFF_NEEDSGIANT; 259 ifp->if_start = gem_start; 260 ifp->if_ioctl = gem_ioctl; 261 ifp->if_watchdog = gem_watchdog; 262 ifp->if_init = gem_init; 263 ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN; 264 /* 265 * Walk along the list of attached MII devices and 266 * establish an `MII instance' to `phy number' 267 * mapping. We'll use this mapping in media change 268 * requests to determine which phy to use to program 269 * the MIF configuration register. 270 */ 271 for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL; 272 child = LIST_NEXT(child, mii_list)) { 273 /* 274 * Note: we support just two PHYs: the built-in 275 * internal device and an external on the MII 276 * connector. 277 */ 278 if (child->mii_phy > 1 || child->mii_inst > 1) { 279 device_printf(sc->sc_dev, "cannot accomodate " 280 "MII device %s at phy %d, instance %d\n", 281 device_get_name(child->mii_dev), 282 child->mii_phy, child->mii_inst); 283 continue; 284 } 285 286 sc->sc_phys[child->mii_inst] = child->mii_phy; 287 } 288 289 /* 290 * Now select and activate the PHY we will use. 291 * 292 * The order of preference is External (MDI1), 293 * Internal (MDI0), Serial Link (no MII). 294 */ 295 if (sc->sc_phys[1]) { 296 #ifdef GEM_DEBUG 297 printf("using external phy\n"); 298 #endif 299 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 300 } else { 301 #ifdef GEM_DEBUG 302 printf("using internal phy\n"); 303 #endif 304 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 305 } 306 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 307 sc->sc_mif_config); 308 /* Attach the interface. */ 309 ether_ifattach(ifp, sc->sc_enaddr); 310 311 #if notyet 312 /* 313 * Add a suspend hook to make sure we come back up after a 314 * resume. 315 */ 316 sc->sc_powerhook = powerhook_establish(gem_power, sc); 317 if (sc->sc_powerhook == NULL) 318 device_printf(sc->sc_dev, "WARNING: unable to establish power " 319 "hook\n"); 320 #endif 321 322 callout_init(&sc->sc_tick_ch, 0); 323 callout_init(&sc->sc_rx_ch, 0); 324 return (0); 325 326 /* 327 * Free any resources we've allocated during the failed attach 328 * attempt. Do this in reverse order and fall through. 329 */ 330 fail_rxd: 331 for (i = 0; i < GEM_NRXDESC; i++) { 332 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 333 bus_dmamap_destroy(sc->sc_rdmatag, 334 sc->sc_rxsoft[i].rxs_dmamap); 335 } 336 fail_txd: 337 for (i = 0; i < GEM_TXQUEUELEN; i++) { 338 if (sc->sc_txsoft[i].txs_dmamap != NULL) 339 bus_dmamap_destroy(sc->sc_tdmatag, 340 sc->sc_txsoft[i].txs_dmamap); 341 } 342 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 343 fail_cmem: 344 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 345 sc->sc_cddmamap); 346 fail_ctag: 347 bus_dma_tag_destroy(sc->sc_cdmatag); 348 fail_ttag: 349 bus_dma_tag_destroy(sc->sc_tdmatag); 350 fail_rtag: 351 bus_dma_tag_destroy(sc->sc_rdmatag); 352 fail_ptag: 353 bus_dma_tag_destroy(sc->sc_pdmatag); 354 fail_ifnet: 355 if_free(ifp); 356 return (error); 357 } 358 359 void 360 gem_detach(sc) 361 struct gem_softc *sc; 362 { 363 struct ifnet *ifp = sc->sc_ifp; 364 int i; 365 366 gem_stop(ifp, 1); 367 ether_ifdetach(ifp); 368 if_free(ifp); 369 device_delete_child(sc->sc_dev, sc->sc_miibus); 370 371 for (i = 0; i < GEM_NRXDESC; i++) { 372 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 373 bus_dmamap_destroy(sc->sc_rdmatag, 374 sc->sc_rxsoft[i].rxs_dmamap); 375 } 376 for (i = 0; i < GEM_TXQUEUELEN; i++) { 377 if (sc->sc_txsoft[i].txs_dmamap != NULL) 378 bus_dmamap_destroy(sc->sc_tdmatag, 379 sc->sc_txsoft[i].txs_dmamap); 380 } 381 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 382 GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE); 383 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 384 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 385 sc->sc_cddmamap); 386 bus_dma_tag_destroy(sc->sc_cdmatag); 387 bus_dma_tag_destroy(sc->sc_tdmatag); 388 bus_dma_tag_destroy(sc->sc_rdmatag); 389 bus_dma_tag_destroy(sc->sc_pdmatag); 390 } 391 392 void 393 gem_suspend(sc) 394 struct gem_softc *sc; 395 { 396 struct ifnet *ifp = sc->sc_ifp; 397 398 gem_stop(ifp, 0); 399 } 400 401 void 402 gem_resume(sc) 403 struct gem_softc *sc; 404 { 405 struct ifnet *ifp = sc->sc_ifp; 406 407 if (ifp->if_flags & IFF_UP) 408 gem_init(ifp); 409 } 410 411 static void 412 gem_cddma_callback(xsc, segs, nsegs, error) 413 void *xsc; 414 bus_dma_segment_t *segs; 415 int nsegs; 416 int error; 417 { 418 struct gem_softc *sc = (struct gem_softc *)xsc; 419 420 if (error != 0) 421 return; 422 if (nsegs != 1) { 423 /* can't happen... */ 424 panic("gem_cddma_callback: bad control buffer segment count"); 425 } 426 sc->sc_cddma = segs[0].ds_addr; 427 } 428 429 static void 430 gem_rxdma_callback(xsc, segs, nsegs, totsz, error) 431 void *xsc; 432 bus_dma_segment_t *segs; 433 int nsegs; 434 bus_size_t totsz; 435 int error; 436 { 437 struct gem_rxsoft *rxs = (struct gem_rxsoft *)xsc; 438 439 if (error != 0) 440 return; 441 KASSERT(nsegs == 1, ("gem_rxdma_callback: bad dma segment count")); 442 rxs->rxs_paddr = segs[0].ds_addr; 443 } 444 445 static void 446 gem_txdma_callback(xsc, segs, nsegs, totsz, error) 447 void *xsc; 448 bus_dma_segment_t *segs; 449 int nsegs; 450 bus_size_t totsz; 451 int error; 452 { 453 struct gem_txdma *txd = (struct gem_txdma *)xsc; 454 struct gem_softc *sc = txd->txd_sc; 455 struct gem_txsoft *txs = txd->txd_txs; 456 bus_size_t len = 0; 457 uint64_t flags = 0; 458 int seg, nexttx; 459 460 if (error != 0) 461 return; 462 /* 463 * Ensure we have enough descriptors free to describe 464 * the packet. Note, we always reserve one descriptor 465 * at the end of the ring as a termination point, to 466 * prevent wrap-around. 467 */ 468 if (nsegs > sc->sc_txfree - 1) { 469 txs->txs_ndescs = -1; 470 return; 471 } 472 txs->txs_ndescs = nsegs; 473 474 nexttx = txs->txs_firstdesc; 475 /* 476 * Initialize the transmit descriptors. 477 */ 478 for (seg = 0; seg < nsegs; 479 seg++, nexttx = GEM_NEXTTX(nexttx)) { 480 #ifdef GEM_DEBUG 481 CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len " 482 "%lx, addr %#lx (%#lx)", seg, nexttx, 483 segs[seg].ds_len, segs[seg].ds_addr, 484 GEM_DMA_WRITE(sc, segs[seg].ds_addr)); 485 #endif 486 487 if (segs[seg].ds_len == 0) 488 continue; 489 sc->sc_txdescs[nexttx].gd_addr = 490 GEM_DMA_WRITE(sc, segs[seg].ds_addr); 491 KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE, 492 ("gem_txdma_callback: segment size too large!")); 493 flags = segs[seg].ds_len & GEM_TD_BUFSIZE; 494 if (len == 0) { 495 #ifdef GEM_DEBUG 496 CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, " 497 "tx %d", seg, nexttx); 498 #endif 499 flags |= GEM_TD_START_OF_PACKET; 500 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 501 sc->sc_txwin = 0; 502 flags |= GEM_TD_INTERRUPT_ME; 503 } 504 } 505 if (len + segs[seg].ds_len == totsz) { 506 #ifdef GEM_DEBUG 507 CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, " 508 "tx %d", seg, nexttx); 509 #endif 510 flags |= GEM_TD_END_OF_PACKET; 511 } 512 sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags); 513 txs->txs_lastdesc = nexttx; 514 len += segs[seg].ds_len; 515 } 516 KASSERT((flags & GEM_TD_END_OF_PACKET) != 0, 517 ("gem_txdma_callback: missed end of packet!")); 518 } 519 520 static void 521 gem_tick(arg) 522 void *arg; 523 { 524 struct gem_softc *sc = arg; 525 int s; 526 527 s = splnet(); 528 mii_tick(sc->sc_mii); 529 splx(s); 530 531 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 532 } 533 534 static int 535 gem_bitwait(sc, r, clr, set) 536 struct gem_softc *sc; 537 bus_addr_t r; 538 u_int32_t clr; 539 u_int32_t set; 540 { 541 int i; 542 u_int32_t reg; 543 544 for (i = TRIES; i--; DELAY(100)) { 545 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 546 if ((r & clr) == 0 && (r & set) == set) 547 return (1); 548 } 549 return (0); 550 } 551 552 void 553 gem_reset(sc) 554 struct gem_softc *sc; 555 { 556 bus_space_tag_t t = sc->sc_bustag; 557 bus_space_handle_t h = sc->sc_h; 558 int s; 559 560 s = splnet(); 561 #ifdef GEM_DEBUG 562 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 563 #endif 564 gem_reset_rx(sc); 565 gem_reset_tx(sc); 566 567 /* Do a full reset */ 568 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 569 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 570 device_printf(sc->sc_dev, "cannot reset device\n"); 571 splx(s); 572 } 573 574 575 /* 576 * gem_rxdrain: 577 * 578 * Drain the receive queue. 579 */ 580 static void 581 gem_rxdrain(sc) 582 struct gem_softc *sc; 583 { 584 struct gem_rxsoft *rxs; 585 int i; 586 587 for (i = 0; i < GEM_NRXDESC; i++) { 588 rxs = &sc->sc_rxsoft[i]; 589 if (rxs->rxs_mbuf != NULL) { 590 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 591 BUS_DMASYNC_POSTREAD); 592 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 593 m_freem(rxs->rxs_mbuf); 594 rxs->rxs_mbuf = NULL; 595 } 596 } 597 } 598 599 /* 600 * Reset the whole thing. 601 */ 602 static void 603 gem_stop(ifp, disable) 604 struct ifnet *ifp; 605 int disable; 606 { 607 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 608 struct gem_txsoft *txs; 609 610 #ifdef GEM_DEBUG 611 CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev)); 612 #endif 613 614 callout_stop(&sc->sc_tick_ch); 615 616 /* XXX - Should we reset these instead? */ 617 gem_disable_tx(sc); 618 gem_disable_rx(sc); 619 620 /* 621 * Release any queued transmit buffers. 622 */ 623 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 624 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 625 if (txs->txs_ndescs != 0) { 626 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 627 BUS_DMASYNC_POSTWRITE); 628 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 629 if (txs->txs_mbuf != NULL) { 630 m_freem(txs->txs_mbuf); 631 txs->txs_mbuf = NULL; 632 } 633 } 634 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 635 } 636 637 if (disable) 638 gem_rxdrain(sc); 639 640 /* 641 * Mark the interface down and cancel the watchdog timer. 642 */ 643 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 644 ifp->if_timer = 0; 645 } 646 647 /* 648 * Reset the receiver 649 */ 650 int 651 gem_reset_rx(sc) 652 struct gem_softc *sc; 653 { 654 bus_space_tag_t t = sc->sc_bustag; 655 bus_space_handle_t h = sc->sc_h; 656 657 /* 658 * Resetting while DMA is in progress can cause a bus hang, so we 659 * disable DMA first. 660 */ 661 gem_disable_rx(sc); 662 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 663 /* Wait till it finishes */ 664 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 665 device_printf(sc->sc_dev, "cannot disable read dma\n"); 666 667 /* Wait 5ms extra. */ 668 DELAY(5000); 669 670 /* Finally, reset the ERX */ 671 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 672 /* Wait till it finishes */ 673 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 674 device_printf(sc->sc_dev, "cannot reset receiver\n"); 675 return (1); 676 } 677 return (0); 678 } 679 680 681 /* 682 * Reset the transmitter 683 */ 684 static int 685 gem_reset_tx(sc) 686 struct gem_softc *sc; 687 { 688 bus_space_tag_t t = sc->sc_bustag; 689 bus_space_handle_t h = sc->sc_h; 690 int i; 691 692 /* 693 * Resetting while DMA is in progress can cause a bus hang, so we 694 * disable DMA first. 695 */ 696 gem_disable_tx(sc); 697 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 698 /* Wait till it finishes */ 699 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 700 device_printf(sc->sc_dev, "cannot disable read dma\n"); 701 702 /* Wait 5ms extra. */ 703 DELAY(5000); 704 705 /* Finally, reset the ETX */ 706 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 707 /* Wait till it finishes */ 708 for (i = TRIES; i--; DELAY(100)) 709 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 710 break; 711 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 712 device_printf(sc->sc_dev, "cannot reset receiver\n"); 713 return (1); 714 } 715 return (0); 716 } 717 718 /* 719 * disable receiver. 720 */ 721 static int 722 gem_disable_rx(sc) 723 struct gem_softc *sc; 724 { 725 bus_space_tag_t t = sc->sc_bustag; 726 bus_space_handle_t h = sc->sc_h; 727 u_int32_t cfg; 728 729 /* Flip the enable bit */ 730 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 731 cfg &= ~GEM_MAC_RX_ENABLE; 732 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 733 734 /* Wait for it to finish */ 735 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 736 } 737 738 /* 739 * disable transmitter. 740 */ 741 static int 742 gem_disable_tx(sc) 743 struct gem_softc *sc; 744 { 745 bus_space_tag_t t = sc->sc_bustag; 746 bus_space_handle_t h = sc->sc_h; 747 u_int32_t cfg; 748 749 /* Flip the enable bit */ 750 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 751 cfg &= ~GEM_MAC_TX_ENABLE; 752 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 753 754 /* Wait for it to finish */ 755 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 756 } 757 758 /* 759 * Initialize interface. 760 */ 761 static int 762 gem_meminit(sc) 763 struct gem_softc *sc; 764 { 765 struct gem_rxsoft *rxs; 766 int i, error; 767 768 /* 769 * Initialize the transmit descriptor ring. 770 */ 771 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 772 for (i = 0; i < GEM_NTXDESC; i++) { 773 sc->sc_txdescs[i].gd_flags = 0; 774 sc->sc_txdescs[i].gd_addr = 0; 775 } 776 sc->sc_txfree = GEM_MAXTXFREE; 777 sc->sc_txnext = 0; 778 sc->sc_txwin = 0; 779 780 /* 781 * Initialize the receive descriptor and receive job 782 * descriptor rings. 783 */ 784 for (i = 0; i < GEM_NRXDESC; i++) { 785 rxs = &sc->sc_rxsoft[i]; 786 if (rxs->rxs_mbuf == NULL) { 787 if ((error = gem_add_rxbuf(sc, i)) != 0) { 788 device_printf(sc->sc_dev, "unable to " 789 "allocate or map rx buffer %d, error = " 790 "%d\n", i, error); 791 /* 792 * XXX Should attempt to run with fewer receive 793 * XXX buffers instead of just failing. 794 */ 795 gem_rxdrain(sc); 796 return (1); 797 } 798 } else 799 GEM_INIT_RXDESC(sc, i); 800 } 801 sc->sc_rxptr = 0; 802 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 803 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 804 805 return (0); 806 } 807 808 static int 809 gem_ringsize(sz) 810 int sz; 811 { 812 int v = 0; 813 814 switch (sz) { 815 case 32: 816 v = GEM_RING_SZ_32; 817 break; 818 case 64: 819 v = GEM_RING_SZ_64; 820 break; 821 case 128: 822 v = GEM_RING_SZ_128; 823 break; 824 case 256: 825 v = GEM_RING_SZ_256; 826 break; 827 case 512: 828 v = GEM_RING_SZ_512; 829 break; 830 case 1024: 831 v = GEM_RING_SZ_1024; 832 break; 833 case 2048: 834 v = GEM_RING_SZ_2048; 835 break; 836 case 4096: 837 v = GEM_RING_SZ_4096; 838 break; 839 case 8192: 840 v = GEM_RING_SZ_8192; 841 break; 842 default: 843 printf("gem: invalid Receive Descriptor ring size\n"); 844 break; 845 } 846 return (v); 847 } 848 849 /* 850 * Initialization of interface; set up initialization block 851 * and transmit/receive descriptor rings. 852 */ 853 static void 854 gem_init(xsc) 855 void *xsc; 856 { 857 struct gem_softc *sc = (struct gem_softc *)xsc; 858 struct ifnet *ifp = sc->sc_ifp; 859 bus_space_tag_t t = sc->sc_bustag; 860 bus_space_handle_t h = sc->sc_h; 861 int s; 862 u_int32_t v; 863 864 s = splnet(); 865 866 #ifdef GEM_DEBUG 867 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 868 #endif 869 /* 870 * Initialization sequence. The numbered steps below correspond 871 * to the sequence outlined in section 6.3.5.1 in the Ethernet 872 * Channel Engine manual (part of the PCIO manual). 873 * See also the STP2002-STQ document from Sun Microsystems. 874 */ 875 876 /* step 1 & 2. Reset the Ethernet Channel */ 877 gem_stop(sc->sc_ifp, 0); 878 gem_reset(sc); 879 #ifdef GEM_DEBUG 880 CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev)); 881 #endif 882 883 /* Re-initialize the MIF */ 884 gem_mifinit(sc); 885 886 /* step 3. Setup data structures in host memory */ 887 gem_meminit(sc); 888 889 /* step 4. TX MAC registers & counters */ 890 gem_init_regs(sc); 891 /* XXX: VLAN code from NetBSD temporarily removed. */ 892 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 893 (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 894 895 /* step 5. RX MAC registers & counters */ 896 gem_setladrf(sc); 897 898 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 899 /* NOTE: we use only 32-bit DMA addresses here. */ 900 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 901 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 902 903 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 904 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 905 #ifdef GEM_DEBUG 906 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 907 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 908 #endif 909 910 /* step 8. Global Configuration & Interrupt Mask */ 911 bus_space_write_4(t, h, GEM_INTMASK, 912 ~(GEM_INTR_TX_INTME| 913 GEM_INTR_TX_EMPTY| 914 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 915 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 916 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 917 GEM_INTR_BERR)); 918 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 919 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 920 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 921 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 922 923 /* step 9. ETX Configuration: use mostly default values */ 924 925 /* Enable DMA */ 926 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 927 bus_space_write_4(t, h, GEM_TX_CONFIG, 928 v|GEM_TX_CONFIG_TXDMA_EN| 929 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 930 931 /* step 10. ERX Configuration */ 932 933 /* Encode Receive Descriptor ring size: four possible values */ 934 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 935 936 /* Enable DMA */ 937 bus_space_write_4(t, h, GEM_RX_CONFIG, 938 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 939 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 940 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 941 /* 942 * The following value is for an OFF Threshold of about 3/4 full 943 * and an ON Threshold of 1/4 full. 944 */ 945 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 946 (3 * sc->sc_rxfifosize / 256) | 947 ( (sc->sc_rxfifosize / 256) << 12)); 948 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 949 950 /* step 11. Configure Media */ 951 mii_mediachg(sc->sc_mii); 952 953 /* step 12. RX_MAC Configuration Register */ 954 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 955 v |= GEM_MAC_RX_ENABLE; 956 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 957 958 /* step 14. Issue Transmit Pending command */ 959 960 /* step 15. Give the reciever a swift kick */ 961 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 962 963 /* Start the one second timer. */ 964 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 965 966 ifp->if_flags |= IFF_RUNNING; 967 ifp->if_flags &= ~IFF_OACTIVE; 968 ifp->if_timer = 0; 969 sc->sc_ifflags = ifp->if_flags; 970 splx(s); 971 } 972 973 static int 974 gem_load_txmbuf(sc, m0) 975 struct gem_softc *sc; 976 struct mbuf *m0; 977 { 978 struct gem_txdma txd; 979 struct gem_txsoft *txs; 980 int error; 981 982 /* Get a work queue entry. */ 983 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 984 /* Ran out of descriptors. */ 985 return (-1); 986 } 987 txd.txd_sc = sc; 988 txd.txd_txs = txs; 989 txs->txs_mbuf = m0; 990 txs->txs_firstdesc = sc->sc_txnext; 991 error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0, 992 gem_txdma_callback, &txd, BUS_DMA_NOWAIT); 993 if (error != 0) 994 goto fail; 995 if (txs->txs_ndescs == -1) { 996 error = -1; 997 goto fail; 998 } 999 1000 /* Sync the DMA map. */ 1001 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1002 BUS_DMASYNC_PREWRITE); 1003 1004 #ifdef GEM_DEBUG 1005 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, " 1006 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc, 1007 txs->txs_ndescs); 1008 #endif 1009 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1010 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1011 1012 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1013 sc->sc_txfree -= txs->txs_ndescs; 1014 return (0); 1015 1016 fail: 1017 #ifdef GEM_DEBUG 1018 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error); 1019 #endif 1020 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1021 return (error); 1022 } 1023 1024 static void 1025 gem_init_regs(sc) 1026 struct gem_softc *sc; 1027 { 1028 bus_space_tag_t t = sc->sc_bustag; 1029 bus_space_handle_t h = sc->sc_h; 1030 const u_char *laddr = IFP2ENADDR(sc->sc_ifp); 1031 u_int32_t v; 1032 1033 /* These regs are not cleared on reset */ 1034 if (!sc->sc_inited) { 1035 1036 /* Wooo. Magic values. */ 1037 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 1038 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 1039 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 1040 1041 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1042 /* Max frame and max burst size */ 1043 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1044 ETHER_MAX_LEN | (0x2000<<16)); 1045 1046 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 1047 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 1048 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1049 /* Dunno.... */ 1050 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1051 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1052 ((laddr[5]<<8)|laddr[4])&0x3ff); 1053 1054 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1055 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1056 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1057 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1058 1059 /* MAC control addr set to 01:80:c2:00:00:01 */ 1060 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1061 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1062 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1063 1064 /* MAC filter addr set to 0:0:0:0:0:0 */ 1065 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1066 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1067 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1068 1069 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1070 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1071 1072 sc->sc_inited = 1; 1073 } 1074 1075 /* Counters need to be zeroed */ 1076 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1077 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1078 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1079 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1080 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1081 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1082 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1083 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1084 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1085 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1086 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1087 1088 /* Un-pause stuff */ 1089 #if 0 1090 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1091 #else 1092 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 1093 #endif 1094 1095 /* 1096 * Set the station address. 1097 */ 1098 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1099 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1100 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1101 1102 /* 1103 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1104 */ 1105 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1106 v = GEM_MAC_XIF_TX_MII_ENA; 1107 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1108 v |= GEM_MAC_XIF_FDPLX_LED; 1109 if (sc->sc_flags & GEM_GIGABIT) 1110 v |= GEM_MAC_XIF_GMII_MODE; 1111 } 1112 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1113 } 1114 1115 static void 1116 gem_start(ifp) 1117 struct ifnet *ifp; 1118 { 1119 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1120 struct mbuf *m0 = NULL; 1121 int firsttx, ntx = 0, ofree, txmfail; 1122 1123 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1124 return; 1125 1126 /* 1127 * Remember the previous number of free descriptors and 1128 * the first descriptor we'll use. 1129 */ 1130 ofree = sc->sc_txfree; 1131 firsttx = sc->sc_txnext; 1132 1133 #ifdef GEM_DEBUG 1134 CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d", 1135 device_get_name(sc->sc_dev), ofree, firsttx); 1136 #endif 1137 1138 /* 1139 * Loop through the send queue, setting up transmit descriptors 1140 * until we drain the queue, or use up all available transmit 1141 * descriptors. 1142 */ 1143 txmfail = 0; 1144 do { 1145 /* 1146 * Grab a packet off the queue. 1147 */ 1148 IF_DEQUEUE(&ifp->if_snd, m0); 1149 if (m0 == NULL) 1150 break; 1151 1152 txmfail = gem_load_txmbuf(sc, m0); 1153 if (txmfail > 0) { 1154 /* Drop the mbuf and complain. */ 1155 printf("gem_start: error %d while loading mbuf dma " 1156 "map\n", txmfail); 1157 continue; 1158 } 1159 /* Not enough descriptors. */ 1160 if (txmfail == -1) { 1161 if (sc->sc_txfree == GEM_MAXTXFREE) 1162 panic("gem_start: mbuf chain too long!"); 1163 IF_PREPEND(&ifp->if_snd, m0); 1164 break; 1165 } 1166 1167 ntx++; 1168 /* Kick the transmitter. */ 1169 #ifdef GEM_DEBUG 1170 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d", 1171 device_get_name(sc->sc_dev), sc->sc_txnext); 1172 #endif 1173 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1174 sc->sc_txnext); 1175 1176 if (ifp->if_bpf != NULL) 1177 bpf_mtap(ifp->if_bpf, m0); 1178 } while (1); 1179 1180 if (txmfail == -1 || sc->sc_txfree == 0) { 1181 /* No more slots left; notify upper layer. */ 1182 ifp->if_flags |= IFF_OACTIVE; 1183 } 1184 1185 if (ntx > 0) { 1186 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1187 1188 #ifdef GEM_DEBUG 1189 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1190 device_get_name(sc->sc_dev), firsttx); 1191 #endif 1192 1193 /* Set a watchdog timer in case the chip flakes out. */ 1194 ifp->if_timer = 5; 1195 #ifdef GEM_DEBUG 1196 CTR2(KTR_GEM, "%s: gem_start: watchdog %d", 1197 device_get_name(sc->sc_dev), ifp->if_timer); 1198 #endif 1199 } 1200 } 1201 1202 /* 1203 * Transmit interrupt. 1204 */ 1205 static void 1206 gem_tint(sc) 1207 struct gem_softc *sc; 1208 { 1209 struct ifnet *ifp = sc->sc_ifp; 1210 bus_space_tag_t t = sc->sc_bustag; 1211 bus_space_handle_t mac = sc->sc_h; 1212 struct gem_txsoft *txs; 1213 int txlast; 1214 int progress = 0; 1215 1216 1217 #ifdef GEM_DEBUG 1218 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 1219 #endif 1220 1221 /* 1222 * Unload collision counters 1223 */ 1224 ifp->if_collisions += 1225 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1226 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1227 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1228 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1229 1230 /* 1231 * then clear the hardware counters. 1232 */ 1233 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1234 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1235 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1236 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1237 1238 /* 1239 * Go through our Tx list and free mbufs for those 1240 * frames that have been transmitted. 1241 */ 1242 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1243 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1244 1245 #ifdef GEM_DEBUG 1246 if (ifp->if_flags & IFF_DEBUG) { 1247 int i; 1248 printf(" txsoft %p transmit chain:\n", txs); 1249 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1250 printf("descriptor %d: ", i); 1251 printf("gd_flags: 0x%016llx\t", (long long) 1252 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1253 printf("gd_addr: 0x%016llx\n", (long long) 1254 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1255 if (i == txs->txs_lastdesc) 1256 break; 1257 } 1258 } 1259 #endif 1260 1261 /* 1262 * In theory, we could harveast some descriptors before 1263 * the ring is empty, but that's a bit complicated. 1264 * 1265 * GEM_TX_COMPLETION points to the last descriptor 1266 * processed +1. 1267 */ 1268 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1269 #ifdef GEM_DEBUG 1270 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 1271 "txs->txs_lastdesc = %d, txlast = %d", 1272 txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1273 #endif 1274 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1275 if ((txlast >= txs->txs_firstdesc) && 1276 (txlast <= txs->txs_lastdesc)) 1277 break; 1278 } else { 1279 /* Ick -- this command wraps */ 1280 if ((txlast >= txs->txs_firstdesc) || 1281 (txlast <= txs->txs_lastdesc)) 1282 break; 1283 } 1284 1285 #ifdef GEM_DEBUG 1286 CTR0(KTR_GEM, "gem_tint: releasing a desc"); 1287 #endif 1288 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1289 1290 sc->sc_txfree += txs->txs_ndescs; 1291 1292 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1293 BUS_DMASYNC_POSTWRITE); 1294 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1295 if (txs->txs_mbuf != NULL) { 1296 m_freem(txs->txs_mbuf); 1297 txs->txs_mbuf = NULL; 1298 } 1299 1300 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1301 1302 ifp->if_opackets++; 1303 progress = 1; 1304 } 1305 1306 #ifdef GEM_DEBUG 1307 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 1308 "GEM_TX_DATA_PTR %llx " 1309 "GEM_TX_COMPLETION %x", 1310 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1311 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1312 GEM_TX_DATA_PTR_HI) << 32) | 1313 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1314 GEM_TX_DATA_PTR_LO), 1315 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION)); 1316 #endif 1317 1318 if (progress) { 1319 if (sc->sc_txfree == GEM_NTXDESC - 1) 1320 sc->sc_txwin = 0; 1321 1322 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1323 ifp->if_flags &= ~IFF_OACTIVE; 1324 gem_start(ifp); 1325 1326 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1327 ifp->if_timer = 0; 1328 } 1329 1330 #ifdef GEM_DEBUG 1331 CTR2(KTR_GEM, "%s: gem_tint: watchdog %d", 1332 device_get_name(sc->sc_dev), ifp->if_timer); 1333 #endif 1334 } 1335 1336 #if 0 1337 static void 1338 gem_rint_timeout(arg) 1339 void *arg; 1340 { 1341 1342 gem_rint((struct gem_softc *)arg); 1343 } 1344 #endif 1345 1346 /* 1347 * Receive interrupt. 1348 */ 1349 static void 1350 gem_rint(sc) 1351 struct gem_softc *sc; 1352 { 1353 struct ifnet *ifp = sc->sc_ifp; 1354 bus_space_tag_t t = sc->sc_bustag; 1355 bus_space_handle_t h = sc->sc_h; 1356 struct gem_rxsoft *rxs; 1357 struct mbuf *m; 1358 u_int64_t rxstat; 1359 u_int32_t rxcomp; 1360 int i, len, progress = 0; 1361 1362 callout_stop(&sc->sc_rx_ch); 1363 #ifdef GEM_DEBUG 1364 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 1365 #endif 1366 1367 /* 1368 * Read the completion register once. This limits 1369 * how long the following loop can execute. 1370 */ 1371 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1372 1373 #ifdef GEM_DEBUG 1374 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 1375 sc->sc_rxptr, rxcomp); 1376 #endif 1377 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1378 for (i = sc->sc_rxptr; i != rxcomp; 1379 i = GEM_NEXTRX(i)) { 1380 rxs = &sc->sc_rxsoft[i]; 1381 1382 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1383 1384 if (rxstat & GEM_RD_OWN) { 1385 #if 0 /* XXX: In case of emergency, re-enable this. */ 1386 /* 1387 * The descriptor is still marked as owned, although 1388 * it is supposed to have completed. This has been 1389 * observed on some machines. Just exiting here 1390 * might leave the packet sitting around until another 1391 * one arrives to trigger a new interrupt, which is 1392 * generally undesirable, so set up a timeout. 1393 */ 1394 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1395 gem_rint_timeout, sc); 1396 #endif 1397 break; 1398 } 1399 1400 progress++; 1401 ifp->if_ipackets++; 1402 1403 if (rxstat & GEM_RD_BAD_CRC) { 1404 ifp->if_ierrors++; 1405 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1406 GEM_INIT_RXDESC(sc, i); 1407 continue; 1408 } 1409 1410 #ifdef GEM_DEBUG 1411 if (ifp->if_flags & IFF_DEBUG) { 1412 printf(" rxsoft %p descriptor %d: ", rxs, i); 1413 printf("gd_flags: 0x%016llx\t", (long long) 1414 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1415 printf("gd_addr: 0x%016llx\n", (long long) 1416 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1417 } 1418 #endif 1419 1420 /* 1421 * No errors; receive the packet. Note the Gem 1422 * includes the CRC with every packet. 1423 */ 1424 len = GEM_RD_BUFLEN(rxstat); 1425 1426 /* 1427 * Allocate a new mbuf cluster. If that fails, we are 1428 * out of memory, and must drop the packet and recycle 1429 * the buffer that's already attached to this descriptor. 1430 */ 1431 m = rxs->rxs_mbuf; 1432 if (gem_add_rxbuf(sc, i) != 0) { 1433 ifp->if_ierrors++; 1434 GEM_INIT_RXDESC(sc, i); 1435 continue; 1436 } 1437 m->m_data += 2; /* We're already off by two */ 1438 1439 m->m_pkthdr.rcvif = ifp; 1440 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN; 1441 1442 /* Pass it on. */ 1443 (*ifp->if_input)(ifp, m); 1444 } 1445 1446 if (progress) { 1447 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1448 /* Update the receive pointer. */ 1449 if (i == sc->sc_rxptr) { 1450 device_printf(sc->sc_dev, "rint: ring wrap\n"); 1451 } 1452 sc->sc_rxptr = i; 1453 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1454 } 1455 1456 #ifdef GEM_DEBUG 1457 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", 1458 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 1459 #endif 1460 } 1461 1462 1463 /* 1464 * gem_add_rxbuf: 1465 * 1466 * Add a receive buffer to the indicated descriptor. 1467 */ 1468 static int 1469 gem_add_rxbuf(sc, idx) 1470 struct gem_softc *sc; 1471 int idx; 1472 { 1473 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1474 struct mbuf *m; 1475 int error; 1476 1477 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1478 if (m == NULL) 1479 return (ENOBUFS); 1480 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1481 1482 #ifdef GEM_DEBUG 1483 /* bzero the packet to check dma */ 1484 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1485 #endif 1486 1487 if (rxs->rxs_mbuf != NULL) { 1488 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1489 BUS_DMASYNC_POSTREAD); 1490 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1491 } 1492 1493 rxs->rxs_mbuf = m; 1494 1495 error = bus_dmamap_load_mbuf(sc->sc_rdmatag, rxs->rxs_dmamap, 1496 m, gem_rxdma_callback, rxs, BUS_DMA_NOWAIT); 1497 if (error != 0 || rxs->rxs_paddr == 0) { 1498 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " 1499 "%d\n", idx, error); 1500 panic("gem_add_rxbuf"); /* XXX */ 1501 } 1502 1503 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1504 1505 GEM_INIT_RXDESC(sc, idx); 1506 1507 return (0); 1508 } 1509 1510 1511 static void 1512 gem_eint(sc, status) 1513 struct gem_softc *sc; 1514 u_int status; 1515 { 1516 1517 if ((status & GEM_INTR_MIF) != 0) { 1518 device_printf(sc->sc_dev, "XXXlink status changed\n"); 1519 return; 1520 } 1521 1522 device_printf(sc->sc_dev, "status=%x\n", status); 1523 } 1524 1525 1526 void 1527 gem_intr(v) 1528 void *v; 1529 { 1530 struct gem_softc *sc = (struct gem_softc *)v; 1531 bus_space_tag_t t = sc->sc_bustag; 1532 bus_space_handle_t seb = sc->sc_h; 1533 u_int32_t status; 1534 1535 status = bus_space_read_4(t, seb, GEM_STATUS); 1536 #ifdef GEM_DEBUG 1537 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 1538 device_get_name(sc->sc_dev), (status>>19), 1539 (u_int)status); 1540 #endif 1541 1542 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1543 gem_eint(sc, status); 1544 1545 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1546 gem_tint(sc); 1547 1548 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1549 gem_rint(sc); 1550 1551 /* We should eventually do more than just print out error stats. */ 1552 if (status & GEM_INTR_TX_MAC) { 1553 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1554 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1555 device_printf(sc->sc_dev, "MAC tx fault, status %x\n", 1556 txstat); 1557 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1558 gem_init(sc); 1559 } 1560 if (status & GEM_INTR_RX_MAC) { 1561 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1562 if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1563 device_printf(sc->sc_dev, "MAC rx fault, status %x\n", 1564 rxstat); 1565 if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0) 1566 gem_init(sc); 1567 } 1568 } 1569 1570 1571 static void 1572 gem_watchdog(ifp) 1573 struct ifnet *ifp; 1574 { 1575 struct gem_softc *sc = ifp->if_softc; 1576 1577 #ifdef GEM_DEBUG 1578 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1579 "GEM_MAC_RX_CONFIG %x", 1580 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1581 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1582 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)); 1583 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 1584 "GEM_MAC_TX_CONFIG %x", 1585 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 1586 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS), 1587 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 1588 #endif 1589 1590 device_printf(sc->sc_dev, "device timeout\n"); 1591 ++ifp->if_oerrors; 1592 1593 /* Try to get more packets going. */ 1594 gem_start(ifp); 1595 } 1596 1597 /* 1598 * Initialize the MII Management Interface 1599 */ 1600 static void 1601 gem_mifinit(sc) 1602 struct gem_softc *sc; 1603 { 1604 bus_space_tag_t t = sc->sc_bustag; 1605 bus_space_handle_t mif = sc->sc_h; 1606 1607 /* Configure the MIF in frame mode */ 1608 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1609 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1610 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1611 } 1612 1613 /* 1614 * MII interface 1615 * 1616 * The GEM MII interface supports at least three different operating modes: 1617 * 1618 * Bitbang mode is implemented using data, clock and output enable registers. 1619 * 1620 * Frame mode is implemented by loading a complete frame into the frame 1621 * register and polling the valid bit for completion. 1622 * 1623 * Polling mode uses the frame register but completion is indicated by 1624 * an interrupt. 1625 * 1626 */ 1627 int 1628 gem_mii_readreg(dev, phy, reg) 1629 device_t dev; 1630 int phy, reg; 1631 { 1632 struct gem_softc *sc = device_get_softc(dev); 1633 bus_space_tag_t t = sc->sc_bustag; 1634 bus_space_handle_t mif = sc->sc_h; 1635 int n; 1636 u_int32_t v; 1637 1638 #ifdef GEM_DEBUG_PHY 1639 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1640 #endif 1641 1642 #if 0 1643 /* Select the desired PHY in the MIF configuration register */ 1644 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1645 /* Clear PHY select bit */ 1646 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1647 if (phy == GEM_PHYAD_EXTERNAL) 1648 /* Set PHY select bit to get at external device */ 1649 v |= GEM_MIF_CONFIG_PHY_SEL; 1650 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1651 #endif 1652 1653 /* Construct the frame command */ 1654 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1655 GEM_MIF_FRAME_READ; 1656 1657 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1658 for (n = 0; n < 100; n++) { 1659 DELAY(1); 1660 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1661 if (v & GEM_MIF_FRAME_TA0) 1662 return (v & GEM_MIF_FRAME_DATA); 1663 } 1664 1665 device_printf(sc->sc_dev, "mii_read timeout\n"); 1666 return (0); 1667 } 1668 1669 int 1670 gem_mii_writereg(dev, phy, reg, val) 1671 device_t dev; 1672 int phy, reg, val; 1673 { 1674 struct gem_softc *sc = device_get_softc(dev); 1675 bus_space_tag_t t = sc->sc_bustag; 1676 bus_space_handle_t mif = sc->sc_h; 1677 int n; 1678 u_int32_t v; 1679 1680 #ifdef GEM_DEBUG_PHY 1681 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 1682 #endif 1683 1684 #if 0 1685 /* Select the desired PHY in the MIF configuration register */ 1686 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1687 /* Clear PHY select bit */ 1688 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1689 if (phy == GEM_PHYAD_EXTERNAL) 1690 /* Set PHY select bit to get at external device */ 1691 v |= GEM_MIF_CONFIG_PHY_SEL; 1692 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1693 #endif 1694 /* Construct the frame command */ 1695 v = GEM_MIF_FRAME_WRITE | 1696 (phy << GEM_MIF_PHY_SHIFT) | 1697 (reg << GEM_MIF_REG_SHIFT) | 1698 (val & GEM_MIF_FRAME_DATA); 1699 1700 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1701 for (n = 0; n < 100; n++) { 1702 DELAY(1); 1703 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1704 if (v & GEM_MIF_FRAME_TA0) 1705 return (1); 1706 } 1707 1708 device_printf(sc->sc_dev, "mii_write timeout\n"); 1709 return (0); 1710 } 1711 1712 void 1713 gem_mii_statchg(dev) 1714 device_t dev; 1715 { 1716 struct gem_softc *sc = device_get_softc(dev); 1717 #ifdef GEM_DEBUG 1718 int instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 1719 #endif 1720 bus_space_tag_t t = sc->sc_bustag; 1721 bus_space_handle_t mac = sc->sc_h; 1722 u_int32_t v; 1723 1724 #ifdef GEM_DEBUG 1725 if (sc->sc_debug) 1726 printf("gem_mii_statchg: status change: phy = %d\n", 1727 sc->sc_phys[instance]); 1728 #endif 1729 1730 /* Set tx full duplex options */ 1731 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1732 DELAY(10000); /* reg must be cleared and delay before changing. */ 1733 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1734 GEM_MAC_TX_ENABLE; 1735 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 1736 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1737 } 1738 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1739 1740 /* XIF Configuration */ 1741 /* We should really calculate all this rather than rely on defaults */ 1742 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1743 v = GEM_MAC_XIF_LINK_LED; 1744 v |= GEM_MAC_XIF_TX_MII_ENA; 1745 1746 /* If an external transceiver is connected, enable its MII drivers */ 1747 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1748 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1749 /* External MII needs echo disable if half duplex. */ 1750 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 1751 /* turn on full duplex LED */ 1752 v |= GEM_MAC_XIF_FDPLX_LED; 1753 else 1754 /* half duplex -- disable echo */ 1755 v |= GEM_MAC_XIF_ECHO_DISABL; 1756 1757 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T) 1758 v |= GEM_MAC_XIF_GMII_MODE; 1759 else 1760 v &= ~GEM_MAC_XIF_GMII_MODE; 1761 } else { 1762 /* Internal MII needs buf enable */ 1763 v |= GEM_MAC_XIF_MII_BUF_ENA; 1764 } 1765 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1766 } 1767 1768 int 1769 gem_mediachange(ifp) 1770 struct ifnet *ifp; 1771 { 1772 struct gem_softc *sc = ifp->if_softc; 1773 1774 /* XXX Add support for serial media. */ 1775 1776 return (mii_mediachg(sc->sc_mii)); 1777 } 1778 1779 void 1780 gem_mediastatus(ifp, ifmr) 1781 struct ifnet *ifp; 1782 struct ifmediareq *ifmr; 1783 { 1784 struct gem_softc *sc = ifp->if_softc; 1785 1786 if ((ifp->if_flags & IFF_UP) == 0) 1787 return; 1788 1789 mii_pollstat(sc->sc_mii); 1790 ifmr->ifm_active = sc->sc_mii->mii_media_active; 1791 ifmr->ifm_status = sc->sc_mii->mii_media_status; 1792 } 1793 1794 /* 1795 * Process an ioctl request. 1796 */ 1797 static int 1798 gem_ioctl(ifp, cmd, data) 1799 struct ifnet *ifp; 1800 u_long cmd; 1801 caddr_t data; 1802 { 1803 struct gem_softc *sc = ifp->if_softc; 1804 struct ifreq *ifr = (struct ifreq *)data; 1805 int s, error = 0; 1806 1807 switch (cmd) { 1808 case SIOCSIFADDR: 1809 case SIOCGIFADDR: 1810 case SIOCSIFMTU: 1811 error = ether_ioctl(ifp, cmd, data); 1812 break; 1813 case SIOCSIFFLAGS: 1814 if (ifp->if_flags & IFF_UP) { 1815 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC) 1816 gem_setladrf(sc); 1817 else 1818 gem_init(sc); 1819 } else { 1820 if (ifp->if_flags & IFF_RUNNING) 1821 gem_stop(ifp, 0); 1822 } 1823 sc->sc_ifflags = ifp->if_flags; 1824 error = 0; 1825 break; 1826 case SIOCADDMULTI: 1827 case SIOCDELMULTI: 1828 gem_setladrf(sc); 1829 error = 0; 1830 break; 1831 case SIOCGIFMEDIA: 1832 case SIOCSIFMEDIA: 1833 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 1834 break; 1835 default: 1836 error = ENOTTY; 1837 break; 1838 } 1839 1840 /* Try to get things going again */ 1841 if (ifp->if_flags & IFF_UP) 1842 gem_start(ifp); 1843 splx(s); 1844 return (error); 1845 } 1846 1847 /* 1848 * Set up the logical address filter. 1849 */ 1850 static void 1851 gem_setladrf(sc) 1852 struct gem_softc *sc; 1853 { 1854 struct ifnet *ifp = sc->sc_ifp; 1855 struct ifmultiaddr *inm; 1856 bus_space_tag_t t = sc->sc_bustag; 1857 bus_space_handle_t h = sc->sc_h; 1858 u_int32_t crc; 1859 u_int32_t hash[16]; 1860 u_int32_t v; 1861 int i; 1862 1863 /* Get current RX configuration */ 1864 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1865 1866 /* 1867 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1868 * and hash filter. Depending on the case, the right bit will be 1869 * enabled. 1870 */ 1871 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1872 GEM_MAC_RX_PROMISC_GRP); 1873 1874 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1875 /* Turn on promiscuous mode */ 1876 v |= GEM_MAC_RX_PROMISCUOUS; 1877 goto chipit; 1878 } 1879 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 1880 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1881 ifp->if_flags |= IFF_ALLMULTI; 1882 v |= GEM_MAC_RX_PROMISC_GRP; 1883 goto chipit; 1884 } 1885 1886 /* 1887 * Set up multicast address filter by passing all multicast addresses 1888 * through a crc generator, and then using the high order 8 bits as an 1889 * index into the 256 bit logical address filter. The high order 4 1890 * bits selects the word, while the other 4 bits select the bit within 1891 * the word (where bit 0 is the MSB). 1892 */ 1893 1894 /* Clear hash table */ 1895 memset(hash, 0, sizeof(hash)); 1896 1897 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 1898 if (inm->ifma_addr->sa_family != AF_LINK) 1899 continue; 1900 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1901 inm->ifma_addr), ETHER_ADDR_LEN); 1902 1903 /* Just want the 8 most significant bits. */ 1904 crc >>= 24; 1905 1906 /* Set the corresponding bit in the filter. */ 1907 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1908 } 1909 1910 v |= GEM_MAC_RX_HASH_FILTER; 1911 ifp->if_flags &= ~IFF_ALLMULTI; 1912 1913 /* Now load the hash table into the chip (if we are using it) */ 1914 for (i = 0; i < 16; i++) { 1915 bus_space_write_4(t, h, 1916 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1917 hash[i]); 1918 } 1919 1920 chipit: 1921 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1922 } 1923