1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 3 * 4 * Copyright (C) 2001 Eduardo Horvath. 5 * Copyright (c) 2001-2003 Thomas Moestl 6 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 38 */ 39 40 #if 0 41 #define GEM_DEBUG 42 #endif 43 44 #if 0 /* XXX: In case of emergency, re-enable this. */ 45 #define GEM_RINT_TIMEOUT 46 #endif 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/callout.h> 52 #include <sys/endian.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/lock.h> 57 #include <sys/module.h> 58 #include <sys/mutex.h> 59 #include <sys/socket.h> 60 #include <sys/sockio.h> 61 #include <sys/rman.h> 62 63 #include <net/bpf.h> 64 #include <net/ethernet.h> 65 #include <net/if.h> 66 #include <net/if_var.h> 67 #include <net/if_arp.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_types.h> 71 #include <net/if_vlan_var.h> 72 73 #include <netinet/in.h> 74 #include <netinet/in_systm.h> 75 #include <netinet/ip.h> 76 #include <netinet/tcp.h> 77 #include <netinet/udp.h> 78 79 #include <machine/bus.h> 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <dev/gem/if_gemreg.h> 85 #include <dev/gem/if_gemvar.h> 86 87 CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 88 CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 89 90 #define GEM_TRIES 10000 91 92 /* 93 * The hardware supports basic TCP/UDP checksum offloading. However, 94 * the hardware doesn't compensate the checksum for UDP datagram which 95 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 96 * by default. It can be reactivated by setting special link option 97 * link0 with ifconfig(8). 98 */ 99 #define GEM_CSUM_FEATURES (CSUM_TCP) 100 101 static int gem_add_rxbuf(struct gem_softc *sc, int idx); 102 static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 103 uint32_t clr, uint32_t set); 104 static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 105 int nsegs, int error); 106 static int gem_disable_rx(struct gem_softc *sc); 107 static int gem_disable_tx(struct gem_softc *sc); 108 static void gem_eint(struct gem_softc *sc, u_int status); 109 static void gem_init(void *xsc); 110 static void gem_init_locked(struct gem_softc *sc); 111 static void gem_init_regs(struct gem_softc *sc); 112 static int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 113 static int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 114 static int gem_meminit(struct gem_softc *sc); 115 static void gem_mifinit(struct gem_softc *sc); 116 static void gem_reset(struct gem_softc *sc); 117 static int gem_reset_rx(struct gem_softc *sc); 118 static void gem_reset_rxdma(struct gem_softc *sc); 119 static int gem_reset_tx(struct gem_softc *sc); 120 static u_int gem_ringsize(u_int sz); 121 static void gem_rint(struct gem_softc *sc); 122 #ifdef GEM_RINT_TIMEOUT 123 static void gem_rint_timeout(void *arg); 124 #endif 125 static inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 126 static void gem_rxdrain(struct gem_softc *sc); 127 static void gem_setladrf(struct gem_softc *sc); 128 static void gem_start(struct ifnet *ifp); 129 static void gem_start_locked(struct ifnet *ifp); 130 static void gem_stop(struct ifnet *ifp, int disable); 131 static void gem_tick(void *arg); 132 static void gem_tint(struct gem_softc *sc); 133 static inline void gem_txkick(struct gem_softc *sc); 134 static int gem_watchdog(struct gem_softc *sc); 135 136 DRIVER_MODULE(miibus, gem, miibus_driver, 0, 0); 137 MODULE_DEPEND(gem, miibus, 1, 1, 1); 138 139 #ifdef GEM_DEBUG 140 #include <sys/ktr.h> 141 #define KTR_GEM KTR_SPARE2 142 #endif 143 144 #define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 145 gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 146 #define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 147 gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 148 149 int 150 gem_attach(struct gem_softc *sc) 151 { 152 struct gem_txsoft *txs; 153 struct ifnet *ifp; 154 int error, i, phy; 155 uint32_t v; 156 157 if (bootverbose) 158 device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 159 160 /* Set up ifnet structure. */ 161 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 162 if (ifp == NULL) 163 return (ENOSPC); 164 sc->sc_csum_features = GEM_CSUM_FEATURES; 165 ifp->if_softc = sc; 166 if_initname(ifp, device_get_name(sc->sc_dev), 167 device_get_unit(sc->sc_dev)); 168 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 169 ifp->if_start = gem_start; 170 ifp->if_ioctl = gem_ioctl; 171 ifp->if_init = gem_init; 172 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 173 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 174 IFQ_SET_READY(&ifp->if_snd); 175 176 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 177 #ifdef GEM_RINT_TIMEOUT 178 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 179 #endif 180 181 /* Make sure the chip is stopped. */ 182 gem_reset(sc); 183 184 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 185 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 186 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 187 NULL, &sc->sc_pdmatag); 188 if (error != 0) 189 goto fail_ifnet; 190 191 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 192 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 193 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 194 if (error != 0) 195 goto fail_ptag; 196 197 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 198 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 199 MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 200 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 201 if (error != 0) 202 goto fail_rtag; 203 204 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 205 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 206 sizeof(struct gem_control_data), 1, 207 sizeof(struct gem_control_data), 0, 208 NULL, NULL, &sc->sc_cdmatag); 209 if (error != 0) 210 goto fail_ttag; 211 212 /* 213 * Allocate the control data structures, create and load the 214 * DMA map for it. 215 */ 216 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 217 (void **)&sc->sc_control_data, 218 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 219 &sc->sc_cddmamap)) != 0) { 220 device_printf(sc->sc_dev, 221 "unable to allocate control data, error = %d\n", error); 222 goto fail_ctag; 223 } 224 225 sc->sc_cddma = 0; 226 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 227 sc->sc_control_data, sizeof(struct gem_control_data), 228 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 229 device_printf(sc->sc_dev, 230 "unable to load control data DMA map, error = %d\n", 231 error); 232 goto fail_cmem; 233 } 234 235 /* 236 * Initialize the transmit job descriptors. 237 */ 238 STAILQ_INIT(&sc->sc_txfreeq); 239 STAILQ_INIT(&sc->sc_txdirtyq); 240 241 /* 242 * Create the transmit buffer DMA maps. 243 */ 244 error = ENOMEM; 245 for (i = 0; i < GEM_TXQUEUELEN; i++) { 246 txs = &sc->sc_txsoft[i]; 247 txs->txs_mbuf = NULL; 248 txs->txs_ndescs = 0; 249 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 250 &txs->txs_dmamap)) != 0) { 251 device_printf(sc->sc_dev, 252 "unable to create TX DMA map %d, error = %d\n", 253 i, error); 254 goto fail_txd; 255 } 256 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 257 } 258 259 /* 260 * Create the receive buffer DMA maps. 261 */ 262 for (i = 0; i < GEM_NRXDESC; i++) { 263 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 264 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 265 device_printf(sc->sc_dev, 266 "unable to create RX DMA map %d, error = %d\n", 267 i, error); 268 goto fail_rxd; 269 } 270 sc->sc_rxsoft[i].rxs_mbuf = NULL; 271 } 272 273 /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 274 if ((sc->sc_flags & GEM_SERDES) != 0) 275 goto serdes; 276 277 /* Bad things will happen when touching this register on ERI. */ 278 if (sc->sc_variant != GEM_SUN_ERI) { 279 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 280 GEM_MII_DATAPATH_MII); 281 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 282 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 283 } 284 285 gem_mifinit(sc); 286 287 /* 288 * Look for an external PHY. 289 */ 290 error = ENXIO; 291 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 292 if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 293 v |= GEM_MIF_CONFIG_PHY_SEL; 294 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 295 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 296 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 297 switch (sc->sc_variant) { 298 case GEM_SUN_ERI: 299 phy = GEM_PHYAD_EXTERNAL; 300 break; 301 default: 302 phy = MII_PHY_ANY; 303 break; 304 } 305 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 306 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 307 MII_OFFSET_ANY, MIIF_DOPAUSE); 308 } 309 310 /* 311 * Fall back on an internal PHY if no external PHY was found. 312 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 313 * trusted when the firmware has powered down the chip. 314 */ 315 if (error != 0 && 316 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 317 v &= ~GEM_MIF_CONFIG_PHY_SEL; 318 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 319 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 320 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 321 switch (sc->sc_variant) { 322 case GEM_SUN_ERI: 323 case GEM_APPLE_K2_GMAC: 324 phy = GEM_PHYAD_INTERNAL; 325 break; 326 case GEM_APPLE_GMAC: 327 phy = GEM_PHYAD_EXTERNAL; 328 break; 329 default: 330 phy = MII_PHY_ANY; 331 break; 332 } 333 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 334 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 335 MII_OFFSET_ANY, MIIF_DOPAUSE); 336 } 337 338 /* 339 * Try the external PCS SERDES if we didn't find any PHYs. 340 */ 341 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 342 serdes: 343 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 344 GEM_MII_DATAPATH_SERDES); 345 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 346 BUS_SPACE_BARRIER_WRITE); 347 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 348 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 349 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 350 BUS_SPACE_BARRIER_WRITE); 351 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 352 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 353 BUS_SPACE_BARRIER_WRITE); 354 sc->sc_flags |= GEM_SERDES; 355 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 356 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, 357 GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 358 } 359 if (error != 0) { 360 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 361 goto fail_rxd; 362 } 363 sc->sc_mii = device_get_softc(sc->sc_miibus); 364 365 /* 366 * From this point forward, the attachment cannot fail. A failure 367 * before this point releases all resources that may have been 368 * allocated. 369 */ 370 371 /* Get RX FIFO size. */ 372 sc->sc_rxfifosize = 64 * 373 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 374 375 /* Get TX FIFO size. */ 376 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 377 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 378 sc->sc_rxfifosize / 1024, v / 16); 379 380 /* Attach the interface. */ 381 ether_ifattach(ifp, sc->sc_enaddr); 382 383 /* 384 * Tell the upper layer(s) we support long frames/checksum offloads. 385 */ 386 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 387 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 388 ifp->if_hwassist |= sc->sc_csum_features; 389 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 390 391 return (0); 392 393 /* 394 * Free any resources we've allocated during the failed attach 395 * attempt. Do this in reverse order and fall through. 396 */ 397 fail_rxd: 398 for (i = 0; i < GEM_NRXDESC; i++) 399 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 400 bus_dmamap_destroy(sc->sc_rdmatag, 401 sc->sc_rxsoft[i].rxs_dmamap); 402 fail_txd: 403 for (i = 0; i < GEM_TXQUEUELEN; i++) 404 if (sc->sc_txsoft[i].txs_dmamap != NULL) 405 bus_dmamap_destroy(sc->sc_tdmatag, 406 sc->sc_txsoft[i].txs_dmamap); 407 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 408 fail_cmem: 409 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 410 sc->sc_cddmamap); 411 fail_ctag: 412 bus_dma_tag_destroy(sc->sc_cdmatag); 413 fail_ttag: 414 bus_dma_tag_destroy(sc->sc_tdmatag); 415 fail_rtag: 416 bus_dma_tag_destroy(sc->sc_rdmatag); 417 fail_ptag: 418 bus_dma_tag_destroy(sc->sc_pdmatag); 419 fail_ifnet: 420 if_free(ifp); 421 return (error); 422 } 423 424 void 425 gem_detach(struct gem_softc *sc) 426 { 427 struct ifnet *ifp = sc->sc_ifp; 428 int i; 429 430 ether_ifdetach(ifp); 431 GEM_LOCK(sc); 432 gem_stop(ifp, 1); 433 GEM_UNLOCK(sc); 434 callout_drain(&sc->sc_tick_ch); 435 #ifdef GEM_RINT_TIMEOUT 436 callout_drain(&sc->sc_rx_ch); 437 #endif 438 if_free(ifp); 439 device_delete_child(sc->sc_dev, sc->sc_miibus); 440 441 for (i = 0; i < GEM_NRXDESC; i++) 442 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 443 bus_dmamap_destroy(sc->sc_rdmatag, 444 sc->sc_rxsoft[i].rxs_dmamap); 445 for (i = 0; i < GEM_TXQUEUELEN; i++) 446 if (sc->sc_txsoft[i].txs_dmamap != NULL) 447 bus_dmamap_destroy(sc->sc_tdmatag, 448 sc->sc_txsoft[i].txs_dmamap); 449 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 450 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 451 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 452 sc->sc_cddmamap); 453 bus_dma_tag_destroy(sc->sc_cdmatag); 454 bus_dma_tag_destroy(sc->sc_tdmatag); 455 bus_dma_tag_destroy(sc->sc_rdmatag); 456 bus_dma_tag_destroy(sc->sc_pdmatag); 457 } 458 459 void 460 gem_suspend(struct gem_softc *sc) 461 { 462 struct ifnet *ifp = sc->sc_ifp; 463 464 GEM_LOCK(sc); 465 gem_stop(ifp, 0); 466 GEM_UNLOCK(sc); 467 } 468 469 void 470 gem_resume(struct gem_softc *sc) 471 { 472 struct ifnet *ifp = sc->sc_ifp; 473 474 GEM_LOCK(sc); 475 /* 476 * On resume all registers have to be initialized again like 477 * after power-on. 478 */ 479 sc->sc_flags &= ~GEM_INITED; 480 if (ifp->if_flags & IFF_UP) 481 gem_init_locked(sc); 482 GEM_UNLOCK(sc); 483 } 484 485 static inline void 486 gem_rxcksum(struct mbuf *m, uint64_t flags) 487 { 488 struct ether_header *eh; 489 struct ip *ip; 490 struct udphdr *uh; 491 uint16_t *opts; 492 int32_t hlen, len, pktlen; 493 uint32_t temp32; 494 uint16_t cksum; 495 496 pktlen = m->m_pkthdr.len; 497 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 498 return; 499 eh = mtod(m, struct ether_header *); 500 if (eh->ether_type != htons(ETHERTYPE_IP)) 501 return; 502 ip = (struct ip *)(eh + 1); 503 if (ip->ip_v != IPVERSION) 504 return; 505 506 hlen = ip->ip_hl << 2; 507 pktlen -= sizeof(struct ether_header); 508 if (hlen < sizeof(struct ip)) 509 return; 510 if (ntohs(ip->ip_len) < hlen) 511 return; 512 if (ntohs(ip->ip_len) != pktlen) 513 return; 514 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 515 return; /* Cannot handle fragmented packet. */ 516 517 switch (ip->ip_p) { 518 case IPPROTO_TCP: 519 if (pktlen < (hlen + sizeof(struct tcphdr))) 520 return; 521 break; 522 case IPPROTO_UDP: 523 if (pktlen < (hlen + sizeof(struct udphdr))) 524 return; 525 uh = (struct udphdr *)((uint8_t *)ip + hlen); 526 if (uh->uh_sum == 0) 527 return; /* no checksum */ 528 break; 529 default: 530 return; 531 } 532 533 cksum = ~(flags & GEM_RD_CHECKSUM); 534 /* checksum fixup for IP options */ 535 len = hlen - sizeof(struct ip); 536 if (len > 0) { 537 opts = (uint16_t *)(ip + 1); 538 for (; len > 0; len -= sizeof(uint16_t), opts++) { 539 temp32 = cksum - *opts; 540 temp32 = (temp32 >> 16) + (temp32 & 65535); 541 cksum = temp32 & 65535; 542 } 543 } 544 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 545 m->m_pkthdr.csum_data = cksum; 546 } 547 548 static void 549 gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 550 { 551 struct gem_softc *sc = xsc; 552 553 if (error != 0) 554 return; 555 if (nsegs != 1) 556 panic("%s: bad control buffer segment count", __func__); 557 sc->sc_cddma = segs[0].ds_addr; 558 } 559 560 static void 561 gem_tick(void *arg) 562 { 563 struct gem_softc *sc = arg; 564 struct ifnet *ifp = sc->sc_ifp; 565 uint32_t v; 566 567 GEM_LOCK_ASSERT(sc, MA_OWNED); 568 569 /* 570 * Unload collision and error counters. 571 */ 572 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 573 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 574 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT)); 575 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 576 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 577 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v); 578 if_inc_counter(ifp, IFCOUNTER_OERRORS, v); 579 if_inc_counter(ifp, IFCOUNTER_IERRORS, 580 GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 581 GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 582 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 583 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL)); 584 585 /* 586 * Then clear the hardware counters. 587 */ 588 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 589 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 590 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 591 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 592 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 593 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 594 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 595 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 596 597 mii_tick(sc->sc_mii); 598 599 if (gem_watchdog(sc) == EJUSTRETURN) 600 return; 601 602 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 603 } 604 605 static int 606 gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 607 uint32_t set) 608 { 609 int i; 610 uint32_t reg; 611 612 for (i = GEM_TRIES; i--; DELAY(100)) { 613 reg = GEM_BANKN_READ_M(bank, 4, sc, r); 614 if ((reg & clr) == 0 && (reg & set) == set) 615 return (1); 616 } 617 return (0); 618 } 619 620 static void 621 gem_reset(struct gem_softc *sc) 622 { 623 624 #ifdef GEM_DEBUG 625 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 626 #endif 627 gem_reset_rx(sc); 628 gem_reset_tx(sc); 629 630 /* Do a full reset. */ 631 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX | 632 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE << 633 GEM_RESET_CLSZ_SHFT : 0)); 634 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 635 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 636 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 637 device_printf(sc->sc_dev, "cannot reset device\n"); 638 } 639 640 static void 641 gem_rxdrain(struct gem_softc *sc) 642 { 643 struct gem_rxsoft *rxs; 644 int i; 645 646 for (i = 0; i < GEM_NRXDESC; i++) { 647 rxs = &sc->sc_rxsoft[i]; 648 if (rxs->rxs_mbuf != NULL) { 649 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 650 BUS_DMASYNC_POSTREAD); 651 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 652 m_freem(rxs->rxs_mbuf); 653 rxs->rxs_mbuf = NULL; 654 } 655 } 656 } 657 658 static void 659 gem_stop(struct ifnet *ifp, int disable) 660 { 661 struct gem_softc *sc = ifp->if_softc; 662 struct gem_txsoft *txs; 663 664 #ifdef GEM_DEBUG 665 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 666 #endif 667 668 callout_stop(&sc->sc_tick_ch); 669 #ifdef GEM_RINT_TIMEOUT 670 callout_stop(&sc->sc_rx_ch); 671 #endif 672 673 gem_reset_tx(sc); 674 gem_reset_rx(sc); 675 676 /* 677 * Release any queued transmit buffers. 678 */ 679 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 680 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 681 if (txs->txs_ndescs != 0) { 682 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 683 BUS_DMASYNC_POSTWRITE); 684 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 685 if (txs->txs_mbuf != NULL) { 686 m_freem(txs->txs_mbuf); 687 txs->txs_mbuf = NULL; 688 } 689 } 690 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 691 } 692 693 if (disable) 694 gem_rxdrain(sc); 695 696 /* 697 * Mark the interface down and cancel the watchdog timer. 698 */ 699 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 700 sc->sc_flags &= ~GEM_LINK; 701 sc->sc_wdog_timer = 0; 702 } 703 704 static int 705 gem_reset_rx(struct gem_softc *sc) 706 { 707 708 /* 709 * Resetting while DMA is in progress can cause a bus hang, so we 710 * disable DMA first. 711 */ 712 (void)gem_disable_rx(sc); 713 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 714 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 715 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 716 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 717 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 718 719 /* Wait 5ms extra. */ 720 DELAY(5000); 721 722 /* Reset the ERX. */ 723 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | 724 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE << 725 GEM_RESET_CLSZ_SHFT : 0)); 726 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 727 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 728 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX, 0)) { 729 device_printf(sc->sc_dev, "cannot reset receiver\n"); 730 return (1); 731 } 732 733 /* Finally, reset RX MAC. */ 734 GEM_BANK1_WRITE_4(sc, GEM_MAC_RXRESET, 1); 735 GEM_BANK1_BARRIER(sc, GEM_MAC_RXRESET, 4, 736 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 737 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RXRESET, 1, 0)) { 738 device_printf(sc->sc_dev, "cannot reset RX MAC\n"); 739 return (1); 740 } 741 742 return (0); 743 } 744 745 /* 746 * Reset the receiver DMA engine. 747 * 748 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 749 * etc in order to reset the receiver DMA engine only and not do a full 750 * reset which amongst others also downs the link and clears the FIFOs. 751 */ 752 static void 753 gem_reset_rxdma(struct gem_softc *sc) 754 { 755 int i; 756 757 if (gem_reset_rx(sc) != 0) { 758 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 759 return (gem_init_locked(sc)); 760 } 761 for (i = 0; i < GEM_NRXDESC; i++) 762 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 763 GEM_UPDATE_RXDESC(sc, i); 764 sc->sc_rxptr = 0; 765 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 766 767 /* NOTE: we use only 32-bit DMA addresses here. */ 768 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 769 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 770 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 771 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 772 gem_ringsize(GEM_NRXDESC /* XXX */) | 773 ((ETHER_HDR_LEN + sizeof(struct ip)) << 774 GEM_RX_CONFIG_CXM_START_SHFT) | 775 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 776 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 777 /* Adjusting for the SBus clock probably isn't worth the fuzz. */ 778 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 779 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 780 GEM_RX_BLANKING_TIME_SHIFT) | 6); 781 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 782 (3 * sc->sc_rxfifosize / 256) | 783 ((sc->sc_rxfifosize / 256) << 12)); 784 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 785 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 786 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 787 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 788 /* 789 * Clear the RX filter and reprogram it. This will also set the 790 * current RX MAC configuration and enable it. 791 */ 792 gem_setladrf(sc); 793 } 794 795 static int 796 gem_reset_tx(struct gem_softc *sc) 797 { 798 799 /* 800 * Resetting while DMA is in progress can cause a bus hang, so we 801 * disable DMA first. 802 */ 803 (void)gem_disable_tx(sc); 804 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 805 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 806 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 807 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 808 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 809 810 /* Wait 5ms extra. */ 811 DELAY(5000); 812 813 /* Finally, reset the ETX. */ 814 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX | 815 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE << 816 GEM_RESET_CLSZ_SHFT : 0)); 817 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 818 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 819 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_TX, 0)) { 820 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 821 return (1); 822 } 823 return (0); 824 } 825 826 static int 827 gem_disable_rx(struct gem_softc *sc) 828 { 829 830 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 831 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 832 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 833 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 834 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 835 return (1); 836 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 837 return (0); 838 } 839 840 static int 841 gem_disable_tx(struct gem_softc *sc) 842 { 843 844 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 845 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 846 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 847 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 848 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 849 return (1); 850 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 851 return (0); 852 } 853 854 static int 855 gem_meminit(struct gem_softc *sc) 856 { 857 struct gem_rxsoft *rxs; 858 int error, i; 859 860 GEM_LOCK_ASSERT(sc, MA_OWNED); 861 862 /* 863 * Initialize the transmit descriptor ring. 864 */ 865 for (i = 0; i < GEM_NTXDESC; i++) { 866 sc->sc_txdescs[i].gd_flags = 0; 867 sc->sc_txdescs[i].gd_addr = 0; 868 } 869 sc->sc_txfree = GEM_MAXTXFREE; 870 sc->sc_txnext = 0; 871 sc->sc_txwin = 0; 872 873 /* 874 * Initialize the receive descriptor and receive job 875 * descriptor rings. 876 */ 877 for (i = 0; i < GEM_NRXDESC; i++) { 878 rxs = &sc->sc_rxsoft[i]; 879 if (rxs->rxs_mbuf == NULL) { 880 if ((error = gem_add_rxbuf(sc, i)) != 0) { 881 device_printf(sc->sc_dev, 882 "unable to allocate or map RX buffer %d, " 883 "error = %d\n", i, error); 884 /* 885 * XXX we should attempt to run with fewer 886 * receive buffers instead of just failing. 887 */ 888 gem_rxdrain(sc); 889 return (1); 890 } 891 } else 892 GEM_INIT_RXDESC(sc, i); 893 } 894 sc->sc_rxptr = 0; 895 896 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 897 898 return (0); 899 } 900 901 static u_int 902 gem_ringsize(u_int sz) 903 { 904 905 switch (sz) { 906 case 32: 907 return (GEM_RING_SZ_32); 908 case 64: 909 return (GEM_RING_SZ_64); 910 case 128: 911 return (GEM_RING_SZ_128); 912 case 256: 913 return (GEM_RING_SZ_256); 914 case 512: 915 return (GEM_RING_SZ_512); 916 case 1024: 917 return (GEM_RING_SZ_1024); 918 case 2048: 919 return (GEM_RING_SZ_2048); 920 case 4096: 921 return (GEM_RING_SZ_4096); 922 case 8192: 923 return (GEM_RING_SZ_8192); 924 default: 925 printf("%s: invalid ring size %d\n", __func__, sz); 926 return (GEM_RING_SZ_32); 927 } 928 } 929 930 static void 931 gem_init(void *xsc) 932 { 933 struct gem_softc *sc = xsc; 934 935 GEM_LOCK(sc); 936 gem_init_locked(sc); 937 GEM_UNLOCK(sc); 938 } 939 940 /* 941 * Initialization of interface; set up initialization block 942 * and transmit/receive descriptor rings. 943 */ 944 static void 945 gem_init_locked(struct gem_softc *sc) 946 { 947 struct ifnet *ifp = sc->sc_ifp; 948 uint32_t v; 949 950 GEM_LOCK_ASSERT(sc, MA_OWNED); 951 952 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 953 return; 954 955 #ifdef GEM_DEBUG 956 CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 957 __func__); 958 #endif 959 /* 960 * Initialization sequence. The numbered steps below correspond 961 * to the sequence outlined in section 6.3.5.1 in the Ethernet 962 * Channel Engine manual (part of the PCIO manual). 963 * See also the STP2002-STQ document from Sun Microsystems. 964 */ 965 966 /* step 1 & 2. Reset the Ethernet Channel. */ 967 gem_stop(ifp, 0); 968 gem_reset(sc); 969 #ifdef GEM_DEBUG 970 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 971 __func__); 972 #endif 973 974 if ((sc->sc_flags & GEM_SERDES) == 0) 975 /* Re-initialize the MIF. */ 976 gem_mifinit(sc); 977 978 /* step 3. Setup data structures in host memory. */ 979 if (gem_meminit(sc) != 0) 980 return; 981 982 /* step 4. TX MAC registers & counters */ 983 gem_init_regs(sc); 984 985 /* step 5. RX MAC registers & counters */ 986 987 /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 988 /* NOTE: we use only 32-bit DMA addresses here. */ 989 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 990 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 991 992 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 993 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 994 #ifdef GEM_DEBUG 995 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 996 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 997 #endif 998 999 /* step 8. Global Configuration & Interrupt Mask */ 1000 1001 /* 1002 * Set the internal arbitration to "infinite" bursts of the 1003 * maximum length of 31 * 64 bytes so DMA transfers aren't 1004 * split up in cache line size chunks. This greatly improves 1005 * RX performance. 1006 * Enable silicon bug workarounds for the Apple variants. 1007 */ 1008 GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 1009 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1010 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 1011 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1012 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1013 1014 GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 1015 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 1016 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 1017 GEM_INTR_BERR 1018 #ifdef GEM_DEBUG 1019 | GEM_INTR_PCS | GEM_INTR_MIF 1020 #endif 1021 )); 1022 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 1023 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1024 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 1025 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1026 GEM_MAC_TX_PEAK_EXP); 1027 #ifdef GEM_DEBUG 1028 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 1029 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 1030 #else 1031 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 1032 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1033 #endif 1034 1035 /* step 9. ETX Configuration: use mostly default values. */ 1036 1037 /* Enable DMA. */ 1038 v = gem_ringsize(GEM_NTXDESC); 1039 /* Set TX FIFO threshold and enable DMA. */ 1040 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1041 GEM_TX_CONFIG_TXFIFO_TH; 1042 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 1043 1044 /* step 10. ERX Configuration */ 1045 1046 /* Encode Receive Descriptor ring size. */ 1047 v = gem_ringsize(GEM_NRXDESC /* XXX */); 1048 /* RX TCP/UDP checksum offset */ 1049 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 1050 GEM_RX_CONFIG_CXM_START_SHFT); 1051 /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1052 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1053 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1054 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1055 GEM_RX_CONFIG_RXDMA_EN); 1056 1057 /* Adjusting for the SBus clock probably isn't worth the fuzz. */ 1058 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1059 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1060 GEM_RX_BLANKING_TIME_SHIFT) | 6); 1061 1062 /* 1063 * The following value is for an OFF Threshold of about 3/4 full 1064 * and an ON Threshold of 1/4 full. 1065 */ 1066 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 1067 (3 * sc->sc_rxfifosize / 256) | 1068 ((sc->sc_rxfifosize / 256) << 12)); 1069 1070 /* step 11. Configure Media. */ 1071 1072 /* step 12. RX_MAC Configuration Register */ 1073 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1074 v &= ~GEM_MAC_RX_ENABLE; 1075 v |= GEM_MAC_RX_STRIP_CRC; 1076 sc->sc_mac_rxcfg = v; 1077 /* 1078 * Clear the RX filter and reprogram it. This will also set the 1079 * current RX MAC configuration and enable it. 1080 */ 1081 gem_setladrf(sc); 1082 1083 /* step 13. TX_MAC Configuration Register */ 1084 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1085 v |= GEM_MAC_TX_ENABLE; 1086 (void)gem_disable_tx(sc); 1087 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1088 1089 /* step 14. Issue Transmit Pending command. */ 1090 1091 /* step 15. Give the receiver a swift kick. */ 1092 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 1093 1094 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1095 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1096 1097 mii_mediachg(sc->sc_mii); 1098 1099 /* Start the one second timer. */ 1100 sc->sc_wdog_timer = 0; 1101 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1102 } 1103 1104 static int 1105 gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 1106 { 1107 bus_dma_segment_t txsegs[GEM_NTXSEGS]; 1108 struct gem_txsoft *txs; 1109 struct ip *ip; 1110 struct mbuf *m; 1111 uint64_t cflags, flags; 1112 int error, nexttx, nsegs, offset, seg; 1113 1114 GEM_LOCK_ASSERT(sc, MA_OWNED); 1115 1116 /* Get a work queue entry. */ 1117 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1118 /* Ran out of descriptors. */ 1119 return (ENOBUFS); 1120 } 1121 1122 cflags = 0; 1123 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1124 if (M_WRITABLE(*m_head) == 0) { 1125 m = m_dup(*m_head, M_NOWAIT); 1126 m_freem(*m_head); 1127 *m_head = m; 1128 if (m == NULL) 1129 return (ENOBUFS); 1130 } 1131 offset = sizeof(struct ether_header); 1132 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1133 if (m == NULL) { 1134 *m_head = NULL; 1135 return (ENOBUFS); 1136 } 1137 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1138 offset += (ip->ip_hl << 2); 1139 cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1140 ((offset + m->m_pkthdr.csum_data) << 1141 GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1142 *m_head = m; 1143 } 1144 1145 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1146 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1147 if (error == EFBIG) { 1148 m = m_collapse(*m_head, M_NOWAIT, GEM_NTXSEGS); 1149 if (m == NULL) { 1150 m_freem(*m_head); 1151 *m_head = NULL; 1152 return (ENOBUFS); 1153 } 1154 *m_head = m; 1155 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1156 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1157 BUS_DMA_NOWAIT); 1158 if (error != 0) { 1159 m_freem(*m_head); 1160 *m_head = NULL; 1161 return (error); 1162 } 1163 } else if (error != 0) 1164 return (error); 1165 /* If nsegs is wrong then the stack is corrupt. */ 1166 KASSERT(nsegs <= GEM_NTXSEGS, 1167 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1168 if (nsegs == 0) { 1169 m_freem(*m_head); 1170 *m_head = NULL; 1171 return (EIO); 1172 } 1173 1174 /* 1175 * Ensure we have enough descriptors free to describe 1176 * the packet. Note, we always reserve one descriptor 1177 * at the end of the ring as a termination point, in 1178 * order to prevent wrap-around. 1179 */ 1180 if (nsegs > sc->sc_txfree - 1) { 1181 txs->txs_ndescs = 0; 1182 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1183 return (ENOBUFS); 1184 } 1185 1186 txs->txs_ndescs = nsegs; 1187 txs->txs_firstdesc = sc->sc_txnext; 1188 nexttx = txs->txs_firstdesc; 1189 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1190 #ifdef GEM_DEBUG 1191 CTR6(KTR_GEM, 1192 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1193 __func__, seg, nexttx, txsegs[seg].ds_len, 1194 txsegs[seg].ds_addr, 1195 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1196 #endif 1197 sc->sc_txdescs[nexttx].gd_addr = 1198 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1199 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1200 ("%s: segment size too large!", __func__)); 1201 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1202 sc->sc_txdescs[nexttx].gd_flags = 1203 GEM_DMA_WRITE(sc, flags | cflags); 1204 txs->txs_lastdesc = nexttx; 1205 } 1206 1207 /* Set EOP on the last descriptor. */ 1208 #ifdef GEM_DEBUG 1209 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1210 __func__, seg, nexttx); 1211 #endif 1212 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1213 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1214 1215 /* Lastly set SOP on the first descriptor. */ 1216 #ifdef GEM_DEBUG 1217 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1218 __func__, seg, nexttx); 1219 #endif 1220 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1221 sc->sc_txwin = 0; 1222 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1223 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1224 GEM_TD_START_OF_PACKET); 1225 } else 1226 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1227 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1228 1229 /* Sync the DMA map. */ 1230 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1231 BUS_DMASYNC_PREWRITE); 1232 1233 #ifdef GEM_DEBUG 1234 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1235 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1236 txs->txs_ndescs); 1237 #endif 1238 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1239 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1240 txs->txs_mbuf = *m_head; 1241 1242 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1243 sc->sc_txfree -= txs->txs_ndescs; 1244 1245 return (0); 1246 } 1247 1248 static void 1249 gem_init_regs(struct gem_softc *sc) 1250 { 1251 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1252 1253 GEM_LOCK_ASSERT(sc, MA_OWNED); 1254 1255 /* These registers are not cleared on reset. */ 1256 if ((sc->sc_flags & GEM_INITED) == 0) { 1257 /* magic values */ 1258 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1259 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1260 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 1261 1262 /* min frame length */ 1263 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1264 /* max frame length and max burst size */ 1265 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1266 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1267 1268 /* more magic values */ 1269 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1270 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1271 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1272 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8808); 1273 1274 /* random number seed */ 1275 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1276 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1277 1278 /* secondary MAC address: 0:0:0:0:0:0 */ 1279 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1280 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1281 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1282 1283 /* MAC control address: 01:80:c2:00:00:01 */ 1284 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1285 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1286 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 1287 1288 /* MAC filter address: 0:0:0:0:0:0 */ 1289 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1290 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1291 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1292 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1293 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 1294 1295 sc->sc_flags |= GEM_INITED; 1296 } 1297 1298 /* Counters need to be zeroed. */ 1299 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1300 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1301 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1302 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1303 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1304 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1305 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1306 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1307 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1308 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1309 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 1310 1311 /* Set XOFF PAUSE time. */ 1312 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1313 1314 /* Set the station address. */ 1315 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1316 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1317 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1318 1319 /* Enable MII outputs. */ 1320 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 1321 } 1322 1323 static void 1324 gem_start(struct ifnet *ifp) 1325 { 1326 struct gem_softc *sc = ifp->if_softc; 1327 1328 GEM_LOCK(sc); 1329 gem_start_locked(ifp); 1330 GEM_UNLOCK(sc); 1331 } 1332 1333 static inline void 1334 gem_txkick(struct gem_softc *sc) 1335 { 1336 1337 /* 1338 * Update the TX kick register. This register has to point to the 1339 * descriptor after the last valid one and for optimum performance 1340 * should be incremented in multiples of 4 (the DMA engine fetches/ 1341 * updates descriptors in batches of 4). 1342 */ 1343 #ifdef GEM_DEBUG 1344 CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1345 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1346 #endif 1347 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1348 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1349 } 1350 1351 static void 1352 gem_start_locked(struct ifnet *ifp) 1353 { 1354 struct gem_softc *sc = ifp->if_softc; 1355 struct mbuf *m; 1356 int kicked, ntx; 1357 1358 GEM_LOCK_ASSERT(sc, MA_OWNED); 1359 1360 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1361 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 1362 return; 1363 1364 #ifdef GEM_DEBUG 1365 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1366 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1367 sc->sc_txnext); 1368 #endif 1369 ntx = 0; 1370 kicked = 0; 1371 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1372 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1373 if (m == NULL) 1374 break; 1375 if (gem_load_txmbuf(sc, &m) != 0) { 1376 if (m == NULL) 1377 break; 1378 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1379 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1380 break; 1381 } 1382 if ((sc->sc_txnext % 4) == 0) { 1383 gem_txkick(sc); 1384 kicked = 1; 1385 } else 1386 kicked = 0; 1387 ntx++; 1388 BPF_MTAP(ifp, m); 1389 } 1390 1391 if (ntx > 0) { 1392 if (kicked == 0) 1393 gem_txkick(sc); 1394 #ifdef GEM_DEBUG 1395 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1396 device_get_name(sc->sc_dev), sc->sc_txnext); 1397 #endif 1398 1399 /* Set a watchdog timer in case the chip flakes out. */ 1400 sc->sc_wdog_timer = 5; 1401 #ifdef GEM_DEBUG 1402 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1403 device_get_name(sc->sc_dev), __func__, 1404 sc->sc_wdog_timer); 1405 #endif 1406 } 1407 } 1408 1409 static void 1410 gem_tint(struct gem_softc *sc) 1411 { 1412 struct ifnet *ifp = sc->sc_ifp; 1413 struct gem_txsoft *txs; 1414 int progress; 1415 uint32_t txlast; 1416 #ifdef GEM_DEBUG 1417 int i; 1418 1419 GEM_LOCK_ASSERT(sc, MA_OWNED); 1420 1421 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1422 #endif 1423 1424 /* 1425 * Go through our TX list and free mbufs for those 1426 * frames that have been transmitted. 1427 */ 1428 progress = 0; 1429 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1430 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1431 #ifdef GEM_DEBUG 1432 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1433 printf(" txsoft %p transmit chain:\n", txs); 1434 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1435 printf("descriptor %d: ", i); 1436 printf("gd_flags: 0x%016llx\t", 1437 (long long)GEM_DMA_READ(sc, 1438 sc->sc_txdescs[i].gd_flags)); 1439 printf("gd_addr: 0x%016llx\n", 1440 (long long)GEM_DMA_READ(sc, 1441 sc->sc_txdescs[i].gd_addr)); 1442 if (i == txs->txs_lastdesc) 1443 break; 1444 } 1445 } 1446 #endif 1447 1448 /* 1449 * In theory, we could harvest some descriptors before 1450 * the ring is empty, but that's a bit complicated. 1451 * 1452 * GEM_TX_COMPLETION points to the last descriptor 1453 * processed + 1. 1454 */ 1455 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1456 #ifdef GEM_DEBUG 1457 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 1458 "txs->txs_lastdesc = %d, txlast = %d", 1459 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1460 #endif 1461 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1462 if ((txlast >= txs->txs_firstdesc) && 1463 (txlast <= txs->txs_lastdesc)) 1464 break; 1465 } else { 1466 /* Ick -- this command wraps. */ 1467 if ((txlast >= txs->txs_firstdesc) || 1468 (txlast <= txs->txs_lastdesc)) 1469 break; 1470 } 1471 1472 #ifdef GEM_DEBUG 1473 CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1474 #endif 1475 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1476 1477 sc->sc_txfree += txs->txs_ndescs; 1478 1479 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1480 BUS_DMASYNC_POSTWRITE); 1481 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1482 if (txs->txs_mbuf != NULL) { 1483 m_freem(txs->txs_mbuf); 1484 txs->txs_mbuf = NULL; 1485 } 1486 1487 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1488 1489 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1490 progress = 1; 1491 } 1492 1493 #ifdef GEM_DEBUG 1494 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1495 "GEM_TX_COMPLETION %x", 1496 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1497 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1498 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1499 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1500 #endif 1501 1502 if (progress) { 1503 if (sc->sc_txfree == GEM_NTXDESC - 1) 1504 sc->sc_txwin = 0; 1505 1506 /* 1507 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1508 * and restart. 1509 */ 1510 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1511 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1512 sc->sc_wdog_timer = 0; 1513 gem_start_locked(ifp); 1514 } 1515 1516 #ifdef GEM_DEBUG 1517 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1518 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1519 #endif 1520 } 1521 1522 #ifdef GEM_RINT_TIMEOUT 1523 static void 1524 gem_rint_timeout(void *arg) 1525 { 1526 struct gem_softc *sc = arg; 1527 1528 GEM_LOCK_ASSERT(sc, MA_OWNED); 1529 1530 gem_rint(sc); 1531 } 1532 #endif 1533 1534 static void 1535 gem_rint(struct gem_softc *sc) 1536 { 1537 struct ifnet *ifp = sc->sc_ifp; 1538 struct mbuf *m; 1539 uint64_t rxstat; 1540 uint32_t rxcomp; 1541 1542 GEM_LOCK_ASSERT(sc, MA_OWNED); 1543 1544 #ifdef GEM_RINT_TIMEOUT 1545 callout_stop(&sc->sc_rx_ch); 1546 #endif 1547 #ifdef GEM_DEBUG 1548 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1549 #endif 1550 1551 /* 1552 * Read the completion register once. This limits 1553 * how long the following loop can execute. 1554 */ 1555 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1556 #ifdef GEM_DEBUG 1557 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1558 __func__, sc->sc_rxptr, rxcomp); 1559 #endif 1560 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1561 for (; sc->sc_rxptr != rxcomp;) { 1562 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1563 rxstat = GEM_DMA_READ(sc, 1564 sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 1565 1566 if (rxstat & GEM_RD_OWN) { 1567 #ifdef GEM_RINT_TIMEOUT 1568 /* 1569 * The descriptor is still marked as owned, although 1570 * it is supposed to have completed. This has been 1571 * observed on some machines. Just exiting here 1572 * might leave the packet sitting around until another 1573 * one arrives to trigger a new interrupt, which is 1574 * generally undesirable, so set up a timeout. 1575 */ 1576 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1577 gem_rint_timeout, sc); 1578 #endif 1579 m = NULL; 1580 goto kickit; 1581 } 1582 1583 if (rxstat & GEM_RD_BAD_CRC) { 1584 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1585 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1586 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1587 m = NULL; 1588 goto kickit; 1589 } 1590 1591 #ifdef GEM_DEBUG 1592 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1593 printf(" rxsoft %p descriptor %d: ", 1594 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1595 printf("gd_flags: 0x%016llx\t", 1596 (long long)GEM_DMA_READ(sc, 1597 sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1598 printf("gd_addr: 0x%016llx\n", 1599 (long long)GEM_DMA_READ(sc, 1600 sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 1601 } 1602 #endif 1603 1604 /* 1605 * Allocate a new mbuf cluster. If that fails, we are 1606 * out of memory, and must drop the packet and recycle 1607 * the buffer that's already attached to this descriptor. 1608 */ 1609 if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 1610 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1611 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1612 m = NULL; 1613 } 1614 1615 kickit: 1616 /* 1617 * Update the RX kick register. This register has to point 1618 * to the descriptor after the last valid one (before the 1619 * current batch) and for optimum performance should be 1620 * incremented in multiples of 4 (the DMA engine fetches/ 1621 * updates descriptors in batches of 4). 1622 */ 1623 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1624 if ((sc->sc_rxptr % 4) == 0) { 1625 GEM_CDSYNC(sc, 1626 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1627 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1628 (sc->sc_rxptr + GEM_NRXDESC - 4) & 1629 GEM_NRXDESC_MASK); 1630 } 1631 1632 if (m == NULL) { 1633 if (rxstat & GEM_RD_OWN) 1634 break; 1635 continue; 1636 } 1637 1638 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1639 m->m_data += ETHER_ALIGN; /* first byte offset */ 1640 m->m_pkthdr.rcvif = ifp; 1641 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 1642 1643 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1644 gem_rxcksum(m, rxstat); 1645 1646 /* Pass it on. */ 1647 GEM_UNLOCK(sc); 1648 (*ifp->if_input)(ifp, m); 1649 GEM_LOCK(sc); 1650 } 1651 1652 #ifdef GEM_DEBUG 1653 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1654 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1655 #endif 1656 } 1657 1658 static int 1659 gem_add_rxbuf(struct gem_softc *sc, int idx) 1660 { 1661 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1662 struct mbuf *m; 1663 bus_dma_segment_t segs[1]; 1664 int error, nsegs; 1665 1666 GEM_LOCK_ASSERT(sc, MA_OWNED); 1667 1668 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1669 if (m == NULL) 1670 return (ENOBUFS); 1671 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1672 1673 #ifdef GEM_DEBUG 1674 /* Bzero the packet to check DMA. */ 1675 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1676 #endif 1677 1678 if (rxs->rxs_mbuf != NULL) { 1679 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1680 BUS_DMASYNC_POSTREAD); 1681 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1682 } 1683 1684 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1685 m, segs, &nsegs, BUS_DMA_NOWAIT); 1686 if (error != 0) { 1687 device_printf(sc->sc_dev, 1688 "cannot load RS DMA map %d, error = %d\n", idx, error); 1689 m_freem(m); 1690 return (error); 1691 } 1692 /* If nsegs is wrong then the stack is corrupt. */ 1693 KASSERT(nsegs == 1, 1694 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1695 rxs->rxs_mbuf = m; 1696 rxs->rxs_paddr = segs[0].ds_addr; 1697 1698 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1699 BUS_DMASYNC_PREREAD); 1700 1701 GEM_INIT_RXDESC(sc, idx); 1702 1703 return (0); 1704 } 1705 1706 static void 1707 gem_eint(struct gem_softc *sc, u_int status) 1708 { 1709 1710 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1); 1711 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1712 gem_reset_rxdma(sc); 1713 return; 1714 } 1715 1716 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1717 if ((status & GEM_INTR_BERR) != 0) { 1718 if ((sc->sc_flags & GEM_PCI) != 0) 1719 printf(", PCI bus error 0x%x\n", 1720 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1721 else 1722 printf(", SBus error 0x%x\n", 1723 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1724 } 1725 } 1726 1727 void 1728 gem_intr(void *v) 1729 { 1730 struct gem_softc *sc = v; 1731 uint32_t status, status2; 1732 1733 GEM_LOCK(sc); 1734 status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1735 1736 #ifdef GEM_DEBUG 1737 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1738 device_get_name(sc->sc_dev), __func__, 1739 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1740 1741 /* 1742 * PCS interrupts must be cleared, otherwise no traffic is passed! 1743 */ 1744 if ((status & GEM_INTR_PCS) != 0) { 1745 status2 = 1746 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1747 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1748 if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1749 device_printf(sc->sc_dev, 1750 "%s: PCS link status changed\n", __func__); 1751 } 1752 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1753 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1754 if ((status2 & GEM_MAC_PAUSED) != 0) 1755 device_printf(sc->sc_dev, 1756 "%s: PAUSE received (PAUSE time %d slots)\n", 1757 __func__, GEM_MAC_PAUSE_TIME(status2)); 1758 if ((status2 & GEM_MAC_PAUSE) != 0) 1759 device_printf(sc->sc_dev, 1760 "%s: transited to PAUSE state\n", __func__); 1761 if ((status2 & GEM_MAC_RESUME) != 0) 1762 device_printf(sc->sc_dev, 1763 "%s: transited to non-PAUSE state\n", __func__); 1764 } 1765 if ((status & GEM_INTR_MIF) != 0) 1766 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1767 #endif 1768 1769 if (__predict_false(status & 1770 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 1771 gem_eint(sc, status); 1772 1773 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1774 gem_rint(sc); 1775 1776 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1777 gem_tint(sc); 1778 1779 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1780 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1781 if ((status2 & 1782 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1783 GEM_MAC_TX_PEAK_EXP)) != 0) 1784 device_printf(sc->sc_dev, 1785 "MAC TX fault, status %x\n", status2); 1786 if ((status2 & 1787 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1788 if_inc_counter(sc->sc_ifp, IFCOUNTER_OERRORS, 1); 1789 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1790 gem_init_locked(sc); 1791 } 1792 } 1793 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1794 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1795 /* 1796 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1797 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1798 * silicon bug so handle them silently. Moreover, it's 1799 * likely that the receiver has hung so we reset it. 1800 */ 1801 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1802 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1); 1803 gem_reset_rxdma(sc); 1804 } else if ((status2 & 1805 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1806 device_printf(sc->sc_dev, 1807 "MAC RX fault, status %x\n", status2); 1808 } 1809 GEM_UNLOCK(sc); 1810 } 1811 1812 static int 1813 gem_watchdog(struct gem_softc *sc) 1814 { 1815 struct ifnet *ifp = sc->sc_ifp; 1816 1817 GEM_LOCK_ASSERT(sc, MA_OWNED); 1818 1819 #ifdef GEM_DEBUG 1820 CTR4(KTR_GEM, 1821 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1822 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1823 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1824 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1825 CTR4(KTR_GEM, 1826 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1827 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1828 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1829 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1830 #endif 1831 1832 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1833 return (0); 1834 1835 if ((sc->sc_flags & GEM_LINK) != 0) 1836 device_printf(sc->sc_dev, "device timeout\n"); 1837 else if (bootverbose) 1838 device_printf(sc->sc_dev, "device timeout (no link)\n"); 1839 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1840 1841 /* Try to get more packets going. */ 1842 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1843 gem_init_locked(sc); 1844 gem_start_locked(ifp); 1845 return (EJUSTRETURN); 1846 } 1847 1848 static void 1849 gem_mifinit(struct gem_softc *sc) 1850 { 1851 1852 /* Configure the MIF in frame mode. */ 1853 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1854 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1855 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 1856 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1857 } 1858 1859 /* 1860 * MII interface 1861 * 1862 * The MII interface supports at least three different operating modes: 1863 * 1864 * Bitbang mode is implemented using data, clock and output enable registers. 1865 * 1866 * Frame mode is implemented by loading a complete frame into the frame 1867 * register and polling the valid bit for completion. 1868 * 1869 * Polling mode uses the frame register but completion is indicated by 1870 * an interrupt. 1871 * 1872 */ 1873 int 1874 gem_mii_readreg(device_t dev, int phy, int reg) 1875 { 1876 struct gem_softc *sc; 1877 int n; 1878 uint32_t v; 1879 1880 #ifdef GEM_DEBUG_PHY 1881 printf("%s: phy %d reg %d\n", __func__, phy, reg); 1882 #endif 1883 1884 sc = device_get_softc(dev); 1885 if ((sc->sc_flags & GEM_SERDES) != 0) { 1886 switch (reg) { 1887 case MII_BMCR: 1888 reg = GEM_MII_CONTROL; 1889 break; 1890 case MII_BMSR: 1891 reg = GEM_MII_STATUS; 1892 break; 1893 case MII_PHYIDR1: 1894 case MII_PHYIDR2: 1895 return (0); 1896 case MII_ANAR: 1897 reg = GEM_MII_ANAR; 1898 break; 1899 case MII_ANLPAR: 1900 reg = GEM_MII_ANLPAR; 1901 break; 1902 case MII_EXTSR: 1903 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1904 default: 1905 device_printf(sc->sc_dev, 1906 "%s: unhandled register %d\n", __func__, reg); 1907 return (0); 1908 } 1909 return (GEM_BANK1_READ_4(sc, reg)); 1910 } 1911 1912 /* Construct the frame command. */ 1913 v = GEM_MIF_FRAME_READ | 1914 (phy << GEM_MIF_PHY_SHIFT) | 1915 (reg << GEM_MIF_REG_SHIFT); 1916 1917 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1918 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1919 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1920 for (n = 0; n < 100; n++) { 1921 DELAY(1); 1922 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1923 if (v & GEM_MIF_FRAME_TA0) 1924 return (v & GEM_MIF_FRAME_DATA); 1925 } 1926 1927 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1928 return (0); 1929 } 1930 1931 int 1932 gem_mii_writereg(device_t dev, int phy, int reg, int val) 1933 { 1934 struct gem_softc *sc; 1935 int n; 1936 uint32_t v; 1937 1938 #ifdef GEM_DEBUG_PHY 1939 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 1940 #endif 1941 1942 sc = device_get_softc(dev); 1943 if ((sc->sc_flags & GEM_SERDES) != 0) { 1944 switch (reg) { 1945 case MII_BMSR: 1946 reg = GEM_MII_STATUS; 1947 break; 1948 case MII_BMCR: 1949 reg = GEM_MII_CONTROL; 1950 if ((val & GEM_MII_CONTROL_RESET) == 0) 1951 break; 1952 GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1953 GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1954 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1955 if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1956 GEM_MII_CONTROL_RESET, 0)) 1957 device_printf(sc->sc_dev, 1958 "cannot reset PCS\n"); 1959 /* FALLTHROUGH */ 1960 case MII_ANAR: 1961 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1962 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1963 BUS_SPACE_BARRIER_WRITE); 1964 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1965 GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 1966 BUS_SPACE_BARRIER_WRITE); 1967 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1968 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1969 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 1970 BUS_SPACE_BARRIER_WRITE); 1971 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1972 GEM_MII_CONFIG_ENABLE); 1973 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1974 BUS_SPACE_BARRIER_WRITE); 1975 return (0); 1976 case MII_ANLPAR: 1977 reg = GEM_MII_ANLPAR; 1978 break; 1979 default: 1980 device_printf(sc->sc_dev, 1981 "%s: unhandled register %d\n", __func__, reg); 1982 return (0); 1983 } 1984 GEM_BANK1_WRITE_4(sc, reg, val); 1985 GEM_BANK1_BARRIER(sc, reg, 4, 1986 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1987 return (0); 1988 } 1989 1990 /* Construct the frame command. */ 1991 v = GEM_MIF_FRAME_WRITE | 1992 (phy << GEM_MIF_PHY_SHIFT) | 1993 (reg << GEM_MIF_REG_SHIFT) | 1994 (val & GEM_MIF_FRAME_DATA); 1995 1996 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1997 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1998 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1999 for (n = 0; n < 100; n++) { 2000 DELAY(1); 2001 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 2002 if (v & GEM_MIF_FRAME_TA0) 2003 return (1); 2004 } 2005 2006 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2007 return (0); 2008 } 2009 2010 void 2011 gem_mii_statchg(device_t dev) 2012 { 2013 struct gem_softc *sc; 2014 int gigabit; 2015 uint32_t rxcfg, txcfg, v; 2016 2017 sc = device_get_softc(dev); 2018 2019 GEM_LOCK_ASSERT(sc, MA_OWNED); 2020 2021 #ifdef GEM_DEBUG 2022 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 2023 device_printf(sc->sc_dev, "%s: status change\n", __func__); 2024 #endif 2025 2026 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2027 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2028 sc->sc_flags |= GEM_LINK; 2029 else 2030 sc->sc_flags &= ~GEM_LINK; 2031 2032 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2033 case IFM_1000_SX: 2034 case IFM_1000_LX: 2035 case IFM_1000_CX: 2036 case IFM_1000_T: 2037 gigabit = 1; 2038 break; 2039 default: 2040 gigabit = 0; 2041 } 2042 2043 /* 2044 * The configuration done here corresponds to the steps F) and 2045 * G) and as far as enabling of RX and TX MAC goes also step H) 2046 * of the initialization sequence outlined in section 3.2.1 of 2047 * the GEM Gigabit Ethernet ASIC Specification. 2048 */ 2049 2050 rxcfg = sc->sc_mac_rxcfg; 2051 rxcfg &= ~GEM_MAC_RX_CARR_EXTEND; 2052 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2053 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2054 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2055 else if (gigabit != 0) { 2056 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2057 txcfg |= GEM_MAC_TX_CARR_EXTEND; 2058 } 2059 (void)gem_disable_tx(sc); 2060 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2061 (void)gem_disable_rx(sc); 2062 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2063 2064 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2065 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2066 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2067 IFM_ETH_RXPAUSE) != 0) 2068 v |= GEM_MAC_CC_RX_PAUSE; 2069 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2070 IFM_ETH_TXPAUSE) != 0) 2071 v |= GEM_MAC_CC_TX_PAUSE; 2072 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2073 2074 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2075 gigabit != 0) 2076 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2077 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2078 else 2079 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2080 GEM_MAC_SLOT_TIME_NORMAL); 2081 2082 /* XIF Configuration */ 2083 v = GEM_MAC_XIF_LINK_LED; 2084 v |= GEM_MAC_XIF_TX_MII_ENA; 2085 if ((sc->sc_flags & GEM_SERDES) == 0) { 2086 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2087 GEM_MIF_CONFIG_PHY_SEL) != 0) { 2088 /* External MII needs echo disable if half duplex. */ 2089 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2090 IFM_FDX) == 0) 2091 v |= GEM_MAC_XIF_ECHO_DISABL; 2092 } else 2093 /* 2094 * Internal MII needs buffer enable. 2095 * XXX buffer enable makes only sense for an 2096 * external PHY. 2097 */ 2098 v |= GEM_MAC_XIF_MII_BUF_ENA; 2099 } 2100 if (gigabit != 0) 2101 v |= GEM_MAC_XIF_GMII_MODE; 2102 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2103 v |= GEM_MAC_XIF_FDPLX_LED; 2104 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 2105 2106 sc->sc_mac_rxcfg = rxcfg; 2107 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2108 (sc->sc_flags & GEM_LINK) != 0) { 2109 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2110 txcfg | GEM_MAC_TX_ENABLE); 2111 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2112 rxcfg | GEM_MAC_RX_ENABLE); 2113 } 2114 } 2115 2116 int 2117 gem_mediachange(struct ifnet *ifp) 2118 { 2119 struct gem_softc *sc = ifp->if_softc; 2120 int error; 2121 2122 /* XXX add support for serial media. */ 2123 2124 GEM_LOCK(sc); 2125 error = mii_mediachg(sc->sc_mii); 2126 GEM_UNLOCK(sc); 2127 return (error); 2128 } 2129 2130 void 2131 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2132 { 2133 struct gem_softc *sc = ifp->if_softc; 2134 2135 GEM_LOCK(sc); 2136 if ((ifp->if_flags & IFF_UP) == 0) { 2137 GEM_UNLOCK(sc); 2138 return; 2139 } 2140 2141 mii_pollstat(sc->sc_mii); 2142 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2143 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2144 GEM_UNLOCK(sc); 2145 } 2146 2147 static int 2148 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2149 { 2150 struct gem_softc *sc = ifp->if_softc; 2151 struct ifreq *ifr = (struct ifreq *)data; 2152 int error; 2153 2154 error = 0; 2155 switch (cmd) { 2156 case SIOCSIFFLAGS: 2157 GEM_LOCK(sc); 2158 if ((ifp->if_flags & IFF_UP) != 0) { 2159 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2160 ((ifp->if_flags ^ sc->sc_ifflags) & 2161 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2162 gem_setladrf(sc); 2163 else 2164 gem_init_locked(sc); 2165 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2166 gem_stop(ifp, 0); 2167 if ((ifp->if_flags & IFF_LINK0) != 0) 2168 sc->sc_csum_features |= CSUM_UDP; 2169 else 2170 sc->sc_csum_features &= ~CSUM_UDP; 2171 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2172 ifp->if_hwassist = sc->sc_csum_features; 2173 sc->sc_ifflags = ifp->if_flags; 2174 GEM_UNLOCK(sc); 2175 break; 2176 case SIOCADDMULTI: 2177 case SIOCDELMULTI: 2178 GEM_LOCK(sc); 2179 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2180 gem_setladrf(sc); 2181 GEM_UNLOCK(sc); 2182 break; 2183 case SIOCGIFMEDIA: 2184 case SIOCSIFMEDIA: 2185 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2186 break; 2187 case SIOCSIFCAP: 2188 GEM_LOCK(sc); 2189 ifp->if_capenable = ifr->ifr_reqcap; 2190 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2191 ifp->if_hwassist = sc->sc_csum_features; 2192 else 2193 ifp->if_hwassist = 0; 2194 GEM_UNLOCK(sc); 2195 break; 2196 default: 2197 error = ether_ioctl(ifp, cmd, data); 2198 break; 2199 } 2200 2201 return (error); 2202 } 2203 2204 static u_int 2205 gem_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2206 { 2207 uint32_t crc, *hash = arg; 2208 2209 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 2210 /* We just want the 8 most significant bits. */ 2211 crc >>= 24; 2212 /* Set the corresponding bit in the filter. */ 2213 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2214 2215 return (1); 2216 } 2217 2218 static void 2219 gem_setladrf(struct gem_softc *sc) 2220 { 2221 struct ifnet *ifp = sc->sc_ifp; 2222 int i; 2223 uint32_t hash[16]; 2224 uint32_t v; 2225 2226 GEM_LOCK_ASSERT(sc, MA_OWNED); 2227 2228 /* 2229 * Turn off the RX MAC and the hash filter as required by the Sun GEM 2230 * programming restrictions. 2231 */ 2232 v = sc->sc_mac_rxcfg & ~GEM_MAC_RX_HASH_FILTER; 2233 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2234 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2235 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2236 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER | 2237 GEM_MAC_RX_ENABLE, 0)) 2238 device_printf(sc->sc_dev, 2239 "cannot disable RX MAC or hash filter\n"); 2240 2241 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_PROMISC_GRP); 2242 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2243 v |= GEM_MAC_RX_PROMISCUOUS; 2244 goto chipit; 2245 } 2246 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2247 v |= GEM_MAC_RX_PROMISC_GRP; 2248 goto chipit; 2249 } 2250 2251 /* 2252 * Set up multicast address filter by passing all multicast 2253 * addresses through a crc generator, and then using the high 2254 * order 8 bits as an index into the 256 bit logical address 2255 * filter. The high order 4 bits selects the word, while the 2256 * other 4 bits select the bit within the word (where bit 0 2257 * is the MSB). 2258 */ 2259 2260 memset(hash, 0, sizeof(hash)); 2261 if_foreach_llmaddr(ifp, gem_hash_maddr, hash); 2262 2263 v |= GEM_MAC_RX_HASH_FILTER; 2264 2265 /* Now load the hash table into the chip (if we are using it). */ 2266 for (i = 0; i < 16; i++) 2267 GEM_BANK1_WRITE_4(sc, 2268 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 2269 hash[i]); 2270 2271 chipit: 2272 sc->sc_mac_rxcfg = v; 2273 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v | GEM_MAC_RX_ENABLE); 2274 } 2275