1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 36 */ 37 38 #if 0 39 #define GEM_DEBUG 40 #endif 41 42 #if 0 /* XXX: In case of emergency, re-enable this. */ 43 #define GEM_RINT_TIMEOUT 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/callout.h> 50 #include <sys/endian.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/lock.h> 55 #include <sys/module.h> 56 #include <sys/mutex.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/rman.h> 60 61 #include <net/bpf.h> 62 #include <net/ethernet.h> 63 #include <net/if.h> 64 #include <net/if_arp.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/ip.h> 73 #include <netinet/tcp.h> 74 #include <netinet/udp.h> 75 76 #include <machine/bus.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <dev/gem/if_gemreg.h> 82 #include <dev/gem/if_gemvar.h> 83 84 CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85 CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86 87 #define GEM_TRIES 10000 88 89 /* 90 * The hardware supports basic TCP/UDP checksum offloading. However, 91 * the hardware doesn't compensate the checksum for UDP datagram which 92 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93 * by default. It can be reactivated by setting special link option 94 * link0 with ifconfig(8). 95 */ 96 #define GEM_CSUM_FEATURES (CSUM_TCP) 97 98 static int gem_add_rxbuf(struct gem_softc *sc, int idx); 99 static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 100 uint32_t clr, uint32_t set); 101 static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 102 int nsegs, int error); 103 static int gem_disable_rx(struct gem_softc *sc); 104 static int gem_disable_tx(struct gem_softc *sc); 105 static void gem_eint(struct gem_softc *sc, u_int status); 106 static void gem_init(void *xsc); 107 static void gem_init_locked(struct gem_softc *sc); 108 static void gem_init_regs(struct gem_softc *sc); 109 static int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 110 static int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 111 static int gem_meminit(struct gem_softc *sc); 112 static void gem_mifinit(struct gem_softc *sc); 113 static void gem_reset(struct gem_softc *sc); 114 static int gem_reset_rx(struct gem_softc *sc); 115 static void gem_reset_rxdma(struct gem_softc *sc); 116 static int gem_reset_tx(struct gem_softc *sc); 117 static u_int gem_ringsize(u_int sz); 118 static void gem_rint(struct gem_softc *sc); 119 #ifdef GEM_RINT_TIMEOUT 120 static void gem_rint_timeout(void *arg); 121 #endif 122 static inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 123 static void gem_rxdrain(struct gem_softc *sc); 124 static void gem_setladrf(struct gem_softc *sc); 125 static void gem_start(struct ifnet *ifp); 126 static void gem_start_locked(struct ifnet *ifp); 127 static void gem_stop(struct ifnet *ifp, int disable); 128 static void gem_tick(void *arg); 129 static void gem_tint(struct gem_softc *sc); 130 static inline void gem_txkick(struct gem_softc *sc); 131 static int gem_watchdog(struct gem_softc *sc); 132 133 devclass_t gem_devclass; 134 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 135 MODULE_DEPEND(gem, miibus, 1, 1, 1); 136 137 #ifdef GEM_DEBUG 138 #include <sys/ktr.h> 139 #define KTR_GEM KTR_CT2 140 #endif 141 142 #define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 143 gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 144 #define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 145 gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 146 147 int 148 gem_attach(struct gem_softc *sc) 149 { 150 struct gem_txsoft *txs; 151 struct ifnet *ifp; 152 int error, i; 153 uint32_t v; 154 155 if (bootverbose) 156 device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 157 158 /* Set up ifnet structure. */ 159 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160 if (ifp == NULL) 161 return (ENOSPC); 162 sc->sc_csum_features = GEM_CSUM_FEATURES; 163 ifp->if_softc = sc; 164 if_initname(ifp, device_get_name(sc->sc_dev), 165 device_get_unit(sc->sc_dev)); 166 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 167 ifp->if_start = gem_start; 168 ifp->if_ioctl = gem_ioctl; 169 ifp->if_init = gem_init; 170 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 171 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 172 IFQ_SET_READY(&ifp->if_snd); 173 174 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 175 #ifdef GEM_RINT_TIMEOUT 176 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 177 #endif 178 179 /* Make sure the chip is stopped. */ 180 gem_reset(sc); 181 182 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 184 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 185 NULL, &sc->sc_pdmatag); 186 if (error != 0) 187 goto fail_ifnet; 188 189 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 190 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 191 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 192 if (error != 0) 193 goto fail_ptag; 194 195 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 196 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 197 MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 199 if (error != 0) 200 goto fail_rtag; 201 202 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 203 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 204 sizeof(struct gem_control_data), 1, 205 sizeof(struct gem_control_data), 0, 206 NULL, NULL, &sc->sc_cdmatag); 207 if (error != 0) 208 goto fail_ttag; 209 210 /* 211 * Allocate the control data structures, create and load the 212 * DMA map for it. 213 */ 214 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 215 (void **)&sc->sc_control_data, 216 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 217 &sc->sc_cddmamap)) != 0) { 218 device_printf(sc->sc_dev, 219 "unable to allocate control data, error = %d\n", error); 220 goto fail_ctag; 221 } 222 223 sc->sc_cddma = 0; 224 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 225 sc->sc_control_data, sizeof(struct gem_control_data), 226 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 227 device_printf(sc->sc_dev, 228 "unable to load control data DMA map, error = %d\n", 229 error); 230 goto fail_cmem; 231 } 232 233 /* 234 * Initialize the transmit job descriptors. 235 */ 236 STAILQ_INIT(&sc->sc_txfreeq); 237 STAILQ_INIT(&sc->sc_txdirtyq); 238 239 /* 240 * Create the transmit buffer DMA maps. 241 */ 242 error = ENOMEM; 243 for (i = 0; i < GEM_TXQUEUELEN; i++) { 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 txs->txs_ndescs = 0; 247 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 248 &txs->txs_dmamap)) != 0) { 249 device_printf(sc->sc_dev, 250 "unable to create TX DMA map %d, error = %d\n", 251 i, error); 252 goto fail_txd; 253 } 254 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 262 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 device_printf(sc->sc_dev, 264 "unable to create RX DMA map %d, error = %d\n", 265 i, error); 266 goto fail_rxd; 267 } 268 sc->sc_rxsoft[i].rxs_mbuf = NULL; 269 } 270 271 /* Bad things will happen when touching this register on ERI. */ 272 if (sc->sc_variant != GEM_SUN_ERI) 273 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 274 GEM_MII_DATAPATH_MII); 275 276 gem_mifinit(sc); 277 278 /* 279 * Look for an external PHY. 280 */ 281 error = ENXIO; 282 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 283 if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 284 v |= GEM_MIF_CONFIG_PHY_SEL; 285 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 286 switch (sc->sc_variant) { 287 case GEM_SUN_ERI: 288 sc->sc_phyad = GEM_PHYAD_EXTERNAL; 289 break; 290 default: 291 sc->sc_phyad = -1; 292 break; 293 } 294 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 295 gem_mediachange, gem_mediastatus); 296 } 297 298 /* 299 * Fall back on an internal PHY if no external PHY was found. 300 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 301 * trusted when the firmware has powered down the chip. 302 */ 303 if (error != 0 && 304 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 305 v &= ~GEM_MIF_CONFIG_PHY_SEL; 306 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 307 switch (sc->sc_variant) { 308 case GEM_SUN_ERI: 309 case GEM_APPLE_K2_GMAC: 310 sc->sc_phyad = GEM_PHYAD_INTERNAL; 311 break; 312 case GEM_APPLE_GMAC: 313 sc->sc_phyad = GEM_PHYAD_EXTERNAL; 314 break; 315 default: 316 sc->sc_phyad = -1; 317 break; 318 } 319 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 320 gem_mediachange, gem_mediastatus); 321 } 322 323 /* 324 * Try the external PCS SERDES if we didn't find any PHYs. 325 */ 326 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 327 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 328 GEM_MII_DATAPATH_SERDES); 329 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 330 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 331 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 332 sc->sc_flags |= GEM_SERDES; 333 sc->sc_phyad = GEM_PHYAD_EXTERNAL; 334 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 335 gem_mediachange, gem_mediastatus); 336 } 337 338 if (error != 0) { 339 device_printf(sc->sc_dev, "PHY probe failed: %d\n", error); 340 goto fail_rxd; 341 } 342 sc->sc_mii = device_get_softc(sc->sc_miibus); 343 344 /* 345 * From this point forward, the attachment cannot fail. A failure 346 * before this point releases all resources that may have been 347 * allocated. 348 */ 349 350 /* Get RX FIFO size. */ 351 sc->sc_rxfifosize = 64 * 352 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 353 354 /* Get TX FIFO size. */ 355 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 356 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 357 sc->sc_rxfifosize / 1024, v / 16); 358 359 /* Attach the interface. */ 360 ether_ifattach(ifp, sc->sc_enaddr); 361 362 /* 363 * Tell the upper layer(s) we support long frames/checksum offloads. 364 */ 365 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 366 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 367 ifp->if_hwassist |= sc->sc_csum_features; 368 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 369 370 return (0); 371 372 /* 373 * Free any resources we've allocated during the failed attach 374 * attempt. Do this in reverse order and fall through. 375 */ 376 fail_rxd: 377 for (i = 0; i < GEM_NRXDESC; i++) 378 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 379 bus_dmamap_destroy(sc->sc_rdmatag, 380 sc->sc_rxsoft[i].rxs_dmamap); 381 fail_txd: 382 for (i = 0; i < GEM_TXQUEUELEN; i++) 383 if (sc->sc_txsoft[i].txs_dmamap != NULL) 384 bus_dmamap_destroy(sc->sc_tdmatag, 385 sc->sc_txsoft[i].txs_dmamap); 386 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 387 fail_cmem: 388 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 389 sc->sc_cddmamap); 390 fail_ctag: 391 bus_dma_tag_destroy(sc->sc_cdmatag); 392 fail_ttag: 393 bus_dma_tag_destroy(sc->sc_tdmatag); 394 fail_rtag: 395 bus_dma_tag_destroy(sc->sc_rdmatag); 396 fail_ptag: 397 bus_dma_tag_destroy(sc->sc_pdmatag); 398 fail_ifnet: 399 if_free(ifp); 400 return (error); 401 } 402 403 void 404 gem_detach(struct gem_softc *sc) 405 { 406 struct ifnet *ifp = sc->sc_ifp; 407 int i; 408 409 ether_ifdetach(ifp); 410 GEM_LOCK(sc); 411 gem_stop(ifp, 1); 412 GEM_UNLOCK(sc); 413 callout_drain(&sc->sc_tick_ch); 414 #ifdef GEM_RINT_TIMEOUT 415 callout_drain(&sc->sc_rx_ch); 416 #endif 417 if_free(ifp); 418 device_delete_child(sc->sc_dev, sc->sc_miibus); 419 420 for (i = 0; i < GEM_NRXDESC; i++) 421 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 422 bus_dmamap_destroy(sc->sc_rdmatag, 423 sc->sc_rxsoft[i].rxs_dmamap); 424 for (i = 0; i < GEM_TXQUEUELEN; i++) 425 if (sc->sc_txsoft[i].txs_dmamap != NULL) 426 bus_dmamap_destroy(sc->sc_tdmatag, 427 sc->sc_txsoft[i].txs_dmamap); 428 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 429 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 430 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 431 sc->sc_cddmamap); 432 bus_dma_tag_destroy(sc->sc_cdmatag); 433 bus_dma_tag_destroy(sc->sc_tdmatag); 434 bus_dma_tag_destroy(sc->sc_rdmatag); 435 bus_dma_tag_destroy(sc->sc_pdmatag); 436 } 437 438 void 439 gem_suspend(struct gem_softc *sc) 440 { 441 struct ifnet *ifp = sc->sc_ifp; 442 443 GEM_LOCK(sc); 444 gem_stop(ifp, 0); 445 GEM_UNLOCK(sc); 446 } 447 448 void 449 gem_resume(struct gem_softc *sc) 450 { 451 struct ifnet *ifp = sc->sc_ifp; 452 453 GEM_LOCK(sc); 454 /* 455 * On resume all registers have to be initialized again like 456 * after power-on. 457 */ 458 sc->sc_flags &= ~GEM_INITED; 459 if (ifp->if_flags & IFF_UP) 460 gem_init_locked(sc); 461 GEM_UNLOCK(sc); 462 } 463 464 static inline void 465 gem_rxcksum(struct mbuf *m, uint64_t flags) 466 { 467 struct ether_header *eh; 468 struct ip *ip; 469 struct udphdr *uh; 470 uint16_t *opts; 471 int32_t hlen, len, pktlen; 472 uint32_t temp32; 473 uint16_t cksum; 474 475 pktlen = m->m_pkthdr.len; 476 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 477 return; 478 eh = mtod(m, struct ether_header *); 479 if (eh->ether_type != htons(ETHERTYPE_IP)) 480 return; 481 ip = (struct ip *)(eh + 1); 482 if (ip->ip_v != IPVERSION) 483 return; 484 485 hlen = ip->ip_hl << 2; 486 pktlen -= sizeof(struct ether_header); 487 if (hlen < sizeof(struct ip)) 488 return; 489 if (ntohs(ip->ip_len) < hlen) 490 return; 491 if (ntohs(ip->ip_len) != pktlen) 492 return; 493 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 494 return; /* Cannot handle fragmented packet. */ 495 496 switch (ip->ip_p) { 497 case IPPROTO_TCP: 498 if (pktlen < (hlen + sizeof(struct tcphdr))) 499 return; 500 break; 501 case IPPROTO_UDP: 502 if (pktlen < (hlen + sizeof(struct udphdr))) 503 return; 504 uh = (struct udphdr *)((uint8_t *)ip + hlen); 505 if (uh->uh_sum == 0) 506 return; /* no checksum */ 507 break; 508 default: 509 return; 510 } 511 512 cksum = ~(flags & GEM_RD_CHECKSUM); 513 /* checksum fixup for IP options */ 514 len = hlen - sizeof(struct ip); 515 if (len > 0) { 516 opts = (uint16_t *)(ip + 1); 517 for (; len > 0; len -= sizeof(uint16_t), opts++) { 518 temp32 = cksum - *opts; 519 temp32 = (temp32 >> 16) + (temp32 & 65535); 520 cksum = temp32 & 65535; 521 } 522 } 523 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 524 m->m_pkthdr.csum_data = cksum; 525 } 526 527 static void 528 gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 529 { 530 struct gem_softc *sc = xsc; 531 532 if (error != 0) 533 return; 534 if (nsegs != 1) 535 panic("%s: bad control buffer segment count", __func__); 536 sc->sc_cddma = segs[0].ds_addr; 537 } 538 539 static void 540 gem_tick(void *arg) 541 { 542 struct gem_softc *sc = arg; 543 struct ifnet *ifp = sc->sc_ifp; 544 uint32_t v; 545 546 GEM_LOCK_ASSERT(sc, MA_OWNED); 547 548 /* 549 * Unload collision and error counters. 550 */ 551 ifp->if_collisions += 552 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 553 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 554 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 555 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 556 ifp->if_collisions += v; 557 ifp->if_oerrors += v; 558 ifp->if_ierrors += 559 GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 560 GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 561 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 562 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 563 564 /* 565 * Then clear the hardware counters. 566 */ 567 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 568 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 569 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 570 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 571 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 572 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 573 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 574 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 575 576 mii_tick(sc->sc_mii); 577 578 if (gem_watchdog(sc) == EJUSTRETURN) 579 return; 580 581 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 582 } 583 584 static int 585 gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 586 uint32_t set) 587 { 588 int i; 589 uint32_t reg; 590 591 for (i = GEM_TRIES; i--; DELAY(100)) { 592 reg = GEM_BANKN_READ_M(bank, 4, sc, r); 593 if ((reg & clr) == 0 && (reg & set) == set) 594 return (1); 595 } 596 return (0); 597 } 598 599 static void 600 gem_reset(struct gem_softc *sc) 601 { 602 603 #ifdef GEM_DEBUG 604 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 605 #endif 606 gem_reset_rx(sc); 607 gem_reset_tx(sc); 608 609 /* Do a full reset. */ 610 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 611 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 612 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 613 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 614 device_printf(sc->sc_dev, "cannot reset device\n"); 615 } 616 617 static void 618 gem_rxdrain(struct gem_softc *sc) 619 { 620 struct gem_rxsoft *rxs; 621 int i; 622 623 for (i = 0; i < GEM_NRXDESC; i++) { 624 rxs = &sc->sc_rxsoft[i]; 625 if (rxs->rxs_mbuf != NULL) { 626 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 627 BUS_DMASYNC_POSTREAD); 628 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 629 m_freem(rxs->rxs_mbuf); 630 rxs->rxs_mbuf = NULL; 631 } 632 } 633 } 634 635 static void 636 gem_stop(struct ifnet *ifp, int disable) 637 { 638 struct gem_softc *sc = ifp->if_softc; 639 struct gem_txsoft *txs; 640 641 #ifdef GEM_DEBUG 642 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 643 #endif 644 645 callout_stop(&sc->sc_tick_ch); 646 #ifdef GEM_RINT_TIMEOUT 647 callout_stop(&sc->sc_rx_ch); 648 #endif 649 650 gem_reset_tx(sc); 651 gem_reset_rx(sc); 652 653 /* 654 * Release any queued transmit buffers. 655 */ 656 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 657 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 658 if (txs->txs_ndescs != 0) { 659 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 660 BUS_DMASYNC_POSTWRITE); 661 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 662 if (txs->txs_mbuf != NULL) { 663 m_freem(txs->txs_mbuf); 664 txs->txs_mbuf = NULL; 665 } 666 } 667 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 668 } 669 670 if (disable) 671 gem_rxdrain(sc); 672 673 /* 674 * Mark the interface down and cancel the watchdog timer. 675 */ 676 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 677 sc->sc_flags &= ~GEM_LINK; 678 sc->sc_wdog_timer = 0; 679 } 680 681 static int 682 gem_reset_rx(struct gem_softc *sc) 683 { 684 685 /* 686 * Resetting while DMA is in progress can cause a bus hang, so we 687 * disable DMA first. 688 */ 689 gem_disable_rx(sc); 690 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 691 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 692 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 693 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 694 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 695 696 /* Finally, reset the ERX. */ 697 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX); 698 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 699 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 700 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 701 0)) { 702 device_printf(sc->sc_dev, "cannot reset receiver\n"); 703 return (1); 704 } 705 return (0); 706 } 707 708 /* 709 * Reset the receiver DMA engine. 710 * 711 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 712 * etc in order to reset the receiver DMA engine only and not do a full 713 * reset which amongst others also downs the link and clears the FIFOs. 714 */ 715 static void 716 gem_reset_rxdma(struct gem_softc *sc) 717 { 718 int i; 719 720 if (gem_reset_rx(sc) != 0) 721 return (gem_init_locked(sc)); 722 for (i = 0; i < GEM_NRXDESC; i++) 723 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 724 GEM_UPDATE_RXDESC(sc, i); 725 sc->sc_rxptr = 0; 726 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 727 728 /* NOTE: we use only 32-bit DMA addresses here. */ 729 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 730 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 731 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 732 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 733 gem_ringsize(GEM_NRXDESC /* XXX */) | 734 ((ETHER_HDR_LEN + sizeof(struct ip)) << 735 GEM_RX_CONFIG_CXM_START_SHFT) | 736 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 737 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 738 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 739 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 740 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 741 GEM_RX_BLANKING_TIME_SHIFT) | 6); 742 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 743 (3 * sc->sc_rxfifosize / 256) | 744 ((sc->sc_rxfifosize / 256) << 12)); 745 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 746 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 747 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 748 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 749 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 750 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE); 751 } 752 753 static int 754 gem_reset_tx(struct gem_softc *sc) 755 { 756 757 /* 758 * Resetting while DMA is in progress can cause a bus hang, so we 759 * disable DMA first. 760 */ 761 gem_disable_tx(sc); 762 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 763 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 764 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 765 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 766 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 767 768 /* Finally, reset the ETX. */ 769 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX); 770 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 771 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 772 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 773 0)) { 774 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 775 return (1); 776 } 777 return (0); 778 } 779 780 static int 781 gem_disable_rx(struct gem_softc *sc) 782 { 783 784 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 785 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 786 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 787 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 788 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 789 0)); 790 } 791 792 static int 793 gem_disable_tx(struct gem_softc *sc) 794 { 795 796 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 797 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 798 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 799 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 800 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 801 0)); 802 } 803 804 static int 805 gem_meminit(struct gem_softc *sc) 806 { 807 struct gem_rxsoft *rxs; 808 int error, i; 809 810 GEM_LOCK_ASSERT(sc, MA_OWNED); 811 812 /* 813 * Initialize the transmit descriptor ring. 814 */ 815 for (i = 0; i < GEM_NTXDESC; i++) { 816 sc->sc_txdescs[i].gd_flags = 0; 817 sc->sc_txdescs[i].gd_addr = 0; 818 } 819 sc->sc_txfree = GEM_MAXTXFREE; 820 sc->sc_txnext = 0; 821 sc->sc_txwin = 0; 822 823 /* 824 * Initialize the receive descriptor and receive job 825 * descriptor rings. 826 */ 827 for (i = 0; i < GEM_NRXDESC; i++) { 828 rxs = &sc->sc_rxsoft[i]; 829 if (rxs->rxs_mbuf == NULL) { 830 if ((error = gem_add_rxbuf(sc, i)) != 0) { 831 device_printf(sc->sc_dev, 832 "unable to allocate or map RX buffer %d, " 833 "error = %d\n", i, error); 834 /* 835 * XXX we should attempt to run with fewer 836 * receive buffers instead of just failing. 837 */ 838 gem_rxdrain(sc); 839 return (1); 840 } 841 } else 842 GEM_INIT_RXDESC(sc, i); 843 } 844 sc->sc_rxptr = 0; 845 846 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 847 848 return (0); 849 } 850 851 static u_int 852 gem_ringsize(u_int sz) 853 { 854 855 switch (sz) { 856 case 32: 857 return (GEM_RING_SZ_32); 858 case 64: 859 return (GEM_RING_SZ_64); 860 case 128: 861 return (GEM_RING_SZ_128); 862 case 256: 863 return (GEM_RING_SZ_256); 864 case 512: 865 return (GEM_RING_SZ_512); 866 case 1024: 867 return (GEM_RING_SZ_1024); 868 case 2048: 869 return (GEM_RING_SZ_2048); 870 case 4096: 871 return (GEM_RING_SZ_4096); 872 case 8192: 873 return (GEM_RING_SZ_8192); 874 default: 875 printf("%s: invalid ring size %d\n", __func__, sz); 876 return (GEM_RING_SZ_32); 877 } 878 } 879 880 static void 881 gem_init(void *xsc) 882 { 883 struct gem_softc *sc = xsc; 884 885 GEM_LOCK(sc); 886 gem_init_locked(sc); 887 GEM_UNLOCK(sc); 888 } 889 890 /* 891 * Initialization of interface; set up initialization block 892 * and transmit/receive descriptor rings. 893 */ 894 static void 895 gem_init_locked(struct gem_softc *sc) 896 { 897 struct ifnet *ifp = sc->sc_ifp; 898 uint32_t v; 899 900 GEM_LOCK_ASSERT(sc, MA_OWNED); 901 902 #ifdef GEM_DEBUG 903 CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 904 __func__); 905 #endif 906 /* 907 * Initialization sequence. The numbered steps below correspond 908 * to the sequence outlined in section 6.3.5.1 in the Ethernet 909 * Channel Engine manual (part of the PCIO manual). 910 * See also the STP2002-STQ document from Sun Microsystems. 911 */ 912 913 /* step 1 & 2. Reset the Ethernet Channel. */ 914 gem_stop(ifp, 0); 915 gem_reset(sc); 916 #ifdef GEM_DEBUG 917 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 918 __func__); 919 #endif 920 921 /* Re-initialize the MIF. */ 922 gem_mifinit(sc); 923 924 /* step 3. Setup data structures in host memory. */ 925 if (gem_meminit(sc) != 0) 926 return; 927 928 /* step 4. TX MAC registers & counters */ 929 gem_init_regs(sc); 930 931 /* step 5. RX MAC registers & counters */ 932 gem_setladrf(sc); 933 934 /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 935 /* NOTE: we use only 32-bit DMA addresses here. */ 936 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 937 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 938 939 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 940 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 941 #ifdef GEM_DEBUG 942 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 943 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 944 #endif 945 946 /* step 8. Global Configuration & Interrupt Mask */ 947 948 /* 949 * Set the internal arbitration to "infinite" bursts of the 950 * maximum length of 31 * 64 bytes so DMA transfers aren't 951 * split up in cache line size chunks. This greatly improves 952 * RX performance. 953 * Enable silicon bug workarounds for the Apple variants. 954 */ 955 GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 956 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 957 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 958 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 959 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 960 961 GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 962 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 963 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 964 GEM_INTR_BERR 965 #ifdef GEM_DEBUG 966 | GEM_INTR_PCS | GEM_INTR_MIF 967 #endif 968 )); 969 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 970 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 971 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 972 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 973 GEM_MAC_TX_PEAK_EXP); 974 #ifdef GEM_DEBUG 975 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 976 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 977 #else 978 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 979 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 980 #endif 981 982 /* step 9. ETX Configuration: use mostly default values. */ 983 984 /* Enable DMA. */ 985 v = gem_ringsize(GEM_NTXDESC); 986 /* Set TX FIFO threshold and enable DMA. */ 987 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 988 GEM_TX_CONFIG_TXFIFO_TH; 989 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 990 991 /* step 10. ERX Configuration */ 992 993 /* Encode Receive Descriptor ring size. */ 994 v = gem_ringsize(GEM_NRXDESC /* XXX */); 995 /* RX TCP/UDP checksum offset */ 996 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 997 GEM_RX_CONFIG_CXM_START_SHFT); 998 /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 999 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1000 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1001 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1002 GEM_RX_CONFIG_RXDMA_EN); 1003 1004 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1005 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1006 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1007 GEM_RX_BLANKING_TIME_SHIFT) | 6); 1008 1009 /* 1010 * The following value is for an OFF Threshold of about 3/4 full 1011 * and an ON Threshold of 1/4 full. 1012 */ 1013 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 1014 (3 * sc->sc_rxfifosize / 256) | 1015 ((sc->sc_rxfifosize / 256) << 12)); 1016 1017 /* step 11. Configure Media. */ 1018 1019 /* step 12. RX_MAC Configuration Register */ 1020 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1021 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1022 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 1023 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1024 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1025 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1026 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1027 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 1028 1029 /* step 13. TX_MAC Configuration Register */ 1030 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1031 v |= GEM_MAC_TX_ENABLE; 1032 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1033 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1034 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1035 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1036 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1037 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1038 1039 /* step 14. Issue Transmit Pending command. */ 1040 1041 /* step 15. Give the reciever a swift kick. */ 1042 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 1043 1044 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1045 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1046 1047 mii_mediachg(sc->sc_mii); 1048 1049 /* Start the one second timer. */ 1050 sc->sc_wdog_timer = 0; 1051 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1052 } 1053 1054 static int 1055 gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 1056 { 1057 bus_dma_segment_t txsegs[GEM_NTXSEGS]; 1058 struct gem_txsoft *txs; 1059 struct ip *ip; 1060 struct mbuf *m; 1061 uint64_t cflags, flags; 1062 int error, nexttx, nsegs, offset, seg; 1063 1064 GEM_LOCK_ASSERT(sc, MA_OWNED); 1065 1066 /* Get a work queue entry. */ 1067 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1068 /* Ran out of descriptors. */ 1069 return (ENOBUFS); 1070 } 1071 1072 cflags = 0; 1073 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1074 if (M_WRITABLE(*m_head) == 0) { 1075 m = m_dup(*m_head, M_DONTWAIT); 1076 m_freem(*m_head); 1077 *m_head = m; 1078 if (m == NULL) 1079 return (ENOBUFS); 1080 } 1081 offset = sizeof(struct ether_header); 1082 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1083 if (m == NULL) { 1084 *m_head = NULL; 1085 return (ENOBUFS); 1086 } 1087 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1088 offset += (ip->ip_hl << 2); 1089 cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1090 ((offset + m->m_pkthdr.csum_data) << 1091 GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1092 *m_head = m; 1093 } 1094 1095 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1096 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1097 if (error == EFBIG) { 1098 m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 1099 if (m == NULL) { 1100 m_freem(*m_head); 1101 *m_head = NULL; 1102 return (ENOBUFS); 1103 } 1104 *m_head = m; 1105 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1106 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1107 BUS_DMA_NOWAIT); 1108 if (error != 0) { 1109 m_freem(*m_head); 1110 *m_head = NULL; 1111 return (error); 1112 } 1113 } else if (error != 0) 1114 return (error); 1115 /* If nsegs is wrong then the stack is corrupt. */ 1116 KASSERT(nsegs <= GEM_NTXSEGS, 1117 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1118 if (nsegs == 0) { 1119 m_freem(*m_head); 1120 *m_head = NULL; 1121 return (EIO); 1122 } 1123 1124 /* 1125 * Ensure we have enough descriptors free to describe 1126 * the packet. Note, we always reserve one descriptor 1127 * at the end of the ring as a termination point, in 1128 * order to prevent wrap-around. 1129 */ 1130 if (nsegs > sc->sc_txfree - 1) { 1131 txs->txs_ndescs = 0; 1132 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1133 return (ENOBUFS); 1134 } 1135 1136 txs->txs_ndescs = nsegs; 1137 txs->txs_firstdesc = sc->sc_txnext; 1138 nexttx = txs->txs_firstdesc; 1139 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1140 #ifdef GEM_DEBUG 1141 CTR6(KTR_GEM, 1142 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1143 __func__, seg, nexttx, txsegs[seg].ds_len, 1144 txsegs[seg].ds_addr, 1145 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1146 #endif 1147 sc->sc_txdescs[nexttx].gd_addr = 1148 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1149 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1150 ("%s: segment size too large!", __func__)); 1151 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1152 sc->sc_txdescs[nexttx].gd_flags = 1153 GEM_DMA_WRITE(sc, flags | cflags); 1154 txs->txs_lastdesc = nexttx; 1155 } 1156 1157 /* Set EOP on the last descriptor. */ 1158 #ifdef GEM_DEBUG 1159 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1160 __func__, seg, nexttx); 1161 #endif 1162 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1163 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1164 1165 /* Lastly set SOP on the first descriptor. */ 1166 #ifdef GEM_DEBUG 1167 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1168 __func__, seg, nexttx); 1169 #endif 1170 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1171 sc->sc_txwin = 0; 1172 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1173 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1174 GEM_TD_START_OF_PACKET); 1175 } else 1176 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1177 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1178 1179 /* Sync the DMA map. */ 1180 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1181 BUS_DMASYNC_PREWRITE); 1182 1183 #ifdef GEM_DEBUG 1184 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1185 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1186 txs->txs_ndescs); 1187 #endif 1188 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1189 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1190 txs->txs_mbuf = *m_head; 1191 1192 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1193 sc->sc_txfree -= txs->txs_ndescs; 1194 1195 return (0); 1196 } 1197 1198 static void 1199 gem_init_regs(struct gem_softc *sc) 1200 { 1201 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1202 1203 GEM_LOCK_ASSERT(sc, MA_OWNED); 1204 1205 /* These registers are not cleared on reset. */ 1206 if ((sc->sc_flags & GEM_INITED) == 0) { 1207 /* magic values */ 1208 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1209 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1210 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 1211 1212 /* min frame length */ 1213 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1214 /* max frame length and max burst size */ 1215 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1216 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1217 1218 /* more magic values */ 1219 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1220 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1221 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1222 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088); 1223 1224 /* random number seed */ 1225 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1226 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1227 1228 /* secondary MAC address: 0:0:0:0:0:0 */ 1229 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1230 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1231 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1232 1233 /* MAC control address: 01:80:c2:00:00:01 */ 1234 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1235 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1236 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 1237 1238 /* MAC filter address: 0:0:0:0:0:0 */ 1239 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1240 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1241 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1242 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1243 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 1244 1245 sc->sc_flags |= GEM_INITED; 1246 } 1247 1248 /* Counters need to be zeroed. */ 1249 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1250 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1251 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1252 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1253 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1254 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1255 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1256 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1257 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1258 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1259 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 1260 1261 /* Set XOFF PAUSE time. */ 1262 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1263 1264 /* Set the station address. */ 1265 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1266 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1267 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1268 1269 /* Enable MII outputs. */ 1270 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 1271 } 1272 1273 static void 1274 gem_start(struct ifnet *ifp) 1275 { 1276 struct gem_softc *sc = ifp->if_softc; 1277 1278 GEM_LOCK(sc); 1279 gem_start_locked(ifp); 1280 GEM_UNLOCK(sc); 1281 } 1282 1283 static inline void 1284 gem_txkick(struct gem_softc *sc) 1285 { 1286 1287 /* 1288 * Update the TX kick register. This register has to point to the 1289 * descriptor after the last valid one and for optimum performance 1290 * should be incremented in multiples of 4 (the DMA engine fetches/ 1291 * updates descriptors in batches of 4). 1292 */ 1293 #ifdef GEM_DEBUG 1294 CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1295 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1296 #endif 1297 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1298 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1299 } 1300 1301 static void 1302 gem_start_locked(struct ifnet *ifp) 1303 { 1304 struct gem_softc *sc = ifp->if_softc; 1305 struct mbuf *m; 1306 int kicked, ntx; 1307 1308 GEM_LOCK_ASSERT(sc, MA_OWNED); 1309 1310 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1311 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 1312 return; 1313 1314 #ifdef GEM_DEBUG 1315 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1316 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1317 sc->sc_txnext); 1318 #endif 1319 ntx = 0; 1320 kicked = 0; 1321 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1322 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1323 if (m == NULL) 1324 break; 1325 if (gem_load_txmbuf(sc, &m) != 0) { 1326 if (m == NULL) 1327 break; 1328 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1329 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1330 break; 1331 } 1332 if ((sc->sc_txnext % 4) == 0) { 1333 gem_txkick(sc); 1334 kicked = 1; 1335 } else 1336 kicked = 0; 1337 ntx++; 1338 BPF_MTAP(ifp, m); 1339 } 1340 1341 if (ntx > 0) { 1342 if (kicked == 0) 1343 gem_txkick(sc); 1344 #ifdef GEM_DEBUG 1345 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1346 device_get_name(sc->sc_dev), sc->sc_txnext); 1347 #endif 1348 1349 /* Set a watchdog timer in case the chip flakes out. */ 1350 sc->sc_wdog_timer = 5; 1351 #ifdef GEM_DEBUG 1352 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1353 device_get_name(sc->sc_dev), __func__, 1354 sc->sc_wdog_timer); 1355 #endif 1356 } 1357 } 1358 1359 static void 1360 gem_tint(struct gem_softc *sc) 1361 { 1362 struct ifnet *ifp = sc->sc_ifp; 1363 struct gem_txsoft *txs; 1364 int progress; 1365 uint32_t txlast; 1366 #ifdef GEM_DEBUG 1367 int i; 1368 1369 GEM_LOCK_ASSERT(sc, MA_OWNED); 1370 1371 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1372 #endif 1373 1374 /* 1375 * Go through our TX list and free mbufs for those 1376 * frames that have been transmitted. 1377 */ 1378 progress = 0; 1379 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1380 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1381 #ifdef GEM_DEBUG 1382 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1383 printf(" txsoft %p transmit chain:\n", txs); 1384 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1385 printf("descriptor %d: ", i); 1386 printf("gd_flags: 0x%016llx\t", 1387 (long long)GEM_DMA_READ(sc, 1388 sc->sc_txdescs[i].gd_flags)); 1389 printf("gd_addr: 0x%016llx\n", 1390 (long long)GEM_DMA_READ(sc, 1391 sc->sc_txdescs[i].gd_addr)); 1392 if (i == txs->txs_lastdesc) 1393 break; 1394 } 1395 } 1396 #endif 1397 1398 /* 1399 * In theory, we could harvest some descriptors before 1400 * the ring is empty, but that's a bit complicated. 1401 * 1402 * GEM_TX_COMPLETION points to the last descriptor 1403 * processed + 1. 1404 */ 1405 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1406 #ifdef GEM_DEBUG 1407 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 1408 "txs->txs_lastdesc = %d, txlast = %d", 1409 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1410 #endif 1411 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1412 if ((txlast >= txs->txs_firstdesc) && 1413 (txlast <= txs->txs_lastdesc)) 1414 break; 1415 } else { 1416 /* Ick -- this command wraps. */ 1417 if ((txlast >= txs->txs_firstdesc) || 1418 (txlast <= txs->txs_lastdesc)) 1419 break; 1420 } 1421 1422 #ifdef GEM_DEBUG 1423 CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1424 #endif 1425 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1426 1427 sc->sc_txfree += txs->txs_ndescs; 1428 1429 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1430 BUS_DMASYNC_POSTWRITE); 1431 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1432 if (txs->txs_mbuf != NULL) { 1433 m_freem(txs->txs_mbuf); 1434 txs->txs_mbuf = NULL; 1435 } 1436 1437 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1438 1439 ifp->if_opackets++; 1440 progress = 1; 1441 } 1442 1443 #ifdef GEM_DEBUG 1444 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1445 "GEM_TX_COMPLETION %x", 1446 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1447 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1448 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1449 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1450 #endif 1451 1452 if (progress) { 1453 if (sc->sc_txfree == GEM_NTXDESC - 1) 1454 sc->sc_txwin = 0; 1455 1456 /* 1457 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1458 * and restart. 1459 */ 1460 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1461 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1462 sc->sc_wdog_timer = 0; 1463 gem_start_locked(ifp); 1464 } 1465 1466 #ifdef GEM_DEBUG 1467 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1468 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1469 #endif 1470 } 1471 1472 #ifdef GEM_RINT_TIMEOUT 1473 static void 1474 gem_rint_timeout(void *arg) 1475 { 1476 struct gem_softc *sc = arg; 1477 1478 GEM_LOCK_ASSERT(sc, MA_OWNED); 1479 1480 gem_rint(sc); 1481 } 1482 #endif 1483 1484 static void 1485 gem_rint(struct gem_softc *sc) 1486 { 1487 struct ifnet *ifp = sc->sc_ifp; 1488 struct mbuf *m; 1489 uint64_t rxstat; 1490 uint32_t rxcomp; 1491 1492 GEM_LOCK_ASSERT(sc, MA_OWNED); 1493 1494 #ifdef GEM_RINT_TIMEOUT 1495 callout_stop(&sc->sc_rx_ch); 1496 #endif 1497 #ifdef GEM_DEBUG 1498 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1499 #endif 1500 1501 /* 1502 * Read the completion register once. This limits 1503 * how long the following loop can execute. 1504 */ 1505 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1506 #ifdef GEM_DEBUG 1507 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1508 __func__, sc->sc_rxptr, rxcomp); 1509 #endif 1510 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1511 for (; sc->sc_rxptr != rxcomp;) { 1512 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1513 rxstat = GEM_DMA_READ(sc, 1514 sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 1515 1516 if (rxstat & GEM_RD_OWN) { 1517 #ifdef GEM_RINT_TIMEOUT 1518 /* 1519 * The descriptor is still marked as owned, although 1520 * it is supposed to have completed. This has been 1521 * observed on some machines. Just exiting here 1522 * might leave the packet sitting around until another 1523 * one arrives to trigger a new interrupt, which is 1524 * generally undesirable, so set up a timeout. 1525 */ 1526 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1527 gem_rint_timeout, sc); 1528 #endif 1529 m = NULL; 1530 goto kickit; 1531 } 1532 1533 if (rxstat & GEM_RD_BAD_CRC) { 1534 ifp->if_ierrors++; 1535 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1536 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1537 m = NULL; 1538 goto kickit; 1539 } 1540 1541 #ifdef GEM_DEBUG 1542 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1543 printf(" rxsoft %p descriptor %d: ", 1544 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1545 printf("gd_flags: 0x%016llx\t", 1546 (long long)GEM_DMA_READ(sc, 1547 sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1548 printf("gd_addr: 0x%016llx\n", 1549 (long long)GEM_DMA_READ(sc, 1550 sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 1551 } 1552 #endif 1553 1554 /* 1555 * Allocate a new mbuf cluster. If that fails, we are 1556 * out of memory, and must drop the packet and recycle 1557 * the buffer that's already attached to this descriptor. 1558 */ 1559 if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 1560 ifp->if_ierrors++; 1561 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1562 m = NULL; 1563 } 1564 1565 kickit: 1566 /* 1567 * Update the RX kick register. This register has to point 1568 * to the descriptor after the last valid one (before the 1569 * current batch) and for optimum performance should be 1570 * incremented in multiples of 4 (the DMA engine fetches/ 1571 * updates descriptors in batches of 4). 1572 */ 1573 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1574 if ((sc->sc_rxptr % 4) == 0) { 1575 GEM_CDSYNC(sc, 1576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1577 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1578 (sc->sc_rxptr + GEM_NRXDESC - 4) & 1579 GEM_NRXDESC_MASK); 1580 } 1581 1582 if (m == NULL) { 1583 if (rxstat & GEM_RD_OWN) 1584 break; 1585 continue; 1586 } 1587 1588 ifp->if_ipackets++; 1589 m->m_data += ETHER_ALIGN; /* first byte offset */ 1590 m->m_pkthdr.rcvif = ifp; 1591 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 1592 1593 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1594 gem_rxcksum(m, rxstat); 1595 1596 /* Pass it on. */ 1597 GEM_UNLOCK(sc); 1598 (*ifp->if_input)(ifp, m); 1599 GEM_LOCK(sc); 1600 } 1601 1602 #ifdef GEM_DEBUG 1603 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1604 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1605 #endif 1606 } 1607 1608 static int 1609 gem_add_rxbuf(struct gem_softc *sc, int idx) 1610 { 1611 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1612 struct mbuf *m; 1613 bus_dma_segment_t segs[1]; 1614 int error, nsegs; 1615 1616 GEM_LOCK_ASSERT(sc, MA_OWNED); 1617 1618 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1619 if (m == NULL) 1620 return (ENOBUFS); 1621 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1622 1623 #ifdef GEM_DEBUG 1624 /* Bzero the packet to check DMA. */ 1625 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1626 #endif 1627 1628 if (rxs->rxs_mbuf != NULL) { 1629 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1630 BUS_DMASYNC_POSTREAD); 1631 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1632 } 1633 1634 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1635 m, segs, &nsegs, BUS_DMA_NOWAIT); 1636 if (error != 0) { 1637 device_printf(sc->sc_dev, 1638 "cannot load RS DMA map %d, error = %d\n", idx, error); 1639 m_freem(m); 1640 return (error); 1641 } 1642 /* If nsegs is wrong then the stack is corrupt. */ 1643 KASSERT(nsegs == 1, 1644 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1645 rxs->rxs_mbuf = m; 1646 rxs->rxs_paddr = segs[0].ds_addr; 1647 1648 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1649 BUS_DMASYNC_PREREAD); 1650 1651 GEM_INIT_RXDESC(sc, idx); 1652 1653 return (0); 1654 } 1655 1656 static void 1657 gem_eint(struct gem_softc *sc, u_int status) 1658 { 1659 1660 sc->sc_ifp->if_ierrors++; 1661 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1662 gem_reset_rxdma(sc); 1663 return; 1664 } 1665 1666 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1667 if ((status & GEM_INTR_BERR) != 0) { 1668 if ((sc->sc_flags & GEM_PCI) != 0) 1669 printf(", PCI bus error 0x%x\n", 1670 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1671 else 1672 printf(", SBus error 0x%x\n", 1673 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1674 } 1675 } 1676 1677 void 1678 gem_intr(void *v) 1679 { 1680 struct gem_softc *sc = v; 1681 uint32_t status, status2; 1682 1683 GEM_LOCK(sc); 1684 status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1685 1686 #ifdef GEM_DEBUG 1687 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1688 device_get_name(sc->sc_dev), __func__, 1689 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1690 1691 /* 1692 * PCS interrupts must be cleared, otherwise no traffic is passed! 1693 */ 1694 if ((status & GEM_INTR_PCS) != 0) { 1695 status2 = 1696 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1697 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1698 if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1699 device_printf(sc->sc_dev, 1700 "%s: PCS link status changed\n", __func__); 1701 } 1702 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1703 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1704 if ((status2 & GEM_MAC_PAUSED) != 0) 1705 device_printf(sc->sc_dev, 1706 "%s: PAUSE received (PAUSE time %d slots)\n", 1707 __func__, GEM_MAC_PAUSE_TIME(status2)); 1708 if ((status2 & GEM_MAC_PAUSE) != 0) 1709 device_printf(sc->sc_dev, 1710 "%s: transited to PAUSE state\n", __func__); 1711 if ((status2 & GEM_MAC_RESUME) != 0) 1712 device_printf(sc->sc_dev, 1713 "%s: transited to non-PAUSE state\n", __func__); 1714 } 1715 if ((status & GEM_INTR_MIF) != 0) 1716 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1717 #endif 1718 1719 if (__predict_false(status & 1720 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 1721 gem_eint(sc, status); 1722 1723 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1724 gem_rint(sc); 1725 1726 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1727 gem_tint(sc); 1728 1729 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1730 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1731 if ((status2 & 1732 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1733 GEM_MAC_TX_PEAK_EXP)) != 0) 1734 device_printf(sc->sc_dev, 1735 "MAC TX fault, status %x\n", status2); 1736 if ((status2 & 1737 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1738 sc->sc_ifp->if_oerrors++; 1739 gem_init_locked(sc); 1740 } 1741 } 1742 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1743 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1744 /* 1745 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1746 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1747 * silicon bug so handle them silently. Moreover, it's 1748 * likely that the receiver has hung so we reset it. 1749 */ 1750 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1751 sc->sc_ifp->if_ierrors++; 1752 gem_reset_rxdma(sc); 1753 } else if ((status2 & 1754 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1755 device_printf(sc->sc_dev, 1756 "MAC RX fault, status %x\n", status2); 1757 } 1758 GEM_UNLOCK(sc); 1759 } 1760 1761 static int 1762 gem_watchdog(struct gem_softc *sc) 1763 { 1764 struct ifnet *ifp = sc->sc_ifp; 1765 1766 GEM_LOCK_ASSERT(sc, MA_OWNED); 1767 1768 #ifdef GEM_DEBUG 1769 CTR4(KTR_GEM, 1770 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1771 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1772 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1773 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1774 CTR4(KTR_GEM, 1775 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1776 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1777 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1778 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1779 #endif 1780 1781 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1782 return (0); 1783 1784 if ((sc->sc_flags & GEM_LINK) != 0) 1785 device_printf(sc->sc_dev, "device timeout\n"); 1786 else if (bootverbose) 1787 device_printf(sc->sc_dev, "device timeout (no link)\n"); 1788 ++ifp->if_oerrors; 1789 1790 /* Try to get more packets going. */ 1791 gem_init_locked(sc); 1792 gem_start_locked(ifp); 1793 return (EJUSTRETURN); 1794 } 1795 1796 static void 1797 gem_mifinit(struct gem_softc *sc) 1798 { 1799 1800 /* Configure the MIF in frame mode. */ 1801 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1802 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1803 } 1804 1805 /* 1806 * MII interface 1807 * 1808 * The MII interface supports at least three different operating modes: 1809 * 1810 * Bitbang mode is implemented using data, clock and output enable registers. 1811 * 1812 * Frame mode is implemented by loading a complete frame into the frame 1813 * register and polling the valid bit for completion. 1814 * 1815 * Polling mode uses the frame register but completion is indicated by 1816 * an interrupt. 1817 * 1818 */ 1819 int 1820 gem_mii_readreg(device_t dev, int phy, int reg) 1821 { 1822 struct gem_softc *sc; 1823 int n; 1824 uint32_t v; 1825 1826 #ifdef GEM_DEBUG_PHY 1827 printf("%s: phy %d reg %d\n", __func__, phy, reg); 1828 #endif 1829 1830 sc = device_get_softc(dev); 1831 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 1832 return (0); 1833 1834 if ((sc->sc_flags & GEM_SERDES) != 0) { 1835 switch (reg) { 1836 case MII_BMCR: 1837 reg = GEM_MII_CONTROL; 1838 break; 1839 case MII_BMSR: 1840 reg = GEM_MII_STATUS; 1841 break; 1842 case MII_PHYIDR1: 1843 case MII_PHYIDR2: 1844 return (0); 1845 case MII_ANAR: 1846 reg = GEM_MII_ANAR; 1847 break; 1848 case MII_ANLPAR: 1849 reg = GEM_MII_ANLPAR; 1850 break; 1851 case MII_EXTSR: 1852 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1853 default: 1854 device_printf(sc->sc_dev, 1855 "%s: unhandled register %d\n", __func__, reg); 1856 return (0); 1857 } 1858 return (GEM_BANK1_READ_4(sc, reg)); 1859 } 1860 1861 /* Construct the frame command. */ 1862 v = GEM_MIF_FRAME_READ | 1863 (phy << GEM_MIF_PHY_SHIFT) | 1864 (reg << GEM_MIF_REG_SHIFT); 1865 1866 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1867 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1868 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1869 for (n = 0; n < 100; n++) { 1870 DELAY(1); 1871 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1872 if (v & GEM_MIF_FRAME_TA0) 1873 return (v & GEM_MIF_FRAME_DATA); 1874 } 1875 1876 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1877 return (0); 1878 } 1879 1880 int 1881 gem_mii_writereg(device_t dev, int phy, int reg, int val) 1882 { 1883 struct gem_softc *sc; 1884 int n; 1885 uint32_t v; 1886 1887 #ifdef GEM_DEBUG_PHY 1888 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 1889 #endif 1890 1891 sc = device_get_softc(dev); 1892 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 1893 return (0); 1894 1895 if ((sc->sc_flags & GEM_SERDES) != 0) { 1896 switch (reg) { 1897 case MII_BMSR: 1898 reg = GEM_MII_STATUS; 1899 break; 1900 case MII_BMCR: 1901 reg = GEM_MII_CONTROL; 1902 if ((val & GEM_MII_CONTROL_RESET) == 0) 1903 break; 1904 GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1905 GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1906 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1907 if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1908 GEM_MII_CONTROL_RESET, 0)) 1909 device_printf(sc->sc_dev, 1910 "cannot reset PCS\n"); 1911 /* FALLTHROUGH */ 1912 case MII_ANAR: 1913 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1914 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1915 BUS_SPACE_BARRIER_WRITE); 1916 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1917 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1918 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1919 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1920 GEM_MII_CONFIG_ENABLE); 1921 return (0); 1922 case MII_ANLPAR: 1923 reg = GEM_MII_ANLPAR; 1924 break; 1925 default: 1926 device_printf(sc->sc_dev, 1927 "%s: unhandled register %d\n", __func__, reg); 1928 return (0); 1929 } 1930 GEM_BANK1_WRITE_4(sc, reg, val); 1931 return (0); 1932 } 1933 1934 /* Construct the frame command. */ 1935 v = GEM_MIF_FRAME_WRITE | 1936 (phy << GEM_MIF_PHY_SHIFT) | 1937 (reg << GEM_MIF_REG_SHIFT) | 1938 (val & GEM_MIF_FRAME_DATA); 1939 1940 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1941 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1942 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1943 for (n = 0; n < 100; n++) { 1944 DELAY(1); 1945 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1946 if (v & GEM_MIF_FRAME_TA0) 1947 return (1); 1948 } 1949 1950 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1951 return (0); 1952 } 1953 1954 void 1955 gem_mii_statchg(device_t dev) 1956 { 1957 struct gem_softc *sc; 1958 int gigabit; 1959 uint32_t rxcfg, txcfg, v; 1960 1961 sc = device_get_softc(dev); 1962 1963 GEM_LOCK_ASSERT(sc, MA_OWNED); 1964 1965 #ifdef GEM_DEBUG 1966 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1967 device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", 1968 __func__, sc->sc_phyad); 1969 #endif 1970 1971 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 1972 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 1973 sc->sc_flags |= GEM_LINK; 1974 else 1975 sc->sc_flags &= ~GEM_LINK; 1976 1977 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 1978 case IFM_1000_SX: 1979 case IFM_1000_LX: 1980 case IFM_1000_CX: 1981 case IFM_1000_T: 1982 gigabit = 1; 1983 break; 1984 default: 1985 gigabit = 0; 1986 } 1987 1988 /* 1989 * The configuration done here corresponds to the steps F) and 1990 * G) and as far as enabling of RX and TX MAC goes also step H) 1991 * of the initialization sequence outlined in section 3.2.1 of 1992 * the GEM Gigabit Ethernet ASIC Specification. 1993 */ 1994 1995 rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1996 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 1997 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 1998 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 1999 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2000 else if (gigabit != 0) { 2001 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2002 txcfg |= GEM_MAC_TX_CARR_EXTEND; 2003 } 2004 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 2005 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 2006 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2007 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2008 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2009 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2010 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 2011 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2012 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2013 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2014 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2015 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2016 2017 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2018 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2019 #ifdef notyet 2020 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2021 IFM_ETH_RXPAUSE) != 0) 2022 v |= GEM_MAC_CC_RX_PAUSE; 2023 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2024 IFM_ETH_TXPAUSE) != 0) 2025 v |= GEM_MAC_CC_TX_PAUSE; 2026 #endif 2027 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2028 2029 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2030 gigabit != 0) 2031 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2032 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2033 else 2034 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2035 GEM_MAC_SLOT_TIME_NORMAL); 2036 2037 /* XIF Configuration */ 2038 v = GEM_MAC_XIF_LINK_LED; 2039 v |= GEM_MAC_XIF_TX_MII_ENA; 2040 if ((sc->sc_flags & GEM_SERDES) == 0) { 2041 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2042 GEM_MIF_CONFIG_PHY_SEL) != 0) { 2043 /* External MII needs echo disable if half duplex. */ 2044 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2045 IFM_FDX) == 0) 2046 v |= GEM_MAC_XIF_ECHO_DISABL; 2047 } else 2048 /* 2049 * Internal MII needs buffer enable. 2050 * XXX buffer enable makes only sense for an 2051 * external PHY. 2052 */ 2053 v |= GEM_MAC_XIF_MII_BUF_ENA; 2054 } 2055 if (gigabit != 0) 2056 v |= GEM_MAC_XIF_GMII_MODE; 2057 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2058 v |= GEM_MAC_XIF_FDPLX_LED; 2059 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 2060 2061 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2062 (sc->sc_flags & GEM_LINK) != 0) { 2063 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2064 txcfg | GEM_MAC_TX_ENABLE); 2065 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2066 rxcfg | GEM_MAC_RX_ENABLE); 2067 } 2068 } 2069 2070 int 2071 gem_mediachange(struct ifnet *ifp) 2072 { 2073 struct gem_softc *sc = ifp->if_softc; 2074 int error; 2075 2076 /* XXX add support for serial media. */ 2077 2078 GEM_LOCK(sc); 2079 error = mii_mediachg(sc->sc_mii); 2080 GEM_UNLOCK(sc); 2081 return (error); 2082 } 2083 2084 void 2085 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2086 { 2087 struct gem_softc *sc = ifp->if_softc; 2088 2089 GEM_LOCK(sc); 2090 if ((ifp->if_flags & IFF_UP) == 0) { 2091 GEM_UNLOCK(sc); 2092 return; 2093 } 2094 2095 mii_pollstat(sc->sc_mii); 2096 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2097 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2098 GEM_UNLOCK(sc); 2099 } 2100 2101 static int 2102 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2103 { 2104 struct gem_softc *sc = ifp->if_softc; 2105 struct ifreq *ifr = (struct ifreq *)data; 2106 int error; 2107 2108 error = 0; 2109 switch (cmd) { 2110 case SIOCSIFFLAGS: 2111 GEM_LOCK(sc); 2112 if ((ifp->if_flags & IFF_UP) != 0) { 2113 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2114 ((ifp->if_flags ^ sc->sc_ifflags) & 2115 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2116 gem_setladrf(sc); 2117 else 2118 gem_init_locked(sc); 2119 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2120 gem_stop(ifp, 0); 2121 if ((ifp->if_flags & IFF_LINK0) != 0) 2122 sc->sc_csum_features |= CSUM_UDP; 2123 else 2124 sc->sc_csum_features &= ~CSUM_UDP; 2125 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2126 ifp->if_hwassist = sc->sc_csum_features; 2127 sc->sc_ifflags = ifp->if_flags; 2128 GEM_UNLOCK(sc); 2129 break; 2130 case SIOCADDMULTI: 2131 case SIOCDELMULTI: 2132 GEM_LOCK(sc); 2133 gem_setladrf(sc); 2134 GEM_UNLOCK(sc); 2135 break; 2136 case SIOCGIFMEDIA: 2137 case SIOCSIFMEDIA: 2138 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2139 break; 2140 case SIOCSIFCAP: 2141 GEM_LOCK(sc); 2142 ifp->if_capenable = ifr->ifr_reqcap; 2143 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2144 ifp->if_hwassist = sc->sc_csum_features; 2145 else 2146 ifp->if_hwassist = 0; 2147 GEM_UNLOCK(sc); 2148 break; 2149 default: 2150 error = ether_ioctl(ifp, cmd, data); 2151 break; 2152 } 2153 2154 return (error); 2155 } 2156 2157 static void 2158 gem_setladrf(struct gem_softc *sc) 2159 { 2160 struct ifnet *ifp = sc->sc_ifp; 2161 struct ifmultiaddr *inm; 2162 int i; 2163 uint32_t hash[16]; 2164 uint32_t crc, v; 2165 2166 GEM_LOCK_ASSERT(sc, MA_OWNED); 2167 2168 /* Get the current RX configuration. */ 2169 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2170 2171 /* 2172 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2173 * and hash filter. Depending on the case, the right bit will be 2174 * enabled. 2175 */ 2176 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2177 GEM_MAC_RX_PROMISC_GRP); 2178 2179 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2180 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2181 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2182 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 2183 0)) 2184 device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2185 2186 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2187 v |= GEM_MAC_RX_PROMISCUOUS; 2188 goto chipit; 2189 } 2190 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2191 v |= GEM_MAC_RX_PROMISC_GRP; 2192 goto chipit; 2193 } 2194 2195 /* 2196 * Set up multicast address filter by passing all multicast 2197 * addresses through a crc generator, and then using the high 2198 * order 8 bits as an index into the 256 bit logical address 2199 * filter. The high order 4 bits selects the word, while the 2200 * other 4 bits select the bit within the word (where bit 0 2201 * is the MSB). 2202 */ 2203 2204 /* Clear the hash table. */ 2205 memset(hash, 0, sizeof(hash)); 2206 2207 if_maddr_rlock(ifp); 2208 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2209 if (inm->ifma_addr->sa_family != AF_LINK) 2210 continue; 2211 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2212 inm->ifma_addr), ETHER_ADDR_LEN); 2213 2214 /* We just want the 8 most significant bits. */ 2215 crc >>= 24; 2216 2217 /* Set the corresponding bit in the filter. */ 2218 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2219 } 2220 if_maddr_runlock(ifp); 2221 2222 v |= GEM_MAC_RX_HASH_FILTER; 2223 2224 /* Now load the hash table into the chip (if we are using it). */ 2225 for (i = 0; i < 16; i++) 2226 GEM_BANK1_WRITE_4(sc, 2227 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 2228 hash[i]); 2229 2230 chipit: 2231 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2232 } 2233