1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 36 */ 37 38 #if 0 39 #define GEM_DEBUG 40 #endif 41 42 #if 0 /* XXX: In case of emergency, re-enable this. */ 43 #define GEM_RINT_TIMEOUT 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/callout.h> 50 #include <sys/endian.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/lock.h> 55 #include <sys/module.h> 56 #include <sys/mutex.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/rman.h> 60 61 #include <net/bpf.h> 62 #include <net/ethernet.h> 63 #include <net/if.h> 64 #include <net/if_arp.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/ip.h> 73 #include <netinet/tcp.h> 74 #include <netinet/udp.h> 75 76 #include <machine/bus.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <dev/gem/if_gemreg.h> 82 #include <dev/gem/if_gemvar.h> 83 84 CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85 CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86 87 #define GEM_TRIES 10000 88 89 /* 90 * The hardware supports basic TCP/UDP checksum offloading. However, 91 * the hardware doesn't compensate the checksum for UDP datagram which 92 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93 * by default. It can be reactivated by setting special link option 94 * link0 with ifconfig(8). 95 */ 96 #define GEM_CSUM_FEATURES (CSUM_TCP) 97 98 static int gem_add_rxbuf(struct gem_softc *sc, int idx); 99 static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 100 uint32_t clr, uint32_t set); 101 static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 102 int nsegs, int error); 103 static int gem_disable_rx(struct gem_softc *sc); 104 static int gem_disable_tx(struct gem_softc *sc); 105 static void gem_eint(struct gem_softc *sc, u_int status); 106 static void gem_init(void *xsc); 107 static void gem_init_locked(struct gem_softc *sc); 108 static void gem_init_regs(struct gem_softc *sc); 109 static int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 110 static int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 111 static int gem_meminit(struct gem_softc *sc); 112 static void gem_mifinit(struct gem_softc *sc); 113 static void gem_reset(struct gem_softc *sc); 114 static int gem_reset_rx(struct gem_softc *sc); 115 static void gem_reset_rxdma(struct gem_softc *sc); 116 static int gem_reset_tx(struct gem_softc *sc); 117 static u_int gem_ringsize(u_int sz); 118 static void gem_rint(struct gem_softc *sc); 119 #ifdef GEM_RINT_TIMEOUT 120 static void gem_rint_timeout(void *arg); 121 #endif 122 static inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 123 static void gem_rxdrain(struct gem_softc *sc); 124 static void gem_setladrf(struct gem_softc *sc); 125 static void gem_start(struct ifnet *ifp); 126 static void gem_start_locked(struct ifnet *ifp); 127 static void gem_stop(struct ifnet *ifp, int disable); 128 static void gem_tick(void *arg); 129 static void gem_tint(struct gem_softc *sc); 130 static inline void gem_txkick(struct gem_softc *sc); 131 static int gem_watchdog(struct gem_softc *sc); 132 133 devclass_t gem_devclass; 134 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 135 MODULE_DEPEND(gem, miibus, 1, 1, 1); 136 137 #ifdef GEM_DEBUG 138 #include <sys/ktr.h> 139 #define KTR_GEM KTR_SPARE2 140 #endif 141 142 #define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 143 gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 144 #define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 145 gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 146 147 int 148 gem_attach(struct gem_softc *sc) 149 { 150 struct gem_txsoft *txs; 151 struct ifnet *ifp; 152 int error, i; 153 uint32_t v; 154 155 if (bootverbose) 156 device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 157 158 /* Set up ifnet structure. */ 159 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160 if (ifp == NULL) 161 return (ENOSPC); 162 sc->sc_csum_features = GEM_CSUM_FEATURES; 163 ifp->if_softc = sc; 164 if_initname(ifp, device_get_name(sc->sc_dev), 165 device_get_unit(sc->sc_dev)); 166 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 167 ifp->if_start = gem_start; 168 ifp->if_ioctl = gem_ioctl; 169 ifp->if_init = gem_init; 170 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 171 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 172 IFQ_SET_READY(&ifp->if_snd); 173 174 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 175 #ifdef GEM_RINT_TIMEOUT 176 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 177 #endif 178 179 /* Make sure the chip is stopped. */ 180 gem_reset(sc); 181 182 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 184 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 185 NULL, &sc->sc_pdmatag); 186 if (error != 0) 187 goto fail_ifnet; 188 189 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 190 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 191 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 192 if (error != 0) 193 goto fail_ptag; 194 195 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 196 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 197 MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 199 if (error != 0) 200 goto fail_rtag; 201 202 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 203 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 204 sizeof(struct gem_control_data), 1, 205 sizeof(struct gem_control_data), 0, 206 NULL, NULL, &sc->sc_cdmatag); 207 if (error != 0) 208 goto fail_ttag; 209 210 /* 211 * Allocate the control data structures, create and load the 212 * DMA map for it. 213 */ 214 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 215 (void **)&sc->sc_control_data, 216 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 217 &sc->sc_cddmamap)) != 0) { 218 device_printf(sc->sc_dev, 219 "unable to allocate control data, error = %d\n", error); 220 goto fail_ctag; 221 } 222 223 sc->sc_cddma = 0; 224 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 225 sc->sc_control_data, sizeof(struct gem_control_data), 226 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 227 device_printf(sc->sc_dev, 228 "unable to load control data DMA map, error = %d\n", 229 error); 230 goto fail_cmem; 231 } 232 233 /* 234 * Initialize the transmit job descriptors. 235 */ 236 STAILQ_INIT(&sc->sc_txfreeq); 237 STAILQ_INIT(&sc->sc_txdirtyq); 238 239 /* 240 * Create the transmit buffer DMA maps. 241 */ 242 error = ENOMEM; 243 for (i = 0; i < GEM_TXQUEUELEN; i++) { 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 txs->txs_ndescs = 0; 247 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 248 &txs->txs_dmamap)) != 0) { 249 device_printf(sc->sc_dev, 250 "unable to create TX DMA map %d, error = %d\n", 251 i, error); 252 goto fail_txd; 253 } 254 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 262 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 device_printf(sc->sc_dev, 264 "unable to create RX DMA map %d, error = %d\n", 265 i, error); 266 goto fail_rxd; 267 } 268 sc->sc_rxsoft[i].rxs_mbuf = NULL; 269 } 270 271 /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 272 if ((sc->sc_flags & GEM_SERDES) != 0) 273 goto serdes; 274 275 /* Bad things will happen when touching this register on ERI. */ 276 if (sc->sc_variant != GEM_SUN_ERI) { 277 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 278 GEM_MII_DATAPATH_MII); 279 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 280 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 281 } 282 283 gem_mifinit(sc); 284 285 /* 286 * Look for an external PHY. 287 */ 288 error = ENXIO; 289 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 290 if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 291 v |= GEM_MIF_CONFIG_PHY_SEL; 292 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 293 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 294 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 295 switch (sc->sc_variant) { 296 case GEM_SUN_ERI: 297 sc->sc_phyad = GEM_PHYAD_EXTERNAL; 298 break; 299 default: 300 sc->sc_phyad = -1; 301 break; 302 } 303 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 304 gem_mediachange, gem_mediastatus); 305 } 306 307 /* 308 * Fall back on an internal PHY if no external PHY was found. 309 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 310 * trusted when the firmware has powered down the chip. 311 */ 312 if (error != 0 && 313 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 314 v &= ~GEM_MIF_CONFIG_PHY_SEL; 315 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 316 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 317 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 318 switch (sc->sc_variant) { 319 case GEM_SUN_ERI: 320 case GEM_APPLE_K2_GMAC: 321 sc->sc_phyad = GEM_PHYAD_INTERNAL; 322 break; 323 case GEM_APPLE_GMAC: 324 sc->sc_phyad = GEM_PHYAD_EXTERNAL; 325 break; 326 default: 327 sc->sc_phyad = -1; 328 break; 329 } 330 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 331 gem_mediachange, gem_mediastatus); 332 } 333 334 /* 335 * Try the external PCS SERDES if we didn't find any PHYs. 336 */ 337 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 338 serdes: 339 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 340 GEM_MII_DATAPATH_SERDES); 341 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 342 BUS_SPACE_BARRIER_WRITE); 343 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 344 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 345 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 346 BUS_SPACE_BARRIER_WRITE); 347 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 348 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 349 BUS_SPACE_BARRIER_WRITE); 350 sc->sc_flags |= GEM_SERDES; 351 sc->sc_phyad = GEM_PHYAD_EXTERNAL; 352 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 353 gem_mediachange, gem_mediastatus); 354 } 355 if (error != 0) { 356 device_printf(sc->sc_dev, "PHY probe failed: %d\n", error); 357 goto fail_rxd; 358 } 359 sc->sc_mii = device_get_softc(sc->sc_miibus); 360 361 /* 362 * From this point forward, the attachment cannot fail. A failure 363 * before this point releases all resources that may have been 364 * allocated. 365 */ 366 367 /* Get RX FIFO size. */ 368 sc->sc_rxfifosize = 64 * 369 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 370 371 /* Get TX FIFO size. */ 372 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 373 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 374 sc->sc_rxfifosize / 1024, v / 16); 375 376 /* Attach the interface. */ 377 ether_ifattach(ifp, sc->sc_enaddr); 378 379 /* 380 * Tell the upper layer(s) we support long frames/checksum offloads. 381 */ 382 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 383 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 384 ifp->if_hwassist |= sc->sc_csum_features; 385 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 386 387 return (0); 388 389 /* 390 * Free any resources we've allocated during the failed attach 391 * attempt. Do this in reverse order and fall through. 392 */ 393 fail_rxd: 394 for (i = 0; i < GEM_NRXDESC; i++) 395 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 396 bus_dmamap_destroy(sc->sc_rdmatag, 397 sc->sc_rxsoft[i].rxs_dmamap); 398 fail_txd: 399 for (i = 0; i < GEM_TXQUEUELEN; i++) 400 if (sc->sc_txsoft[i].txs_dmamap != NULL) 401 bus_dmamap_destroy(sc->sc_tdmatag, 402 sc->sc_txsoft[i].txs_dmamap); 403 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 404 fail_cmem: 405 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 406 sc->sc_cddmamap); 407 fail_ctag: 408 bus_dma_tag_destroy(sc->sc_cdmatag); 409 fail_ttag: 410 bus_dma_tag_destroy(sc->sc_tdmatag); 411 fail_rtag: 412 bus_dma_tag_destroy(sc->sc_rdmatag); 413 fail_ptag: 414 bus_dma_tag_destroy(sc->sc_pdmatag); 415 fail_ifnet: 416 if_free(ifp); 417 return (error); 418 } 419 420 void 421 gem_detach(struct gem_softc *sc) 422 { 423 struct ifnet *ifp = sc->sc_ifp; 424 int i; 425 426 ether_ifdetach(ifp); 427 GEM_LOCK(sc); 428 gem_stop(ifp, 1); 429 GEM_UNLOCK(sc); 430 callout_drain(&sc->sc_tick_ch); 431 #ifdef GEM_RINT_TIMEOUT 432 callout_drain(&sc->sc_rx_ch); 433 #endif 434 if_free(ifp); 435 device_delete_child(sc->sc_dev, sc->sc_miibus); 436 437 for (i = 0; i < GEM_NRXDESC; i++) 438 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 439 bus_dmamap_destroy(sc->sc_rdmatag, 440 sc->sc_rxsoft[i].rxs_dmamap); 441 for (i = 0; i < GEM_TXQUEUELEN; i++) 442 if (sc->sc_txsoft[i].txs_dmamap != NULL) 443 bus_dmamap_destroy(sc->sc_tdmatag, 444 sc->sc_txsoft[i].txs_dmamap); 445 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 446 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 447 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 448 sc->sc_cddmamap); 449 bus_dma_tag_destroy(sc->sc_cdmatag); 450 bus_dma_tag_destroy(sc->sc_tdmatag); 451 bus_dma_tag_destroy(sc->sc_rdmatag); 452 bus_dma_tag_destroy(sc->sc_pdmatag); 453 } 454 455 void 456 gem_suspend(struct gem_softc *sc) 457 { 458 struct ifnet *ifp = sc->sc_ifp; 459 460 GEM_LOCK(sc); 461 gem_stop(ifp, 0); 462 GEM_UNLOCK(sc); 463 } 464 465 void 466 gem_resume(struct gem_softc *sc) 467 { 468 struct ifnet *ifp = sc->sc_ifp; 469 470 GEM_LOCK(sc); 471 /* 472 * On resume all registers have to be initialized again like 473 * after power-on. 474 */ 475 sc->sc_flags &= ~GEM_INITED; 476 if (ifp->if_flags & IFF_UP) 477 gem_init_locked(sc); 478 GEM_UNLOCK(sc); 479 } 480 481 static inline void 482 gem_rxcksum(struct mbuf *m, uint64_t flags) 483 { 484 struct ether_header *eh; 485 struct ip *ip; 486 struct udphdr *uh; 487 uint16_t *opts; 488 int32_t hlen, len, pktlen; 489 uint32_t temp32; 490 uint16_t cksum; 491 492 pktlen = m->m_pkthdr.len; 493 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 494 return; 495 eh = mtod(m, struct ether_header *); 496 if (eh->ether_type != htons(ETHERTYPE_IP)) 497 return; 498 ip = (struct ip *)(eh + 1); 499 if (ip->ip_v != IPVERSION) 500 return; 501 502 hlen = ip->ip_hl << 2; 503 pktlen -= sizeof(struct ether_header); 504 if (hlen < sizeof(struct ip)) 505 return; 506 if (ntohs(ip->ip_len) < hlen) 507 return; 508 if (ntohs(ip->ip_len) != pktlen) 509 return; 510 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 511 return; /* Cannot handle fragmented packet. */ 512 513 switch (ip->ip_p) { 514 case IPPROTO_TCP: 515 if (pktlen < (hlen + sizeof(struct tcphdr))) 516 return; 517 break; 518 case IPPROTO_UDP: 519 if (pktlen < (hlen + sizeof(struct udphdr))) 520 return; 521 uh = (struct udphdr *)((uint8_t *)ip + hlen); 522 if (uh->uh_sum == 0) 523 return; /* no checksum */ 524 break; 525 default: 526 return; 527 } 528 529 cksum = ~(flags & GEM_RD_CHECKSUM); 530 /* checksum fixup for IP options */ 531 len = hlen - sizeof(struct ip); 532 if (len > 0) { 533 opts = (uint16_t *)(ip + 1); 534 for (; len > 0; len -= sizeof(uint16_t), opts++) { 535 temp32 = cksum - *opts; 536 temp32 = (temp32 >> 16) + (temp32 & 65535); 537 cksum = temp32 & 65535; 538 } 539 } 540 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 541 m->m_pkthdr.csum_data = cksum; 542 } 543 544 static void 545 gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 546 { 547 struct gem_softc *sc = xsc; 548 549 if (error != 0) 550 return; 551 if (nsegs != 1) 552 panic("%s: bad control buffer segment count", __func__); 553 sc->sc_cddma = segs[0].ds_addr; 554 } 555 556 static void 557 gem_tick(void *arg) 558 { 559 struct gem_softc *sc = arg; 560 struct ifnet *ifp = sc->sc_ifp; 561 uint32_t v; 562 563 GEM_LOCK_ASSERT(sc, MA_OWNED); 564 565 /* 566 * Unload collision and error counters. 567 */ 568 ifp->if_collisions += 569 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 570 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 571 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 572 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 573 ifp->if_collisions += v; 574 ifp->if_oerrors += v; 575 ifp->if_ierrors += 576 GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 577 GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 578 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 579 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 580 581 /* 582 * Then clear the hardware counters. 583 */ 584 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 585 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 586 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 587 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 588 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 589 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 590 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 591 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 592 593 mii_tick(sc->sc_mii); 594 595 if (gem_watchdog(sc) == EJUSTRETURN) 596 return; 597 598 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 599 } 600 601 static int 602 gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 603 uint32_t set) 604 { 605 int i; 606 uint32_t reg; 607 608 for (i = GEM_TRIES; i--; DELAY(100)) { 609 reg = GEM_BANKN_READ_M(bank, 4, sc, r); 610 if ((reg & clr) == 0 && (reg & set) == set) 611 return (1); 612 } 613 return (0); 614 } 615 616 static void 617 gem_reset(struct gem_softc *sc) 618 { 619 620 #ifdef GEM_DEBUG 621 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 622 #endif 623 gem_reset_rx(sc); 624 gem_reset_tx(sc); 625 626 /* Do a full reset. */ 627 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 628 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 629 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 630 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 631 device_printf(sc->sc_dev, "cannot reset device\n"); 632 } 633 634 static void 635 gem_rxdrain(struct gem_softc *sc) 636 { 637 struct gem_rxsoft *rxs; 638 int i; 639 640 for (i = 0; i < GEM_NRXDESC; i++) { 641 rxs = &sc->sc_rxsoft[i]; 642 if (rxs->rxs_mbuf != NULL) { 643 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 644 BUS_DMASYNC_POSTREAD); 645 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 646 m_freem(rxs->rxs_mbuf); 647 rxs->rxs_mbuf = NULL; 648 } 649 } 650 } 651 652 static void 653 gem_stop(struct ifnet *ifp, int disable) 654 { 655 struct gem_softc *sc = ifp->if_softc; 656 struct gem_txsoft *txs; 657 658 #ifdef GEM_DEBUG 659 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 660 #endif 661 662 callout_stop(&sc->sc_tick_ch); 663 #ifdef GEM_RINT_TIMEOUT 664 callout_stop(&sc->sc_rx_ch); 665 #endif 666 667 gem_reset_tx(sc); 668 gem_reset_rx(sc); 669 670 /* 671 * Release any queued transmit buffers. 672 */ 673 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 674 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 675 if (txs->txs_ndescs != 0) { 676 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 677 BUS_DMASYNC_POSTWRITE); 678 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 679 if (txs->txs_mbuf != NULL) { 680 m_freem(txs->txs_mbuf); 681 txs->txs_mbuf = NULL; 682 } 683 } 684 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 685 } 686 687 if (disable) 688 gem_rxdrain(sc); 689 690 /* 691 * Mark the interface down and cancel the watchdog timer. 692 */ 693 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 694 sc->sc_flags &= ~GEM_LINK; 695 sc->sc_wdog_timer = 0; 696 } 697 698 static int 699 gem_reset_rx(struct gem_softc *sc) 700 { 701 702 /* 703 * Resetting while DMA is in progress can cause a bus hang, so we 704 * disable DMA first. 705 */ 706 gem_disable_rx(sc); 707 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 708 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 709 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 710 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 711 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 712 713 /* Finally, reset the ERX. */ 714 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX); 715 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 716 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 717 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 718 0)) { 719 device_printf(sc->sc_dev, "cannot reset receiver\n"); 720 return (1); 721 } 722 return (0); 723 } 724 725 /* 726 * Reset the receiver DMA engine. 727 * 728 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 729 * etc in order to reset the receiver DMA engine only and not do a full 730 * reset which amongst others also downs the link and clears the FIFOs. 731 */ 732 static void 733 gem_reset_rxdma(struct gem_softc *sc) 734 { 735 int i; 736 737 if (gem_reset_rx(sc) != 0) 738 return (gem_init_locked(sc)); 739 for (i = 0; i < GEM_NRXDESC; i++) 740 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 741 GEM_UPDATE_RXDESC(sc, i); 742 sc->sc_rxptr = 0; 743 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 744 745 /* NOTE: we use only 32-bit DMA addresses here. */ 746 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 747 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 748 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 749 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 750 gem_ringsize(GEM_NRXDESC /* XXX */) | 751 ((ETHER_HDR_LEN + sizeof(struct ip)) << 752 GEM_RX_CONFIG_CXM_START_SHFT) | 753 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 754 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 755 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 756 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 757 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 758 GEM_RX_BLANKING_TIME_SHIFT) | 6); 759 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 760 (3 * sc->sc_rxfifosize / 256) | 761 ((sc->sc_rxfifosize / 256) << 12)); 762 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 763 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 764 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 765 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 766 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 767 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE); 768 } 769 770 static int 771 gem_reset_tx(struct gem_softc *sc) 772 { 773 774 /* 775 * Resetting while DMA is in progress can cause a bus hang, so we 776 * disable DMA first. 777 */ 778 gem_disable_tx(sc); 779 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 780 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 781 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 782 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 783 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 784 785 /* Finally, reset the ETX. */ 786 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX); 787 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 788 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 789 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 790 0)) { 791 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 792 return (1); 793 } 794 return (0); 795 } 796 797 static int 798 gem_disable_rx(struct gem_softc *sc) 799 { 800 801 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 802 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 803 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 804 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 805 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 806 0)); 807 } 808 809 static int 810 gem_disable_tx(struct gem_softc *sc) 811 { 812 813 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 814 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 815 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 816 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 817 return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 818 0)); 819 } 820 821 static int 822 gem_meminit(struct gem_softc *sc) 823 { 824 struct gem_rxsoft *rxs; 825 int error, i; 826 827 GEM_LOCK_ASSERT(sc, MA_OWNED); 828 829 /* 830 * Initialize the transmit descriptor ring. 831 */ 832 for (i = 0; i < GEM_NTXDESC; i++) { 833 sc->sc_txdescs[i].gd_flags = 0; 834 sc->sc_txdescs[i].gd_addr = 0; 835 } 836 sc->sc_txfree = GEM_MAXTXFREE; 837 sc->sc_txnext = 0; 838 sc->sc_txwin = 0; 839 840 /* 841 * Initialize the receive descriptor and receive job 842 * descriptor rings. 843 */ 844 for (i = 0; i < GEM_NRXDESC; i++) { 845 rxs = &sc->sc_rxsoft[i]; 846 if (rxs->rxs_mbuf == NULL) { 847 if ((error = gem_add_rxbuf(sc, i)) != 0) { 848 device_printf(sc->sc_dev, 849 "unable to allocate or map RX buffer %d, " 850 "error = %d\n", i, error); 851 /* 852 * XXX we should attempt to run with fewer 853 * receive buffers instead of just failing. 854 */ 855 gem_rxdrain(sc); 856 return (1); 857 } 858 } else 859 GEM_INIT_RXDESC(sc, i); 860 } 861 sc->sc_rxptr = 0; 862 863 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 864 865 return (0); 866 } 867 868 static u_int 869 gem_ringsize(u_int sz) 870 { 871 872 switch (sz) { 873 case 32: 874 return (GEM_RING_SZ_32); 875 case 64: 876 return (GEM_RING_SZ_64); 877 case 128: 878 return (GEM_RING_SZ_128); 879 case 256: 880 return (GEM_RING_SZ_256); 881 case 512: 882 return (GEM_RING_SZ_512); 883 case 1024: 884 return (GEM_RING_SZ_1024); 885 case 2048: 886 return (GEM_RING_SZ_2048); 887 case 4096: 888 return (GEM_RING_SZ_4096); 889 case 8192: 890 return (GEM_RING_SZ_8192); 891 default: 892 printf("%s: invalid ring size %d\n", __func__, sz); 893 return (GEM_RING_SZ_32); 894 } 895 } 896 897 static void 898 gem_init(void *xsc) 899 { 900 struct gem_softc *sc = xsc; 901 902 GEM_LOCK(sc); 903 gem_init_locked(sc); 904 GEM_UNLOCK(sc); 905 } 906 907 /* 908 * Initialization of interface; set up initialization block 909 * and transmit/receive descriptor rings. 910 */ 911 static void 912 gem_init_locked(struct gem_softc *sc) 913 { 914 struct ifnet *ifp = sc->sc_ifp; 915 uint32_t v; 916 917 GEM_LOCK_ASSERT(sc, MA_OWNED); 918 919 #ifdef GEM_DEBUG 920 CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 921 __func__); 922 #endif 923 /* 924 * Initialization sequence. The numbered steps below correspond 925 * to the sequence outlined in section 6.3.5.1 in the Ethernet 926 * Channel Engine manual (part of the PCIO manual). 927 * See also the STP2002-STQ document from Sun Microsystems. 928 */ 929 930 /* step 1 & 2. Reset the Ethernet Channel. */ 931 gem_stop(ifp, 0); 932 gem_reset(sc); 933 #ifdef GEM_DEBUG 934 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 935 __func__); 936 #endif 937 938 if ((sc->sc_flags & GEM_SERDES) == 0) 939 /* Re-initialize the MIF. */ 940 gem_mifinit(sc); 941 942 /* step 3. Setup data structures in host memory. */ 943 if (gem_meminit(sc) != 0) 944 return; 945 946 /* step 4. TX MAC registers & counters */ 947 gem_init_regs(sc); 948 949 /* step 5. RX MAC registers & counters */ 950 gem_setladrf(sc); 951 952 /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 953 /* NOTE: we use only 32-bit DMA addresses here. */ 954 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 955 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 956 957 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 958 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 959 #ifdef GEM_DEBUG 960 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 961 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 962 #endif 963 964 /* step 8. Global Configuration & Interrupt Mask */ 965 966 /* 967 * Set the internal arbitration to "infinite" bursts of the 968 * maximum length of 31 * 64 bytes so DMA transfers aren't 969 * split up in cache line size chunks. This greatly improves 970 * RX performance. 971 * Enable silicon bug workarounds for the Apple variants. 972 */ 973 GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 974 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 975 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 976 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 977 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 978 979 GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 980 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 981 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 982 GEM_INTR_BERR 983 #ifdef GEM_DEBUG 984 | GEM_INTR_PCS | GEM_INTR_MIF 985 #endif 986 )); 987 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 988 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 989 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 990 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 991 GEM_MAC_TX_PEAK_EXP); 992 #ifdef GEM_DEBUG 993 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 994 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 995 #else 996 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 997 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 998 #endif 999 1000 /* step 9. ETX Configuration: use mostly default values. */ 1001 1002 /* Enable DMA. */ 1003 v = gem_ringsize(GEM_NTXDESC); 1004 /* Set TX FIFO threshold and enable DMA. */ 1005 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1006 GEM_TX_CONFIG_TXFIFO_TH; 1007 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 1008 1009 /* step 10. ERX Configuration */ 1010 1011 /* Encode Receive Descriptor ring size. */ 1012 v = gem_ringsize(GEM_NRXDESC /* XXX */); 1013 /* RX TCP/UDP checksum offset */ 1014 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 1015 GEM_RX_CONFIG_CXM_START_SHFT); 1016 /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1017 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1018 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1019 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1020 GEM_RX_CONFIG_RXDMA_EN); 1021 1022 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1023 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1024 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1025 GEM_RX_BLANKING_TIME_SHIFT) | 6); 1026 1027 /* 1028 * The following value is for an OFF Threshold of about 3/4 full 1029 * and an ON Threshold of 1/4 full. 1030 */ 1031 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 1032 (3 * sc->sc_rxfifosize / 256) | 1033 ((sc->sc_rxfifosize / 256) << 12)); 1034 1035 /* step 11. Configure Media. */ 1036 1037 /* step 12. RX_MAC Configuration Register */ 1038 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1039 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1040 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 1041 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1042 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1043 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1044 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1045 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 1046 1047 /* step 13. TX_MAC Configuration Register */ 1048 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1049 v |= GEM_MAC_TX_ENABLE; 1050 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1051 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1052 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1053 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1054 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1055 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1056 1057 /* step 14. Issue Transmit Pending command. */ 1058 1059 /* step 15. Give the reciever a swift kick. */ 1060 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 1061 1062 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1063 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1064 1065 mii_mediachg(sc->sc_mii); 1066 1067 /* Start the one second timer. */ 1068 sc->sc_wdog_timer = 0; 1069 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1070 } 1071 1072 static int 1073 gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 1074 { 1075 bus_dma_segment_t txsegs[GEM_NTXSEGS]; 1076 struct gem_txsoft *txs; 1077 struct ip *ip; 1078 struct mbuf *m; 1079 uint64_t cflags, flags; 1080 int error, nexttx, nsegs, offset, seg; 1081 1082 GEM_LOCK_ASSERT(sc, MA_OWNED); 1083 1084 /* Get a work queue entry. */ 1085 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1086 /* Ran out of descriptors. */ 1087 return (ENOBUFS); 1088 } 1089 1090 cflags = 0; 1091 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1092 if (M_WRITABLE(*m_head) == 0) { 1093 m = m_dup(*m_head, M_DONTWAIT); 1094 m_freem(*m_head); 1095 *m_head = m; 1096 if (m == NULL) 1097 return (ENOBUFS); 1098 } 1099 offset = sizeof(struct ether_header); 1100 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1101 if (m == NULL) { 1102 *m_head = NULL; 1103 return (ENOBUFS); 1104 } 1105 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1106 offset += (ip->ip_hl << 2); 1107 cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1108 ((offset + m->m_pkthdr.csum_data) << 1109 GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1110 *m_head = m; 1111 } 1112 1113 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1114 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1115 if (error == EFBIG) { 1116 m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 1117 if (m == NULL) { 1118 m_freem(*m_head); 1119 *m_head = NULL; 1120 return (ENOBUFS); 1121 } 1122 *m_head = m; 1123 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1124 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1125 BUS_DMA_NOWAIT); 1126 if (error != 0) { 1127 m_freem(*m_head); 1128 *m_head = NULL; 1129 return (error); 1130 } 1131 } else if (error != 0) 1132 return (error); 1133 /* If nsegs is wrong then the stack is corrupt. */ 1134 KASSERT(nsegs <= GEM_NTXSEGS, 1135 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1136 if (nsegs == 0) { 1137 m_freem(*m_head); 1138 *m_head = NULL; 1139 return (EIO); 1140 } 1141 1142 /* 1143 * Ensure we have enough descriptors free to describe 1144 * the packet. Note, we always reserve one descriptor 1145 * at the end of the ring as a termination point, in 1146 * order to prevent wrap-around. 1147 */ 1148 if (nsegs > sc->sc_txfree - 1) { 1149 txs->txs_ndescs = 0; 1150 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1151 return (ENOBUFS); 1152 } 1153 1154 txs->txs_ndescs = nsegs; 1155 txs->txs_firstdesc = sc->sc_txnext; 1156 nexttx = txs->txs_firstdesc; 1157 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1158 #ifdef GEM_DEBUG 1159 CTR6(KTR_GEM, 1160 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1161 __func__, seg, nexttx, txsegs[seg].ds_len, 1162 txsegs[seg].ds_addr, 1163 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1164 #endif 1165 sc->sc_txdescs[nexttx].gd_addr = 1166 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1167 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1168 ("%s: segment size too large!", __func__)); 1169 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1170 sc->sc_txdescs[nexttx].gd_flags = 1171 GEM_DMA_WRITE(sc, flags | cflags); 1172 txs->txs_lastdesc = nexttx; 1173 } 1174 1175 /* Set EOP on the last descriptor. */ 1176 #ifdef GEM_DEBUG 1177 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1178 __func__, seg, nexttx); 1179 #endif 1180 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1181 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1182 1183 /* Lastly set SOP on the first descriptor. */ 1184 #ifdef GEM_DEBUG 1185 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1186 __func__, seg, nexttx); 1187 #endif 1188 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1189 sc->sc_txwin = 0; 1190 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1191 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1192 GEM_TD_START_OF_PACKET); 1193 } else 1194 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1195 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1196 1197 /* Sync the DMA map. */ 1198 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1199 BUS_DMASYNC_PREWRITE); 1200 1201 #ifdef GEM_DEBUG 1202 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1203 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1204 txs->txs_ndescs); 1205 #endif 1206 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1207 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1208 txs->txs_mbuf = *m_head; 1209 1210 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1211 sc->sc_txfree -= txs->txs_ndescs; 1212 1213 return (0); 1214 } 1215 1216 static void 1217 gem_init_regs(struct gem_softc *sc) 1218 { 1219 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1220 1221 GEM_LOCK_ASSERT(sc, MA_OWNED); 1222 1223 /* These registers are not cleared on reset. */ 1224 if ((sc->sc_flags & GEM_INITED) == 0) { 1225 /* magic values */ 1226 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1227 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1228 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 1229 1230 /* min frame length */ 1231 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1232 /* max frame length and max burst size */ 1233 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1234 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1235 1236 /* more magic values */ 1237 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1238 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1239 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1240 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088); 1241 1242 /* random number seed */ 1243 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1244 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1245 1246 /* secondary MAC address: 0:0:0:0:0:0 */ 1247 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1248 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1249 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1250 1251 /* MAC control address: 01:80:c2:00:00:01 */ 1252 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1253 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1254 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 1255 1256 /* MAC filter address: 0:0:0:0:0:0 */ 1257 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1258 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1259 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1260 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1261 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 1262 1263 sc->sc_flags |= GEM_INITED; 1264 } 1265 1266 /* Counters need to be zeroed. */ 1267 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1268 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1269 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1270 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1271 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1272 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1273 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1274 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1275 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1276 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1277 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 1278 1279 /* Set XOFF PAUSE time. */ 1280 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1281 1282 /* Set the station address. */ 1283 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1284 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1285 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1286 1287 /* Enable MII outputs. */ 1288 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 1289 } 1290 1291 static void 1292 gem_start(struct ifnet *ifp) 1293 { 1294 struct gem_softc *sc = ifp->if_softc; 1295 1296 GEM_LOCK(sc); 1297 gem_start_locked(ifp); 1298 GEM_UNLOCK(sc); 1299 } 1300 1301 static inline void 1302 gem_txkick(struct gem_softc *sc) 1303 { 1304 1305 /* 1306 * Update the TX kick register. This register has to point to the 1307 * descriptor after the last valid one and for optimum performance 1308 * should be incremented in multiples of 4 (the DMA engine fetches/ 1309 * updates descriptors in batches of 4). 1310 */ 1311 #ifdef GEM_DEBUG 1312 CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1313 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1314 #endif 1315 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1316 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1317 } 1318 1319 static void 1320 gem_start_locked(struct ifnet *ifp) 1321 { 1322 struct gem_softc *sc = ifp->if_softc; 1323 struct mbuf *m; 1324 int kicked, ntx; 1325 1326 GEM_LOCK_ASSERT(sc, MA_OWNED); 1327 1328 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1329 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 1330 return; 1331 1332 #ifdef GEM_DEBUG 1333 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1334 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1335 sc->sc_txnext); 1336 #endif 1337 ntx = 0; 1338 kicked = 0; 1339 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1340 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1341 if (m == NULL) 1342 break; 1343 if (gem_load_txmbuf(sc, &m) != 0) { 1344 if (m == NULL) 1345 break; 1346 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1347 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1348 break; 1349 } 1350 if ((sc->sc_txnext % 4) == 0) { 1351 gem_txkick(sc); 1352 kicked = 1; 1353 } else 1354 kicked = 0; 1355 ntx++; 1356 BPF_MTAP(ifp, m); 1357 } 1358 1359 if (ntx > 0) { 1360 if (kicked == 0) 1361 gem_txkick(sc); 1362 #ifdef GEM_DEBUG 1363 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1364 device_get_name(sc->sc_dev), sc->sc_txnext); 1365 #endif 1366 1367 /* Set a watchdog timer in case the chip flakes out. */ 1368 sc->sc_wdog_timer = 5; 1369 #ifdef GEM_DEBUG 1370 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1371 device_get_name(sc->sc_dev), __func__, 1372 sc->sc_wdog_timer); 1373 #endif 1374 } 1375 } 1376 1377 static void 1378 gem_tint(struct gem_softc *sc) 1379 { 1380 struct ifnet *ifp = sc->sc_ifp; 1381 struct gem_txsoft *txs; 1382 int progress; 1383 uint32_t txlast; 1384 #ifdef GEM_DEBUG 1385 int i; 1386 1387 GEM_LOCK_ASSERT(sc, MA_OWNED); 1388 1389 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1390 #endif 1391 1392 /* 1393 * Go through our TX list and free mbufs for those 1394 * frames that have been transmitted. 1395 */ 1396 progress = 0; 1397 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1398 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1399 #ifdef GEM_DEBUG 1400 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1401 printf(" txsoft %p transmit chain:\n", txs); 1402 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1403 printf("descriptor %d: ", i); 1404 printf("gd_flags: 0x%016llx\t", 1405 (long long)GEM_DMA_READ(sc, 1406 sc->sc_txdescs[i].gd_flags)); 1407 printf("gd_addr: 0x%016llx\n", 1408 (long long)GEM_DMA_READ(sc, 1409 sc->sc_txdescs[i].gd_addr)); 1410 if (i == txs->txs_lastdesc) 1411 break; 1412 } 1413 } 1414 #endif 1415 1416 /* 1417 * In theory, we could harvest some descriptors before 1418 * the ring is empty, but that's a bit complicated. 1419 * 1420 * GEM_TX_COMPLETION points to the last descriptor 1421 * processed + 1. 1422 */ 1423 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1424 #ifdef GEM_DEBUG 1425 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 1426 "txs->txs_lastdesc = %d, txlast = %d", 1427 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1428 #endif 1429 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1430 if ((txlast >= txs->txs_firstdesc) && 1431 (txlast <= txs->txs_lastdesc)) 1432 break; 1433 } else { 1434 /* Ick -- this command wraps. */ 1435 if ((txlast >= txs->txs_firstdesc) || 1436 (txlast <= txs->txs_lastdesc)) 1437 break; 1438 } 1439 1440 #ifdef GEM_DEBUG 1441 CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1442 #endif 1443 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1444 1445 sc->sc_txfree += txs->txs_ndescs; 1446 1447 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1448 BUS_DMASYNC_POSTWRITE); 1449 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1450 if (txs->txs_mbuf != NULL) { 1451 m_freem(txs->txs_mbuf); 1452 txs->txs_mbuf = NULL; 1453 } 1454 1455 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1456 1457 ifp->if_opackets++; 1458 progress = 1; 1459 } 1460 1461 #ifdef GEM_DEBUG 1462 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1463 "GEM_TX_COMPLETION %x", 1464 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1465 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1466 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1467 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1468 #endif 1469 1470 if (progress) { 1471 if (sc->sc_txfree == GEM_NTXDESC - 1) 1472 sc->sc_txwin = 0; 1473 1474 /* 1475 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1476 * and restart. 1477 */ 1478 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1479 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1480 sc->sc_wdog_timer = 0; 1481 gem_start_locked(ifp); 1482 } 1483 1484 #ifdef GEM_DEBUG 1485 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1486 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1487 #endif 1488 } 1489 1490 #ifdef GEM_RINT_TIMEOUT 1491 static void 1492 gem_rint_timeout(void *arg) 1493 { 1494 struct gem_softc *sc = arg; 1495 1496 GEM_LOCK_ASSERT(sc, MA_OWNED); 1497 1498 gem_rint(sc); 1499 } 1500 #endif 1501 1502 static void 1503 gem_rint(struct gem_softc *sc) 1504 { 1505 struct ifnet *ifp = sc->sc_ifp; 1506 struct mbuf *m; 1507 uint64_t rxstat; 1508 uint32_t rxcomp; 1509 1510 GEM_LOCK_ASSERT(sc, MA_OWNED); 1511 1512 #ifdef GEM_RINT_TIMEOUT 1513 callout_stop(&sc->sc_rx_ch); 1514 #endif 1515 #ifdef GEM_DEBUG 1516 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1517 #endif 1518 1519 /* 1520 * Read the completion register once. This limits 1521 * how long the following loop can execute. 1522 */ 1523 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1524 #ifdef GEM_DEBUG 1525 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1526 __func__, sc->sc_rxptr, rxcomp); 1527 #endif 1528 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1529 for (; sc->sc_rxptr != rxcomp;) { 1530 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1531 rxstat = GEM_DMA_READ(sc, 1532 sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 1533 1534 if (rxstat & GEM_RD_OWN) { 1535 #ifdef GEM_RINT_TIMEOUT 1536 /* 1537 * The descriptor is still marked as owned, although 1538 * it is supposed to have completed. This has been 1539 * observed on some machines. Just exiting here 1540 * might leave the packet sitting around until another 1541 * one arrives to trigger a new interrupt, which is 1542 * generally undesirable, so set up a timeout. 1543 */ 1544 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1545 gem_rint_timeout, sc); 1546 #endif 1547 m = NULL; 1548 goto kickit; 1549 } 1550 1551 if (rxstat & GEM_RD_BAD_CRC) { 1552 ifp->if_ierrors++; 1553 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1554 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1555 m = NULL; 1556 goto kickit; 1557 } 1558 1559 #ifdef GEM_DEBUG 1560 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1561 printf(" rxsoft %p descriptor %d: ", 1562 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1563 printf("gd_flags: 0x%016llx\t", 1564 (long long)GEM_DMA_READ(sc, 1565 sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1566 printf("gd_addr: 0x%016llx\n", 1567 (long long)GEM_DMA_READ(sc, 1568 sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 1569 } 1570 #endif 1571 1572 /* 1573 * Allocate a new mbuf cluster. If that fails, we are 1574 * out of memory, and must drop the packet and recycle 1575 * the buffer that's already attached to this descriptor. 1576 */ 1577 if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 1578 ifp->if_ierrors++; 1579 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1580 m = NULL; 1581 } 1582 1583 kickit: 1584 /* 1585 * Update the RX kick register. This register has to point 1586 * to the descriptor after the last valid one (before the 1587 * current batch) and for optimum performance should be 1588 * incremented in multiples of 4 (the DMA engine fetches/ 1589 * updates descriptors in batches of 4). 1590 */ 1591 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1592 if ((sc->sc_rxptr % 4) == 0) { 1593 GEM_CDSYNC(sc, 1594 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1595 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1596 (sc->sc_rxptr + GEM_NRXDESC - 4) & 1597 GEM_NRXDESC_MASK); 1598 } 1599 1600 if (m == NULL) { 1601 if (rxstat & GEM_RD_OWN) 1602 break; 1603 continue; 1604 } 1605 1606 ifp->if_ipackets++; 1607 m->m_data += ETHER_ALIGN; /* first byte offset */ 1608 m->m_pkthdr.rcvif = ifp; 1609 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 1610 1611 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1612 gem_rxcksum(m, rxstat); 1613 1614 /* Pass it on. */ 1615 GEM_UNLOCK(sc); 1616 (*ifp->if_input)(ifp, m); 1617 GEM_LOCK(sc); 1618 } 1619 1620 #ifdef GEM_DEBUG 1621 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1622 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1623 #endif 1624 } 1625 1626 static int 1627 gem_add_rxbuf(struct gem_softc *sc, int idx) 1628 { 1629 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1630 struct mbuf *m; 1631 bus_dma_segment_t segs[1]; 1632 int error, nsegs; 1633 1634 GEM_LOCK_ASSERT(sc, MA_OWNED); 1635 1636 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1637 if (m == NULL) 1638 return (ENOBUFS); 1639 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1640 1641 #ifdef GEM_DEBUG 1642 /* Bzero the packet to check DMA. */ 1643 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1644 #endif 1645 1646 if (rxs->rxs_mbuf != NULL) { 1647 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1648 BUS_DMASYNC_POSTREAD); 1649 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1650 } 1651 1652 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1653 m, segs, &nsegs, BUS_DMA_NOWAIT); 1654 if (error != 0) { 1655 device_printf(sc->sc_dev, 1656 "cannot load RS DMA map %d, error = %d\n", idx, error); 1657 m_freem(m); 1658 return (error); 1659 } 1660 /* If nsegs is wrong then the stack is corrupt. */ 1661 KASSERT(nsegs == 1, 1662 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1663 rxs->rxs_mbuf = m; 1664 rxs->rxs_paddr = segs[0].ds_addr; 1665 1666 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1667 BUS_DMASYNC_PREREAD); 1668 1669 GEM_INIT_RXDESC(sc, idx); 1670 1671 return (0); 1672 } 1673 1674 static void 1675 gem_eint(struct gem_softc *sc, u_int status) 1676 { 1677 1678 sc->sc_ifp->if_ierrors++; 1679 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1680 gem_reset_rxdma(sc); 1681 return; 1682 } 1683 1684 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1685 if ((status & GEM_INTR_BERR) != 0) { 1686 if ((sc->sc_flags & GEM_PCI) != 0) 1687 printf(", PCI bus error 0x%x\n", 1688 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1689 else 1690 printf(", SBus error 0x%x\n", 1691 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1692 } 1693 } 1694 1695 void 1696 gem_intr(void *v) 1697 { 1698 struct gem_softc *sc = v; 1699 uint32_t status, status2; 1700 1701 GEM_LOCK(sc); 1702 status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1703 1704 #ifdef GEM_DEBUG 1705 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1706 device_get_name(sc->sc_dev), __func__, 1707 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1708 1709 /* 1710 * PCS interrupts must be cleared, otherwise no traffic is passed! 1711 */ 1712 if ((status & GEM_INTR_PCS) != 0) { 1713 status2 = 1714 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1715 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1716 if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1717 device_printf(sc->sc_dev, 1718 "%s: PCS link status changed\n", __func__); 1719 } 1720 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1721 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1722 if ((status2 & GEM_MAC_PAUSED) != 0) 1723 device_printf(sc->sc_dev, 1724 "%s: PAUSE received (PAUSE time %d slots)\n", 1725 __func__, GEM_MAC_PAUSE_TIME(status2)); 1726 if ((status2 & GEM_MAC_PAUSE) != 0) 1727 device_printf(sc->sc_dev, 1728 "%s: transited to PAUSE state\n", __func__); 1729 if ((status2 & GEM_MAC_RESUME) != 0) 1730 device_printf(sc->sc_dev, 1731 "%s: transited to non-PAUSE state\n", __func__); 1732 } 1733 if ((status & GEM_INTR_MIF) != 0) 1734 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1735 #endif 1736 1737 if (__predict_false(status & 1738 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 1739 gem_eint(sc, status); 1740 1741 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1742 gem_rint(sc); 1743 1744 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1745 gem_tint(sc); 1746 1747 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1748 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1749 if ((status2 & 1750 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1751 GEM_MAC_TX_PEAK_EXP)) != 0) 1752 device_printf(sc->sc_dev, 1753 "MAC TX fault, status %x\n", status2); 1754 if ((status2 & 1755 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1756 sc->sc_ifp->if_oerrors++; 1757 gem_init_locked(sc); 1758 } 1759 } 1760 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1761 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1762 /* 1763 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1764 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1765 * silicon bug so handle them silently. Moreover, it's 1766 * likely that the receiver has hung so we reset it. 1767 */ 1768 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1769 sc->sc_ifp->if_ierrors++; 1770 gem_reset_rxdma(sc); 1771 } else if ((status2 & 1772 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1773 device_printf(sc->sc_dev, 1774 "MAC RX fault, status %x\n", status2); 1775 } 1776 GEM_UNLOCK(sc); 1777 } 1778 1779 static int 1780 gem_watchdog(struct gem_softc *sc) 1781 { 1782 struct ifnet *ifp = sc->sc_ifp; 1783 1784 GEM_LOCK_ASSERT(sc, MA_OWNED); 1785 1786 #ifdef GEM_DEBUG 1787 CTR4(KTR_GEM, 1788 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1789 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1790 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1791 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1792 CTR4(KTR_GEM, 1793 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1794 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1795 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1796 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1797 #endif 1798 1799 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1800 return (0); 1801 1802 if ((sc->sc_flags & GEM_LINK) != 0) 1803 device_printf(sc->sc_dev, "device timeout\n"); 1804 else if (bootverbose) 1805 device_printf(sc->sc_dev, "device timeout (no link)\n"); 1806 ++ifp->if_oerrors; 1807 1808 /* Try to get more packets going. */ 1809 gem_init_locked(sc); 1810 gem_start_locked(ifp); 1811 return (EJUSTRETURN); 1812 } 1813 1814 static void 1815 gem_mifinit(struct gem_softc *sc) 1816 { 1817 1818 /* Configure the MIF in frame mode. */ 1819 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1820 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1821 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 1822 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1823 } 1824 1825 /* 1826 * MII interface 1827 * 1828 * The MII interface supports at least three different operating modes: 1829 * 1830 * Bitbang mode is implemented using data, clock and output enable registers. 1831 * 1832 * Frame mode is implemented by loading a complete frame into the frame 1833 * register and polling the valid bit for completion. 1834 * 1835 * Polling mode uses the frame register but completion is indicated by 1836 * an interrupt. 1837 * 1838 */ 1839 int 1840 gem_mii_readreg(device_t dev, int phy, int reg) 1841 { 1842 struct gem_softc *sc; 1843 int n; 1844 uint32_t v; 1845 1846 #ifdef GEM_DEBUG_PHY 1847 printf("%s: phy %d reg %d\n", __func__, phy, reg); 1848 #endif 1849 1850 sc = device_get_softc(dev); 1851 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 1852 return (0); 1853 1854 if ((sc->sc_flags & GEM_SERDES) != 0) { 1855 switch (reg) { 1856 case MII_BMCR: 1857 reg = GEM_MII_CONTROL; 1858 break; 1859 case MII_BMSR: 1860 reg = GEM_MII_STATUS; 1861 break; 1862 case MII_PHYIDR1: 1863 case MII_PHYIDR2: 1864 return (0); 1865 case MII_ANAR: 1866 reg = GEM_MII_ANAR; 1867 break; 1868 case MII_ANLPAR: 1869 reg = GEM_MII_ANLPAR; 1870 break; 1871 case MII_EXTSR: 1872 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1873 default: 1874 device_printf(sc->sc_dev, 1875 "%s: unhandled register %d\n", __func__, reg); 1876 return (0); 1877 } 1878 return (GEM_BANK1_READ_4(sc, reg)); 1879 } 1880 1881 /* Construct the frame command. */ 1882 v = GEM_MIF_FRAME_READ | 1883 (phy << GEM_MIF_PHY_SHIFT) | 1884 (reg << GEM_MIF_REG_SHIFT); 1885 1886 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1887 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1888 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1889 for (n = 0; n < 100; n++) { 1890 DELAY(1); 1891 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1892 if (v & GEM_MIF_FRAME_TA0) 1893 return (v & GEM_MIF_FRAME_DATA); 1894 } 1895 1896 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1897 return (0); 1898 } 1899 1900 int 1901 gem_mii_writereg(device_t dev, int phy, int reg, int val) 1902 { 1903 struct gem_softc *sc; 1904 int n; 1905 uint32_t v; 1906 1907 #ifdef GEM_DEBUG_PHY 1908 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 1909 #endif 1910 1911 sc = device_get_softc(dev); 1912 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 1913 return (0); 1914 1915 if ((sc->sc_flags & GEM_SERDES) != 0) { 1916 switch (reg) { 1917 case MII_BMSR: 1918 reg = GEM_MII_STATUS; 1919 break; 1920 case MII_BMCR: 1921 reg = GEM_MII_CONTROL; 1922 if ((val & GEM_MII_CONTROL_RESET) == 0) 1923 break; 1924 GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1925 GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1926 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1927 if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1928 GEM_MII_CONTROL_RESET, 0)) 1929 device_printf(sc->sc_dev, 1930 "cannot reset PCS\n"); 1931 /* FALLTHROUGH */ 1932 case MII_ANAR: 1933 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1934 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1935 BUS_SPACE_BARRIER_WRITE); 1936 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1937 GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 1938 BUS_SPACE_BARRIER_WRITE); 1939 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1940 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1941 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 1942 BUS_SPACE_BARRIER_WRITE); 1943 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1944 GEM_MII_CONFIG_ENABLE); 1945 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1946 BUS_SPACE_BARRIER_WRITE); 1947 return (0); 1948 case MII_ANLPAR: 1949 reg = GEM_MII_ANLPAR; 1950 break; 1951 default: 1952 device_printf(sc->sc_dev, 1953 "%s: unhandled register %d\n", __func__, reg); 1954 return (0); 1955 } 1956 GEM_BANK1_WRITE_4(sc, reg, val); 1957 GEM_BANK1_BARRIER(sc, reg, 4, 1958 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1959 return (0); 1960 } 1961 1962 /* Construct the frame command. */ 1963 v = GEM_MIF_FRAME_WRITE | 1964 (phy << GEM_MIF_PHY_SHIFT) | 1965 (reg << GEM_MIF_REG_SHIFT) | 1966 (val & GEM_MIF_FRAME_DATA); 1967 1968 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1969 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1970 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1971 for (n = 0; n < 100; n++) { 1972 DELAY(1); 1973 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1974 if (v & GEM_MIF_FRAME_TA0) 1975 return (1); 1976 } 1977 1978 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1979 return (0); 1980 } 1981 1982 void 1983 gem_mii_statchg(device_t dev) 1984 { 1985 struct gem_softc *sc; 1986 int gigabit; 1987 uint32_t rxcfg, txcfg, v; 1988 1989 sc = device_get_softc(dev); 1990 1991 GEM_LOCK_ASSERT(sc, MA_OWNED); 1992 1993 #ifdef GEM_DEBUG 1994 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1995 device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", 1996 __func__, sc->sc_phyad); 1997 #endif 1998 1999 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2000 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2001 sc->sc_flags |= GEM_LINK; 2002 else 2003 sc->sc_flags &= ~GEM_LINK; 2004 2005 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2006 case IFM_1000_SX: 2007 case IFM_1000_LX: 2008 case IFM_1000_CX: 2009 case IFM_1000_T: 2010 gigabit = 1; 2011 break; 2012 default: 2013 gigabit = 0; 2014 } 2015 2016 /* 2017 * The configuration done here corresponds to the steps F) and 2018 * G) and as far as enabling of RX and TX MAC goes also step H) 2019 * of the initialization sequence outlined in section 3.2.1 of 2020 * the GEM Gigabit Ethernet ASIC Specification. 2021 */ 2022 2023 rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2024 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2025 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2026 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2027 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2028 else if (gigabit != 0) { 2029 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2030 txcfg |= GEM_MAC_TX_CARR_EXTEND; 2031 } 2032 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 2033 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 2034 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2035 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2036 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2037 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2038 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 2039 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2040 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2041 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2042 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2043 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2044 2045 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2046 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2047 #ifdef notyet 2048 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2049 IFM_ETH_RXPAUSE) != 0) 2050 v |= GEM_MAC_CC_RX_PAUSE; 2051 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2052 IFM_ETH_TXPAUSE) != 0) 2053 v |= GEM_MAC_CC_TX_PAUSE; 2054 #endif 2055 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2056 2057 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2058 gigabit != 0) 2059 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2060 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2061 else 2062 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2063 GEM_MAC_SLOT_TIME_NORMAL); 2064 2065 /* XIF Configuration */ 2066 v = GEM_MAC_XIF_LINK_LED; 2067 v |= GEM_MAC_XIF_TX_MII_ENA; 2068 if ((sc->sc_flags & GEM_SERDES) == 0) { 2069 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2070 GEM_MIF_CONFIG_PHY_SEL) != 0) { 2071 /* External MII needs echo disable if half duplex. */ 2072 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2073 IFM_FDX) == 0) 2074 v |= GEM_MAC_XIF_ECHO_DISABL; 2075 } else 2076 /* 2077 * Internal MII needs buffer enable. 2078 * XXX buffer enable makes only sense for an 2079 * external PHY. 2080 */ 2081 v |= GEM_MAC_XIF_MII_BUF_ENA; 2082 } 2083 if (gigabit != 0) 2084 v |= GEM_MAC_XIF_GMII_MODE; 2085 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2086 v |= GEM_MAC_XIF_FDPLX_LED; 2087 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 2088 2089 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2090 (sc->sc_flags & GEM_LINK) != 0) { 2091 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2092 txcfg | GEM_MAC_TX_ENABLE); 2093 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2094 rxcfg | GEM_MAC_RX_ENABLE); 2095 } 2096 } 2097 2098 int 2099 gem_mediachange(struct ifnet *ifp) 2100 { 2101 struct gem_softc *sc = ifp->if_softc; 2102 int error; 2103 2104 /* XXX add support for serial media. */ 2105 2106 GEM_LOCK(sc); 2107 error = mii_mediachg(sc->sc_mii); 2108 GEM_UNLOCK(sc); 2109 return (error); 2110 } 2111 2112 void 2113 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2114 { 2115 struct gem_softc *sc = ifp->if_softc; 2116 2117 GEM_LOCK(sc); 2118 if ((ifp->if_flags & IFF_UP) == 0) { 2119 GEM_UNLOCK(sc); 2120 return; 2121 } 2122 2123 mii_pollstat(sc->sc_mii); 2124 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2125 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2126 GEM_UNLOCK(sc); 2127 } 2128 2129 static int 2130 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2131 { 2132 struct gem_softc *sc = ifp->if_softc; 2133 struct ifreq *ifr = (struct ifreq *)data; 2134 int error; 2135 2136 error = 0; 2137 switch (cmd) { 2138 case SIOCSIFFLAGS: 2139 GEM_LOCK(sc); 2140 if ((ifp->if_flags & IFF_UP) != 0) { 2141 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2142 ((ifp->if_flags ^ sc->sc_ifflags) & 2143 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2144 gem_setladrf(sc); 2145 else 2146 gem_init_locked(sc); 2147 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2148 gem_stop(ifp, 0); 2149 if ((ifp->if_flags & IFF_LINK0) != 0) 2150 sc->sc_csum_features |= CSUM_UDP; 2151 else 2152 sc->sc_csum_features &= ~CSUM_UDP; 2153 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2154 ifp->if_hwassist = sc->sc_csum_features; 2155 sc->sc_ifflags = ifp->if_flags; 2156 GEM_UNLOCK(sc); 2157 break; 2158 case SIOCADDMULTI: 2159 case SIOCDELMULTI: 2160 GEM_LOCK(sc); 2161 gem_setladrf(sc); 2162 GEM_UNLOCK(sc); 2163 break; 2164 case SIOCGIFMEDIA: 2165 case SIOCSIFMEDIA: 2166 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2167 break; 2168 case SIOCSIFCAP: 2169 GEM_LOCK(sc); 2170 ifp->if_capenable = ifr->ifr_reqcap; 2171 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2172 ifp->if_hwassist = sc->sc_csum_features; 2173 else 2174 ifp->if_hwassist = 0; 2175 GEM_UNLOCK(sc); 2176 break; 2177 default: 2178 error = ether_ioctl(ifp, cmd, data); 2179 break; 2180 } 2181 2182 return (error); 2183 } 2184 2185 static void 2186 gem_setladrf(struct gem_softc *sc) 2187 { 2188 struct ifnet *ifp = sc->sc_ifp; 2189 struct ifmultiaddr *inm; 2190 int i; 2191 uint32_t hash[16]; 2192 uint32_t crc, v; 2193 2194 GEM_LOCK_ASSERT(sc, MA_OWNED); 2195 2196 /* Get the current RX configuration. */ 2197 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2198 2199 /* 2200 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2201 * and hash filter. Depending on the case, the right bit will be 2202 * enabled. 2203 */ 2204 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2205 GEM_MAC_RX_PROMISC_GRP); 2206 2207 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2208 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2209 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2210 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 2211 0)) 2212 device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2213 2214 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2215 v |= GEM_MAC_RX_PROMISCUOUS; 2216 goto chipit; 2217 } 2218 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2219 v |= GEM_MAC_RX_PROMISC_GRP; 2220 goto chipit; 2221 } 2222 2223 /* 2224 * Set up multicast address filter by passing all multicast 2225 * addresses through a crc generator, and then using the high 2226 * order 8 bits as an index into the 256 bit logical address 2227 * filter. The high order 4 bits selects the word, while the 2228 * other 4 bits select the bit within the word (where bit 0 2229 * is the MSB). 2230 */ 2231 2232 /* Clear the hash table. */ 2233 memset(hash, 0, sizeof(hash)); 2234 2235 if_maddr_rlock(ifp); 2236 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2237 if (inm->ifma_addr->sa_family != AF_LINK) 2238 continue; 2239 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2240 inm->ifma_addr), ETHER_ADDR_LEN); 2241 2242 /* We just want the 8 most significant bits. */ 2243 crc >>= 24; 2244 2245 /* Set the corresponding bit in the filter. */ 2246 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2247 } 2248 if_maddr_runlock(ifp); 2249 2250 v |= GEM_MAC_RX_HASH_FILTER; 2251 2252 /* Now load the hash table into the chip (if we are using it). */ 2253 for (i = 0; i < 16; i++) 2254 GEM_BANK1_WRITE_4(sc, 2255 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 2256 hash[i]); 2257 2258 chipit: 2259 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2260 } 2261