1aad970f1SDavid E. O'Brien /*- 242c1b001SThomas Moestl * Copyright (C) 2001 Eduardo Horvath. 3305f2c06SThomas Moestl * Copyright (c) 2001-2003 Thomas Moestl 42a79fd39SMarius Strobl * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 542c1b001SThomas Moestl * All rights reserved. 642c1b001SThomas Moestl * 742c1b001SThomas Moestl * Redistribution and use in source and binary forms, with or without 842c1b001SThomas Moestl * modification, are permitted provided that the following conditions 942c1b001SThomas Moestl * are met: 1042c1b001SThomas Moestl * 1. Redistributions of source code must retain the above copyright 1142c1b001SThomas Moestl * notice, this list of conditions and the following disclaimer. 1242c1b001SThomas Moestl * 2. Redistributions in binary form must reproduce the above copyright 1342c1b001SThomas Moestl * notice, this list of conditions and the following disclaimer in the 1442c1b001SThomas Moestl * documentation and/or other materials provided with the distribution. 1542c1b001SThomas Moestl * 1642c1b001SThomas Moestl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1742c1b001SThomas Moestl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1842c1b001SThomas Moestl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1942c1b001SThomas Moestl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 2042c1b001SThomas Moestl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2142c1b001SThomas Moestl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2242c1b001SThomas Moestl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2342c1b001SThomas Moestl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2442c1b001SThomas Moestl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2542c1b001SThomas Moestl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2642c1b001SThomas Moestl * SUCH DAMAGE. 2742c1b001SThomas Moestl * 28336cca9eSBenno Rice * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 2942c1b001SThomas Moestl */ 3042c1b001SThomas Moestl 31aad970f1SDavid E. O'Brien #include <sys/cdefs.h> 32aad970f1SDavid E. O'Brien __FBSDID("$FreeBSD$"); 33aad970f1SDavid E. O'Brien 3442c1b001SThomas Moestl /* 351ed3fed7SMarius Strobl * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 3642c1b001SThomas Moestl */ 3742c1b001SThomas Moestl 3818100346SThomas Moestl #if 0 3942c1b001SThomas Moestl #define GEM_DEBUG 4018100346SThomas Moestl #endif 4142c1b001SThomas Moestl 42c3d5598aSMarius Strobl #if 0 /* XXX: In case of emergency, re-enable this. */ 43c3d5598aSMarius Strobl #define GEM_RINT_TIMEOUT 44c3d5598aSMarius Strobl #endif 45c3d5598aSMarius Strobl 4642c1b001SThomas Moestl #include <sys/param.h> 4742c1b001SThomas Moestl #include <sys/systm.h> 4842c1b001SThomas Moestl #include <sys/bus.h> 4942c1b001SThomas Moestl #include <sys/callout.h> 50a30d4b32SMike Barcroft #include <sys/endian.h> 5142c1b001SThomas Moestl #include <sys/mbuf.h> 5242c1b001SThomas Moestl #include <sys/malloc.h> 5342c1b001SThomas Moestl #include <sys/kernel.h> 548cfaff7dSMarius Strobl #include <sys/lock.h> 55186f2b9eSPoul-Henning Kamp #include <sys/module.h> 568cfaff7dSMarius Strobl #include <sys/mutex.h> 5742c1b001SThomas Moestl #include <sys/socket.h> 5842c1b001SThomas Moestl #include <sys/sockio.h> 59e1bb13cdSPoul-Henning Kamp #include <sys/rman.h> 6042c1b001SThomas Moestl 6108e0fdebSThomas Moestl #include <net/bpf.h> 6242c1b001SThomas Moestl #include <net/ethernet.h> 6342c1b001SThomas Moestl #include <net/if.h> 6442c1b001SThomas Moestl #include <net/if_arp.h> 6542c1b001SThomas Moestl #include <net/if_dl.h> 6642c1b001SThomas Moestl #include <net/if_media.h> 67fc74a9f9SBrooks Davis #include <net/if_types.h> 6800d12766SMarius Strobl #include <net/if_vlan_var.h> 6942c1b001SThomas Moestl 7012fb0330SPyun YongHyeon #include <netinet/in.h> 7112fb0330SPyun YongHyeon #include <netinet/in_systm.h> 7212fb0330SPyun YongHyeon #include <netinet/ip.h> 7312fb0330SPyun YongHyeon #include <netinet/tcp.h> 7412fb0330SPyun YongHyeon #include <netinet/udp.h> 7512fb0330SPyun YongHyeon 7642c1b001SThomas Moestl #include <machine/bus.h> 7742c1b001SThomas Moestl 7842c1b001SThomas Moestl #include <dev/mii/mii.h> 7942c1b001SThomas Moestl #include <dev/mii/miivar.h> 8042c1b001SThomas Moestl 81681f7d03SWarner Losh #include <dev/gem/if_gemreg.h> 82681f7d03SWarner Losh #include <dev/gem/if_gemvar.h> 8342c1b001SThomas Moestl 841ed3fed7SMarius Strobl CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 851ed3fed7SMarius Strobl CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 861ed3fed7SMarius Strobl 879ba2b298SMarius Strobl #define GEM_TRIES 10000 881ed3fed7SMarius Strobl 8912fb0330SPyun YongHyeon /* 9078d22f42SMarius Strobl * The hardware supports basic TCP/UDP checksum offloading. However, 9112fb0330SPyun YongHyeon * the hardware doesn't compensate the checksum for UDP datagram which 9212fb0330SPyun YongHyeon * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 9312fb0330SPyun YongHyeon * by default. It can be reactivated by setting special link option 9412fb0330SPyun YongHyeon * link0 with ifconfig(8). 9512fb0330SPyun YongHyeon */ 9612fb0330SPyun YongHyeon #define GEM_CSUM_FEATURES (CSUM_TCP) 9742c1b001SThomas Moestl 982a79fd39SMarius Strobl static int gem_add_rxbuf(struct gem_softc *sc, int idx); 99bd3d9826SMarius Strobl static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 100bd3d9826SMarius Strobl uint32_t clr, uint32_t set); 1012a79fd39SMarius Strobl static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 1022a79fd39SMarius Strobl int nsegs, int error); 1032a79fd39SMarius Strobl static int gem_disable_rx(struct gem_softc *sc); 1042a79fd39SMarius Strobl static int gem_disable_tx(struct gem_softc *sc); 1052a79fd39SMarius Strobl static void gem_eint(struct gem_softc *sc, u_int status); 1062a79fd39SMarius Strobl static void gem_init(void *xsc); 1072a79fd39SMarius Strobl static void gem_init_locked(struct gem_softc *sc); 1082a79fd39SMarius Strobl static void gem_init_regs(struct gem_softc *sc); 1092a79fd39SMarius Strobl static int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 1102a79fd39SMarius Strobl static int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 1112a79fd39SMarius Strobl static int gem_meminit(struct gem_softc *sc); 1122a79fd39SMarius Strobl static void gem_mifinit(struct gem_softc *sc); 1132a79fd39SMarius Strobl static void gem_reset(struct gem_softc *sc); 1142a79fd39SMarius Strobl static int gem_reset_rx(struct gem_softc *sc); 1151ed3fed7SMarius Strobl static void gem_reset_rxdma(struct gem_softc *sc); 1162a79fd39SMarius Strobl static int gem_reset_tx(struct gem_softc *sc); 1172a79fd39SMarius Strobl static u_int gem_ringsize(u_int sz); 1182a79fd39SMarius Strobl static void gem_rint(struct gem_softc *sc); 119c3d5598aSMarius Strobl #ifdef GEM_RINT_TIMEOUT 1202a79fd39SMarius Strobl static void gem_rint_timeout(void *arg); 12111e3f060SJake Burkholder #endif 1229ba2b298SMarius Strobl static inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 1232a79fd39SMarius Strobl static void gem_rxdrain(struct gem_softc *sc); 124*c0e3e9d4SMarius Strobl static void gem_setladrf(struct gem_softc *sc, u_int enable); 1252a79fd39SMarius Strobl static void gem_start(struct ifnet *ifp); 1262a79fd39SMarius Strobl static void gem_start_locked(struct ifnet *ifp); 1272a79fd39SMarius Strobl static void gem_stop(struct ifnet *ifp, int disable); 1282a79fd39SMarius Strobl static void gem_tick(void *arg); 1292a79fd39SMarius Strobl static void gem_tint(struct gem_softc *sc); 1309ba2b298SMarius Strobl static inline void gem_txkick(struct gem_softc *sc); 1312a79fd39SMarius Strobl static int gem_watchdog(struct gem_softc *sc); 13242c1b001SThomas Moestl 13342c1b001SThomas Moestl devclass_t gem_devclass; 13442c1b001SThomas Moestl DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 13542c1b001SThomas Moestl MODULE_DEPEND(gem, miibus, 1, 1, 1); 13642c1b001SThomas Moestl 13742c1b001SThomas Moestl #ifdef GEM_DEBUG 13842c1b001SThomas Moestl #include <sys/ktr.h> 139651aa2d8SAttilio Rao #define KTR_GEM KTR_SPARE2 14042c1b001SThomas Moestl #endif 14142c1b001SThomas Moestl 142bd3d9826SMarius Strobl #define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 143bd3d9826SMarius Strobl gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 144bd3d9826SMarius Strobl #define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 145bd3d9826SMarius Strobl gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 146bd3d9826SMarius Strobl 14742c1b001SThomas Moestl int 1482a79fd39SMarius Strobl gem_attach(struct gem_softc *sc) 14942c1b001SThomas Moestl { 1502a79fd39SMarius Strobl struct gem_txsoft *txs; 151fc74a9f9SBrooks Davis struct ifnet *ifp; 1528e5d93dbSMarius Strobl int error, i, phy; 1532a79fd39SMarius Strobl uint32_t v; 15442c1b001SThomas Moestl 1559ba2b298SMarius Strobl if (bootverbose) 1569ba2b298SMarius Strobl device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 1579ba2b298SMarius Strobl 1589ba2b298SMarius Strobl /* Set up ifnet structure. */ 159fc74a9f9SBrooks Davis ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160fc74a9f9SBrooks Davis if (ifp == NULL) 161fc74a9f9SBrooks Davis return (ENOSPC); 1629ba2b298SMarius Strobl sc->sc_csum_features = GEM_CSUM_FEATURES; 1639ba2b298SMarius Strobl ifp->if_softc = sc; 1649ba2b298SMarius Strobl if_initname(ifp, device_get_name(sc->sc_dev), 1659ba2b298SMarius Strobl device_get_unit(sc->sc_dev)); 1669ba2b298SMarius Strobl ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1679ba2b298SMarius Strobl ifp->if_start = gem_start; 1689ba2b298SMarius Strobl ifp->if_ioctl = gem_ioctl; 1699ba2b298SMarius Strobl ifp->if_init = gem_init; 1709ba2b298SMarius Strobl IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 1719ba2b298SMarius Strobl ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 1729ba2b298SMarius Strobl IFQ_SET_READY(&ifp->if_snd); 173fc74a9f9SBrooks Davis 1741f317bf9SMarius Strobl callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 1751f317bf9SMarius Strobl #ifdef GEM_RINT_TIMEOUT 1761f317bf9SMarius Strobl callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 1771f317bf9SMarius Strobl #endif 1781f317bf9SMarius Strobl 17942c1b001SThomas Moestl /* Make sure the chip is stopped. */ 18042c1b001SThomas Moestl gem_reset(sc); 18142c1b001SThomas Moestl 182378f231eSJohn-Mark Gurney error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183378f231eSJohn-Mark Gurney BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1842a79fd39SMarius Strobl BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 1852a79fd39SMarius Strobl NULL, &sc->sc_pdmatag); 1869ba2b298SMarius Strobl if (error != 0) 187fc74a9f9SBrooks Davis goto fail_ifnet; 18842c1b001SThomas Moestl 18942c1b001SThomas Moestl error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 19012fb0330SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 19112fb0330SPyun YongHyeon 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 1929ba2b298SMarius Strobl if (error != 0) 193305f2c06SThomas Moestl goto fail_ptag; 194305f2c06SThomas Moestl 195305f2c06SThomas Moestl error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 19612fb0330SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 19712fb0330SPyun YongHyeon MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198f6b1c44dSScott Long BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 1999ba2b298SMarius Strobl if (error != 0) 200305f2c06SThomas Moestl goto fail_rtag; 20142c1b001SThomas Moestl 20242c1b001SThomas Moestl error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 20312fb0330SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 20442c1b001SThomas Moestl sizeof(struct gem_control_data), 1, 20512fb0330SPyun YongHyeon sizeof(struct gem_control_data), 0, 20612fb0330SPyun YongHyeon NULL, NULL, &sc->sc_cdmatag); 2079ba2b298SMarius Strobl if (error != 0) 208305f2c06SThomas Moestl goto fail_ttag; 20942c1b001SThomas Moestl 21042c1b001SThomas Moestl /* 2112a79fd39SMarius Strobl * Allocate the control data structures, create and load the 21242c1b001SThomas Moestl * DMA map for it. 21342c1b001SThomas Moestl */ 21442c1b001SThomas Moestl if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 21512fb0330SPyun YongHyeon (void **)&sc->sc_control_data, 21612fb0330SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2179ba2b298SMarius Strobl &sc->sc_cddmamap)) != 0) { 2182a79fd39SMarius Strobl device_printf(sc->sc_dev, 2192a79fd39SMarius Strobl "unable to allocate control data, error = %d\n", error); 220305f2c06SThomas Moestl goto fail_ctag; 22142c1b001SThomas Moestl } 22242c1b001SThomas Moestl 22342c1b001SThomas Moestl sc->sc_cddma = 0; 22442c1b001SThomas Moestl if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 22542c1b001SThomas Moestl sc->sc_control_data, sizeof(struct gem_control_data), 22642c1b001SThomas Moestl gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 2272a79fd39SMarius Strobl device_printf(sc->sc_dev, 2282a79fd39SMarius Strobl "unable to load control data DMA map, error = %d\n", 2292a79fd39SMarius Strobl error); 230305f2c06SThomas Moestl goto fail_cmem; 23142c1b001SThomas Moestl } 23242c1b001SThomas Moestl 23342c1b001SThomas Moestl /* 23442c1b001SThomas Moestl * Initialize the transmit job descriptors. 23542c1b001SThomas Moestl */ 23642c1b001SThomas Moestl STAILQ_INIT(&sc->sc_txfreeq); 23742c1b001SThomas Moestl STAILQ_INIT(&sc->sc_txdirtyq); 23842c1b001SThomas Moestl 23942c1b001SThomas Moestl /* 24042c1b001SThomas Moestl * Create the transmit buffer DMA maps. 24142c1b001SThomas Moestl */ 24242c1b001SThomas Moestl error = ENOMEM; 24342c1b001SThomas Moestl for (i = 0; i < GEM_TXQUEUELEN; i++) { 24442c1b001SThomas Moestl txs = &sc->sc_txsoft[i]; 24542c1b001SThomas Moestl txs->txs_mbuf = NULL; 24642c1b001SThomas Moestl txs->txs_ndescs = 0; 247305f2c06SThomas Moestl if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 24842c1b001SThomas Moestl &txs->txs_dmamap)) != 0) { 2492a79fd39SMarius Strobl device_printf(sc->sc_dev, 2502a79fd39SMarius Strobl "unable to create TX DMA map %d, error = %d\n", 2512a79fd39SMarius Strobl i, error); 252305f2c06SThomas Moestl goto fail_txd; 25342c1b001SThomas Moestl } 25442c1b001SThomas Moestl STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 25542c1b001SThomas Moestl } 25642c1b001SThomas Moestl 25742c1b001SThomas Moestl /* 25842c1b001SThomas Moestl * Create the receive buffer DMA maps. 25942c1b001SThomas Moestl */ 26042c1b001SThomas Moestl for (i = 0; i < GEM_NRXDESC; i++) { 261305f2c06SThomas Moestl if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 26242c1b001SThomas Moestl &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 2632a79fd39SMarius Strobl device_printf(sc->sc_dev, 2642a79fd39SMarius Strobl "unable to create RX DMA map %d, error = %d\n", 2652a79fd39SMarius Strobl i, error); 266305f2c06SThomas Moestl goto fail_rxd; 26742c1b001SThomas Moestl } 26842c1b001SThomas Moestl sc->sc_rxsoft[i].rxs_mbuf = NULL; 26942c1b001SThomas Moestl } 27042c1b001SThomas Moestl 27165f2c0ffSMarius Strobl /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 27265f2c0ffSMarius Strobl if ((sc->sc_flags & GEM_SERDES) != 0) 27365f2c0ffSMarius Strobl goto serdes; 27465f2c0ffSMarius Strobl 2751ed3fed7SMarius Strobl /* Bad things will happen when touching this register on ERI. */ 27665f2c0ffSMarius Strobl if (sc->sc_variant != GEM_SUN_ERI) { 277bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 2781ed3fed7SMarius Strobl GEM_MII_DATAPATH_MII); 27965f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 28065f2c0ffSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 28165f2c0ffSMarius Strobl } 2821ed3fed7SMarius Strobl 28342c1b001SThomas Moestl gem_mifinit(sc); 28442c1b001SThomas Moestl 2851ed3fed7SMarius Strobl /* 2861ed3fed7SMarius Strobl * Look for an external PHY. 2871ed3fed7SMarius Strobl */ 2881ed3fed7SMarius Strobl error = ENXIO; 289bd3d9826SMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 2901ed3fed7SMarius Strobl if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 2911ed3fed7SMarius Strobl v |= GEM_MIF_CONFIG_PHY_SEL; 292bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 29365f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 29465f2c0ffSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2951ed3fed7SMarius Strobl switch (sc->sc_variant) { 2961ed3fed7SMarius Strobl case GEM_SUN_ERI: 2978e5d93dbSMarius Strobl phy = GEM_PHYAD_EXTERNAL; 2981ed3fed7SMarius Strobl break; 2991ed3fed7SMarius Strobl default: 3008e5d93dbSMarius Strobl phy = MII_PHY_ANY; 3011ed3fed7SMarius Strobl break; 3021ed3fed7SMarius Strobl } 3038e5d93dbSMarius Strobl error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 3048e5d93dbSMarius Strobl gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 3059a68cbd3SMarius Strobl MII_OFFSET_ANY, MIIF_DOPAUSE); 3061ed3fed7SMarius Strobl } 3071ed3fed7SMarius Strobl 3081ed3fed7SMarius Strobl /* 3091ed3fed7SMarius Strobl * Fall back on an internal PHY if no external PHY was found. 3109e48f1e7SMarius Strobl * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 3119e48f1e7SMarius Strobl * trusted when the firmware has powered down the chip. 3121ed3fed7SMarius Strobl */ 3139e48f1e7SMarius Strobl if (error != 0 && 3149e48f1e7SMarius Strobl ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 3151ed3fed7SMarius Strobl v &= ~GEM_MIF_CONFIG_PHY_SEL; 316bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 31765f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 31865f2c0ffSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 3191ed3fed7SMarius Strobl switch (sc->sc_variant) { 3201ed3fed7SMarius Strobl case GEM_SUN_ERI: 3211ed3fed7SMarius Strobl case GEM_APPLE_K2_GMAC: 3228e5d93dbSMarius Strobl phy = GEM_PHYAD_INTERNAL; 3231ed3fed7SMarius Strobl break; 3241ed3fed7SMarius Strobl case GEM_APPLE_GMAC: 3258e5d93dbSMarius Strobl phy = GEM_PHYAD_EXTERNAL; 3261ed3fed7SMarius Strobl break; 3271ed3fed7SMarius Strobl default: 3288e5d93dbSMarius Strobl phy = MII_PHY_ANY; 3291ed3fed7SMarius Strobl break; 3301ed3fed7SMarius Strobl } 3318e5d93dbSMarius Strobl error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 3328e5d93dbSMarius Strobl gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 3339a68cbd3SMarius Strobl MII_OFFSET_ANY, MIIF_DOPAUSE); 3341ed3fed7SMarius Strobl } 3351ed3fed7SMarius Strobl 3361ed3fed7SMarius Strobl /* 3371ed3fed7SMarius Strobl * Try the external PCS SERDES if we didn't find any PHYs. 3381ed3fed7SMarius Strobl */ 3391ed3fed7SMarius Strobl if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 34065f2c0ffSMarius Strobl serdes: 341bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 3421ed3fed7SMarius Strobl GEM_MII_DATAPATH_SERDES); 34365f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 34465f2c0ffSMarius Strobl BUS_SPACE_BARRIER_WRITE); 345bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 3461ed3fed7SMarius Strobl GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 34765f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 34865f2c0ffSMarius Strobl BUS_SPACE_BARRIER_WRITE); 349bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 35065f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 35165f2c0ffSMarius Strobl BUS_SPACE_BARRIER_WRITE); 3521ed3fed7SMarius Strobl sc->sc_flags |= GEM_SERDES; 3538e5d93dbSMarius Strobl error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 3548e5d93dbSMarius Strobl gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, 3559a68cbd3SMarius Strobl GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 3561ed3fed7SMarius Strobl } 3571ed3fed7SMarius Strobl if (error != 0) { 3588e5d93dbSMarius Strobl device_printf(sc->sc_dev, "attaching PHYs failed\n"); 359305f2c06SThomas Moestl goto fail_rxd; 36042c1b001SThomas Moestl } 36142c1b001SThomas Moestl sc->sc_mii = device_get_softc(sc->sc_miibus); 36242c1b001SThomas Moestl 36342c1b001SThomas Moestl /* 36442c1b001SThomas Moestl * From this point forward, the attachment cannot fail. A failure 36542c1b001SThomas Moestl * before this point releases all resources that may have been 36642c1b001SThomas Moestl * allocated. 36742c1b001SThomas Moestl */ 36842c1b001SThomas Moestl 369801772ecSMarius Strobl /* Get RX FIFO size. */ 370336cca9eSBenno Rice sc->sc_rxfifosize = 64 * 371bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 372336cca9eSBenno Rice 373801772ecSMarius Strobl /* Get TX FIFO size. */ 374bd3d9826SMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 3753a5aee5aSThomas Moestl device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 3763a5aee5aSThomas Moestl sc->sc_rxfifosize / 1024, v / 16); 37742c1b001SThomas Moestl 37842c1b001SThomas Moestl /* Attach the interface. */ 379fc74a9f9SBrooks Davis ether_ifattach(ifp, sc->sc_enaddr); 38042c1b001SThomas Moestl 38100d12766SMarius Strobl /* 38212fb0330SPyun YongHyeon * Tell the upper layer(s) we support long frames/checksum offloads. 38300d12766SMarius Strobl */ 38400d12766SMarius Strobl ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 38512fb0330SPyun YongHyeon ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 38612fb0330SPyun YongHyeon ifp->if_hwassist |= sc->sc_csum_features; 38712fb0330SPyun YongHyeon ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 38800d12766SMarius Strobl 38942c1b001SThomas Moestl return (0); 39042c1b001SThomas Moestl 39142c1b001SThomas Moestl /* 39242c1b001SThomas Moestl * Free any resources we've allocated during the failed attach 39342c1b001SThomas Moestl * attempt. Do this in reverse order and fall through. 39442c1b001SThomas Moestl */ 395305f2c06SThomas Moestl fail_rxd: 3962a79fd39SMarius Strobl for (i = 0; i < GEM_NRXDESC; i++) 39742c1b001SThomas Moestl if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 398305f2c06SThomas Moestl bus_dmamap_destroy(sc->sc_rdmatag, 39942c1b001SThomas Moestl sc->sc_rxsoft[i].rxs_dmamap); 400305f2c06SThomas Moestl fail_txd: 4012a79fd39SMarius Strobl for (i = 0; i < GEM_TXQUEUELEN; i++) 40242c1b001SThomas Moestl if (sc->sc_txsoft[i].txs_dmamap != NULL) 403305f2c06SThomas Moestl bus_dmamap_destroy(sc->sc_tdmatag, 40442c1b001SThomas Moestl sc->sc_txsoft[i].txs_dmamap); 405305f2c06SThomas Moestl bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 406305f2c06SThomas Moestl fail_cmem: 40742c1b001SThomas Moestl bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 40842c1b001SThomas Moestl sc->sc_cddmamap); 409305f2c06SThomas Moestl fail_ctag: 41042c1b001SThomas Moestl bus_dma_tag_destroy(sc->sc_cdmatag); 411305f2c06SThomas Moestl fail_ttag: 412305f2c06SThomas Moestl bus_dma_tag_destroy(sc->sc_tdmatag); 413305f2c06SThomas Moestl fail_rtag: 414305f2c06SThomas Moestl bus_dma_tag_destroy(sc->sc_rdmatag); 415305f2c06SThomas Moestl fail_ptag: 41642c1b001SThomas Moestl bus_dma_tag_destroy(sc->sc_pdmatag); 417fc74a9f9SBrooks Davis fail_ifnet: 418fc74a9f9SBrooks Davis if_free(ifp); 41942c1b001SThomas Moestl return (error); 42042c1b001SThomas Moestl } 42142c1b001SThomas Moestl 422cbbdf236SThomas Moestl void 4232a79fd39SMarius Strobl gem_detach(struct gem_softc *sc) 424cbbdf236SThomas Moestl { 425fc74a9f9SBrooks Davis struct ifnet *ifp = sc->sc_ifp; 426cbbdf236SThomas Moestl int i; 427cbbdf236SThomas Moestl 428b3a1f860SMarius Strobl ether_ifdetach(ifp); 4298cfaff7dSMarius Strobl GEM_LOCK(sc); 43025bd46d0SBrooks Davis gem_stop(ifp, 1); 4318cfaff7dSMarius Strobl GEM_UNLOCK(sc); 4321f317bf9SMarius Strobl callout_drain(&sc->sc_tick_ch); 4331f317bf9SMarius Strobl #ifdef GEM_RINT_TIMEOUT 4341f317bf9SMarius Strobl callout_drain(&sc->sc_rx_ch); 4351f317bf9SMarius Strobl #endif 436fc74a9f9SBrooks Davis if_free(ifp); 437cbbdf236SThomas Moestl device_delete_child(sc->sc_dev, sc->sc_miibus); 438cbbdf236SThomas Moestl 4392a79fd39SMarius Strobl for (i = 0; i < GEM_NRXDESC; i++) 440cbbdf236SThomas Moestl if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 441cbbdf236SThomas Moestl bus_dmamap_destroy(sc->sc_rdmatag, 442cbbdf236SThomas Moestl sc->sc_rxsoft[i].rxs_dmamap); 4432a79fd39SMarius Strobl for (i = 0; i < GEM_TXQUEUELEN; i++) 444cbbdf236SThomas Moestl if (sc->sc_txsoft[i].txs_dmamap != NULL) 445cbbdf236SThomas Moestl bus_dmamap_destroy(sc->sc_tdmatag, 446cbbdf236SThomas Moestl sc->sc_txsoft[i].txs_dmamap); 447ccb1212aSMarius Strobl GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 448cbbdf236SThomas Moestl bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 449cbbdf236SThomas Moestl bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 450cbbdf236SThomas Moestl sc->sc_cddmamap); 451cbbdf236SThomas Moestl bus_dma_tag_destroy(sc->sc_cdmatag); 452cbbdf236SThomas Moestl bus_dma_tag_destroy(sc->sc_tdmatag); 453cbbdf236SThomas Moestl bus_dma_tag_destroy(sc->sc_rdmatag); 454cbbdf236SThomas Moestl bus_dma_tag_destroy(sc->sc_pdmatag); 455cbbdf236SThomas Moestl } 456cbbdf236SThomas Moestl 457cbbdf236SThomas Moestl void 4582a79fd39SMarius Strobl gem_suspend(struct gem_softc *sc) 459cbbdf236SThomas Moestl { 460fc74a9f9SBrooks Davis struct ifnet *ifp = sc->sc_ifp; 461cbbdf236SThomas Moestl 4628cfaff7dSMarius Strobl GEM_LOCK(sc); 463cbbdf236SThomas Moestl gem_stop(ifp, 0); 4648cfaff7dSMarius Strobl GEM_UNLOCK(sc); 465cbbdf236SThomas Moestl } 466cbbdf236SThomas Moestl 467cbbdf236SThomas Moestl void 4682a79fd39SMarius Strobl gem_resume(struct gem_softc *sc) 469cbbdf236SThomas Moestl { 470fc74a9f9SBrooks Davis struct ifnet *ifp = sc->sc_ifp; 471cbbdf236SThomas Moestl 4728cfaff7dSMarius Strobl GEM_LOCK(sc); 47300d12766SMarius Strobl /* 47400d12766SMarius Strobl * On resume all registers have to be initialized again like 47500d12766SMarius Strobl * after power-on. 47600d12766SMarius Strobl */ 4771ed3fed7SMarius Strobl sc->sc_flags &= ~GEM_INITED; 478cbbdf236SThomas Moestl if (ifp->if_flags & IFF_UP) 4798cfaff7dSMarius Strobl gem_init_locked(sc); 4808cfaff7dSMarius Strobl GEM_UNLOCK(sc); 481cbbdf236SThomas Moestl } 482cbbdf236SThomas Moestl 4839ba2b298SMarius Strobl static inline void 48412fb0330SPyun YongHyeon gem_rxcksum(struct mbuf *m, uint64_t flags) 48512fb0330SPyun YongHyeon { 48612fb0330SPyun YongHyeon struct ether_header *eh; 48712fb0330SPyun YongHyeon struct ip *ip; 48812fb0330SPyun YongHyeon struct udphdr *uh; 4892a79fd39SMarius Strobl uint16_t *opts; 49012fb0330SPyun YongHyeon int32_t hlen, len, pktlen; 49112fb0330SPyun YongHyeon uint32_t temp32; 4922a79fd39SMarius Strobl uint16_t cksum; 49312fb0330SPyun YongHyeon 49412fb0330SPyun YongHyeon pktlen = m->m_pkthdr.len; 49512fb0330SPyun YongHyeon if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 49612fb0330SPyun YongHyeon return; 49712fb0330SPyun YongHyeon eh = mtod(m, struct ether_header *); 49812fb0330SPyun YongHyeon if (eh->ether_type != htons(ETHERTYPE_IP)) 49912fb0330SPyun YongHyeon return; 50012fb0330SPyun YongHyeon ip = (struct ip *)(eh + 1); 50112fb0330SPyun YongHyeon if (ip->ip_v != IPVERSION) 50212fb0330SPyun YongHyeon return; 50312fb0330SPyun YongHyeon 50412fb0330SPyun YongHyeon hlen = ip->ip_hl << 2; 50512fb0330SPyun YongHyeon pktlen -= sizeof(struct ether_header); 50612fb0330SPyun YongHyeon if (hlen < sizeof(struct ip)) 50712fb0330SPyun YongHyeon return; 50812fb0330SPyun YongHyeon if (ntohs(ip->ip_len) < hlen) 50912fb0330SPyun YongHyeon return; 51012fb0330SPyun YongHyeon if (ntohs(ip->ip_len) != pktlen) 51112fb0330SPyun YongHyeon return; 51212fb0330SPyun YongHyeon if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 5132a79fd39SMarius Strobl return; /* Cannot handle fragmented packet. */ 51412fb0330SPyun YongHyeon 51512fb0330SPyun YongHyeon switch (ip->ip_p) { 51612fb0330SPyun YongHyeon case IPPROTO_TCP: 51712fb0330SPyun YongHyeon if (pktlen < (hlen + sizeof(struct tcphdr))) 51812fb0330SPyun YongHyeon return; 51912fb0330SPyun YongHyeon break; 52012fb0330SPyun YongHyeon case IPPROTO_UDP: 52112fb0330SPyun YongHyeon if (pktlen < (hlen + sizeof(struct udphdr))) 52212fb0330SPyun YongHyeon return; 52312fb0330SPyun YongHyeon uh = (struct udphdr *)((uint8_t *)ip + hlen); 52412fb0330SPyun YongHyeon if (uh->uh_sum == 0) 52512fb0330SPyun YongHyeon return; /* no checksum */ 52612fb0330SPyun YongHyeon break; 52712fb0330SPyun YongHyeon default: 52812fb0330SPyun YongHyeon return; 52912fb0330SPyun YongHyeon } 53012fb0330SPyun YongHyeon 53112fb0330SPyun YongHyeon cksum = ~(flags & GEM_RD_CHECKSUM); 53212fb0330SPyun YongHyeon /* checksum fixup for IP options */ 53312fb0330SPyun YongHyeon len = hlen - sizeof(struct ip); 53412fb0330SPyun YongHyeon if (len > 0) { 53512fb0330SPyun YongHyeon opts = (uint16_t *)(ip + 1); 53612fb0330SPyun YongHyeon for (; len > 0; len -= sizeof(uint16_t), opts++) { 53712fb0330SPyun YongHyeon temp32 = cksum - *opts; 53812fb0330SPyun YongHyeon temp32 = (temp32 >> 16) + (temp32 & 65535); 53912fb0330SPyun YongHyeon cksum = temp32 & 65535; 54012fb0330SPyun YongHyeon } 54112fb0330SPyun YongHyeon } 54212fb0330SPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 54312fb0330SPyun YongHyeon m->m_pkthdr.csum_data = cksum; 54412fb0330SPyun YongHyeon } 54512fb0330SPyun YongHyeon 54642c1b001SThomas Moestl static void 5472a79fd39SMarius Strobl gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 54842c1b001SThomas Moestl { 5492a79fd39SMarius Strobl struct gem_softc *sc = xsc; 55042c1b001SThomas Moestl 55142c1b001SThomas Moestl if (error != 0) 55242c1b001SThomas Moestl return; 5532a79fd39SMarius Strobl if (nsegs != 1) 5541ed3fed7SMarius Strobl panic("%s: bad control buffer segment count", __func__); 55542c1b001SThomas Moestl sc->sc_cddma = segs[0].ds_addr; 55642c1b001SThomas Moestl } 55742c1b001SThomas Moestl 55842c1b001SThomas Moestl static void 5592a79fd39SMarius Strobl gem_tick(void *arg) 56042c1b001SThomas Moestl { 56142c1b001SThomas Moestl struct gem_softc *sc = arg; 5629ba2b298SMarius Strobl struct ifnet *ifp = sc->sc_ifp; 56378d22f42SMarius Strobl uint32_t v; 56442c1b001SThomas Moestl 5651f317bf9SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 56612fb0330SPyun YongHyeon 56712fb0330SPyun YongHyeon /* 56878d22f42SMarius Strobl * Unload collision and error counters. 56912fb0330SPyun YongHyeon */ 57012fb0330SPyun YongHyeon ifp->if_collisions += 571bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 57278d22f42SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 57378d22f42SMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 574bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 57578d22f42SMarius Strobl ifp->if_collisions += v; 57678d22f42SMarius Strobl ifp->if_oerrors += v; 57778d22f42SMarius Strobl ifp->if_ierrors += 57878d22f42SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 57978d22f42SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 58078d22f42SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 58178d22f42SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 58212fb0330SPyun YongHyeon 58312fb0330SPyun YongHyeon /* 584801772ecSMarius Strobl * Then clear the hardware counters. 58512fb0330SPyun YongHyeon */ 586bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 587bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 588bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 589bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 59078d22f42SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 59178d22f42SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 59278d22f42SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 59378d22f42SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 59412fb0330SPyun YongHyeon 59542c1b001SThomas Moestl mii_tick(sc->sc_mii); 59642c1b001SThomas Moestl 5978cb37876SMarius Strobl if (gem_watchdog(sc) == EJUSTRETURN) 5988cb37876SMarius Strobl return; 5998cb37876SMarius Strobl 60042c1b001SThomas Moestl callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 60142c1b001SThomas Moestl } 60242c1b001SThomas Moestl 60342c1b001SThomas Moestl static int 604bd3d9826SMarius Strobl gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 605bd3d9826SMarius Strobl uint32_t set) 60642c1b001SThomas Moestl { 60742c1b001SThomas Moestl int i; 6082a79fd39SMarius Strobl uint32_t reg; 60942c1b001SThomas Moestl 6109ba2b298SMarius Strobl for (i = GEM_TRIES; i--; DELAY(100)) { 611bd3d9826SMarius Strobl reg = GEM_BANKN_READ_M(bank, 4, sc, r); 612e87137e1SMarius Strobl if ((reg & clr) == 0 && (reg & set) == set) 61342c1b001SThomas Moestl return (1); 61442c1b001SThomas Moestl } 61542c1b001SThomas Moestl return (0); 61642c1b001SThomas Moestl } 61742c1b001SThomas Moestl 6181ed3fed7SMarius Strobl static void 6199ba2b298SMarius Strobl gem_reset(struct gem_softc *sc) 62042c1b001SThomas Moestl { 62142c1b001SThomas Moestl 62218100346SThomas Moestl #ifdef GEM_DEBUG 62312fb0330SPyun YongHyeon CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 62418100346SThomas Moestl #endif 62542c1b001SThomas Moestl gem_reset_rx(sc); 62642c1b001SThomas Moestl gem_reset_tx(sc); 62742c1b001SThomas Moestl 6282a79fd39SMarius Strobl /* Do a full reset. */ 629bd3d9826SMarius Strobl GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 630ccb1212aSMarius Strobl GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 631ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 632bd3d9826SMarius Strobl if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 63342c1b001SThomas Moestl device_printf(sc->sc_dev, "cannot reset device\n"); 63442c1b001SThomas Moestl } 63542c1b001SThomas Moestl 63642c1b001SThomas Moestl static void 6372a79fd39SMarius Strobl gem_rxdrain(struct gem_softc *sc) 63842c1b001SThomas Moestl { 63942c1b001SThomas Moestl struct gem_rxsoft *rxs; 64042c1b001SThomas Moestl int i; 64142c1b001SThomas Moestl 64242c1b001SThomas Moestl for (i = 0; i < GEM_NRXDESC; i++) { 64342c1b001SThomas Moestl rxs = &sc->sc_rxsoft[i]; 64442c1b001SThomas Moestl if (rxs->rxs_mbuf != NULL) { 645b2d59f42SThomas Moestl bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 646b2d59f42SThomas Moestl BUS_DMASYNC_POSTREAD); 647305f2c06SThomas Moestl bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 64842c1b001SThomas Moestl m_freem(rxs->rxs_mbuf); 64942c1b001SThomas Moestl rxs->rxs_mbuf = NULL; 65042c1b001SThomas Moestl } 65142c1b001SThomas Moestl } 65242c1b001SThomas Moestl } 65342c1b001SThomas Moestl 65442c1b001SThomas Moestl static void 6552a79fd39SMarius Strobl gem_stop(struct ifnet *ifp, int disable) 65642c1b001SThomas Moestl { 6572a79fd39SMarius Strobl struct gem_softc *sc = ifp->if_softc; 65842c1b001SThomas Moestl struct gem_txsoft *txs; 65942c1b001SThomas Moestl 66018100346SThomas Moestl #ifdef GEM_DEBUG 66112fb0330SPyun YongHyeon CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 66218100346SThomas Moestl #endif 66342c1b001SThomas Moestl 66442c1b001SThomas Moestl callout_stop(&sc->sc_tick_ch); 6651f317bf9SMarius Strobl #ifdef GEM_RINT_TIMEOUT 6661f317bf9SMarius Strobl callout_stop(&sc->sc_rx_ch); 6671f317bf9SMarius Strobl #endif 66842c1b001SThomas Moestl 6699ba2b298SMarius Strobl gem_reset_tx(sc); 6709ba2b298SMarius Strobl gem_reset_rx(sc); 67142c1b001SThomas Moestl 67242c1b001SThomas Moestl /* 67342c1b001SThomas Moestl * Release any queued transmit buffers. 67442c1b001SThomas Moestl */ 67542c1b001SThomas Moestl while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 67642c1b001SThomas Moestl STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 67742c1b001SThomas Moestl if (txs->txs_ndescs != 0) { 678b2d59f42SThomas Moestl bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 679b2d59f42SThomas Moestl BUS_DMASYNC_POSTWRITE); 680305f2c06SThomas Moestl bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 68142c1b001SThomas Moestl if (txs->txs_mbuf != NULL) { 68242c1b001SThomas Moestl m_freem(txs->txs_mbuf); 68342c1b001SThomas Moestl txs->txs_mbuf = NULL; 68442c1b001SThomas Moestl } 68542c1b001SThomas Moestl } 68642c1b001SThomas Moestl STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 68742c1b001SThomas Moestl } 68842c1b001SThomas Moestl 68942c1b001SThomas Moestl if (disable) 69042c1b001SThomas Moestl gem_rxdrain(sc); 69142c1b001SThomas Moestl 69242c1b001SThomas Moestl /* 69342c1b001SThomas Moestl * Mark the interface down and cancel the watchdog timer. 69442c1b001SThomas Moestl */ 69513f4c340SRobert Watson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6961ed3fed7SMarius Strobl sc->sc_flags &= ~GEM_LINK; 6978cb37876SMarius Strobl sc->sc_wdog_timer = 0; 69842c1b001SThomas Moestl } 69942c1b001SThomas Moestl 7001ed3fed7SMarius Strobl static int 7012a79fd39SMarius Strobl gem_reset_rx(struct gem_softc *sc) 70242c1b001SThomas Moestl { 70342c1b001SThomas Moestl 70442c1b001SThomas Moestl /* 70542c1b001SThomas Moestl * Resetting while DMA is in progress can cause a bus hang, so we 70642c1b001SThomas Moestl * disable DMA first. 70742c1b001SThomas Moestl */ 708*c0e3e9d4SMarius Strobl (void)gem_disable_rx(sc); 709bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 710ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 711ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 712bd3d9826SMarius Strobl if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 7131ed3fed7SMarius Strobl device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 71442c1b001SThomas Moestl 7159a68cbd3SMarius Strobl /* Wait 5ms extra. */ 7169a68cbd3SMarius Strobl DELAY(5000); 7179a68cbd3SMarius Strobl 718*c0e3e9d4SMarius Strobl /* Reset the ERX. */ 719bd3d9826SMarius Strobl GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX); 720ccb1212aSMarius Strobl GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 721ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 722bd3d9826SMarius Strobl if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 723bd3d9826SMarius Strobl 0)) { 72442c1b001SThomas Moestl device_printf(sc->sc_dev, "cannot reset receiver\n"); 72542c1b001SThomas Moestl return (1); 72642c1b001SThomas Moestl } 727*c0e3e9d4SMarius Strobl 728*c0e3e9d4SMarius Strobl /* Finally, reset RX MAC. */ 729*c0e3e9d4SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RXRESET, 1); 730*c0e3e9d4SMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MAC_RXRESET, 4, 731*c0e3e9d4SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 732*c0e3e9d4SMarius Strobl if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RXRESET, 1, 0)) { 733*c0e3e9d4SMarius Strobl device_printf(sc->sc_dev, "cannot reset RX MAC\n"); 734*c0e3e9d4SMarius Strobl return (1); 735*c0e3e9d4SMarius Strobl } 736*c0e3e9d4SMarius Strobl 73742c1b001SThomas Moestl return (0); 73842c1b001SThomas Moestl } 73942c1b001SThomas Moestl 7401ed3fed7SMarius Strobl /* 7411ed3fed7SMarius Strobl * Reset the receiver DMA engine. 7421ed3fed7SMarius Strobl * 7431ed3fed7SMarius Strobl * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 7441ed3fed7SMarius Strobl * etc in order to reset the receiver DMA engine only and not do a full 7451ed3fed7SMarius Strobl * reset which amongst others also downs the link and clears the FIFOs. 7461ed3fed7SMarius Strobl */ 7471ed3fed7SMarius Strobl static void 7481ed3fed7SMarius Strobl gem_reset_rxdma(struct gem_softc *sc) 7491ed3fed7SMarius Strobl { 7501ed3fed7SMarius Strobl int i; 7511ed3fed7SMarius Strobl 75283242185SPyun YongHyeon if (gem_reset_rx(sc) != 0) { 75383242185SPyun YongHyeon sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7541ed3fed7SMarius Strobl return (gem_init_locked(sc)); 75583242185SPyun YongHyeon } 7561ed3fed7SMarius Strobl for (i = 0; i < GEM_NRXDESC; i++) 7571ed3fed7SMarius Strobl if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 7581ed3fed7SMarius Strobl GEM_UPDATE_RXDESC(sc, i); 7591ed3fed7SMarius Strobl sc->sc_rxptr = 0; 7609ba2b298SMarius Strobl GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 7611ed3fed7SMarius Strobl 7621ed3fed7SMarius Strobl /* NOTE: we use only 32-bit DMA addresses here. */ 763bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 764bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 765bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 766bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 7671ed3fed7SMarius Strobl gem_ringsize(GEM_NRXDESC /* XXX */) | 7681ed3fed7SMarius Strobl ((ETHER_HDR_LEN + sizeof(struct ip)) << 7691ed3fed7SMarius Strobl GEM_RX_CONFIG_CXM_START_SHFT) | 7701ed3fed7SMarius Strobl (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 7719ba2b298SMarius Strobl (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 7729ba2b298SMarius Strobl /* Adjust for the SBus clock probably isn't worth the fuzz. */ 773bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 7749ba2b298SMarius Strobl ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 7759ba2b298SMarius Strobl GEM_RX_BLANKING_TIME_SHIFT) | 6); 776bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 7772a79fd39SMarius Strobl (3 * sc->sc_rxfifosize / 256) | 7782a79fd39SMarius Strobl ((sc->sc_rxfifosize / 256) << 12)); 779*c0e3e9d4SMarius Strobl /* 780*c0e3e9d4SMarius Strobl * Clear the RX filter and reprogram it. This will also set the 781*c0e3e9d4SMarius Strobl * current RX MAC configuration. 782*c0e3e9d4SMarius Strobl */ 783*c0e3e9d4SMarius Strobl gem_setladrf(sc, 0); 784bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 785bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 786bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 7871ed3fed7SMarius Strobl GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 788bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 789*c0e3e9d4SMarius Strobl sc->sc_mac_rxcfg | GEM_MAC_RX_ENABLE); 7901ed3fed7SMarius Strobl } 79142c1b001SThomas Moestl 79242c1b001SThomas Moestl static int 7932a79fd39SMarius Strobl gem_reset_tx(struct gem_softc *sc) 79442c1b001SThomas Moestl { 79542c1b001SThomas Moestl 79642c1b001SThomas Moestl /* 79742c1b001SThomas Moestl * Resetting while DMA is in progress can cause a bus hang, so we 79842c1b001SThomas Moestl * disable DMA first. 79942c1b001SThomas Moestl */ 800*c0e3e9d4SMarius Strobl (void)gem_disable_tx(sc); 801bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 802ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 803ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 804bd3d9826SMarius Strobl if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 8051ed3fed7SMarius Strobl device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 80642c1b001SThomas Moestl 8079a68cbd3SMarius Strobl /* Wait 5ms extra. */ 8089a68cbd3SMarius Strobl DELAY(5000); 8099a68cbd3SMarius Strobl 810801772ecSMarius Strobl /* Finally, reset the ETX. */ 811bd3d9826SMarius Strobl GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX); 812ccb1212aSMarius Strobl GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 813ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 814bd3d9826SMarius Strobl if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 815bd3d9826SMarius Strobl 0)) { 8161ed3fed7SMarius Strobl device_printf(sc->sc_dev, "cannot reset transmitter\n"); 81742c1b001SThomas Moestl return (1); 81842c1b001SThomas Moestl } 81942c1b001SThomas Moestl return (0); 82042c1b001SThomas Moestl } 82142c1b001SThomas Moestl 82242c1b001SThomas Moestl static int 8232a79fd39SMarius Strobl gem_disable_rx(struct gem_softc *sc) 82442c1b001SThomas Moestl { 82542c1b001SThomas Moestl 826bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 827bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 828ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 829ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 830*c0e3e9d4SMarius Strobl if (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 831*c0e3e9d4SMarius Strobl return (1); 832*c0e3e9d4SMarius Strobl device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 833*c0e3e9d4SMarius Strobl return (0); 83442c1b001SThomas Moestl } 83542c1b001SThomas Moestl 83642c1b001SThomas Moestl static int 8372a79fd39SMarius Strobl gem_disable_tx(struct gem_softc *sc) 83842c1b001SThomas Moestl { 83942c1b001SThomas Moestl 840bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 841bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 842ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 843ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 844*c0e3e9d4SMarius Strobl if (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 845*c0e3e9d4SMarius Strobl return (1); 846*c0e3e9d4SMarius Strobl device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 847*c0e3e9d4SMarius Strobl return (0); 84842c1b001SThomas Moestl } 84942c1b001SThomas Moestl 85042c1b001SThomas Moestl static int 8519ba2b298SMarius Strobl gem_meminit(struct gem_softc *sc) 85242c1b001SThomas Moestl { 85342c1b001SThomas Moestl struct gem_rxsoft *rxs; 8542a79fd39SMarius Strobl int error, i; 85542c1b001SThomas Moestl 8569ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 8579ba2b298SMarius Strobl 85842c1b001SThomas Moestl /* 85942c1b001SThomas Moestl * Initialize the transmit descriptor ring. 86042c1b001SThomas Moestl */ 86142c1b001SThomas Moestl for (i = 0; i < GEM_NTXDESC; i++) { 86242c1b001SThomas Moestl sc->sc_txdescs[i].gd_flags = 0; 86342c1b001SThomas Moestl sc->sc_txdescs[i].gd_addr = 0; 86442c1b001SThomas Moestl } 865305f2c06SThomas Moestl sc->sc_txfree = GEM_MAXTXFREE; 86642c1b001SThomas Moestl sc->sc_txnext = 0; 867336cca9eSBenno Rice sc->sc_txwin = 0; 86842c1b001SThomas Moestl 86942c1b001SThomas Moestl /* 87042c1b001SThomas Moestl * Initialize the receive descriptor and receive job 87142c1b001SThomas Moestl * descriptor rings. 87242c1b001SThomas Moestl */ 87342c1b001SThomas Moestl for (i = 0; i < GEM_NRXDESC; i++) { 87442c1b001SThomas Moestl rxs = &sc->sc_rxsoft[i]; 87542c1b001SThomas Moestl if (rxs->rxs_mbuf == NULL) { 87642c1b001SThomas Moestl if ((error = gem_add_rxbuf(sc, i)) != 0) { 8772a79fd39SMarius Strobl device_printf(sc->sc_dev, 8782a79fd39SMarius Strobl "unable to allocate or map RX buffer %d, " 8792a79fd39SMarius Strobl "error = %d\n", i, error); 88042c1b001SThomas Moestl /* 8812a79fd39SMarius Strobl * XXX we should attempt to run with fewer 8822a79fd39SMarius Strobl * receive buffers instead of just failing. 88342c1b001SThomas Moestl */ 88442c1b001SThomas Moestl gem_rxdrain(sc); 88542c1b001SThomas Moestl return (1); 88642c1b001SThomas Moestl } 88742c1b001SThomas Moestl } else 88842c1b001SThomas Moestl GEM_INIT_RXDESC(sc, i); 88942c1b001SThomas Moestl } 89042c1b001SThomas Moestl sc->sc_rxptr = 0; 8919ba2b298SMarius Strobl 8929ba2b298SMarius Strobl GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 89342c1b001SThomas Moestl 89442c1b001SThomas Moestl return (0); 89542c1b001SThomas Moestl } 89642c1b001SThomas Moestl 8971ed3fed7SMarius Strobl static u_int 8982a79fd39SMarius Strobl gem_ringsize(u_int sz) 89942c1b001SThomas Moestl { 90042c1b001SThomas Moestl 90142c1b001SThomas Moestl switch (sz) { 90242c1b001SThomas Moestl case 32: 9031ed3fed7SMarius Strobl return (GEM_RING_SZ_32); 90442c1b001SThomas Moestl case 64: 9051ed3fed7SMarius Strobl return (GEM_RING_SZ_64); 90642c1b001SThomas Moestl case 128: 9071ed3fed7SMarius Strobl return (GEM_RING_SZ_128); 90842c1b001SThomas Moestl case 256: 9091ed3fed7SMarius Strobl return (GEM_RING_SZ_256); 91042c1b001SThomas Moestl case 512: 9111ed3fed7SMarius Strobl return (GEM_RING_SZ_512); 91242c1b001SThomas Moestl case 1024: 9131ed3fed7SMarius Strobl return (GEM_RING_SZ_1024); 91442c1b001SThomas Moestl case 2048: 9151ed3fed7SMarius Strobl return (GEM_RING_SZ_2048); 91642c1b001SThomas Moestl case 4096: 9171ed3fed7SMarius Strobl return (GEM_RING_SZ_4096); 91842c1b001SThomas Moestl case 8192: 9191ed3fed7SMarius Strobl return (GEM_RING_SZ_8192); 92042c1b001SThomas Moestl default: 9211ed3fed7SMarius Strobl printf("%s: invalid ring size %d\n", __func__, sz); 9221ed3fed7SMarius Strobl return (GEM_RING_SZ_32); 92342c1b001SThomas Moestl } 92442c1b001SThomas Moestl } 92542c1b001SThomas Moestl 92642c1b001SThomas Moestl static void 9272a79fd39SMarius Strobl gem_init(void *xsc) 92842c1b001SThomas Moestl { 9292a79fd39SMarius Strobl struct gem_softc *sc = xsc; 9308cfaff7dSMarius Strobl 9318cfaff7dSMarius Strobl GEM_LOCK(sc); 9328cfaff7dSMarius Strobl gem_init_locked(sc); 9338cfaff7dSMarius Strobl GEM_UNLOCK(sc); 9348cfaff7dSMarius Strobl } 9358cfaff7dSMarius Strobl 9368cfaff7dSMarius Strobl /* 9378cfaff7dSMarius Strobl * Initialization of interface; set up initialization block 9388cfaff7dSMarius Strobl * and transmit/receive descriptor rings. 9398cfaff7dSMarius Strobl */ 9408cfaff7dSMarius Strobl static void 9412a79fd39SMarius Strobl gem_init_locked(struct gem_softc *sc) 9428cfaff7dSMarius Strobl { 943fc74a9f9SBrooks Davis struct ifnet *ifp = sc->sc_ifp; 9442a79fd39SMarius Strobl uint32_t v; 94542c1b001SThomas Moestl 9468cfaff7dSMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 94742c1b001SThomas Moestl 94883242185SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 94983242185SPyun YongHyeon return; 95083242185SPyun YongHyeon 95118100346SThomas Moestl #ifdef GEM_DEBUG 95212fb0330SPyun YongHyeon CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 95312fb0330SPyun YongHyeon __func__); 95418100346SThomas Moestl #endif 95542c1b001SThomas Moestl /* 95642c1b001SThomas Moestl * Initialization sequence. The numbered steps below correspond 95742c1b001SThomas Moestl * to the sequence outlined in section 6.3.5.1 in the Ethernet 95842c1b001SThomas Moestl * Channel Engine manual (part of the PCIO manual). 95942c1b001SThomas Moestl * See also the STP2002-STQ document from Sun Microsystems. 96042c1b001SThomas Moestl */ 96142c1b001SThomas Moestl 9622a79fd39SMarius Strobl /* step 1 & 2. Reset the Ethernet Channel. */ 963ccb1212aSMarius Strobl gem_stop(ifp, 0); 96442c1b001SThomas Moestl gem_reset(sc); 96518100346SThomas Moestl #ifdef GEM_DEBUG 96612fb0330SPyun YongHyeon CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 96712fb0330SPyun YongHyeon __func__); 96818100346SThomas Moestl #endif 96942c1b001SThomas Moestl 97065f2c0ffSMarius Strobl if ((sc->sc_flags & GEM_SERDES) == 0) 9712a79fd39SMarius Strobl /* Re-initialize the MIF. */ 97242c1b001SThomas Moestl gem_mifinit(sc); 97342c1b001SThomas Moestl 9742a79fd39SMarius Strobl /* step 3. Setup data structures in host memory. */ 9751ed3fed7SMarius Strobl if (gem_meminit(sc) != 0) 9761ed3fed7SMarius Strobl return; 97742c1b001SThomas Moestl 97842c1b001SThomas Moestl /* step 4. TX MAC registers & counters */ 97942c1b001SThomas Moestl gem_init_regs(sc); 98042c1b001SThomas Moestl 98142c1b001SThomas Moestl /* step 5. RX MAC registers & counters */ 982*c0e3e9d4SMarius Strobl gem_setladrf(sc, 0); 98342c1b001SThomas Moestl 9842a79fd39SMarius Strobl /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 98542c1b001SThomas Moestl /* NOTE: we use only 32-bit DMA addresses here. */ 986bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 987bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 98842c1b001SThomas Moestl 989bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 990bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 99118100346SThomas Moestl #ifdef GEM_DEBUG 9922a79fd39SMarius Strobl CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 99342c1b001SThomas Moestl GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 99418100346SThomas Moestl #endif 99542c1b001SThomas Moestl 99642c1b001SThomas Moestl /* step 8. Global Configuration & Interrupt Mask */ 9979ba2b298SMarius Strobl 9989ba2b298SMarius Strobl /* 9999ba2b298SMarius Strobl * Set the internal arbitration to "infinite" bursts of the 10009ba2b298SMarius Strobl * maximum length of 31 * 64 bytes so DMA transfers aren't 10019ba2b298SMarius Strobl * split up in cache line size chunks. This greatly improves 10029ba2b298SMarius Strobl * RX performance. 10039ba2b298SMarius Strobl * Enable silicon bug workarounds for the Apple variants. 10049ba2b298SMarius Strobl */ 10059ba2b298SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 10069ba2b298SMarius Strobl GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 10079ba2b298SMarius Strobl ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 10089ba2b298SMarius Strobl GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 10099ba2b298SMarius Strobl GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 10109ba2b298SMarius Strobl 1011bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 10121ed3fed7SMarius Strobl ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 10131ed3fed7SMarius Strobl GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 10141ed3fed7SMarius Strobl GEM_INTR_BERR 10151ed3fed7SMarius Strobl #ifdef GEM_DEBUG 10161ed3fed7SMarius Strobl | GEM_INTR_PCS | GEM_INTR_MIF 10171ed3fed7SMarius Strobl #endif 10181ed3fed7SMarius Strobl )); 1019bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 1020336cca9eSBenno Rice GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1021bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 10229ba2b298SMarius Strobl GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 10239ba2b298SMarius Strobl GEM_MAC_TX_PEAK_EXP); 10241ed3fed7SMarius Strobl #ifdef GEM_DEBUG 1025bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 10261ed3fed7SMarius Strobl ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 10271ed3fed7SMarius Strobl #else 1028bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 10291ed3fed7SMarius Strobl GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 10301ed3fed7SMarius Strobl #endif 103142c1b001SThomas Moestl 10322a79fd39SMarius Strobl /* step 9. ETX Configuration: use mostly default values. */ 103342c1b001SThomas Moestl 10342a79fd39SMarius Strobl /* Enable DMA. */ 10359ba2b298SMarius Strobl v = gem_ringsize(GEM_NTXDESC); 10369ba2b298SMarius Strobl /* Set TX FIFO threshold and enable DMA. */ 1037ccb1212aSMarius Strobl v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1038ccb1212aSMarius Strobl GEM_TX_CONFIG_TXFIFO_TH; 1039ccb1212aSMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 104042c1b001SThomas Moestl 104142c1b001SThomas Moestl /* step 10. ERX Configuration */ 104242c1b001SThomas Moestl 10431ed3fed7SMarius Strobl /* Encode Receive Descriptor ring size. */ 104442c1b001SThomas Moestl v = gem_ringsize(GEM_NRXDESC /* XXX */); 10452a79fd39SMarius Strobl /* RX TCP/UDP checksum offset */ 104612fb0330SPyun YongHyeon v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 104712fb0330SPyun YongHyeon GEM_RX_CONFIG_CXM_START_SHFT); 10489ba2b298SMarius Strobl /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1049bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 105042c1b001SThomas Moestl v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 10519ba2b298SMarius Strobl (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 10529ba2b298SMarius Strobl GEM_RX_CONFIG_RXDMA_EN); 10531ed3fed7SMarius Strobl 10549ba2b298SMarius Strobl /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1055bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 10569ba2b298SMarius Strobl ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 10579ba2b298SMarius Strobl GEM_RX_BLANKING_TIME_SHIFT) | 6); 10581ed3fed7SMarius Strobl 105942c1b001SThomas Moestl /* 1060336cca9eSBenno Rice * The following value is for an OFF Threshold of about 3/4 full 1061336cca9eSBenno Rice * and an ON Threshold of 1/4 full. 106242c1b001SThomas Moestl */ 1063bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 1064336cca9eSBenno Rice (3 * sc->sc_rxfifosize / 256) | 1065336cca9eSBenno Rice ((sc->sc_rxfifosize / 256) << 12)); 106642c1b001SThomas Moestl 10672a79fd39SMarius Strobl /* step 11. Configure Media. */ 106842c1b001SThomas Moestl 106942c1b001SThomas Moestl /* step 12. RX_MAC Configuration Register */ 1070bd3d9826SMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1071ccb1212aSMarius Strobl v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1072*c0e3e9d4SMarius Strobl (void)gem_disable_rx(sc); 1073*c0e3e9d4SMarius Strobl sc->sc_mac_rxcfg = v & ~GEM_MAC_RX_ENABLE; 1074bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 107542c1b001SThomas Moestl 1076ccb1212aSMarius Strobl /* step 13. TX_MAC Configuration Register */ 1077ccb1212aSMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1078ccb1212aSMarius Strobl v |= GEM_MAC_TX_ENABLE; 1079*c0e3e9d4SMarius Strobl (void)gem_disable_tx(sc); 1080ccb1212aSMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1081ccb1212aSMarius Strobl 10822a79fd39SMarius Strobl /* step 14. Issue Transmit Pending command. */ 108342c1b001SThomas Moestl 1084af5ac863SMarius Strobl /* step 15. Give the receiver a swift kick. */ 1085bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 108642c1b001SThomas Moestl 108713f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_RUNNING; 108813f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 10891ed3fed7SMarius Strobl 10901ed3fed7SMarius Strobl mii_mediachg(sc->sc_mii); 10911ed3fed7SMarius Strobl 10921ed3fed7SMarius Strobl /* Start the one second timer. */ 10931ed3fed7SMarius Strobl sc->sc_wdog_timer = 0; 10941ed3fed7SMarius Strobl callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 109542c1b001SThomas Moestl } 109642c1b001SThomas Moestl 109712fb0330SPyun YongHyeon static int 10982a79fd39SMarius Strobl gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 109912fb0330SPyun YongHyeon { 110012fb0330SPyun YongHyeon bus_dma_segment_t txsegs[GEM_NTXSEGS]; 11012a79fd39SMarius Strobl struct gem_txsoft *txs; 1102ccb1212aSMarius Strobl struct ip *ip; 110312fb0330SPyun YongHyeon struct mbuf *m; 11042a79fd39SMarius Strobl uint64_t cflags, flags; 1105ccb1212aSMarius Strobl int error, nexttx, nsegs, offset, seg; 110642c1b001SThomas Moestl 11079ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 11089ba2b298SMarius Strobl 110942c1b001SThomas Moestl /* Get a work queue entry. */ 111042c1b001SThomas Moestl if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1111305f2c06SThomas Moestl /* Ran out of descriptors. */ 111212fb0330SPyun YongHyeon return (ENOBUFS); 1113305f2c06SThomas Moestl } 1114ccb1212aSMarius Strobl 1115ccb1212aSMarius Strobl cflags = 0; 1116ccb1212aSMarius Strobl if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1117ccb1212aSMarius Strobl if (M_WRITABLE(*m_head) == 0) { 1118ccb1212aSMarius Strobl m = m_dup(*m_head, M_DONTWAIT); 1119ccb1212aSMarius Strobl m_freem(*m_head); 1120ccb1212aSMarius Strobl *m_head = m; 1121ccb1212aSMarius Strobl if (m == NULL) 1122ccb1212aSMarius Strobl return (ENOBUFS); 1123ccb1212aSMarius Strobl } 1124ccb1212aSMarius Strobl offset = sizeof(struct ether_header); 1125ccb1212aSMarius Strobl m = m_pullup(*m_head, offset + sizeof(struct ip)); 1126ccb1212aSMarius Strobl if (m == NULL) { 1127ccb1212aSMarius Strobl *m_head = NULL; 1128ccb1212aSMarius Strobl return (ENOBUFS); 1129ccb1212aSMarius Strobl } 1130ccb1212aSMarius Strobl ip = (struct ip *)(mtod(m, caddr_t) + offset); 1131ccb1212aSMarius Strobl offset += (ip->ip_hl << 2); 1132ccb1212aSMarius Strobl cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1133ccb1212aSMarius Strobl ((offset + m->m_pkthdr.csum_data) << 1134ccb1212aSMarius Strobl GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1135ccb1212aSMarius Strobl *m_head = m; 1136ccb1212aSMarius Strobl } 1137ccb1212aSMarius Strobl 113812fb0330SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 113912fb0330SPyun YongHyeon *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 114012fb0330SPyun YongHyeon if (error == EFBIG) { 1141304a4c6fSJohn Baldwin m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 114212fb0330SPyun YongHyeon if (m == NULL) { 114312fb0330SPyun YongHyeon m_freem(*m_head); 114412fb0330SPyun YongHyeon *m_head = NULL; 114512fb0330SPyun YongHyeon return (ENOBUFS); 114612fb0330SPyun YongHyeon } 114712fb0330SPyun YongHyeon *m_head = m; 11482a79fd39SMarius Strobl error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 11492a79fd39SMarius Strobl txs->txs_dmamap, *m_head, txsegs, &nsegs, 11502a79fd39SMarius Strobl BUS_DMA_NOWAIT); 115112fb0330SPyun YongHyeon if (error != 0) { 115212fb0330SPyun YongHyeon m_freem(*m_head); 115312fb0330SPyun YongHyeon *m_head = NULL; 115412fb0330SPyun YongHyeon return (error); 115512fb0330SPyun YongHyeon } 115612fb0330SPyun YongHyeon } else if (error != 0) 115712fb0330SPyun YongHyeon return (error); 1158801772ecSMarius Strobl /* If nsegs is wrong then the stack is corrupt. */ 1159801772ecSMarius Strobl KASSERT(nsegs <= GEM_NTXSEGS, 1160801772ecSMarius Strobl ("%s: too many DMA segments (%d)", __func__, nsegs)); 116112fb0330SPyun YongHyeon if (nsegs == 0) { 116212fb0330SPyun YongHyeon m_freem(*m_head); 116312fb0330SPyun YongHyeon *m_head = NULL; 116412fb0330SPyun YongHyeon return (EIO); 116512fb0330SPyun YongHyeon } 116612fb0330SPyun YongHyeon 116712fb0330SPyun YongHyeon /* 116812fb0330SPyun YongHyeon * Ensure we have enough descriptors free to describe 116912fb0330SPyun YongHyeon * the packet. Note, we always reserve one descriptor 11702a79fd39SMarius Strobl * at the end of the ring as a termination point, in 11712a79fd39SMarius Strobl * order to prevent wrap-around. 117212fb0330SPyun YongHyeon */ 117312fb0330SPyun YongHyeon if (nsegs > sc->sc_txfree - 1) { 117412fb0330SPyun YongHyeon txs->txs_ndescs = 0; 117512fb0330SPyun YongHyeon bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 117612fb0330SPyun YongHyeon return (ENOBUFS); 117712fb0330SPyun YongHyeon } 117812fb0330SPyun YongHyeon 117912fb0330SPyun YongHyeon txs->txs_ndescs = nsegs; 1180305f2c06SThomas Moestl txs->txs_firstdesc = sc->sc_txnext; 118112fb0330SPyun YongHyeon nexttx = txs->txs_firstdesc; 118212fb0330SPyun YongHyeon for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 118312fb0330SPyun YongHyeon #ifdef GEM_DEBUG 11842a79fd39SMarius Strobl CTR6(KTR_GEM, 11852a79fd39SMarius Strobl "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 11862a79fd39SMarius Strobl __func__, seg, nexttx, txsegs[seg].ds_len, 11872a79fd39SMarius Strobl txsegs[seg].ds_addr, 118812fb0330SPyun YongHyeon GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 118912fb0330SPyun YongHyeon #endif 119012fb0330SPyun YongHyeon sc->sc_txdescs[nexttx].gd_addr = 119112fb0330SPyun YongHyeon GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 119212fb0330SPyun YongHyeon KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 119312fb0330SPyun YongHyeon ("%s: segment size too large!", __func__)); 119412fb0330SPyun YongHyeon flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 119512fb0330SPyun YongHyeon sc->sc_txdescs[nexttx].gd_flags = 119612fb0330SPyun YongHyeon GEM_DMA_WRITE(sc, flags | cflags); 119712fb0330SPyun YongHyeon txs->txs_lastdesc = nexttx; 119842c1b001SThomas Moestl } 1199305f2c06SThomas Moestl 12002a79fd39SMarius Strobl /* Set EOP on the last descriptor. */ 120112fb0330SPyun YongHyeon #ifdef GEM_DEBUG 12022a79fd39SMarius Strobl CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 12032a79fd39SMarius Strobl __func__, seg, nexttx); 120412fb0330SPyun YongHyeon #endif 120512fb0330SPyun YongHyeon sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 120612fb0330SPyun YongHyeon GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 120712fb0330SPyun YongHyeon 12082a79fd39SMarius Strobl /* Lastly set SOP on the first descriptor. */ 120912fb0330SPyun YongHyeon #ifdef GEM_DEBUG 12102a79fd39SMarius Strobl CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 12112a79fd39SMarius Strobl __func__, seg, nexttx); 121212fb0330SPyun YongHyeon #endif 121312fb0330SPyun YongHyeon if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 121412fb0330SPyun YongHyeon sc->sc_txwin = 0; 121512fb0330SPyun YongHyeon sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 121612fb0330SPyun YongHyeon GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 121712fb0330SPyun YongHyeon GEM_TD_START_OF_PACKET); 121812fb0330SPyun YongHyeon } else 121912fb0330SPyun YongHyeon sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 122012fb0330SPyun YongHyeon GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 122112fb0330SPyun YongHyeon 122242c1b001SThomas Moestl /* Sync the DMA map. */ 12232a79fd39SMarius Strobl bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 12242a79fd39SMarius Strobl BUS_DMASYNC_PREWRITE); 1225305f2c06SThomas Moestl 122618100346SThomas Moestl #ifdef GEM_DEBUG 122712fb0330SPyun YongHyeon CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 12282a79fd39SMarius Strobl __func__, txs->txs_firstdesc, txs->txs_lastdesc, 12292a79fd39SMarius Strobl txs->txs_ndescs); 123018100346SThomas Moestl #endif 123142c1b001SThomas Moestl STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1232305f2c06SThomas Moestl STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 123312fb0330SPyun YongHyeon txs->txs_mbuf = *m_head; 1234305f2c06SThomas Moestl 1235305f2c06SThomas Moestl sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1236305f2c06SThomas Moestl sc->sc_txfree -= txs->txs_ndescs; 123742c1b001SThomas Moestl 123812fb0330SPyun YongHyeon return (0); 123942c1b001SThomas Moestl } 124042c1b001SThomas Moestl 124142c1b001SThomas Moestl static void 12422a79fd39SMarius Strobl gem_init_regs(struct gem_softc *sc) 124342c1b001SThomas Moestl { 12444a0d6638SRuslan Ermilov const u_char *laddr = IF_LLADDR(sc->sc_ifp); 124542c1b001SThomas Moestl 12469ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 12479ba2b298SMarius Strobl 12482a79fd39SMarius Strobl /* These registers are not cleared on reset. */ 12491ed3fed7SMarius Strobl if ((sc->sc_flags & GEM_INITED) == 0) { 12502a79fd39SMarius Strobl /* magic values */ 1251bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1252bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1253bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 125442c1b001SThomas Moestl 12559ba2b298SMarius Strobl /* min frame length */ 1256bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 12579ba2b298SMarius Strobl /* max frame length and max burst size */ 1258bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 12591ed3fed7SMarius Strobl (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1260336cca9eSBenno Rice 12619ba2b298SMarius Strobl /* more magic values */ 1262bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1263bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1264bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 12659a68cbd3SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8808); 12669ba2b298SMarius Strobl 12679ba2b298SMarius Strobl /* random number seed */ 1268bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1269336cca9eSBenno Rice ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1270336cca9eSBenno Rice 12712a79fd39SMarius Strobl /* secondary MAC address: 0:0:0:0:0:0 */ 1272bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1273bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1274bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1275336cca9eSBenno Rice 12762a79fd39SMarius Strobl /* MAC control address: 01:80:c2:00:00:01 */ 1277bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1278bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1279bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 128042c1b001SThomas Moestl 12812a79fd39SMarius Strobl /* MAC filter address: 0:0:0:0:0:0 */ 1282bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1283bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1284bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1285bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1286bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 128742c1b001SThomas Moestl 12881ed3fed7SMarius Strobl sc->sc_flags |= GEM_INITED; 128942c1b001SThomas Moestl } 129042c1b001SThomas Moestl 12912a79fd39SMarius Strobl /* Counters need to be zeroed. */ 1292bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1293bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1294bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1295bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1296bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1297bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1298bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1299bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1300bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1301bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1302bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 130342c1b001SThomas Moestl 13041ed3fed7SMarius Strobl /* Set XOFF PAUSE time. */ 1305bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 13061ed3fed7SMarius Strobl 13072a79fd39SMarius Strobl /* Set the station address. */ 1308bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1309bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1310bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1311336cca9eSBenno Rice 13121ed3fed7SMarius Strobl /* Enable MII outputs. */ 1313bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 131442c1b001SThomas Moestl } 131542c1b001SThomas Moestl 131642c1b001SThomas Moestl static void 13172a79fd39SMarius Strobl gem_start(struct ifnet *ifp) 131842c1b001SThomas Moestl { 13192a79fd39SMarius Strobl struct gem_softc *sc = ifp->if_softc; 13208cfaff7dSMarius Strobl 13218cfaff7dSMarius Strobl GEM_LOCK(sc); 13228cfaff7dSMarius Strobl gem_start_locked(ifp); 13238cfaff7dSMarius Strobl GEM_UNLOCK(sc); 13248cfaff7dSMarius Strobl } 13258cfaff7dSMarius Strobl 13269ba2b298SMarius Strobl static inline void 13279ba2b298SMarius Strobl gem_txkick(struct gem_softc *sc) 13289ba2b298SMarius Strobl { 13299ba2b298SMarius Strobl 13309ba2b298SMarius Strobl /* 13319ba2b298SMarius Strobl * Update the TX kick register. This register has to point to the 13329ba2b298SMarius Strobl * descriptor after the last valid one and for optimum performance 13339ba2b298SMarius Strobl * should be incremented in multiples of 4 (the DMA engine fetches/ 13349ba2b298SMarius Strobl * updates descriptors in batches of 4). 13359ba2b298SMarius Strobl */ 13369ba2b298SMarius Strobl #ifdef GEM_DEBUG 13379ba2b298SMarius Strobl CTR3(KTR_GEM, "%s: %s: kicking TX %d", 13389ba2b298SMarius Strobl device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 13399ba2b298SMarius Strobl #endif 13409ba2b298SMarius Strobl GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 13419ba2b298SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 13429ba2b298SMarius Strobl } 13439ba2b298SMarius Strobl 13448cfaff7dSMarius Strobl static void 13452a79fd39SMarius Strobl gem_start_locked(struct ifnet *ifp) 13468cfaff7dSMarius Strobl { 13472a79fd39SMarius Strobl struct gem_softc *sc = ifp->if_softc; 134812fb0330SPyun YongHyeon struct mbuf *m; 13499ba2b298SMarius Strobl int kicked, ntx; 13509ba2b298SMarius Strobl 13519ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 135242c1b001SThomas Moestl 135313f4c340SRobert Watson if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 13541ed3fed7SMarius Strobl IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 135542c1b001SThomas Moestl return; 135642c1b001SThomas Moestl 135718100346SThomas Moestl #ifdef GEM_DEBUG 135812fb0330SPyun YongHyeon CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 13591ed3fed7SMarius Strobl device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 13601ed3fed7SMarius Strobl sc->sc_txnext); 136118100346SThomas Moestl #endif 13622a79fd39SMarius Strobl ntx = 0; 13639ba2b298SMarius Strobl kicked = 0; 136412fb0330SPyun YongHyeon for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 136512fb0330SPyun YongHyeon IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 136612fb0330SPyun YongHyeon if (m == NULL) 136742c1b001SThomas Moestl break; 13681ed3fed7SMarius Strobl if (gem_load_txmbuf(sc, &m) != 0) { 136912fb0330SPyun YongHyeon if (m == NULL) 137012fb0330SPyun YongHyeon break; 137112fb0330SPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_OACTIVE; 137212fb0330SPyun YongHyeon IFQ_DRV_PREPEND(&ifp->if_snd, m); 137342c1b001SThomas Moestl break; 137442c1b001SThomas Moestl } 13759ba2b298SMarius Strobl if ((sc->sc_txnext % 4) == 0) { 13769ba2b298SMarius Strobl gem_txkick(sc); 13779ba2b298SMarius Strobl kicked = 1; 13789ba2b298SMarius Strobl } else 13799ba2b298SMarius Strobl kicked = 0; 138018100346SThomas Moestl ntx++; 138112fb0330SPyun YongHyeon BPF_MTAP(ifp, m); 1382305f2c06SThomas Moestl } 1383305f2c06SThomas Moestl 1384305f2c06SThomas Moestl if (ntx > 0) { 13859ba2b298SMarius Strobl if (kicked == 0) 13869ba2b298SMarius Strobl gem_txkick(sc); 138718100346SThomas Moestl #ifdef GEM_DEBUG 1388305f2c06SThomas Moestl CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 13891ed3fed7SMarius Strobl device_get_name(sc->sc_dev), sc->sc_txnext); 139018100346SThomas Moestl #endif 1391305f2c06SThomas Moestl 139242c1b001SThomas Moestl /* Set a watchdog timer in case the chip flakes out. */ 13938cb37876SMarius Strobl sc->sc_wdog_timer = 5; 139418100346SThomas Moestl #ifdef GEM_DEBUG 139512fb0330SPyun YongHyeon CTR3(KTR_GEM, "%s: %s: watchdog %d", 13962a79fd39SMarius Strobl device_get_name(sc->sc_dev), __func__, 13972a79fd39SMarius Strobl sc->sc_wdog_timer); 139818100346SThomas Moestl #endif 139942c1b001SThomas Moestl } 140042c1b001SThomas Moestl } 140142c1b001SThomas Moestl 140242c1b001SThomas Moestl static void 14032a79fd39SMarius Strobl gem_tint(struct gem_softc *sc) 140442c1b001SThomas Moestl { 1405fc74a9f9SBrooks Davis struct ifnet *ifp = sc->sc_ifp; 140642c1b001SThomas Moestl struct gem_txsoft *txs; 14079ba2b298SMarius Strobl int progress; 14089ba2b298SMarius Strobl uint32_t txlast; 140918100346SThomas Moestl #ifdef GEM_DEBUG 14102a79fd39SMarius Strobl int i; 14112a79fd39SMarius Strobl 14129ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 14139ba2b298SMarius Strobl 141412fb0330SPyun YongHyeon CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 141518100346SThomas Moestl #endif 141642c1b001SThomas Moestl 141742c1b001SThomas Moestl /* 14182a79fd39SMarius Strobl * Go through our TX list and free mbufs for those 141942c1b001SThomas Moestl * frames that have been transmitted. 142042c1b001SThomas Moestl */ 14212a79fd39SMarius Strobl progress = 0; 1422b2d59f42SThomas Moestl GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 142342c1b001SThomas Moestl while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 142442c1b001SThomas Moestl #ifdef GEM_DEBUG 14252a79fd39SMarius Strobl if ((ifp->if_flags & IFF_DEBUG) != 0) { 142642c1b001SThomas Moestl printf(" txsoft %p transmit chain:\n", txs); 142742c1b001SThomas Moestl for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 142842c1b001SThomas Moestl printf("descriptor %d: ", i); 14292a79fd39SMarius Strobl printf("gd_flags: 0x%016llx\t", 14302a79fd39SMarius Strobl (long long)GEM_DMA_READ(sc, 14312a79fd39SMarius Strobl sc->sc_txdescs[i].gd_flags)); 14322a79fd39SMarius Strobl printf("gd_addr: 0x%016llx\n", 14332a79fd39SMarius Strobl (long long)GEM_DMA_READ(sc, 14342a79fd39SMarius Strobl sc->sc_txdescs[i].gd_addr)); 143542c1b001SThomas Moestl if (i == txs->txs_lastdesc) 143642c1b001SThomas Moestl break; 143742c1b001SThomas Moestl } 143842c1b001SThomas Moestl } 143942c1b001SThomas Moestl #endif 144042c1b001SThomas Moestl 144142c1b001SThomas Moestl /* 14421ed3fed7SMarius Strobl * In theory, we could harvest some descriptors before 144342c1b001SThomas Moestl * the ring is empty, but that's a bit complicated. 144442c1b001SThomas Moestl * 144542c1b001SThomas Moestl * GEM_TX_COMPLETION points to the last descriptor 144642c1b001SThomas Moestl * processed + 1. 144742c1b001SThomas Moestl */ 1448bd3d9826SMarius Strobl txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 144918100346SThomas Moestl #ifdef GEM_DEBUG 145012fb0330SPyun YongHyeon CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 145142c1b001SThomas Moestl "txs->txs_lastdesc = %d, txlast = %d", 145212fb0330SPyun YongHyeon __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 145318100346SThomas Moestl #endif 145442c1b001SThomas Moestl if (txs->txs_firstdesc <= txs->txs_lastdesc) { 145542c1b001SThomas Moestl if ((txlast >= txs->txs_firstdesc) && 145642c1b001SThomas Moestl (txlast <= txs->txs_lastdesc)) 145742c1b001SThomas Moestl break; 145842c1b001SThomas Moestl } else { 14592a79fd39SMarius Strobl /* Ick -- this command wraps. */ 146042c1b001SThomas Moestl if ((txlast >= txs->txs_firstdesc) || 146142c1b001SThomas Moestl (txlast <= txs->txs_lastdesc)) 146242c1b001SThomas Moestl break; 146342c1b001SThomas Moestl } 146442c1b001SThomas Moestl 146518100346SThomas Moestl #ifdef GEM_DEBUG 14662a79fd39SMarius Strobl CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 146718100346SThomas Moestl #endif 146842c1b001SThomas Moestl STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 146942c1b001SThomas Moestl 147042c1b001SThomas Moestl sc->sc_txfree += txs->txs_ndescs; 147142c1b001SThomas Moestl 1472305f2c06SThomas Moestl bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 147342c1b001SThomas Moestl BUS_DMASYNC_POSTWRITE); 1474305f2c06SThomas Moestl bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 147542c1b001SThomas Moestl if (txs->txs_mbuf != NULL) { 147642c1b001SThomas Moestl m_freem(txs->txs_mbuf); 147742c1b001SThomas Moestl txs->txs_mbuf = NULL; 147842c1b001SThomas Moestl } 147942c1b001SThomas Moestl 148042c1b001SThomas Moestl STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 148142c1b001SThomas Moestl 148242c1b001SThomas Moestl ifp->if_opackets++; 1483336cca9eSBenno Rice progress = 1; 148442c1b001SThomas Moestl } 148542c1b001SThomas Moestl 148618100346SThomas Moestl #ifdef GEM_DEBUG 14872a79fd39SMarius Strobl CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 148842c1b001SThomas Moestl "GEM_TX_COMPLETION %x", 1489bd3d9826SMarius Strobl __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1490bd3d9826SMarius Strobl ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1491bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1492bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 149318100346SThomas Moestl #endif 149442c1b001SThomas Moestl 1495336cca9eSBenno Rice if (progress) { 1496336cca9eSBenno Rice if (sc->sc_txfree == GEM_NTXDESC - 1) 1497336cca9eSBenno Rice sc->sc_txwin = 0; 149842c1b001SThomas Moestl 14992a79fd39SMarius Strobl /* 15002a79fd39SMarius Strobl * We freed some descriptors, so reset IFF_DRV_OACTIVE 15012a79fd39SMarius Strobl * and restart. 15022a79fd39SMarius Strobl */ 150313f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 15049ba2b298SMarius Strobl if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 15059ba2b298SMarius Strobl sc->sc_wdog_timer = 0; 150612fb0330SPyun YongHyeon gem_start_locked(ifp); 1507336cca9eSBenno Rice } 150842c1b001SThomas Moestl 150918100346SThomas Moestl #ifdef GEM_DEBUG 151012fb0330SPyun YongHyeon CTR3(KTR_GEM, "%s: %s: watchdog %d", 151112fb0330SPyun YongHyeon device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 151218100346SThomas Moestl #endif 151342c1b001SThomas Moestl } 151442c1b001SThomas Moestl 1515c3d5598aSMarius Strobl #ifdef GEM_RINT_TIMEOUT 15160d80b9bdSThomas Moestl static void 15172a79fd39SMarius Strobl gem_rint_timeout(void *arg) 15180d80b9bdSThomas Moestl { 15192a79fd39SMarius Strobl struct gem_softc *sc = arg; 15200d80b9bdSThomas Moestl 15211f317bf9SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 15229ba2b298SMarius Strobl 15238cfaff7dSMarius Strobl gem_rint(sc); 15240d80b9bdSThomas Moestl } 152511e3f060SJake Burkholder #endif 15260d80b9bdSThomas Moestl 152742c1b001SThomas Moestl static void 15282a79fd39SMarius Strobl gem_rint(struct gem_softc *sc) 152942c1b001SThomas Moestl { 1530fc74a9f9SBrooks Davis struct ifnet *ifp = sc->sc_ifp; 153142c1b001SThomas Moestl struct mbuf *m; 15322a79fd39SMarius Strobl uint64_t rxstat; 15332a79fd39SMarius Strobl uint32_t rxcomp; 153442c1b001SThomas Moestl 15359ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 15369ba2b298SMarius Strobl 1537c3d5598aSMarius Strobl #ifdef GEM_RINT_TIMEOUT 15380d80b9bdSThomas Moestl callout_stop(&sc->sc_rx_ch); 1539c3d5598aSMarius Strobl #endif 154018100346SThomas Moestl #ifdef GEM_DEBUG 154112fb0330SPyun YongHyeon CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 154218100346SThomas Moestl #endif 1543336cca9eSBenno Rice 1544336cca9eSBenno Rice /* 1545336cca9eSBenno Rice * Read the completion register once. This limits 1546336cca9eSBenno Rice * how long the following loop can execute. 1547336cca9eSBenno Rice */ 1548bd3d9826SMarius Strobl rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 154918100346SThomas Moestl #ifdef GEM_DEBUG 15509ba2b298SMarius Strobl CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 155112fb0330SPyun YongHyeon __func__, sc->sc_rxptr, rxcomp); 155218100346SThomas Moestl #endif 15539ba2b298SMarius Strobl GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 15541ed3fed7SMarius Strobl for (; sc->sc_rxptr != rxcomp;) { 15551ed3fed7SMarius Strobl m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 15561ed3fed7SMarius Strobl rxstat = GEM_DMA_READ(sc, 15571ed3fed7SMarius Strobl sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 155842c1b001SThomas Moestl 155942c1b001SThomas Moestl if (rxstat & GEM_RD_OWN) { 1560c3d5598aSMarius Strobl #ifdef GEM_RINT_TIMEOUT 156142c1b001SThomas Moestl /* 15620d80b9bdSThomas Moestl * The descriptor is still marked as owned, although 15630d80b9bdSThomas Moestl * it is supposed to have completed. This has been 15640d80b9bdSThomas Moestl * observed on some machines. Just exiting here 15650d80b9bdSThomas Moestl * might leave the packet sitting around until another 15660d80b9bdSThomas Moestl * one arrives to trigger a new interrupt, which is 15670d80b9bdSThomas Moestl * generally undesirable, so set up a timeout. 156842c1b001SThomas Moestl */ 15690d80b9bdSThomas Moestl callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 15700d80b9bdSThomas Moestl gem_rint_timeout, sc); 1571336cca9eSBenno Rice #endif 15721ed3fed7SMarius Strobl m = NULL; 15731ed3fed7SMarius Strobl goto kickit; 157442c1b001SThomas Moestl } 157542c1b001SThomas Moestl 157642c1b001SThomas Moestl if (rxstat & GEM_RD_BAD_CRC) { 1577336cca9eSBenno Rice ifp->if_ierrors++; 157842c1b001SThomas Moestl device_printf(sc->sc_dev, "receive error: CRC error\n"); 15791ed3fed7SMarius Strobl GEM_INIT_RXDESC(sc, sc->sc_rxptr); 15801ed3fed7SMarius Strobl m = NULL; 15811ed3fed7SMarius Strobl goto kickit; 158242c1b001SThomas Moestl } 158342c1b001SThomas Moestl 158442c1b001SThomas Moestl #ifdef GEM_DEBUG 15852a79fd39SMarius Strobl if ((ifp->if_flags & IFF_DEBUG) != 0) { 15861ed3fed7SMarius Strobl printf(" rxsoft %p descriptor %d: ", 15871ed3fed7SMarius Strobl &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 15882a79fd39SMarius Strobl printf("gd_flags: 0x%016llx\t", 15892a79fd39SMarius Strobl (long long)GEM_DMA_READ(sc, 15902a79fd39SMarius Strobl sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 15912a79fd39SMarius Strobl printf("gd_addr: 0x%016llx\n", 15922a79fd39SMarius Strobl (long long)GEM_DMA_READ(sc, 15932a79fd39SMarius Strobl sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 159442c1b001SThomas Moestl } 159542c1b001SThomas Moestl #endif 159642c1b001SThomas Moestl 159742c1b001SThomas Moestl /* 159842c1b001SThomas Moestl * Allocate a new mbuf cluster. If that fails, we are 159942c1b001SThomas Moestl * out of memory, and must drop the packet and recycle 160042c1b001SThomas Moestl * the buffer that's already attached to this descriptor. 160142c1b001SThomas Moestl */ 16021ed3fed7SMarius Strobl if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 1603*c0e3e9d4SMarius Strobl ifp->if_iqdrops++; 16041ed3fed7SMarius Strobl GEM_INIT_RXDESC(sc, sc->sc_rxptr); 16051ed3fed7SMarius Strobl m = NULL; 16061ed3fed7SMarius Strobl } 16071ed3fed7SMarius Strobl 16081ed3fed7SMarius Strobl kickit: 16091ed3fed7SMarius Strobl /* 16101ed3fed7SMarius Strobl * Update the RX kick register. This register has to point 16111ed3fed7SMarius Strobl * to the descriptor after the last valid one (before the 16129ba2b298SMarius Strobl * current batch) and for optimum performance should be 16139ba2b298SMarius Strobl * incremented in multiples of 4 (the DMA engine fetches/ 16149ba2b298SMarius Strobl * updates descriptors in batches of 4). 16151ed3fed7SMarius Strobl */ 16161ed3fed7SMarius Strobl sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 16171ed3fed7SMarius Strobl if ((sc->sc_rxptr % 4) == 0) { 1618ccb1212aSMarius Strobl GEM_CDSYNC(sc, 1619ccb1212aSMarius Strobl BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1620bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 16211ed3fed7SMarius Strobl (sc->sc_rxptr + GEM_NRXDESC - 4) & 16221ed3fed7SMarius Strobl GEM_NRXDESC_MASK); 16231ed3fed7SMarius Strobl } 16241ed3fed7SMarius Strobl 16251ed3fed7SMarius Strobl if (m == NULL) { 16261ed3fed7SMarius Strobl if (rxstat & GEM_RD_OWN) 16271ed3fed7SMarius Strobl break; 162842c1b001SThomas Moestl continue; 162942c1b001SThomas Moestl } 163042c1b001SThomas Moestl 16311ed3fed7SMarius Strobl ifp->if_ipackets++; 16329ba2b298SMarius Strobl m->m_data += ETHER_ALIGN; /* first byte offset */ 163342c1b001SThomas Moestl m->m_pkthdr.rcvif = ifp; 16341ed3fed7SMarius Strobl m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 163512fb0330SPyun YongHyeon 163612fb0330SPyun YongHyeon if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 163712fb0330SPyun YongHyeon gem_rxcksum(m, rxstat); 163842c1b001SThomas Moestl 163942c1b001SThomas Moestl /* Pass it on. */ 16408cfaff7dSMarius Strobl GEM_UNLOCK(sc); 1641673d9191SSam Leffler (*ifp->if_input)(ifp, m); 16428cfaff7dSMarius Strobl GEM_LOCK(sc); 164342c1b001SThomas Moestl } 164442c1b001SThomas Moestl 164518100346SThomas Moestl #ifdef GEM_DEBUG 16469ba2b298SMarius Strobl CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1647bd3d9826SMarius Strobl sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 164818100346SThomas Moestl #endif 164942c1b001SThomas Moestl } 165042c1b001SThomas Moestl 165142c1b001SThomas Moestl static int 16522a79fd39SMarius Strobl gem_add_rxbuf(struct gem_softc *sc, int idx) 165342c1b001SThomas Moestl { 165442c1b001SThomas Moestl struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 165542c1b001SThomas Moestl struct mbuf *m; 1656c3d5598aSMarius Strobl bus_dma_segment_t segs[1]; 1657c3d5598aSMarius Strobl int error, nsegs; 165842c1b001SThomas Moestl 16599ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 16609ba2b298SMarius Strobl 1661a163d034SWarner Losh m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 166242c1b001SThomas Moestl if (m == NULL) 166342c1b001SThomas Moestl return (ENOBUFS); 1664305f2c06SThomas Moestl m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 166542c1b001SThomas Moestl 166642c1b001SThomas Moestl #ifdef GEM_DEBUG 16672a79fd39SMarius Strobl /* Bzero the packet to check DMA. */ 166842c1b001SThomas Moestl memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 166942c1b001SThomas Moestl #endif 167042c1b001SThomas Moestl 1671b2d59f42SThomas Moestl if (rxs->rxs_mbuf != NULL) { 1672b2d59f42SThomas Moestl bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1673b2d59f42SThomas Moestl BUS_DMASYNC_POSTREAD); 1674305f2c06SThomas Moestl bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1675b2d59f42SThomas Moestl } 167642c1b001SThomas Moestl 1677c3d5598aSMarius Strobl error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1678c3d5598aSMarius Strobl m, segs, &nsegs, BUS_DMA_NOWAIT); 1679c3d5598aSMarius Strobl if (error != 0) { 16802a79fd39SMarius Strobl device_printf(sc->sc_dev, 16812a79fd39SMarius Strobl "cannot load RS DMA map %d, error = %d\n", idx, error); 1682c3d5598aSMarius Strobl m_freem(m); 16831ed3fed7SMarius Strobl return (error); 168442c1b001SThomas Moestl } 16852a79fd39SMarius Strobl /* If nsegs is wrong then the stack is corrupt. */ 1686801772ecSMarius Strobl KASSERT(nsegs == 1, 1687801772ecSMarius Strobl ("%s: too many DMA segments (%d)", __func__, nsegs)); 16881ed3fed7SMarius Strobl rxs->rxs_mbuf = m; 1689c3d5598aSMarius Strobl rxs->rxs_paddr = segs[0].ds_addr; 169042c1b001SThomas Moestl 16912a79fd39SMarius Strobl bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 16922a79fd39SMarius Strobl BUS_DMASYNC_PREREAD); 169342c1b001SThomas Moestl 169442c1b001SThomas Moestl GEM_INIT_RXDESC(sc, idx); 169542c1b001SThomas Moestl 169642c1b001SThomas Moestl return (0); 169742c1b001SThomas Moestl } 169842c1b001SThomas Moestl 169942c1b001SThomas Moestl static void 17002a79fd39SMarius Strobl gem_eint(struct gem_softc *sc, u_int status) 170142c1b001SThomas Moestl { 170242c1b001SThomas Moestl 17031ed3fed7SMarius Strobl sc->sc_ifp->if_ierrors++; 17041ed3fed7SMarius Strobl if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 17051ed3fed7SMarius Strobl gem_reset_rxdma(sc); 170642c1b001SThomas Moestl return; 170742c1b001SThomas Moestl } 170842c1b001SThomas Moestl 17099ba2b298SMarius Strobl device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 17109ba2b298SMarius Strobl if ((status & GEM_INTR_BERR) != 0) { 17119ba2b298SMarius Strobl if ((sc->sc_flags & GEM_PCI) != 0) 17129ba2b298SMarius Strobl printf(", PCI bus error 0x%x\n", 17139ba2b298SMarius Strobl GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 17149ba2b298SMarius Strobl else 17159ba2b298SMarius Strobl printf(", SBus error 0x%x\n", 17169ba2b298SMarius Strobl GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 17179ba2b298SMarius Strobl } 171842c1b001SThomas Moestl } 171942c1b001SThomas Moestl 172042c1b001SThomas Moestl void 17212a79fd39SMarius Strobl gem_intr(void *v) 172242c1b001SThomas Moestl { 17232a79fd39SMarius Strobl struct gem_softc *sc = v; 17241ed3fed7SMarius Strobl uint32_t status, status2; 172542c1b001SThomas Moestl 17268cfaff7dSMarius Strobl GEM_LOCK(sc); 1727bd3d9826SMarius Strobl status = GEM_BANK1_READ_4(sc, GEM_STATUS); 17281ed3fed7SMarius Strobl 172918100346SThomas Moestl #ifdef GEM_DEBUG 173012fb0330SPyun YongHyeon CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 17319ba2b298SMarius Strobl device_get_name(sc->sc_dev), __func__, 17329ba2b298SMarius Strobl (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 17331ed3fed7SMarius Strobl 17341ed3fed7SMarius Strobl /* 17351ed3fed7SMarius Strobl * PCS interrupts must be cleared, otherwise no traffic is passed! 17361ed3fed7SMarius Strobl */ 17371ed3fed7SMarius Strobl if ((status & GEM_INTR_PCS) != 0) { 17382a79fd39SMarius Strobl status2 = 1739bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1740bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 17411ed3fed7SMarius Strobl if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 17421ed3fed7SMarius Strobl device_printf(sc->sc_dev, 17431ed3fed7SMarius Strobl "%s: PCS link status changed\n", __func__); 17441ed3fed7SMarius Strobl } 17451ed3fed7SMarius Strobl if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1746bd3d9826SMarius Strobl status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 17471ed3fed7SMarius Strobl if ((status2 & GEM_MAC_PAUSED) != 0) 17481ed3fed7SMarius Strobl device_printf(sc->sc_dev, 17491ed3fed7SMarius Strobl "%s: PAUSE received (PAUSE time %d slots)\n", 17501ed3fed7SMarius Strobl __func__, GEM_MAC_PAUSE_TIME(status2)); 17511ed3fed7SMarius Strobl if ((status2 & GEM_MAC_PAUSE) != 0) 17521ed3fed7SMarius Strobl device_printf(sc->sc_dev, 17531ed3fed7SMarius Strobl "%s: transited to PAUSE state\n", __func__); 17541ed3fed7SMarius Strobl if ((status2 & GEM_MAC_RESUME) != 0) 17551ed3fed7SMarius Strobl device_printf(sc->sc_dev, 17561ed3fed7SMarius Strobl "%s: transited to non-PAUSE state\n", __func__); 17571ed3fed7SMarius Strobl } 17581ed3fed7SMarius Strobl if ((status & GEM_INTR_MIF) != 0) 17591ed3fed7SMarius Strobl device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 176018100346SThomas Moestl #endif 176142c1b001SThomas Moestl 17629ba2b298SMarius Strobl if (__predict_false(status & 17631ed3fed7SMarius Strobl (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 176442c1b001SThomas Moestl gem_eint(sc, status); 176542c1b001SThomas Moestl 176642c1b001SThomas Moestl if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 176742c1b001SThomas Moestl gem_rint(sc); 176842c1b001SThomas Moestl 17691ed3fed7SMarius Strobl if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 17701ed3fed7SMarius Strobl gem_tint(sc); 17711ed3fed7SMarius Strobl 17729ba2b298SMarius Strobl if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1773bd3d9826SMarius Strobl status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 17742a79fd39SMarius Strobl if ((status2 & 17759ba2b298SMarius Strobl ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 17769ba2b298SMarius Strobl GEM_MAC_TX_PEAK_EXP)) != 0) 17772a79fd39SMarius Strobl device_printf(sc->sc_dev, 17782a79fd39SMarius Strobl "MAC TX fault, status %x\n", status2); 17792a79fd39SMarius Strobl if ((status2 & 17809ba2b298SMarius Strobl (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 17819ba2b298SMarius Strobl sc->sc_ifp->if_oerrors++; 178283242185SPyun YongHyeon sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 17838cfaff7dSMarius Strobl gem_init_locked(sc); 178442c1b001SThomas Moestl } 17859ba2b298SMarius Strobl } 17869ba2b298SMarius Strobl if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1787bd3d9826SMarius Strobl status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 178800d12766SMarius Strobl /* 17891ed3fed7SMarius Strobl * At least with GEM_SUN_GEM and some GEM_SUN_ERI 17901ed3fed7SMarius Strobl * revisions GEM_MAC_RX_OVERFLOW happen often due to a 17911ed3fed7SMarius Strobl * silicon bug so handle them silently. Moreover, it's 17921ed3fed7SMarius Strobl * likely that the receiver has hung so we reset it. 179300d12766SMarius Strobl */ 17942a79fd39SMarius Strobl if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 17951ed3fed7SMarius Strobl sc->sc_ifp->if_ierrors++; 17961ed3fed7SMarius Strobl gem_reset_rxdma(sc); 17972a79fd39SMarius Strobl } else if ((status2 & 17982a79fd39SMarius Strobl ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 17992a79fd39SMarius Strobl device_printf(sc->sc_dev, 18002a79fd39SMarius Strobl "MAC RX fault, status %x\n", status2); 180142c1b001SThomas Moestl } 18028cfaff7dSMarius Strobl GEM_UNLOCK(sc); 180342c1b001SThomas Moestl } 180442c1b001SThomas Moestl 18058cb37876SMarius Strobl static int 18062a79fd39SMarius Strobl gem_watchdog(struct gem_softc *sc) 180742c1b001SThomas Moestl { 1808ccb1212aSMarius Strobl struct ifnet *ifp = sc->sc_ifp; 180942c1b001SThomas Moestl 18108cb37876SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 18118cb37876SMarius Strobl 181218100346SThomas Moestl #ifdef GEM_DEBUG 18132a79fd39SMarius Strobl CTR4(KTR_GEM, 18142a79fd39SMarius Strobl "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1815bd3d9826SMarius Strobl __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1816bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1817bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 18182a79fd39SMarius Strobl CTR4(KTR_GEM, 18192a79fd39SMarius Strobl "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1820bd3d9826SMarius Strobl __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1821bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1822bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 182318100346SThomas Moestl #endif 182442c1b001SThomas Moestl 18258cb37876SMarius Strobl if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 18268cb37876SMarius Strobl return (0); 18278cb37876SMarius Strobl 18281ed3fed7SMarius Strobl if ((sc->sc_flags & GEM_LINK) != 0) 182942c1b001SThomas Moestl device_printf(sc->sc_dev, "device timeout\n"); 18301ed3fed7SMarius Strobl else if (bootverbose) 18311ed3fed7SMarius Strobl device_printf(sc->sc_dev, "device timeout (no link)\n"); 1832ccb1212aSMarius Strobl ++ifp->if_oerrors; 183342c1b001SThomas Moestl 183442c1b001SThomas Moestl /* Try to get more packets going. */ 183583242185SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 18368cfaff7dSMarius Strobl gem_init_locked(sc); 1837ccb1212aSMarius Strobl gem_start_locked(ifp); 18388cb37876SMarius Strobl return (EJUSTRETURN); 183942c1b001SThomas Moestl } 184042c1b001SThomas Moestl 184142c1b001SThomas Moestl static void 18422a79fd39SMarius Strobl gem_mifinit(struct gem_softc *sc) 184342c1b001SThomas Moestl { 184442c1b001SThomas Moestl 1845801772ecSMarius Strobl /* Configure the MIF in frame mode. */ 1846bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1847bd3d9826SMarius Strobl GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 184865f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 184965f2c0ffSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 185042c1b001SThomas Moestl } 185142c1b001SThomas Moestl 185242c1b001SThomas Moestl /* 185342c1b001SThomas Moestl * MII interface 185442c1b001SThomas Moestl * 185578d22f42SMarius Strobl * The MII interface supports at least three different operating modes: 185642c1b001SThomas Moestl * 185742c1b001SThomas Moestl * Bitbang mode is implemented using data, clock and output enable registers. 185842c1b001SThomas Moestl * 185942c1b001SThomas Moestl * Frame mode is implemented by loading a complete frame into the frame 186042c1b001SThomas Moestl * register and polling the valid bit for completion. 186142c1b001SThomas Moestl * 186242c1b001SThomas Moestl * Polling mode uses the frame register but completion is indicated by 186342c1b001SThomas Moestl * an interrupt. 186442c1b001SThomas Moestl * 186542c1b001SThomas Moestl */ 186642c1b001SThomas Moestl int 18672a79fd39SMarius Strobl gem_mii_readreg(device_t dev, int phy, int reg) 186842c1b001SThomas Moestl { 18692a79fd39SMarius Strobl struct gem_softc *sc; 187042c1b001SThomas Moestl int n; 18712a79fd39SMarius Strobl uint32_t v; 187242c1b001SThomas Moestl 187342c1b001SThomas Moestl #ifdef GEM_DEBUG_PHY 18741ed3fed7SMarius Strobl printf("%s: phy %d reg %d\n", __func__, phy, reg); 187542c1b001SThomas Moestl #endif 187642c1b001SThomas Moestl 18772a79fd39SMarius Strobl sc = device_get_softc(dev); 18781ed3fed7SMarius Strobl if ((sc->sc_flags & GEM_SERDES) != 0) { 18791ed3fed7SMarius Strobl switch (reg) { 18801ed3fed7SMarius Strobl case MII_BMCR: 18811ed3fed7SMarius Strobl reg = GEM_MII_CONTROL; 18821ed3fed7SMarius Strobl break; 18831ed3fed7SMarius Strobl case MII_BMSR: 18841ed3fed7SMarius Strobl reg = GEM_MII_STATUS; 18851ed3fed7SMarius Strobl break; 18861ed3fed7SMarius Strobl case MII_PHYIDR1: 18871ed3fed7SMarius Strobl case MII_PHYIDR2: 18881ed3fed7SMarius Strobl return (0); 18891ed3fed7SMarius Strobl case MII_ANAR: 18901ed3fed7SMarius Strobl reg = GEM_MII_ANAR; 18911ed3fed7SMarius Strobl break; 18921ed3fed7SMarius Strobl case MII_ANLPAR: 18931ed3fed7SMarius Strobl reg = GEM_MII_ANLPAR; 18941ed3fed7SMarius Strobl break; 18951ed3fed7SMarius Strobl case MII_EXTSR: 18961ed3fed7SMarius Strobl return (EXTSR_1000XFDX | EXTSR_1000XHDX); 18971ed3fed7SMarius Strobl default: 18981ed3fed7SMarius Strobl device_printf(sc->sc_dev, 18991ed3fed7SMarius Strobl "%s: unhandled register %d\n", __func__, reg); 19001ed3fed7SMarius Strobl return (0); 19011ed3fed7SMarius Strobl } 1902bd3d9826SMarius Strobl return (GEM_BANK1_READ_4(sc, reg)); 19031ed3fed7SMarius Strobl } 190442c1b001SThomas Moestl 19052a79fd39SMarius Strobl /* Construct the frame command. */ 19061ed3fed7SMarius Strobl v = GEM_MIF_FRAME_READ | 19071ed3fed7SMarius Strobl (phy << GEM_MIF_PHY_SHIFT) | 19081ed3fed7SMarius Strobl (reg << GEM_MIF_REG_SHIFT); 190942c1b001SThomas Moestl 1910bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1911ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1912ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 191342c1b001SThomas Moestl for (n = 0; n < 100; n++) { 191442c1b001SThomas Moestl DELAY(1); 1915bd3d9826SMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 19161f317bf9SMarius Strobl if (v & GEM_MIF_FRAME_TA0) 191742c1b001SThomas Moestl return (v & GEM_MIF_FRAME_DATA); 191842c1b001SThomas Moestl } 191942c1b001SThomas Moestl 19202a79fd39SMarius Strobl device_printf(sc->sc_dev, "%s: timed out\n", __func__); 192142c1b001SThomas Moestl return (0); 192242c1b001SThomas Moestl } 192342c1b001SThomas Moestl 192442c1b001SThomas Moestl int 19252a79fd39SMarius Strobl gem_mii_writereg(device_t dev, int phy, int reg, int val) 192642c1b001SThomas Moestl { 19272a79fd39SMarius Strobl struct gem_softc *sc; 192842c1b001SThomas Moestl int n; 19292a79fd39SMarius Strobl uint32_t v; 193042c1b001SThomas Moestl 193142c1b001SThomas Moestl #ifdef GEM_DEBUG_PHY 19321ed3fed7SMarius Strobl printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 193342c1b001SThomas Moestl #endif 193442c1b001SThomas Moestl 19352a79fd39SMarius Strobl sc = device_get_softc(dev); 19361ed3fed7SMarius Strobl if ((sc->sc_flags & GEM_SERDES) != 0) { 19371ed3fed7SMarius Strobl switch (reg) { 19381ed3fed7SMarius Strobl case MII_BMSR: 19391ed3fed7SMarius Strobl reg = GEM_MII_STATUS; 19401ed3fed7SMarius Strobl break; 1941ccb1212aSMarius Strobl case MII_BMCR: 1942ccb1212aSMarius Strobl reg = GEM_MII_CONTROL; 1943ccb1212aSMarius Strobl if ((val & GEM_MII_CONTROL_RESET) == 0) 1944ccb1212aSMarius Strobl break; 1945ccb1212aSMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1946ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1947ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1948ccb1212aSMarius Strobl if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1949ccb1212aSMarius Strobl GEM_MII_CONTROL_RESET, 0)) 1950ccb1212aSMarius Strobl device_printf(sc->sc_dev, 1951ccb1212aSMarius Strobl "cannot reset PCS\n"); 1952ccb1212aSMarius Strobl /* FALLTHROUGH */ 19531ed3fed7SMarius Strobl case MII_ANAR: 1954bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1955bd3d9826SMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 19561ed3fed7SMarius Strobl BUS_SPACE_BARRIER_WRITE); 1957bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 195865f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 195965f2c0ffSMarius Strobl BUS_SPACE_BARRIER_WRITE); 1960bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 19611ed3fed7SMarius Strobl GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 196265f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 196365f2c0ffSMarius Strobl BUS_SPACE_BARRIER_WRITE); 1964bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 19651ed3fed7SMarius Strobl GEM_MII_CONFIG_ENABLE); 196665f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 196765f2c0ffSMarius Strobl BUS_SPACE_BARRIER_WRITE); 19681ed3fed7SMarius Strobl return (0); 19691ed3fed7SMarius Strobl case MII_ANLPAR: 19701ed3fed7SMarius Strobl reg = GEM_MII_ANLPAR; 19711ed3fed7SMarius Strobl break; 19721ed3fed7SMarius Strobl default: 19731ed3fed7SMarius Strobl device_printf(sc->sc_dev, 19741ed3fed7SMarius Strobl "%s: unhandled register %d\n", __func__, reg); 19751ed3fed7SMarius Strobl return (0); 19761ed3fed7SMarius Strobl } 1977bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, reg, val); 197865f2c0ffSMarius Strobl GEM_BANK1_BARRIER(sc, reg, 4, 197965f2c0ffSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 19801ed3fed7SMarius Strobl return (0); 19811ed3fed7SMarius Strobl } 19821ed3fed7SMarius Strobl 19832a79fd39SMarius Strobl /* Construct the frame command. */ 198442c1b001SThomas Moestl v = GEM_MIF_FRAME_WRITE | 198542c1b001SThomas Moestl (phy << GEM_MIF_PHY_SHIFT) | 198642c1b001SThomas Moestl (reg << GEM_MIF_REG_SHIFT) | 198742c1b001SThomas Moestl (val & GEM_MIF_FRAME_DATA); 198842c1b001SThomas Moestl 1989bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1990ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1991ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 199242c1b001SThomas Moestl for (n = 0; n < 100; n++) { 199342c1b001SThomas Moestl DELAY(1); 1994bd3d9826SMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 19951f317bf9SMarius Strobl if (v & GEM_MIF_FRAME_TA0) 199642c1b001SThomas Moestl return (1); 199742c1b001SThomas Moestl } 199842c1b001SThomas Moestl 19992a79fd39SMarius Strobl device_printf(sc->sc_dev, "%s: timed out\n", __func__); 200042c1b001SThomas Moestl return (0); 200142c1b001SThomas Moestl } 200242c1b001SThomas Moestl 200342c1b001SThomas Moestl void 20042a79fd39SMarius Strobl gem_mii_statchg(device_t dev) 200542c1b001SThomas Moestl { 20062a79fd39SMarius Strobl struct gem_softc *sc; 20071ed3fed7SMarius Strobl int gigabit; 20081ed3fed7SMarius Strobl uint32_t rxcfg, txcfg, v; 200942c1b001SThomas Moestl 20102a79fd39SMarius Strobl sc = device_get_softc(dev); 20112a79fd39SMarius Strobl 20129ba2b298SMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 20139ba2b298SMarius Strobl 201442c1b001SThomas Moestl #ifdef GEM_DEBUG 20152a79fd39SMarius Strobl if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 20168e5d93dbSMarius Strobl device_printf(sc->sc_dev, "%s: status change\n", __func__); 201742c1b001SThomas Moestl #endif 201842c1b001SThomas Moestl 20191ed3fed7SMarius Strobl if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 20201ed3fed7SMarius Strobl IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 20211ed3fed7SMarius Strobl sc->sc_flags |= GEM_LINK; 20221ed3fed7SMarius Strobl else 20231ed3fed7SMarius Strobl sc->sc_flags &= ~GEM_LINK; 20241ed3fed7SMarius Strobl 20251ed3fed7SMarius Strobl switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 20261ed3fed7SMarius Strobl case IFM_1000_SX: 20271ed3fed7SMarius Strobl case IFM_1000_LX: 20281ed3fed7SMarius Strobl case IFM_1000_CX: 20291ed3fed7SMarius Strobl case IFM_1000_T: 20301ed3fed7SMarius Strobl gigabit = 1; 20311ed3fed7SMarius Strobl break; 20321ed3fed7SMarius Strobl default: 20331ed3fed7SMarius Strobl gigabit = 0; 203442c1b001SThomas Moestl } 20351ed3fed7SMarius Strobl 20361ed3fed7SMarius Strobl /* 20371ed3fed7SMarius Strobl * The configuration done here corresponds to the steps F) and 20381ed3fed7SMarius Strobl * G) and as far as enabling of RX and TX MAC goes also step H) 20391ed3fed7SMarius Strobl * of the initialization sequence outlined in section 3.2.1 of 20401ed3fed7SMarius Strobl * the GEM Gigabit Ethernet ASIC Specification. 20411ed3fed7SMarius Strobl */ 20421ed3fed7SMarius Strobl 2043*c0e3e9d4SMarius Strobl rxcfg = sc->sc_mac_rxcfg; 2044*c0e3e9d4SMarius Strobl rxcfg &= ~GEM_MAC_RX_CARR_EXTEND; 20451ed3fed7SMarius Strobl txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 20461ed3fed7SMarius Strobl if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 20471ed3fed7SMarius Strobl txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 20481ed3fed7SMarius Strobl else if (gigabit != 0) { 20491ed3fed7SMarius Strobl rxcfg |= GEM_MAC_RX_CARR_EXTEND; 20501ed3fed7SMarius Strobl txcfg |= GEM_MAC_TX_CARR_EXTEND; 20511ed3fed7SMarius Strobl } 2052*c0e3e9d4SMarius Strobl (void)gem_disable_tx(sc); 2053bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2054*c0e3e9d4SMarius Strobl (void)gem_disable_rx(sc); 2055bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 20561ed3fed7SMarius Strobl 2057bd3d9826SMarius Strobl v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 20581ed3fed7SMarius Strobl ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 20592a79fd39SMarius Strobl if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 20602a79fd39SMarius Strobl IFM_ETH_RXPAUSE) != 0) 20611ed3fed7SMarius Strobl v |= GEM_MAC_CC_RX_PAUSE; 20622a79fd39SMarius Strobl if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 20632a79fd39SMarius Strobl IFM_ETH_TXPAUSE) != 0) 20641ed3fed7SMarius Strobl v |= GEM_MAC_CC_TX_PAUSE; 2065bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 20661ed3fed7SMarius Strobl 20671ed3fed7SMarius Strobl if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 20681ed3fed7SMarius Strobl gigabit != 0) 2069bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 20701ed3fed7SMarius Strobl GEM_MAC_SLOT_TIME_CARR_EXTEND); 20711ed3fed7SMarius Strobl else 2072bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 20731ed3fed7SMarius Strobl GEM_MAC_SLOT_TIME_NORMAL); 207442c1b001SThomas Moestl 207542c1b001SThomas Moestl /* XIF Configuration */ 207642c1b001SThomas Moestl v = GEM_MAC_XIF_LINK_LED; 207742c1b001SThomas Moestl v |= GEM_MAC_XIF_TX_MII_ENA; 20781ed3fed7SMarius Strobl if ((sc->sc_flags & GEM_SERDES) == 0) { 2079bd3d9826SMarius Strobl if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 208078d22f42SMarius Strobl GEM_MIF_CONFIG_PHY_SEL) != 0) { 208142c1b001SThomas Moestl /* External MII needs echo disable if half duplex. */ 208278d22f42SMarius Strobl if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 208378d22f42SMarius Strobl IFM_FDX) == 0) 208442c1b001SThomas Moestl v |= GEM_MAC_XIF_ECHO_DISABL; 208578d22f42SMarius Strobl } else 20861ed3fed7SMarius Strobl /* 20871ed3fed7SMarius Strobl * Internal MII needs buffer enable. 20881ed3fed7SMarius Strobl * XXX buffer enable makes only sense for an 20891ed3fed7SMarius Strobl * external PHY. 20901ed3fed7SMarius Strobl */ 209142c1b001SThomas Moestl v |= GEM_MAC_XIF_MII_BUF_ENA; 209242c1b001SThomas Moestl } 20931ed3fed7SMarius Strobl if (gigabit != 0) 20941ed3fed7SMarius Strobl v |= GEM_MAC_XIF_GMII_MODE; 20951ed3fed7SMarius Strobl if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 20961ed3fed7SMarius Strobl v |= GEM_MAC_XIF_FDPLX_LED; 2097bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 20981ed3fed7SMarius Strobl 2099*c0e3e9d4SMarius Strobl sc->sc_mac_rxcfg = rxcfg; 21001ed3fed7SMarius Strobl if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 21011ed3fed7SMarius Strobl (sc->sc_flags & GEM_LINK) != 0) { 2102bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 21031ed3fed7SMarius Strobl txcfg | GEM_MAC_TX_ENABLE); 2104bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 21051ed3fed7SMarius Strobl rxcfg | GEM_MAC_RX_ENABLE); 21061ed3fed7SMarius Strobl } 210742c1b001SThomas Moestl } 210842c1b001SThomas Moestl 210942c1b001SThomas Moestl int 21102a79fd39SMarius Strobl gem_mediachange(struct ifnet *ifp) 211142c1b001SThomas Moestl { 211242c1b001SThomas Moestl struct gem_softc *sc = ifp->if_softc; 21131f317bf9SMarius Strobl int error; 211442c1b001SThomas Moestl 21152a79fd39SMarius Strobl /* XXX add support for serial media. */ 211642c1b001SThomas Moestl 21171f317bf9SMarius Strobl GEM_LOCK(sc); 21181f317bf9SMarius Strobl error = mii_mediachg(sc->sc_mii); 21191f317bf9SMarius Strobl GEM_UNLOCK(sc); 21201f317bf9SMarius Strobl return (error); 212142c1b001SThomas Moestl } 212242c1b001SThomas Moestl 212342c1b001SThomas Moestl void 21242a79fd39SMarius Strobl gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 212542c1b001SThomas Moestl { 212642c1b001SThomas Moestl struct gem_softc *sc = ifp->if_softc; 212742c1b001SThomas Moestl 21288cfaff7dSMarius Strobl GEM_LOCK(sc); 21298cfaff7dSMarius Strobl if ((ifp->if_flags & IFF_UP) == 0) { 21308cfaff7dSMarius Strobl GEM_UNLOCK(sc); 213142c1b001SThomas Moestl return; 21328cfaff7dSMarius Strobl } 213342c1b001SThomas Moestl 213442c1b001SThomas Moestl mii_pollstat(sc->sc_mii); 213542c1b001SThomas Moestl ifmr->ifm_active = sc->sc_mii->mii_media_active; 213642c1b001SThomas Moestl ifmr->ifm_status = sc->sc_mii->mii_media_status; 21378cfaff7dSMarius Strobl GEM_UNLOCK(sc); 213842c1b001SThomas Moestl } 213942c1b001SThomas Moestl 214042c1b001SThomas Moestl static int 21412a79fd39SMarius Strobl gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 214242c1b001SThomas Moestl { 214342c1b001SThomas Moestl struct gem_softc *sc = ifp->if_softc; 214442c1b001SThomas Moestl struct ifreq *ifr = (struct ifreq *)data; 21452a79fd39SMarius Strobl int error; 21468cfaff7dSMarius Strobl 21472a79fd39SMarius Strobl error = 0; 214842c1b001SThomas Moestl switch (cmd) { 214942c1b001SThomas Moestl case SIOCSIFFLAGS: 21501f317bf9SMarius Strobl GEM_LOCK(sc); 21512a79fd39SMarius Strobl if ((ifp->if_flags & IFF_UP) != 0) { 21521ed3fed7SMarius Strobl if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 21531ed3fed7SMarius Strobl ((ifp->if_flags ^ sc->sc_ifflags) & 21541ed3fed7SMarius Strobl (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2155*c0e3e9d4SMarius Strobl gem_setladrf(sc, 1); 215642c1b001SThomas Moestl else 21578cfaff7dSMarius Strobl gem_init_locked(sc); 21582a79fd39SMarius Strobl } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 215942c1b001SThomas Moestl gem_stop(ifp, 0); 216012fb0330SPyun YongHyeon if ((ifp->if_flags & IFF_LINK0) != 0) 216112fb0330SPyun YongHyeon sc->sc_csum_features |= CSUM_UDP; 216212fb0330SPyun YongHyeon else 216312fb0330SPyun YongHyeon sc->sc_csum_features &= ~CSUM_UDP; 216412fb0330SPyun YongHyeon if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 216512fb0330SPyun YongHyeon ifp->if_hwassist = sc->sc_csum_features; 2166336cca9eSBenno Rice sc->sc_ifflags = ifp->if_flags; 21671f317bf9SMarius Strobl GEM_UNLOCK(sc); 216842c1b001SThomas Moestl break; 216942c1b001SThomas Moestl case SIOCADDMULTI: 217042c1b001SThomas Moestl case SIOCDELMULTI: 21711f317bf9SMarius Strobl GEM_LOCK(sc); 2172*c0e3e9d4SMarius Strobl if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2173*c0e3e9d4SMarius Strobl gem_setladrf(sc, 1); 21741f317bf9SMarius Strobl GEM_UNLOCK(sc); 217542c1b001SThomas Moestl break; 217642c1b001SThomas Moestl case SIOCGIFMEDIA: 217742c1b001SThomas Moestl case SIOCSIFMEDIA: 217842c1b001SThomas Moestl error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 217942c1b001SThomas Moestl break; 218012fb0330SPyun YongHyeon case SIOCSIFCAP: 218112fb0330SPyun YongHyeon GEM_LOCK(sc); 218212fb0330SPyun YongHyeon ifp->if_capenable = ifr->ifr_reqcap; 218312fb0330SPyun YongHyeon if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 218412fb0330SPyun YongHyeon ifp->if_hwassist = sc->sc_csum_features; 218512fb0330SPyun YongHyeon else 218612fb0330SPyun YongHyeon ifp->if_hwassist = 0; 218712fb0330SPyun YongHyeon GEM_UNLOCK(sc); 218812fb0330SPyun YongHyeon break; 218942c1b001SThomas Moestl default: 21901f317bf9SMarius Strobl error = ether_ioctl(ifp, cmd, data); 219142c1b001SThomas Moestl break; 219242c1b001SThomas Moestl } 219342c1b001SThomas Moestl 219442c1b001SThomas Moestl return (error); 219542c1b001SThomas Moestl } 219642c1b001SThomas Moestl 219742c1b001SThomas Moestl static void 2198*c0e3e9d4SMarius Strobl gem_setladrf(struct gem_softc *sc, u_int enable) 219942c1b001SThomas Moestl { 2200fc74a9f9SBrooks Davis struct ifnet *ifp = sc->sc_ifp; 220142c1b001SThomas Moestl struct ifmultiaddr *inm; 2202336cca9eSBenno Rice int i; 22032a79fd39SMarius Strobl uint32_t hash[16]; 22042a79fd39SMarius Strobl uint32_t crc, v; 220542c1b001SThomas Moestl 22068cfaff7dSMarius Strobl GEM_LOCK_ASSERT(sc, MA_OWNED); 22078cfaff7dSMarius Strobl 2208336cca9eSBenno Rice /* 2209*c0e3e9d4SMarius Strobl * Turn off the RX MAC and the hash filter as required by the Sun GEM 2210*c0e3e9d4SMarius Strobl * programming restrictions. 2211336cca9eSBenno Rice */ 2212*c0e3e9d4SMarius Strobl v = sc->sc_mac_rxcfg & GEM_MAC_RX_HASH_FILTER; 2213bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2214ccb1212aSMarius Strobl GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2215ccb1212aSMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2216*c0e3e9d4SMarius Strobl if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER | 2217*c0e3e9d4SMarius Strobl GEM_MAC_RX_ENABLE, 0)) 2218*c0e3e9d4SMarius Strobl device_printf(sc->sc_dev, 2219*c0e3e9d4SMarius Strobl "cannot disable RX MAC or hash filter\n"); 22201ed3fed7SMarius Strobl 2221*c0e3e9d4SMarius Strobl v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_PROMISC_GRP); 222242c1b001SThomas Moestl if ((ifp->if_flags & IFF_PROMISC) != 0) { 222342c1b001SThomas Moestl v |= GEM_MAC_RX_PROMISCUOUS; 222442c1b001SThomas Moestl goto chipit; 222542c1b001SThomas Moestl } 222642c1b001SThomas Moestl if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2227336cca9eSBenno Rice v |= GEM_MAC_RX_PROMISC_GRP; 222842c1b001SThomas Moestl goto chipit; 222942c1b001SThomas Moestl } 223042c1b001SThomas Moestl 223142c1b001SThomas Moestl /* 22322a79fd39SMarius Strobl * Set up multicast address filter by passing all multicast 22332a79fd39SMarius Strobl * addresses through a crc generator, and then using the high 22342a79fd39SMarius Strobl * order 8 bits as an index into the 256 bit logical address 22352a79fd39SMarius Strobl * filter. The high order 4 bits selects the word, while the 22362a79fd39SMarius Strobl * other 4 bits select the bit within the word (where bit 0 22372a79fd39SMarius Strobl * is the MSB). 223842c1b001SThomas Moestl */ 223942c1b001SThomas Moestl 22402a79fd39SMarius Strobl /* Clear the hash table. */ 2241336cca9eSBenno Rice memset(hash, 0, sizeof(hash)); 2242336cca9eSBenno Rice 2243eb956cd0SRobert Watson if_maddr_rlock(ifp); 2244fc74a9f9SBrooks Davis TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 224542c1b001SThomas Moestl if (inm->ifma_addr->sa_family != AF_LINK) 224642c1b001SThomas Moestl continue; 2247c240bd8cSMarius Strobl crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2248c240bd8cSMarius Strobl inm->ifma_addr), ETHER_ADDR_LEN); 224942c1b001SThomas Moestl 22502a79fd39SMarius Strobl /* We just want the 8 most significant bits. */ 225142c1b001SThomas Moestl crc >>= 24; 225242c1b001SThomas Moestl 225342c1b001SThomas Moestl /* Set the corresponding bit in the filter. */ 2254336cca9eSBenno Rice hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2255336cca9eSBenno Rice } 2256eb956cd0SRobert Watson if_maddr_runlock(ifp); 2257336cca9eSBenno Rice 2258336cca9eSBenno Rice v |= GEM_MAC_RX_HASH_FILTER; 2259336cca9eSBenno Rice 22602a79fd39SMarius Strobl /* Now load the hash table into the chip (if we are using it). */ 22612a79fd39SMarius Strobl for (i = 0; i < 16; i++) 2262bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, 2263336cca9eSBenno Rice GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 2264336cca9eSBenno Rice hash[i]); 226542c1b001SThomas Moestl 226642c1b001SThomas Moestl chipit: 2267*c0e3e9d4SMarius Strobl sc->sc_mac_rxcfg = v; 2268*c0e3e9d4SMarius Strobl if (enable) 2269*c0e3e9d4SMarius Strobl v |= GEM_MAC_RX_ENABLE; 2270bd3d9826SMarius Strobl GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 227142c1b001SThomas Moestl } 2272