1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast 32 * Ethernet driver 33 */ 34 35 /* 36 * Number of transmit control blocks. This determines the number 37 * of transmit buffers that can be chained in the CB list. 38 * This must be a power of two. 39 */ 40 #define FXP_NTXCB 128 41 42 /* 43 * Size of the TxCB list. 44 */ 45 #define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx)) 46 47 /* 48 * Macro to obtain the DMA address of a virtual address in the 49 * TxCB list based on the base DMA address of the TxCB list. 50 */ 51 #define FXP_TXCB_DMA_ADDR(sc, addr) \ 52 (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \ 53 (uintptr_t)sc->fxp_desc.cbl_list) 54 55 /* 56 * Number of completed TX commands at which point an interrupt 57 * will be generated to garbage collect the attached buffers. 58 * Must be at least one less than FXP_NTXCB, and should be 59 * enough less so that the transmitter doesn't becomes idle 60 * during the buffer rundown (which would reduce performance). 61 */ 62 #define FXP_CXINT_THRESH 120 63 64 /* 65 * TxCB list index mask. This is used to do list wrap-around. 66 */ 67 #define FXP_TXCB_MASK (FXP_NTXCB - 1) 68 69 /* 70 * Number of receive frame area buffers. These are large so chose 71 * wisely. 72 */ 73 #ifdef DEVICE_POLLING 74 #define FXP_NRFABUFS 192 75 #else 76 #define FXP_NRFABUFS 64 77 #endif 78 79 /* 80 * Maximum number of seconds that the receiver can be idle before we 81 * assume it's dead and attempt to reset it by reprogramming the 82 * multicast filter. This is part of a work-around for a bug in the 83 * NIC. See fxp_stats_update(). 84 */ 85 #define FXP_MAX_RX_IDLE 15 86 87 /* 88 * Default maximum time, in microseconds, that an interrupt may be delayed 89 * in an attempt to coalesce interrupts. This is only effective if the Intel 90 * microcode is loaded, and may be changed via either loader tunables or 91 * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. 92 */ 93 #define TUNABLE_INT_DELAY 1000 94 95 /* 96 * Default number of packets that will be bundled, before an interrupt is 97 * generated. This is only effective if the Intel microcode is loaded, and 98 * may be changed via either loader tunables or sysctl. This may not be 99 * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD 100 * entry in rcvbundl.h. 101 */ 102 #define TUNABLE_BUNDLE_MAX 6 103 104 #if __FreeBSD_version < 500000 105 #define FXP_LOCK(_sc) 106 #define FXP_UNLOCK(_sc) 107 #define INTR_MPSAFE 0 108 #define mtx_owned(a) 0 109 #define mtx_assert(a, b) 110 #define mtx_init(a, b, c, d) 111 #define mtx_destroy(a) 112 struct mtx { int dummy; }; 113 #else 114 #define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 115 #define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 116 #endif 117 118 /* 119 * Structures to handle TX and RX descriptors. 120 */ 121 struct fxp_rx { 122 struct fxp_rx *rx_next; 123 struct mbuf *rx_mbuf; 124 bus_dmamap_t rx_map; 125 u_int32_t rx_addr; 126 }; 127 128 struct fxp_tx { 129 struct fxp_tx *tx_next; 130 struct fxp_cb_tx *tx_cb; 131 struct mbuf *tx_mbuf; 132 bus_dmamap_t tx_map; 133 }; 134 135 struct fxp_desc_list { 136 struct fxp_rx rx_list[FXP_NRFABUFS]; 137 struct fxp_tx tx_list[FXP_NTXCB]; 138 struct fxp_tx mcs_tx; 139 struct fxp_rx *rx_head; 140 struct fxp_rx *rx_tail; 141 struct fxp_tx *tx_first; 142 struct fxp_tx *tx_last; 143 struct fxp_rfa *rfa_list; 144 struct fxp_cb_tx *cbl_list; 145 u_int32_t cbl_addr; 146 bus_dma_tag_t rx_tag; 147 }; 148 149 /* 150 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 151 * for functional grouping. 152 */ 153 struct fxp_softc { 154 struct arpcom arpcom; /* per-interface network data */ 155 struct resource *mem; /* resource descriptor for registers */ 156 int rtp; /* register resource type */ 157 int rgd; /* register descriptor in use */ 158 struct resource *irq; /* resource descriptor for interrupt */ 159 void *ih; /* interrupt handler cookie */ 160 struct mtx sc_mtx; 161 bus_space_tag_t sc_st; /* bus space tag */ 162 bus_space_handle_t sc_sh; /* bus space handle */ 163 bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */ 164 bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */ 165 bus_dmamap_t fxp_smap; /* bus DMA map for stats */ 166 bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */ 167 bus_dmamap_t cbl_map; /* DMA map for the TxCB list */ 168 bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */ 169 bus_dmamap_t mcs_map; /* DMA map for the multicast setup */ 170 bus_dmamap_t spare_map; /* spare DMA map */ 171 struct fxp_desc_list fxp_desc; /* descriptors management struct */ 172 int tx_queued; /* # of active TxCB's */ 173 int need_mcsetup; /* multicast filter needs programming */ 174 struct fxp_stats *fxp_stats; /* Pointer to interface stats */ 175 u_int32_t stats_addr; /* DMA address of the stats structure */ 176 int rx_idle_secs; /* # of seconds RX has been idle */ 177 struct callout stat_ch; /* stat callout */ 178 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ 179 u_int32_t mcs_addr; /* DMA address of the multicast cmd */ 180 struct ifmedia sc_media; /* media information */ 181 device_t miibus; 182 device_t dev; 183 struct sysctl_ctx_list sysctl_ctx; 184 struct sysctl_oid *sysctl_tree; 185 int tunable_int_delay; /* interrupt delay value for ucode */ 186 int tunable_bundle_max; /* max # frames per interrupt (ucode) */ 187 int eeprom_size; /* size of serial EEPROM */ 188 int suspended; /* 0 = normal 1 = suspended or dead */ 189 int cu_resume_bug; 190 int revision; 191 int flags; 192 u_int32_t saved_maps[5]; /* pci data */ 193 u_int32_t saved_biosaddr; 194 u_int8_t saved_intline; 195 u_int8_t saved_cachelnsz; 196 u_int8_t saved_lattimer; 197 u_int8_t rfa_size; 198 u_int32_t tx_cmd; 199 }; 200 201 #define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ 202 #define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ 203 #define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ 204 #define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ 205 #define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ 206 #define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ 207 #define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ 208 #define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ 209 #define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ 210 #define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */ 211 #define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */ 212 213 /* Macros to ease CSR access. */ 214 #define CSR_READ_1(sc, reg) \ 215 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 216 #define CSR_READ_2(sc, reg) \ 217 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 218 #define CSR_READ_4(sc, reg) \ 219 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 220 #define CSR_WRITE_1(sc, reg, val) \ 221 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 222 #define CSR_WRITE_2(sc, reg, val) \ 223 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 224 #define CSR_WRITE_4(sc, reg, val) \ 225 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 226 227 #define sc_if arpcom.ac_if 228 229 #define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit 230