1 /* 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #define FXP_VENDORID_INTEL 0x8086 32 33 #define FXP_PCI_MMBA 0x10 34 #define FXP_PCI_IOBA 0x14 35 36 /* 37 * Control/status registers. 38 */ 39 #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 40 #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 41 #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 42 #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 43 #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 44 #define FXP_CSR_PORT 8 /* port (4 bytes) */ 45 #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 46 #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 47 #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48 #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 49 #define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ 50 51 /* 52 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 53 * 54 * volatile u_int8_t :2, 55 * scb_rus:4, 56 * scb_cus:2; 57 */ 58 59 #define FXP_PORT_SOFTWARE_RESET 0 60 #define FXP_PORT_SELFTEST 1 61 #define FXP_PORT_SELECTIVE_RESET 2 62 #define FXP_PORT_DUMP 3 63 64 #define FXP_SCB_RUS_IDLE 0 65 #define FXP_SCB_RUS_SUSPENDED 1 66 #define FXP_SCB_RUS_NORESOURCES 2 67 #define FXP_SCB_RUS_READY 4 68 #define FXP_SCB_RUS_SUSP_NORBDS 9 69 #define FXP_SCB_RUS_NORES_NORBDS 10 70 #define FXP_SCB_RUS_READY_NORBDS 12 71 72 #define FXP_SCB_CUS_IDLE 0 73 #define FXP_SCB_CUS_SUSPENDED 1 74 #define FXP_SCB_CUS_ACTIVE 2 75 76 #define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 77 #define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 78 #define FXP_SCB_INTMASK_FCP 0x04 79 #define FXP_SCB_INTMASK_ER 0x08 80 #define FXP_SCB_INTMASK_RNR 0x10 81 #define FXP_SCB_INTMASK_CNA 0x20 82 #define FXP_SCB_INTMASK_FR 0x40 83 #define FXP_SCB_INTMASK_CXTNO 0x80 84 85 #define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 86 #define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 87 #define FXP_SCB_STATACK_SWI 0x04 88 #define FXP_SCB_STATACK_MDI 0x08 89 #define FXP_SCB_STATACK_RNR 0x10 90 #define FXP_SCB_STATACK_CNA 0x20 91 #define FXP_SCB_STATACK_FR 0x40 92 #define FXP_SCB_STATACK_CXTNO 0x80 93 94 #define FXP_SCB_COMMAND_CU_NOP 0x00 95 #define FXP_SCB_COMMAND_CU_START 0x10 96 #define FXP_SCB_COMMAND_CU_RESUME 0x20 97 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 98 #define FXP_SCB_COMMAND_CU_DUMP 0x50 99 #define FXP_SCB_COMMAND_CU_BASE 0x60 100 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 101 102 #define FXP_SCB_COMMAND_RU_NOP 0 103 #define FXP_SCB_COMMAND_RU_START 1 104 #define FXP_SCB_COMMAND_RU_RESUME 2 105 #define FXP_SCB_COMMAND_RU_ABORT 4 106 #define FXP_SCB_COMMAND_RU_LOADHDS 5 107 #define FXP_SCB_COMMAND_RU_BASE 6 108 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 109 110 /* 111 * Command block definitions 112 */ 113 struct fxp_cb_nop { 114 void *fill[2]; 115 volatile u_int16_t cb_status; 116 volatile u_int16_t cb_command; 117 volatile u_int32_t link_addr; 118 }; 119 struct fxp_cb_ias { 120 void *fill[2]; 121 volatile u_int16_t cb_status; 122 volatile u_int16_t cb_command; 123 volatile u_int32_t link_addr; 124 volatile u_int8_t macaddr[6]; 125 }; 126 /* I hate bit-fields :-( */ 127 struct fxp_cb_config { 128 void *fill[2]; 129 volatile u_int16_t cb_status; 130 volatile u_int16_t cb_command; 131 volatile u_int32_t link_addr; 132 volatile u_int byte_count:6, 133 :2; 134 volatile u_int rx_fifo_limit:4, 135 tx_fifo_limit:3, 136 :1; 137 volatile u_int8_t adaptive_ifs; 138 volatile u_int mwi_enable:1, /* 8,9 */ 139 type_enable:1, /* 8,9 */ 140 read_align_en:1, /* 8,9 */ 141 end_wr_on_cl:1, /* 8,9 */ 142 :4; 143 volatile u_int rx_dma_bytecount:7, 144 :1; 145 volatile u_int tx_dma_bytecount:7, 146 dma_mbce:1; 147 volatile u_int late_scb:1, /* 7 */ 148 direct_dma_dis:1, /* 8,9 */ 149 tno_int_or_tco_en:1, /* 7,9 */ 150 ci_int:1, 151 ext_txcb_dis:1, /* 8,9 */ 152 ext_stats_dis:1, /* 8,9 */ 153 keep_overrun_rx:1, 154 save_bf:1; 155 volatile u_int disc_short_rx:1, 156 underrun_retry:2, 157 :2, 158 ext_rfa:1, /* 550 */ 159 two_frames:1, /* 8,9 */ 160 dyn_tbd:1; /* 8,9 */ 161 volatile u_int mediatype:1, /* 7 */ 162 :6, 163 csma_dis:1; /* 8,9 */ 164 volatile u_int tcp_udp_cksum:1, /* 9 */ 165 :3, 166 vlan_tco:1, /* 8,9 */ 167 link_wake_en:1, /* 8,9 */ 168 arp_wake_en:1, /* 8 */ 169 mc_wake_en:1; /* 8 */ 170 volatile u_int :3, 171 nsai:1, 172 preamble_length:2, 173 loopback:2; 174 volatile u_int linear_priority:3, /* 7 */ 175 :5; 176 volatile u_int linear_pri_mode:1, /* 7 */ 177 :3, 178 interfrm_spacing:4; 179 volatile u_int :8; 180 volatile u_int :8; 181 volatile u_int promiscuous:1, 182 bcast_disable:1, 183 wait_after_win:1, /* 8,9 */ 184 :1, 185 ignore_ul:1, /* 8,9 */ 186 crc16_en:1, /* 9 */ 187 :1, 188 crscdt:1; 189 volatile u_int fc_delay_lsb:8; /* 8,9 */ 190 volatile u_int fc_delay_msb:8; /* 8,9 */ 191 volatile u_int stripping:1, 192 padding:1, 193 rcv_crc_xfer:1, 194 long_rx_en:1, /* 8,9 */ 195 pri_fc_thresh:3, /* 8,9 */ 196 :1; 197 volatile u_int ia_wake_en:1, /* 8 */ 198 magic_pkt_dis:1, /* 8,9,!9ER */ 199 tx_fc_dis:1, /* 8,9 */ 200 rx_fc_restop:1, /* 8,9 */ 201 rx_fc_restart:1, /* 8,9 */ 202 fc_filter:1, /* 8,9 */ 203 force_fdx:1, 204 fdx_pin_en:1; 205 volatile u_int :5, 206 pri_fc_loc:1, /* 8,9 */ 207 multi_ia:1, 208 :1; 209 volatile u_int :3, 210 mc_all:1, 211 :4; 212 volatile u_int8_t gamla_rx:1; /* 550 */ 213 volatile u_int8_t pad[9]; /* 550 */ 214 }; 215 216 #define MAXMCADDR 80 217 struct fxp_cb_mcs { 218 struct fxp_cb_tx *next; 219 struct mbuf *mb_head; 220 volatile u_int16_t cb_status; 221 volatile u_int16_t cb_command; 222 volatile u_int32_t link_addr; 223 volatile u_int16_t mc_cnt; 224 volatile u_int8_t mc_addr[MAXMCADDR][6]; 225 }; 226 227 #define MAXUCODESIZE 192 228 struct fxp_cb_ucode { 229 void *fill[2]; 230 u_int16_t cb_status; 231 u_int16_t cb_command; 232 u_int32_t link_addr; 233 u_int32_t ucode[MAXUCODESIZE]; 234 }; 235 236 /* 237 * Number of DMA segments in a TxCB. Note that this is carefully 238 * chosen to make the total struct size an even power of two. It's 239 * critical that no TxCB be split across a page boundry since 240 * no attempt is made to allocate physically contiguous memory. 241 */ 242 #define FXP_TXCB_FIXED 16 /* cb_status .. tbd_number */ 243 #define FXP_NTXSEG ((256 - (sizeof(void *) * 2) - FXP_TXCB_FIXED) / 8) 244 245 struct fxp_tbd { 246 volatile u_int32_t tb_addr; 247 volatile u_int32_t tb_size; 248 }; 249 250 struct fxp_ipcb { 251 /* 252 * The following fields are valid only when 253 * using the IPCB command block for TX checksum offload 254 * (and TCP large send, VLANs, and (I think) IPsec). To use 255 * them, you must enable extended TxCBs (available only 256 * on the 82559 and later) and use the IPCBXMIT command. 257 * Note that Intel defines the IPCB to be 32 bytes long, 258 * the last 8 bytes of which comprise the first entry 259 * in the TBD array (see note below). This means we only 260 * have to define 8 extra bytes here. 261 */ 262 volatile u_int16_t ipcb_schedule_low; 263 volatile u_int8_t ipcb_ip_schedule; 264 volatile u_int8_t ipcb_ip_activation_high; 265 volatile u_int16_t ipcb_vlan_id; 266 volatile u_int8_t ipcb_ip_header_offset; 267 volatile u_int8_t ipcb_tcp_header_offset; 268 }; 269 270 struct fxp_cb_tx { 271 struct fxp_cb_tx *next; 272 struct mbuf *mb_head; 273 volatile u_int16_t cb_status; 274 volatile u_int16_t cb_command; 275 volatile u_int32_t link_addr; 276 volatile u_int32_t tbd_array_addr; 277 volatile u_int16_t byte_count; 278 volatile u_int8_t tx_threshold; 279 volatile u_int8_t tbd_number; 280 281 /* 282 * The following structure isn't actually part of the TxCB, 283 * unless the extended TxCB feature is being used. In this 284 * case, the first two elements of the structure below are 285 * fetched along with the TxCB. 286 */ 287 union { 288 volatile struct fxp_ipcb; 289 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 290 } tx_cb_u; 291 }; 292 293 #define tbd tx_cb_u.tbd 294 #define ipcb_schedule_low tx_cb_u.ipcb_schedule_low 295 #define ipcb_ip_schedule tx_cb_u.ipcb_ip_schedule 296 #define ipcb_ip_activation_high tx_cb_u.ipcb_ip_activation_high 297 #define ipcb_vlan_id tx_cb_u.ipcb_vlan_id 298 #define ipcb_ip_header_offset tx_cb_u.ipcb_ip_header_offset 299 #define ipcb_tcp_header_offset tx_cb_u.ipcb_tcp_header_offset 300 301 /* 302 * IPCB field definitions 303 */ 304 #define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10 305 #define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20 306 #define FXP_IPCB_TCP_PACKET 0x40 307 #define FXP_IPCB_LARGESEND_ENABLE 0x80 308 #define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01 309 #define FXP_IPCB_INSERTVLAN_ENABLE 0x02 310 311 /* 312 * Control Block (CB) definitions 313 */ 314 315 /* status */ 316 #define FXP_CB_STATUS_OK 0x2000 317 #define FXP_CB_STATUS_C 0x8000 318 /* commands */ 319 #define FXP_CB_COMMAND_NOP 0x0 320 #define FXP_CB_COMMAND_IAS 0x1 321 #define FXP_CB_COMMAND_CONFIG 0x2 322 #define FXP_CB_COMMAND_MCAS 0x3 323 #define FXP_CB_COMMAND_XMIT 0x4 324 #define FXP_CB_COMMAND_UCODE 0x5 325 #define FXP_CB_COMMAND_DUMP 0x6 326 #define FXP_CB_COMMAND_DIAG 0x7 327 #define FXP_CB_COMMAND_LOADFILT 0x8 328 #define FXP_CB_COMMAND_IPCBXMIT 0x9 329 330 /* command flags */ 331 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 332 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 333 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 334 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 335 336 /* 337 * RFA definitions 338 */ 339 340 struct fxp_rfa { 341 volatile u_int16_t rfa_status; 342 volatile u_int16_t rfa_control; 343 volatile u_int8_t link_addr[4]; 344 volatile u_int8_t rbd_addr[4]; 345 volatile u_int16_t actual_size; 346 volatile u_int16_t size; 347 348 /* 349 * The following fields are only available when using 350 * extended receive mode on an 82550/82551 chipset. 351 */ 352 volatile u_int16_t rfax_vlan_id; 353 volatile u_int8_t rfax_rx_parser_sts; 354 volatile u_int8_t rfax_rsvd0; 355 volatile u_int16_t rfax_security_sts; 356 volatile u_int8_t rfax_csum_sts; 357 volatile u_int8_t rfax_zerocopy_sts; 358 volatile u_int8_t rfax_pad[8]; 359 }; 360 #define FXP_RFAX_LEN 16 361 362 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 363 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 364 #define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 365 #define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 366 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 367 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 368 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 369 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 370 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 371 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 372 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 373 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 374 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 375 #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 376 #define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 377 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 378 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 379 380 /* Bits in the 'csum_sts' byte */ 381 #define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10 382 #define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20 383 #define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01 384 #define FXP_RFDX_CS_IP_CSUM_VALID 0x02 385 386 /* Bits in the 'packet parser' byte */ 387 #define FXP_RFDX_P_PARSE_BIT 0x08 388 #define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03 389 #define FXP_RFDX_P_TCP_PACKET 0x00 390 #define FXP_RFDX_P_UDP_PACKET 0x01 391 #define FXP_RFDX_P_IP_PACKET 0x03 392 393 /* 394 * Statistics dump area definitions 395 */ 396 struct fxp_stats { 397 volatile u_int32_t tx_good; 398 volatile u_int32_t tx_maxcols; 399 volatile u_int32_t tx_latecols; 400 volatile u_int32_t tx_underruns; 401 volatile u_int32_t tx_lostcrs; 402 volatile u_int32_t tx_deffered; 403 volatile u_int32_t tx_single_collisions; 404 volatile u_int32_t tx_multiple_collisions; 405 volatile u_int32_t tx_total_collisions; 406 volatile u_int32_t rx_good; 407 volatile u_int32_t rx_crc_errors; 408 volatile u_int32_t rx_alignment_errors; 409 volatile u_int32_t rx_rnr_errors; 410 volatile u_int32_t rx_overrun_errors; 411 volatile u_int32_t rx_cdt_errors; 412 volatile u_int32_t rx_shortframes; 413 volatile u_int32_t completion_status; 414 }; 415 #define FXP_STATS_DUMP_COMPLETE 0xa005 416 #define FXP_STATS_DR_COMPLETE 0xa007 417 418 /* 419 * Serial EEPROM control register bits 420 */ 421 #define FXP_EEPROM_EESK 0x01 /* shift clock */ 422 #define FXP_EEPROM_EECS 0x02 /* chip select */ 423 #define FXP_EEPROM_EEDI 0x04 /* data in */ 424 #define FXP_EEPROM_EEDO 0x08 /* data out */ 425 426 /* 427 * Serial EEPROM opcodes, including start bit 428 */ 429 #define FXP_EEPROM_OPC_ERASE 0x4 430 #define FXP_EEPROM_OPC_WRITE 0x5 431 #define FXP_EEPROM_OPC_READ 0x6 432 433 /* 434 * Management Data Interface opcodes 435 */ 436 #define FXP_MDI_WRITE 0x1 437 #define FXP_MDI_READ 0x2 438 439 /* 440 * PHY device types 441 */ 442 #define FXP_PHY_DEVICE_MASK 0x3f00 443 #define FXP_PHY_SERIAL_ONLY 0x8000 444 #define FXP_PHY_NONE 0 445 #define FXP_PHY_82553A 1 446 #define FXP_PHY_82553C 2 447 #define FXP_PHY_82503 3 448 #define FXP_PHY_DP83840 4 449 #define FXP_PHY_80C240 5 450 #define FXP_PHY_80C24 6 451 #define FXP_PHY_82555 7 452 #define FXP_PHY_DP83840A 10 453 #define FXP_PHY_82555B 11 454 455 /* 456 * Chip revision values. 457 */ 458 #define FXP_REV_82557 1 /* catchall 82557 chip type */ 459 #define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 460 #define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 461 #define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 462 #define FXP_REV_82559S_A 9 /* 82559S A stepping */ 463 #define FXP_REV_82550 12 464 #define FXP_REV_82550_C 13 /* 82550 C stepping */ 465