1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #define FXP_VENDORID_INTEL 0x8086 31 #define FXP_DEVICEID_i82557 0x1229 /* 82557 - 82559 "classic" */ 32 #define FXP_DEVICEID_i82559 0x1030 /* New 82559 device id.. */ 33 #define FXP_DEVICEID_i82559ER 0x1209 /* 82559 for embedded applications */ 34 #define FXP_DEVICEID_i82562 0x2449 /* 82562 PLC devices */ 35 36 #define FXP_PCI_MMBA 0x10 37 #define FXP_PCI_IOBA 0x14 38 39 /* 40 * Control/status registers. 41 */ 42 #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 43 #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 44 #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 45 #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 46 #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 47 #define FXP_CSR_PORT 8 /* port (4 bytes) */ 48 #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 49 #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 50 #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 51 52 /* 53 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 54 * 55 * volatile u_int8_t :2, 56 * scb_rus:4, 57 * scb_cus:2; 58 */ 59 60 #define FXP_PORT_SOFTWARE_RESET 0 61 #define FXP_PORT_SELFTEST 1 62 #define FXP_PORT_SELECTIVE_RESET 2 63 #define FXP_PORT_DUMP 3 64 65 #define FXP_SCB_RUS_IDLE 0 66 #define FXP_SCB_RUS_SUSPENDED 1 67 #define FXP_SCB_RUS_NORESOURCES 2 68 #define FXP_SCB_RUS_READY 4 69 #define FXP_SCB_RUS_SUSP_NORBDS 9 70 #define FXP_SCB_RUS_NORES_NORBDS 10 71 #define FXP_SCB_RUS_READY_NORBDS 12 72 73 #define FXP_SCB_CUS_IDLE 0 74 #define FXP_SCB_CUS_SUSPENDED 1 75 #define FXP_SCB_CUS_ACTIVE 2 76 77 #define FXP_SCB_STATACK_SWI 0x04 78 #define FXP_SCB_STATACK_MDI 0x08 79 #define FXP_SCB_STATACK_RNR 0x10 80 #define FXP_SCB_STATACK_CNA 0x20 81 #define FXP_SCB_STATACK_FR 0x40 82 #define FXP_SCB_STATACK_CXTNO 0x80 83 84 #define FXP_SCB_COMMAND_CU_NOP 0x00 85 #define FXP_SCB_COMMAND_CU_START 0x10 86 #define FXP_SCB_COMMAND_CU_RESUME 0x20 87 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 88 #define FXP_SCB_COMMAND_CU_DUMP 0x50 89 #define FXP_SCB_COMMAND_CU_BASE 0x60 90 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 91 92 #define FXP_SCB_COMMAND_RU_NOP 0 93 #define FXP_SCB_COMMAND_RU_START 1 94 #define FXP_SCB_COMMAND_RU_RESUME 2 95 #define FXP_SCB_COMMAND_RU_ABORT 4 96 #define FXP_SCB_COMMAND_RU_LOADHDS 5 97 #define FXP_SCB_COMMAND_RU_BASE 6 98 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 99 100 /* 101 * Command block definitions 102 */ 103 struct fxp_cb_nop { 104 void *fill[2]; 105 volatile u_int16_t cb_status; 106 volatile u_int16_t cb_command; 107 volatile u_int32_t link_addr; 108 }; 109 struct fxp_cb_ias { 110 void *fill[2]; 111 volatile u_int16_t cb_status; 112 volatile u_int16_t cb_command; 113 volatile u_int32_t link_addr; 114 volatile u_int8_t macaddr[6]; 115 }; 116 /* I hate bit-fields :-( */ 117 struct fxp_cb_config { 118 void *fill[2]; 119 volatile u_int16_t cb_status; 120 volatile u_int16_t cb_command; 121 volatile u_int32_t link_addr; 122 volatile u_int byte_count:6, 123 :2; 124 volatile u_int rx_fifo_limit:4, 125 tx_fifo_limit:3, 126 :1; 127 volatile u_int8_t adaptive_ifs; 128 volatile u_int :8; 129 volatile u_int rx_dma_bytecount:7, 130 :1; 131 volatile u_int tx_dma_bytecount:7, 132 dma_bce:1; 133 volatile u_int late_scb:1, 134 :1, 135 tno_int:1, 136 ci_int:1, 137 :3, 138 save_bf:1; 139 volatile u_int disc_short_rx:1, 140 underrun_retry:2, 141 :5; 142 volatile u_int mediatype:1, 143 :7; 144 volatile u_int :8; 145 volatile u_int :3, 146 nsai:1, 147 preamble_length:2, 148 loopback:2; 149 volatile u_int linear_priority:3, 150 :5; 151 volatile u_int linear_pri_mode:1, 152 :3, 153 interfrm_spacing:4; 154 volatile u_int :8; 155 volatile u_int :8; 156 volatile u_int promiscuous:1, 157 bcast_disable:1, 158 :5, 159 crscdt:1; 160 volatile u_int :8; 161 volatile u_int :8; 162 volatile u_int stripping:1, 163 padding:1, 164 rcv_crc_xfer:1, 165 :5; 166 volatile u_int :6, 167 force_fdx:1, 168 fdx_pin_en:1; 169 volatile u_int :6, 170 multi_ia:1, 171 :1; 172 volatile u_int :3, 173 mc_all:1, 174 :4; 175 }; 176 177 #define MAXMCADDR 80 178 struct fxp_cb_mcs { 179 struct fxp_cb_tx *next; 180 struct mbuf *mb_head; 181 volatile u_int16_t cb_status; 182 volatile u_int16_t cb_command; 183 volatile u_int32_t link_addr; 184 volatile u_int16_t mc_cnt; 185 volatile u_int8_t mc_addr[MAXMCADDR][6]; 186 }; 187 188 /* 189 * Number of DMA segments in a TxCB. Note that this is carefully 190 * chosen to make the total struct size an even power of two. It's 191 * critical that no TxCB be split across a page boundry since 192 * no attempt is made to allocate physically contiguous memory. 193 * 194 */ 195 #ifdef __alpha__ /* XXX - should be conditional on pointer size */ 196 #define FXP_NTXSEG 28 197 #else 198 #define FXP_NTXSEG 29 199 #endif 200 201 struct fxp_tbd { 202 volatile u_int32_t tb_addr; 203 volatile u_int32_t tb_size; 204 }; 205 struct fxp_cb_tx { 206 struct fxp_cb_tx *next; 207 struct mbuf *mb_head; 208 volatile u_int16_t cb_status; 209 volatile u_int16_t cb_command; 210 volatile u_int32_t link_addr; 211 volatile u_int32_t tbd_array_addr; 212 volatile u_int16_t byte_count; 213 volatile u_int8_t tx_threshold; 214 volatile u_int8_t tbd_number; 215 /* 216 * The following isn't actually part of the TxCB. 217 */ 218 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 219 }; 220 221 /* 222 * Control Block (CB) definitions 223 */ 224 225 /* status */ 226 #define FXP_CB_STATUS_OK 0x2000 227 #define FXP_CB_STATUS_C 0x8000 228 /* commands */ 229 #define FXP_CB_COMMAND_NOP 0x0 230 #define FXP_CB_COMMAND_IAS 0x1 231 #define FXP_CB_COMMAND_CONFIG 0x2 232 #define FXP_CB_COMMAND_MCAS 0x3 233 #define FXP_CB_COMMAND_XMIT 0x4 234 #define FXP_CB_COMMAND_RESRV 0x5 235 #define FXP_CB_COMMAND_DUMP 0x6 236 #define FXP_CB_COMMAND_DIAG 0x7 237 /* command flags */ 238 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 239 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 240 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 241 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 242 243 /* 244 * RFA definitions 245 */ 246 247 struct fxp_rfa { 248 volatile u_int16_t rfa_status; 249 volatile u_int16_t rfa_control; 250 volatile u_int8_t link_addr[4]; 251 volatile u_int8_t rbd_addr[4]; 252 volatile u_int16_t actual_size; 253 volatile u_int16_t size; 254 }; 255 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 256 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 257 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 258 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 259 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 260 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 261 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 262 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 263 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 264 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 265 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 266 #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 267 #define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 268 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 269 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 270 271 /* 272 * Statistics dump area definitions 273 */ 274 struct fxp_stats { 275 volatile u_int32_t tx_good; 276 volatile u_int32_t tx_maxcols; 277 volatile u_int32_t tx_latecols; 278 volatile u_int32_t tx_underruns; 279 volatile u_int32_t tx_lostcrs; 280 volatile u_int32_t tx_deffered; 281 volatile u_int32_t tx_single_collisions; 282 volatile u_int32_t tx_multiple_collisions; 283 volatile u_int32_t tx_total_collisions; 284 volatile u_int32_t rx_good; 285 volatile u_int32_t rx_crc_errors; 286 volatile u_int32_t rx_alignment_errors; 287 volatile u_int32_t rx_rnr_errors; 288 volatile u_int32_t rx_overrun_errors; 289 volatile u_int32_t rx_cdt_errors; 290 volatile u_int32_t rx_shortframes; 291 volatile u_int32_t completion_status; 292 }; 293 #define FXP_STATS_DUMP_COMPLETE 0xa005 294 #define FXP_STATS_DR_COMPLETE 0xa007 295 296 /* 297 * Serial EEPROM control register bits 298 */ 299 /* shift clock */ 300 #define FXP_EEPROM_EESK 0x01 301 /* chip select */ 302 #define FXP_EEPROM_EECS 0x02 303 /* data in */ 304 #define FXP_EEPROM_EEDI 0x04 305 /* data out */ 306 #define FXP_EEPROM_EEDO 0x08 307 308 /* 309 * Serial EEPROM opcodes, including start bit 310 */ 311 #define FXP_EEPROM_OPC_ERASE 0x4 312 #define FXP_EEPROM_OPC_WRITE 0x5 313 #define FXP_EEPROM_OPC_READ 0x6 314 315 /* 316 * Management Data Interface opcodes 317 */ 318 #define FXP_MDI_WRITE 0x1 319 #define FXP_MDI_READ 0x2 320 321 /* 322 * PHY device types 323 */ 324 #define FXP_PHY_NONE 0 325 #define FXP_PHY_82553A 1 326 #define FXP_PHY_82553C 2 327 #define FXP_PHY_82503 3 328 #define FXP_PHY_DP83840 4 329 #define FXP_PHY_80C240 5 330 #define FXP_PHY_80C24 6 331 #define FXP_PHY_82555 7 332 #define FXP_PHY_DP83840A 10 333 #define FXP_PHY_82555B 11 334 335 /* 336 * PHY BMCR Basic Mode Control Register 337 * Should probably be in i82555.h or dp83840.h (Intel/National names). 338 * (Called "Management Data Interface Control Reg" in some Intel data books). 339 * (*) indicates bit ignored in auto negotiation mode. 340 */ 341 #define FXP_PHY_BMCR 0x0 342 #define FXP_PHY_BMCR_COLTEST 0x0080 /* not on Intel parts */ 343 #define FXP_PHY_BMCR_FULLDUPLEX 0x0100 /* 1 = Fullduplex (*) */ 344 #define FXP_PHY_BMCR_RESTART_NEG 0x0200 /* ==> 1 to restart autoneg */ 345 #define FXP_PHY_BMCR_ISOLATE 0x0400 /* not on Intel parts */ 346 #define FXP_PHY_BMCR_POWERDOWN 0x0800 /* 1 = low power mode */ 347 #define FXP_PHY_BMCR_AUTOEN 0x1000 /* 1 = for auto mode */ 348 #define FXP_PHY_BMCR_SPEED_100M 0x2000 /* 1 = for 100Mb/sec (*) */ 349 #define FXP_PHY_BMCR_LOOPBACK 0x4000 /* 1 = loopback at the PHY */ 350 #define FXP_PHY_BMCR_RESET 0x8000 /* ==> 1 sets to defaults */ 351 352 /* 353 * Basic Mode Status Register (National name) 354 * Management Data Interface Status reg. (Intel name) 355 * in both Intel and National parts. 356 */ 357 #define FXP_PHY_STS 0x1 358 #define FXP_PHY_STS_EXND 0x0001 /* Extended regs enabled */ 359 #define FXP_PHY_STS_JABR 0x0002 /* Jabber detected */ 360 #define FXP_PHY_STS_LINK_STS 0x0004 /* Link valid */ 361 #define FXP_PHY_STS_CAN_AUTO 0x0008 /* Auto detection available */ 362 #define FXP_PHY_STS_REMT_FAULT 0x0010 /* remote fault detected */ 363 #define FXP_PHY_STS_AUTO_DONE 0x0020 /* auto negotiation completed */ 364 #define FXP_PHY_STS_MGMT_PREAMBLE 0x0040 /* real complicated */ 365 #define FXP_PHY_STS_10HDX_OK 0x0800 /* can do 10Mb HDX */ 366 #define FXP_PHY_STS_10FDX_OK 0x1000 /* can do 10Mb FDX */ 367 #define FXP_PHY_STS_100HDX_OK 0x2000 /* can do 100Mb HDX */ 368 #define FXP_PHY_STS_100FDX_OK 0x4000 /* can do 100Mb FDX */ 369 #define FXP_PHY_STS_100T4_OK 0x8000 /* can do 100bT4 -not Intel */ 370 371 /* 372 * More Phy regs 373 */ 374 #define FXP_PHY_ID1 0x2 375 #define FXP_PHY_ID2 0x3 376 377 /* 378 * MDI Auto negotiation advertisement register. 379 * What we advertise we can do.. 380 * The same bits are used to indicate the response too. 381 */ 382 #define FXP_PHY_ADVRT 0x4 383 #define FXP_PHY_RMT_ADVRT 0x5 /* what the other end said */ 384 #define FXP_PHY_ADVRT_SELECT 0x001F /* real complicated */ 385 #define FXP_PHY_ADVRT_TECH_AVAIL 0x1FE0 /* can do 10Mb HDX */ 386 #define FXP_PHY_ADVRT_RMT_FAULT 0x2000 /* can do 10Mb FDX */ 387 #define FXP_PHY_ADVRT_ACK 0x4000 /* Acked */ 388 #define FXP_PHY_ADVRT_NXT_PAGE 0x8000 /* can do 100Mb FDX */ 389 390 /* 391 * Phy Unit Status and Control Register (another one) 392 * This is not in the National part! 393 */ 394 #define FXP_PHY_USC 0x10 395 #define FXP_PHY_USC_DUPLEX 0x0001 /* in FDX mode */ 396 #define FXP_PHY_USC_SPEED 0x0002 /* 1 = in 100Mb mode */ 397 #define FXP_PHY_USC_POLARITY 0x0100 /* 1 = reverse polarity */ 398 #define FXP_PHY_USC_10_PWRDOWN 0x0200 /* 10Mb PHY powered down */ 399 #define FXP_PHY_USC_100_PWRDOWN 0x0400 /* 100Mb PHY powered down */ 400 #define FXP_PHY_USC_INSYNC 0x0800 /* 100Mb PHY is in sync */ 401 #define FXP_PHY_USC_TX_FLOWCNTRL 0x1000 /* TX FC mode in use */ 402 #define FXP_PHY_USC_PHY_FLOWCNTRL 0x8000 /* PHY FC mode in use */ 403 404 405 /* 406 * DP83830 PHY, PCS Configuration Register 407 * NOT compatible with Intel parts, 408 * (where it is the 100BTX premature eof counter). 409 */ 410 #define FXP_DP83840_PCR 0x17 411 #define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always = FDX */ 412 #define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = link disconnect bypass */ 413 #define FXP_DP83840_PCR_BIT8 0x0100 414 #define FXP_DP83840_PCR_BIT10 0x0400 415 416 /* 417 * DP83830 PHY, Address/status Register 418 * NOT compatible with Intel parts, 419 * (where it is the 10BT jabber detect counter). 420 */ 421 #define FXP_DP83840_PAR 0x19 422 #define FXP_DP83840_PAR_PHYADDR 0x1F 423 #define FXP_DP83840_PAR_CON_STATUS 0x20 424 #define FXP_DP83840_PAR_SPEED_10 0x40 /* 1 == running at 10 Mb/Sec */ 425 426