xref: /freebsd/sys/dev/fxp/if_fxpreg.h (revision 0e97acdf58fe27b09c4824a474b0344daf997c5f)
1 /*-
2  * Copyright (c) 1995, David Greenman
3  * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice unmodified, this list of conditions, and the following
11  *    disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #define FXP_VENDORID_INTEL	0x8086
32 
33 #define FXP_PCI_MMBA	0x10
34 #define FXP_PCI_IOBA	0x14
35 
36 /*
37  * Control/status registers.
38  */
39 #define	FXP_CSR_SCB_RUSCUS	0	/* scb_rus/scb_cus (1 byte) */
40 #define	FXP_CSR_SCB_STATACK	1	/* scb_statack (1 byte) */
41 #define	FXP_CSR_SCB_COMMAND	2	/* scb_command (1 byte) */
42 #define	FXP_CSR_SCB_INTRCNTL	3	/* scb_intrcntl (1 byte) */
43 #define	FXP_CSR_SCB_GENERAL	4	/* scb_general (4 bytes) */
44 #define	FXP_CSR_PORT		8	/* port (4 bytes) */
45 #define	FXP_CSR_FLASHCONTROL	12	/* flash control (2 bytes) */
46 #define	FXP_CSR_EEPROMCONTROL	14	/* eeprom control (2 bytes) */
47 #define	FXP_CSR_MDICONTROL	16	/* mdi control (4 bytes) */
48 #define	FXP_CSR_FC_THRESH	0x19	/* flow control (1 byte) */
49 #define	FXP_CSR_FC_STATUS	0x1A	/* flow control status (1 byte) */
50 #define	FXP_CSR_PMDR		0x1B	/* power management driver (1 byte) */
51 #define	FXP_CSR_GENCONTROL	0x1C	/* general control (1 byte) */
52 
53 /*
54  * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
55  *
56  *	volatile uint8_t	:2,
57  *				scb_rus:4,
58  *				scb_cus:2;
59  */
60 
61 #define FXP_PORT_SOFTWARE_RESET		0
62 #define FXP_PORT_SELFTEST		1
63 #define FXP_PORT_SELECTIVE_RESET	2
64 #define FXP_PORT_DUMP			3
65 
66 #define FXP_SCB_RUS_IDLE		0
67 #define FXP_SCB_RUS_SUSPENDED		1
68 #define FXP_SCB_RUS_NORESOURCES		2
69 #define FXP_SCB_RUS_READY		4
70 #define FXP_SCB_RUS_SUSP_NORBDS		9
71 #define FXP_SCB_RUS_NORES_NORBDS	10
72 #define FXP_SCB_RUS_READY_NORBDS	12
73 
74 #define FXP_SCB_CUS_IDLE		0
75 #define FXP_SCB_CUS_SUSPENDED		1
76 #define FXP_SCB_CUS_ACTIVE		2
77 
78 #define FXP_SCB_INTR_DISABLE		0x01	/* Disable all interrupts */
79 #define FXP_SCB_INTR_SWI		0x02	/* Generate SWI */
80 #define FXP_SCB_INTMASK_FCP		0x04
81 #define FXP_SCB_INTMASK_ER		0x08
82 #define FXP_SCB_INTMASK_RNR		0x10
83 #define FXP_SCB_INTMASK_CNA		0x20
84 #define FXP_SCB_INTMASK_FR		0x40
85 #define FXP_SCB_INTMASK_CXTNO		0x80
86 
87 #define FXP_SCB_STATACK_FCP		0x01	/* Flow Control Pause */
88 #define FXP_SCB_STATACK_ER		0x02	/* Early Receive */
89 #define FXP_SCB_STATACK_SWI		0x04
90 #define FXP_SCB_STATACK_MDI		0x08
91 #define FXP_SCB_STATACK_RNR		0x10
92 #define FXP_SCB_STATACK_CNA		0x20
93 #define FXP_SCB_STATACK_FR		0x40
94 #define FXP_SCB_STATACK_CXTNO		0x80
95 
96 #define FXP_SCB_COMMAND_CU_NOP		0x00
97 #define FXP_SCB_COMMAND_CU_START	0x10
98 #define FXP_SCB_COMMAND_CU_RESUME	0x20
99 #define FXP_SCB_COMMAND_CU_DUMP_ADR	0x40
100 #define FXP_SCB_COMMAND_CU_DUMP		0x50
101 #define FXP_SCB_COMMAND_CU_BASE		0x60
102 #define FXP_SCB_COMMAND_CU_DUMPRESET	0x70
103 
104 #define FXP_SCB_COMMAND_RU_NOP		0
105 #define FXP_SCB_COMMAND_RU_START	1
106 #define FXP_SCB_COMMAND_RU_RESUME	2
107 #define FXP_SCB_COMMAND_RU_ABORT	4
108 #define FXP_SCB_COMMAND_RU_LOADHDS	5
109 #define FXP_SCB_COMMAND_RU_BASE		6
110 #define FXP_SCB_COMMAND_RU_RBDRESUME	7
111 
112 /*
113  * Command block definitions
114  */
115 struct fxp_cb_nop {
116 	uint16_t cb_status;
117 	uint16_t cb_command;
118 	uint32_t link_addr;
119 };
120 struct fxp_cb_ias {
121 	uint16_t cb_status;
122 	uint16_t cb_command;
123 	uint32_t link_addr;
124 	uint8_t macaddr[6];
125 };
126 
127 /* I hate bit-fields :-( */
128 #if BYTE_ORDER == LITTLE_ENDIAN
129 #define __FXP_BITFIELD2(a, b)			a, b
130 #define __FXP_BITFIELD3(a, b, c)		a, b, c
131 #define __FXP_BITFIELD4(a, b, c, d)		a, b, c, d
132 #define __FXP_BITFIELD5(a, b, c, d, e)		a, b, c, d, e
133 #define __FXP_BITFIELD6(a, b, c, d, e, f)	a, b, c, d, e, f
134 #define __FXP_BITFIELD7(a, b, c, d, e, f, g)	a, b, c, d, e, f, g
135 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h)	a, b, c, d, e, f, g, h
136 #else
137 #define __FXP_BITFIELD2(a, b)			b, a
138 #define __FXP_BITFIELD3(a, b, c)		c, b, a
139 #define __FXP_BITFIELD4(a, b, c, d)		d, c, b, a
140 #define __FXP_BITFIELD5(a, b, c, d, e)		e, d, c, b, a
141 #define __FXP_BITFIELD6(a, b, c, d, e, f)	f, e, d, c, b, a
142 #define __FXP_BITFIELD7(a, b, c, d, e, f, g)	g, f, e, d, c, b, a
143 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h)	h, g, f, e, d, c, b, a
144 #endif
145 
146 struct fxp_cb_config {
147 	uint16_t	cb_status;
148 	uint16_t	cb_command;
149 	uint32_t	link_addr;
150 
151 	/* Bytes 0 - 21 -- common to all i8255x */
152 	u_int		__FXP_BITFIELD2(byte_count:6, :2);
153 	u_int		__FXP_BITFIELD3(rx_fifo_limit:4, tx_fifo_limit:3, :1);
154 	uint8_t		adaptive_ifs;
155 	u_int		__FXP_BITFIELD5(mwi_enable:1,		/* 8,9 */
156 			    type_enable:1,			/* 8,9 */
157 			    read_align_en:1,			/* 8,9 */
158 			    end_wr_on_cl:1,			/* 8,9 */
159 			    :4);
160 	u_int		__FXP_BITFIELD2(rx_dma_bytecount:7, :1);
161 	u_int		__FXP_BITFIELD2(tx_dma_bytecount:7, dma_mbce:1);
162 	u_int		__FXP_BITFIELD8(late_scb:1,		/* 7 */
163 			    direct_dma_dis:1,			/* 8,9 */
164 			    tno_int_or_tco_en:1,		/* 7,9 */
165 			    ci_int:1,
166 			    ext_txcb_dis:1,			/* 8,9 */
167 			    ext_stats_dis:1,			/* 8,9 */
168 			    keep_overrun_rx:1,
169 			    save_bf:1);
170 	u_int		__FXP_BITFIELD6(disc_short_rx:1,
171 			    underrun_retry:2,
172 			    :2,
173 			    ext_rfa:1,				/* 550 */
174 			    two_frames:1,			/* 8,9 */
175 			    dyn_tbd:1);				/* 8,9 */
176 	u_int		__FXP_BITFIELD3(mediatype:1,		/* 7 */
177 			    :6,
178 			    csma_dis:1);			/* 8,9 */
179 	u_int		__FXP_BITFIELD6(tcp_udp_cksum:1,	/* 9 */
180 			    :3,
181 			    vlan_tco:1,				/* 8,9 */
182 			    link_wake_en:1,			/* 8,9 */
183 			    arp_wake_en:1,			/* 8 */
184 			    mc_wake_en:1);			/* 8 */
185 	u_int		__FXP_BITFIELD4(:3,
186 			    nsai:1,
187 			    preamble_length:2,
188 			    loopback:2);
189 	u_int		__FXP_BITFIELD2(linear_priority:3,	/* 7 */
190 			    :5);
191 	u_int		__FXP_BITFIELD3(linear_pri_mode:1,	/* 7 */
192 			    :3,
193 			    interfrm_spacing:4);
194 	u_int		:8;
195 	u_int		:8;
196 	u_int		__FXP_BITFIELD8(promiscuous:1,
197 			    bcast_disable:1,
198 			    wait_after_win:1,			/* 8,9 */
199 			    :1,
200 			    ignore_ul:1,			/* 8,9 */
201 			    crc16_en:1,				/* 9 */
202 			    :1,
203 			    crscdt:1);
204 	u_int		fc_delay_lsb:8;				/* 8,9 */
205 	u_int		fc_delay_msb:8;				/* 8,9 */
206 	u_int		__FXP_BITFIELD6(stripping:1,
207 			    padding:1,
208 			    rcv_crc_xfer:1,
209 			    long_rx_en:1,			/* 8,9 */
210 			    pri_fc_thresh:3,			/* 8,9 */
211 			    :1);
212 	u_int		__FXP_BITFIELD8(ia_wake_en:1,		/* 8 */
213 			    magic_pkt_dis:1,			/* 8,9,!9ER */
214 			    tx_fc_dis:1,			/* 8,9 */
215 			    rx_fc_restop:1,			/* 8,9 */
216 			    rx_fc_restart:1,			/* 8,9 */
217 			    fc_filter:1,			/* 8,9 */
218 			    force_fdx:1,
219 			    fdx_pin_en:1);
220 	u_int		__FXP_BITFIELD4(:5,
221 			    pri_fc_loc:1,			/* 8,9 */
222 			    multi_ia:1,
223 			    :1);
224 	u_int		__FXP_BITFIELD3(:3, mc_all:1, :4);
225 
226 	/* Bytes 22 - 31 -- i82550 only */
227 	u_int		__FXP_BITFIELD3(gamla_rx:1,
228 			    vlan_strip_en:1,
229 			    :6);
230 	uint8_t		pad[9];
231 };
232 
233 #define MAXMCADDR 80
234 struct fxp_cb_mcs {
235 	uint16_t cb_status;
236 	uint16_t cb_command;
237 	uint32_t link_addr;
238 	uint16_t mc_cnt;
239 	uint8_t mc_addr[MAXMCADDR][6];
240 };
241 
242 #define MAXUCODESIZE 192
243 struct fxp_cb_ucode {
244 	uint16_t cb_status;
245 	uint16_t cb_command;
246 	uint32_t link_addr;
247 	uint32_t ucode[MAXUCODESIZE];
248 };
249 
250 /*
251  * Number of DMA segments in a TxCB.
252  */
253 #define FXP_NTXSEG	35
254 
255 struct fxp_tbd {
256 	uint32_t tb_addr;
257 	uint32_t tb_size;
258 };
259 
260 struct fxp_ipcb {
261 	/*
262 	 * The following fields are valid only when
263 	 * using the IPCB command block for TX checksum offload
264 	 * (and TCP large send, VLANs, and (I think) IPsec). To use
265 	 * them, you must enable extended TxCBs (available only
266 	 * on the 82559 and later) and use the IPCBXMIT command.
267 	 * Note that Intel defines the IPCB to be 32 bytes long,
268 	 * the last 8 bytes of which comprise the first entry
269 	 * in the TBD array (see note below). This means we only
270 	 * have to define 8 extra bytes here.
271          */
272 	uint16_t ipcb_schedule_low;
273 	uint8_t ipcb_ip_schedule;
274 	uint8_t ipcb_ip_activation_high;
275 	uint16_t ipcb_vlan_id;
276 	uint8_t ipcb_ip_header_offset;
277 	uint8_t ipcb_tcp_header_offset;
278 };
279 
280 struct fxp_cb_tx {
281 	uint16_t cb_status;
282 	uint16_t cb_command;
283 	uint32_t link_addr;
284 	uint32_t tbd_array_addr;
285 	uint16_t byte_count;
286 	uint8_t tx_threshold;
287 	uint8_t tbd_number;
288 
289 	/*
290 	 * The following structure isn't actually part of the TxCB,
291 	 * unless the extended TxCB feature is being used.  In this
292 	 * case, the first two elements of the structure below are
293 	 * fetched along with the TxCB.
294 	 */
295 	union {
296 		struct fxp_ipcb ipcb;
297 		struct fxp_tbd tbd[FXP_NTXSEG + 1];
298 	} tx_cb_u;
299 };
300 
301 #define tbd			tx_cb_u.tbd
302 #define ipcb_schedule_low	tx_cb_u.ipcb.ipcb_schedule_low
303 #define ipcb_ip_schedule	tx_cb_u.ipcb.ipcb_ip_schedule
304 #define ipcb_ip_activation_high tx_cb_u.ipcb.ipcb_ip_activation_high
305 #define ipcb_vlan_id		tx_cb_u.ipcb.ipcb_vlan_id
306 #define ipcb_ip_header_offset	tx_cb_u.ipcb.ipcb_ip_header_offset
307 #define ipcb_tcp_header_offset	tx_cb_u.ipcb.ipcb_tcp_header_offset
308 
309 /*
310  * IPCB field definitions
311  */
312 #define FXP_IPCB_IP_CHECKSUM_ENABLE	0x10
313 #define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE	0x20
314 #define FXP_IPCB_TCP_PACKET		0x40
315 #define FXP_IPCB_LARGESEND_ENABLE	0x80
316 #define FXP_IPCB_HARDWAREPARSING_ENABLE	0x01
317 #define FXP_IPCB_INSERTVLAN_ENABLE	0x02
318 
319 /*
320  * Control Block (CB) definitions
321  */
322 
323 /* status */
324 #define FXP_CB_STATUS_OK	0x2000
325 #define FXP_CB_STATUS_C		0x8000
326 /* commands */
327 #define FXP_CB_COMMAND_NOP	0x0
328 #define FXP_CB_COMMAND_IAS	0x1
329 #define FXP_CB_COMMAND_CONFIG	0x2
330 #define FXP_CB_COMMAND_MCAS	0x3
331 #define FXP_CB_COMMAND_XMIT	0x4
332 #define FXP_CB_COMMAND_UCODE	0x5
333 #define FXP_CB_COMMAND_DUMP	0x6
334 #define FXP_CB_COMMAND_DIAG	0x7
335 #define FXP_CB_COMMAND_LOADFILT	0x8
336 #define FXP_CB_COMMAND_IPCBXMIT 0x9
337 
338 /* command flags */
339 #define FXP_CB_COMMAND_SF	0x0008	/* simple/flexible mode */
340 #define FXP_CB_COMMAND_I	0x2000	/* generate interrupt on completion */
341 #define FXP_CB_COMMAND_S	0x4000	/* suspend on completion */
342 #define FXP_CB_COMMAND_EL	0x8000	/* end of list */
343 
344 /*
345  * RFA definitions
346  */
347 
348 struct fxp_rfa {
349 	uint16_t rfa_status;
350 	uint16_t rfa_control;
351 	uint32_t link_addr;
352 	uint32_t rbd_addr;
353 	uint16_t actual_size;
354 	uint16_t size;
355 
356 	/*
357 	 * The following fields are only available when using
358 	 * extended receive mode on an 82550/82551 chipset.
359 	 */
360 	uint16_t rfax_vlan_id;
361 	uint8_t rfax_rx_parser_sts;
362 	uint8_t rfax_rsvd0;
363 	uint16_t rfax_security_sts;
364 	uint8_t rfax_csum_sts;
365 	uint8_t rfax_zerocopy_sts;
366 	uint8_t rfax_pad[8];
367 } __packed;
368 #define FXP_RFAX_LEN 16
369 
370 #define FXP_RFA_STATUS_RCOL	0x0001	/* receive collision */
371 #define FXP_RFA_STATUS_IAMATCH	0x0002	/* 0 = matches station address */
372 #define FXP_RFA_STATUS_NOAMATCH	0x0004	/* 1 = doesn't match anything */
373 #define FXP_RFA_STATUS_PARSE	0x0008	/* pkt parse ok (82550/1 only) */
374 #define FXP_RFA_STATUS_S4	0x0010	/* receive error from PHY */
375 #define FXP_RFA_STATUS_TL	0x0020	/* type/length */
376 #define FXP_RFA_STATUS_FTS	0x0080	/* frame too short */
377 #define FXP_RFA_STATUS_OVERRUN	0x0100	/* DMA overrun */
378 #define FXP_RFA_STATUS_RNR	0x0200	/* no resources */
379 #define FXP_RFA_STATUS_ALIGN	0x0400	/* alignment error */
380 #define FXP_RFA_STATUS_CRC	0x0800	/* CRC error */
381 #define FXP_RFA_STATUS_VLAN	0x1000	/* VLAN tagged frame */
382 #define FXP_RFA_STATUS_OK	0x2000	/* packet received okay */
383 #define FXP_RFA_STATUS_C	0x8000	/* packet reception complete */
384 #define FXP_RFA_CONTROL_SF	0x08	/* simple/flexible memory mode */
385 #define FXP_RFA_CONTROL_H	0x10	/* header RFD */
386 #define FXP_RFA_CONTROL_S	0x4000	/* suspend after reception */
387 #define FXP_RFA_CONTROL_EL	0x8000	/* end of list */
388 
389 /* Bits in the 'csum_sts' byte */
390 #define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID	0x10
391 #define FXP_RFDX_CS_TCPUDP_CSUM_VALID		0x20
392 #define FXP_RFDX_CS_IP_CSUM_BIT_VALID		0x01
393 #define FXP_RFDX_CS_IP_CSUM_VALID		0x02
394 
395 /* Bits in the 'packet parser' byte */
396 #define FXP_RFDX_P_PARSE_BIT			0x08
397 #define FXP_RFDX_P_CSUM_PROTOCOL_MASK		0x03
398 #define FXP_RFDX_P_TCP_PACKET			0x00
399 #define FXP_RFDX_P_UDP_PACKET			0x01
400 #define FXP_RFDX_P_IP_PACKET			0x03
401 
402 /*
403  * Statistics dump area definitions
404  */
405 struct fxp_stats {
406 	uint32_t tx_good;
407 	uint32_t tx_maxcols;
408 	uint32_t tx_latecols;
409 	uint32_t tx_underruns;
410 	uint32_t tx_lostcrs;
411 	uint32_t tx_deffered;
412 	uint32_t tx_single_collisions;
413 	uint32_t tx_multiple_collisions;
414 	uint32_t tx_total_collisions;
415 	uint32_t rx_good;
416 	uint32_t rx_crc_errors;
417 	uint32_t rx_alignment_errors;
418 	uint32_t rx_rnr_errors;
419 	uint32_t rx_overrun_errors;
420 	uint32_t rx_cdt_errors;
421 	uint32_t rx_shortframes;
422 	uint32_t tx_pause;
423 	uint32_t rx_pause;
424 	uint32_t rx_controls;
425 	uint16_t tx_tco;
426 	uint16_t rx_tco;
427 	uint32_t completion_status;
428 	uint32_t reserved0;
429 	uint32_t reserved1;
430 	uint32_t reserved2;
431 };
432 #define FXP_STATS_DUMP_COMPLETE	0xa005
433 #define FXP_STATS_DR_COMPLETE	0xa007
434 
435 /*
436  * Serial EEPROM control register bits
437  */
438 #define FXP_EEPROM_EESK		0x01 		/* shift clock */
439 #define FXP_EEPROM_EECS		0x02 		/* chip select */
440 #define FXP_EEPROM_EEDI		0x04 		/* data in */
441 #define FXP_EEPROM_EEDO		0x08 		/* data out */
442 
443 /*
444  * Serial EEPROM opcodes, including start bit
445  */
446 #define FXP_EEPROM_OPC_ERASE	0x4
447 #define FXP_EEPROM_OPC_WRITE	0x5
448 #define FXP_EEPROM_OPC_READ	0x6
449 
450 /*
451  * EEPROM map
452  */
453 #define	FXP_EEPROM_MAP_IA0	0x00		/* Station address */
454 #define	FXP_EEPROM_MAP_IA1	0x01
455 #define	FXP_EEPROM_MAP_IA2	0x02
456 #define	FXP_EEPROM_MAP_COMPAT	0x03		/* Compatibility */
457 #define	FXP_EEPROM_MAP_CNTR	0x05		/* Controller/connector type */
458 #define	FXP_EEPROM_MAP_PRI_PHY	0x06		/* Primary PHY record */
459 #define	FXP_EEPROM_MAP_SEC_PHY	0x07		/* Secondary PHY record */
460 #define	FXP_EEPROM_MAP_PWA0	0x08		/* Printed wire assembly num. */
461 #define	FXP_EEPROM_MAP_PWA1	0x09		/* Printed wire assembly num. */
462 #define	FXP_EEPROM_MAP_ID	0x0A		/* EEPROM ID */
463 #define	FXP_EEPROM_MAP_SUBSYS	0x0B		/* Subsystem ID */
464 #define	FXP_EEPROM_MAP_SUBVEN	0x0C		/* Subsystem vendor ID */
465 #define	FXP_EEPROM_MAP_CKSUM64	0x3F		/* 64-word EEPROM checksum */
466 #define	FXP_EEPROM_MAP_CKSUM256	0xFF		/* 256-word EEPROM checksum */
467 
468 /*
469  * Management Data Interface opcodes
470  */
471 #define FXP_MDI_WRITE		0x1
472 #define FXP_MDI_READ		0x2
473 
474 /*
475  * PHY device types
476  */
477 #define FXP_PHY_DEVICE_MASK	0x3f00
478 #define FXP_PHY_SERIAL_ONLY	0x8000
479 #define FXP_PHY_NONE		0
480 #define FXP_PHY_82553A		1
481 #define FXP_PHY_82553C		2
482 #define FXP_PHY_82503		3
483 #define FXP_PHY_DP83840		4
484 #define FXP_PHY_80C240		5
485 #define FXP_PHY_80C24		6
486 #define FXP_PHY_82555		7
487 #define FXP_PHY_DP83840A	10
488 #define FXP_PHY_82555B		11
489 
490 /*
491  * Chip revision values.
492  */
493 #define FXP_REV_82557		1       /* catchall 82557 chip type */
494 #define FXP_REV_82558_A4	4	/* 82558 A4 stepping */
495 #define FXP_REV_82558_B0	5	/* 82558 B0 stepping */
496 #define FXP_REV_82559_A0	8	/* 82559 A0 stepping */
497 #define FXP_REV_82559S_A	9	/* 82559S A stepping */
498 #define FXP_REV_82550		12
499 #define FXP_REV_82550_C		13	/* 82550 C stepping */
500 #define FXP_REV_82551_E		14	/* 82551 */
501 #define FXP_REV_82551_F		15	/* 82551 */
502 #define FXP_REV_82551_10	16	/* 82551 */
503