1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: if_fxpreg.h,v 1.2 1995/12/05 11:49:55 davidg Exp $ 28 */ 29 30 #define FXP_VENDORID_INTEL 0x8086 31 #define FXP_DEVICEID_i82557 0x1229 32 33 #define FXP_PCI_MMBA 0x10 34 #define FXP_PCI_IOBA 0x14 35 36 struct fxp_csr { 37 volatile u_int8_t :2, 38 scb_rus:4, 39 scb_cus:2; 40 volatile u_int8_t scb_statack; 41 volatile u_int8_t scb_command; 42 volatile u_int8_t scb_intrcntl; 43 volatile u_int32_t scb_general; 44 volatile u_int32_t port; 45 volatile u_int16_t flash_control; 46 volatile u_int16_t eeprom_control; 47 volatile u_int32_t mdi_control; 48 }; 49 50 #define FXP_SCB_RUS_IDLE 0 51 #define FXP_SCB_RUS_SUSPENDED 1 52 #define FXP_SCB_RUS_NORESOURCES 2 53 #define FXP_SCB_RUS_READY 4 54 #define FXP_SCB_RUS_SUSP_NORBDS 9 55 #define FXP_SCB_RUS_NORES_NORBDS 10 56 #define FXP_SCB_RUS_READY_NORBDS 12 57 58 #define FXP_SCB_CUS_IDLE 0 59 #define FXP_SCB_CUS_SUSPENDED 1 60 #define FXP_SCB_CUS_ACTIVE 2 61 62 #define FXP_SCB_STATACK_SWI 0x04 63 #define FXP_SCB_STATACK_MDI 0x08 64 #define FXP_SCB_STATACK_RNR 0x10 65 #define FXP_SCB_STATACK_CNA 0x20 66 #define FXP_SCB_STATACK_FR 0x40 67 #define FXP_SCB_STATACK_CXTNO 0x80 68 69 #define FXP_SCB_COMMAND_MASK 0xff 70 #define FXP_SCB_COMMAND_CU_NOP 0x00 71 #define FXP_SCB_COMMAND_CU_START 0x10 72 #define FXP_SCB_COMMAND_CU_RESUME 0x20 73 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 74 #define FXP_SCB_COMMAND_CU_DUMP 0x50 75 #define FXP_SCB_COMMAND_CU_BASE 0x60 76 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 77 78 #define FXP_SCB_COMMAND_RU_NOP 0 79 #define FXP_SCB_COMMAND_RU_START 1 80 #define FXP_SCB_COMMAND_RU_RESUME 2 81 #define FXP_SCB_COMMAND_RU_ABORT 4 82 #define FXP_SCB_COMMAND_RU_LOADHDS 5 83 #define FXP_SCB_COMMAND_RU_BASE 6 84 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 85 86 /* 87 * Command block definitions 88 */ 89 struct fxp_cb_nop { 90 volatile u_int16_t cb_status; 91 volatile u_int16_t cb_command; 92 volatile u_int32_t link_addr; 93 }; 94 struct fxp_cb_ias { 95 volatile u_int16_t cb_status; 96 volatile u_int16_t cb_command; 97 volatile u_int32_t link_addr; 98 volatile u_int8_t macaddr[6]; 99 }; 100 /* I hate bit-fields :-( */ 101 struct fxp_cb_config { 102 volatile u_int16_t cb_status; 103 volatile u_int16_t cb_command; 104 volatile u_int32_t link_addr; 105 volatile u_int8_t byte_count:6, 106 :2; 107 volatile u_int8_t rx_fifo_limit:4, 108 tx_fifo_limit:3, 109 :1; 110 volatile u_int8_t adaptive_ifs; 111 volatile u_int8_t :8; 112 volatile u_int8_t rx_dma_bytecount:7, 113 :1; 114 volatile u_int8_t tx_dma_bytecount:7, 115 dma_bce:1; 116 volatile u_int8_t late_scb:1, 117 :1, 118 tno_int:1, 119 ci_int:1, 120 :3, 121 save_bf:1; 122 volatile u_int8_t disc_short_rx:1, 123 underrun_retry:2, 124 :5; 125 volatile u_int8_t mediatype:1, 126 :7; 127 volatile u_int8_t :8; 128 volatile u_int8_t :3, 129 nsai:1, 130 preamble_length:2, 131 loopback:2; 132 volatile u_int8_t linear_priority:3, 133 :5; 134 volatile u_int8_t linear_pri_mode:1, 135 :3, 136 interfrm_spacing:4; 137 volatile u_int8_t :8; 138 volatile u_int8_t :8; 139 volatile u_int8_t promiscuous:1, 140 bcast_disable:1, 141 :5, 142 crscdt:1; 143 volatile u_int8_t :8; 144 volatile u_int8_t :8; 145 volatile u_int8_t stripping:1, 146 padding:1, 147 rcv_crc_xfer:1, 148 :5; 149 volatile u_int8_t :6, 150 force_fdx:1, 151 fdx_pin_en:1; 152 volatile u_int8_t :6, 153 multi_ia:1, 154 :1; 155 volatile u_int8_t :3, 156 mc_all:1, 157 :4; 158 }; 159 struct fxp_tbd { 160 volatile u_int32_t tb_addr; 161 volatile u_int32_t tb_size; 162 }; 163 164 struct fxp_cb_tx { 165 volatile u_int16_t cb_status; 166 volatile u_int16_t cb_command; 167 volatile u_int32_t link_addr; 168 volatile u_int32_t tbd_array_addr; 169 volatile u_int16_t byte_count; 170 volatile u_int8_t tx_threshold; 171 volatile u_int8_t tbd_number; 172 /* 173 * The following isn't actually part of the TxCB. 174 */ 175 volatile struct fxp_tbd tbd[29]; 176 struct mbuf *mb_head; 177 struct fxp_cb_tx *next; 178 }; 179 180 /* 181 * Control Block (CB) definitions 182 */ 183 184 /* status */ 185 #define FXP_CB_STATUS_OK 0x2000 186 #define FXP_CB_STATUS_C 0x8000 187 /* commands */ 188 #define FXP_CB_COMMAND_NOP 0x0 189 #define FXP_CB_COMMAND_IAS 0x1 190 #define FXP_CB_COMMAND_CONFIG 0x2 191 #define FXP_CB_COMMAND_MAS 0x3 192 #define FXP_CB_COMMAND_XMIT 0x4 193 #define FXP_CB_COMMAND_RESRV 0x5 194 #define FXP_CB_COMMAND_DUMP 0x6 195 #define FXP_CB_COMMAND_DIAG 0x7 196 /* command flags */ 197 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 198 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 199 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 200 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 201 202 /* 203 * RFA definitions 204 */ 205 206 struct fxp_rfa { 207 volatile u_int16_t rfa_status; 208 volatile u_int16_t rfa_control; 209 volatile u_int32_t link_addr; 210 volatile u_int32_t rbd_addr; 211 volatile u_int16_t actual_size; 212 volatile u_int16_t size; 213 }; 214 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 215 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 216 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 217 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 218 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 219 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 220 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 221 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 222 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 223 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 224 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 225 #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 226 #define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 227 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 228 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 229 230 /* 231 * Statistics dump area definitions 232 */ 233 struct fxp_stats { 234 volatile u_int32_t tx_good; 235 volatile u_int32_t tx_maxcols; 236 volatile u_int32_t tx_latecols; 237 volatile u_int32_t tx_underruns; 238 volatile u_int32_t tx_lostcrs; 239 volatile u_int32_t tx_deffered; 240 volatile u_int32_t tx_single_collisions; 241 volatile u_int32_t tx_multiple_collisions; 242 volatile u_int32_t tx_total_collisions; 243 volatile u_int32_t rx_good; 244 volatile u_int32_t rx_crc_errors; 245 volatile u_int32_t rx_alignment_errors; 246 volatile u_int32_t rx_rnr_errors; 247 volatile u_int32_t rx_overrun_errors; 248 volatile u_int32_t rx_cdt_errors; 249 volatile u_int32_t rx_shortframes; 250 volatile u_int32_t completion_status; 251 }; 252 #define FXP_STATS_DUMP_COMPLETE 0xa005 253 #define FXP_STATS_DR_COMPLETE 0xa007 254 255 /* 256 * Serial EEPROM control register bits 257 */ 258 /* shift clock */ 259 #define FXP_EEPROM_EESK 0x01 260 /* chip select */ 261 #define FXP_EEPROM_EECS 0x02 262 /* data in */ 263 #define FXP_EEPROM_EEDI 0x04 264 /* data out */ 265 #define FXP_EEPROM_EEDO 0x08 266 267 /* 268 * Serial EEPROM opcodes, including start bit 269 */ 270 #define FXP_EEPROM_OPC_ERASE 0x4 271 #define FXP_EEPROM_OPC_WRITE 0x5 272 #define FXP_EEPROM_OPC_READ 0x6 273