1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #ifdef NS 49 #include <netns/ns.h> 50 #include <netns/ns_if.h> 51 #endif 52 53 #include <net/bpf.h> 54 #include <sys/sockio.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <net/ethernet.h> 61 #include <net/if_arp.h> 62 63 #include <vm/vm.h> /* for vtophys */ 64 #include <vm/pmap.h> /* for vtophys */ 65 #include <machine/clock.h> /* for DELAY */ 66 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #ifdef FXP_IP_CSUM_WAR 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/ip.h> 74 #include <machine/in_cksum.h> 75 #endif 76 77 #include <pci/pcivar.h> 78 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <dev/fxp/if_fxpreg.h> 84 #include <dev/fxp/if_fxpvar.h> 85 #include <dev/fxp/rcvbundl.h> 86 87 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 88 #include "miibus_if.h" 89 90 /* 91 * NOTE! On the Alpha, we have an alignment constraint. The 92 * card DMAs the packet immediately following the RFA. However, 93 * the first thing in the packet is a 14-byte Ethernet header. 94 * This means that the packet is misaligned. To compensate, 95 * we actually offset the RFA 2 bytes into the cluster. This 96 * alignes the packet after the Ethernet header at a 32-bit 97 * boundary. HOWEVER! This means that the RFA is misaligned! 98 */ 99 #define RFA_ALIGNMENT_FUDGE 2 100 101 /* 102 * Set initial transmit threshold at 64 (512 bytes). This is 103 * increased by 64 (512 bytes) at a time, to maximum of 192 104 * (1536 bytes), if an underrun occurs. 105 */ 106 static int tx_threshold = 64; 107 108 /* 109 * The configuration byte map has several undefined fields which 110 * must be one or must be zero. Set up a template for these bits 111 * only, (assuming a 82557 chip) leaving the actual configuration 112 * to fxp_init. 113 * 114 * See struct fxp_cb_config for the bit definitions. 115 */ 116 static u_char fxp_cb_config_template[] = { 117 0x0, 0x0, /* cb_status */ 118 0x0, 0x0, /* cb_command */ 119 0x0, 0x0, 0x0, 0x0, /* link_addr */ 120 0x0, /* 0 */ 121 0x0, /* 1 */ 122 0x0, /* 2 */ 123 0x0, /* 3 */ 124 0x0, /* 4 */ 125 0x0, /* 5 */ 126 0x32, /* 6 */ 127 0x0, /* 7 */ 128 0x0, /* 8 */ 129 0x0, /* 9 */ 130 0x6, /* 10 */ 131 0x0, /* 11 */ 132 0x0, /* 12 */ 133 0x0, /* 13 */ 134 0xf2, /* 14 */ 135 0x48, /* 15 */ 136 0x0, /* 16 */ 137 0x40, /* 17 */ 138 0xf0, /* 18 */ 139 0x0, /* 19 */ 140 0x3f, /* 20 */ 141 0x5 /* 21 */ 142 }; 143 144 struct fxp_ident { 145 u_int16_t devid; 146 char *name; 147 }; 148 149 /* 150 * Claim various Intel PCI device identifiers for this driver. The 151 * sub-vendor and sub-device field are extensively used to identify 152 * particular variants, but we don't currently differentiate between 153 * them. 154 */ 155 static struct fxp_ident fxp_ident_table[] = { 156 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 157 { 0x2449, "Intel Pro/100 Ethernet" }, 158 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 159 { 0x1029, "Intel Pro/100 Ethernet" }, 160 { 0x1030, "Intel Pro/100 Ethernet" }, 161 { 0x1031, "Intel Pro/100 Ethernet" }, 162 { 0x1032, "Intel Pro/100 Ethernet" }, 163 { 0x1033, "Intel Pro/100 Ethernet" }, 164 { 0x1034, "Intel Pro/100 Ethernet" }, 165 { 0x1035, "Intel Pro/100 Ethernet" }, 166 { 0x1036, "Intel Pro/100 Ethernet" }, 167 { 0x1037, "Intel Pro/100 Ethernet" }, 168 { 0x1038, "Intel Pro/100 Ethernet" }, 169 { 0x1039, "Intel Pro/100 Ethernet" }, 170 { 0x103A, "Intel Pro/100 Ethernet" }, 171 { 0x103B, "Intel Pro/100 Ethernet" }, 172 { 0x103C, "Intel Pro/100 Ethernet" }, 173 { 0x103D, "Intel Pro/100 Ethernet" }, 174 { 0x103E, "Intel Pro/100 Ethernet" }, 175 { 0x1059, "Intel Pro/100 M Mobile Connection" }, 176 { 0, NULL }, 177 }; 178 179 #ifdef FXP_IP_CSUM_WAR 180 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 181 #else 182 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 183 #endif 184 185 static int fxp_probe(device_t dev); 186 static int fxp_attach(device_t dev); 187 static int fxp_detach(device_t dev); 188 static int fxp_shutdown(device_t dev); 189 static int fxp_suspend(device_t dev); 190 static int fxp_resume(device_t dev); 191 192 static void fxp_intr(void *xsc); 193 static void fxp_init(void *xsc); 194 static void fxp_tick(void *xsc); 195 static void fxp_powerstate_d0(device_t dev); 196 static void fxp_start(struct ifnet *ifp); 197 static void fxp_stop(struct fxp_softc *sc); 198 static void fxp_release(struct fxp_softc *sc); 199 static int fxp_ioctl(struct ifnet *ifp, u_long command, 200 caddr_t data); 201 static void fxp_watchdog(struct ifnet *ifp); 202 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 203 static int fxp_mc_addrs(struct fxp_softc *sc); 204 static void fxp_mc_setup(struct fxp_softc *sc); 205 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 206 int autosize); 207 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 208 u_int16_t data); 209 static void fxp_autosize_eeprom(struct fxp_softc *sc); 210 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 211 int offset, int words); 212 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 213 int offset, int words); 214 static int fxp_ifmedia_upd(struct ifnet *ifp); 215 static void fxp_ifmedia_sts(struct ifnet *ifp, 216 struct ifmediareq *ifmr); 217 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 218 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 219 struct ifmediareq *ifmr); 220 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 221 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 222 int value); 223 static void fxp_load_ucode(struct fxp_softc *sc); 224 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 225 int low, int high); 226 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 227 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 228 static __inline void fxp_lwcopy(volatile u_int32_t *src, 229 volatile u_int32_t *dst); 230 static __inline void fxp_scb_wait(struct fxp_softc *sc); 231 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 232 static __inline void fxp_dma_wait(volatile u_int16_t *status, 233 struct fxp_softc *sc); 234 235 static device_method_t fxp_methods[] = { 236 /* Device interface */ 237 DEVMETHOD(device_probe, fxp_probe), 238 DEVMETHOD(device_attach, fxp_attach), 239 DEVMETHOD(device_detach, fxp_detach), 240 DEVMETHOD(device_shutdown, fxp_shutdown), 241 DEVMETHOD(device_suspend, fxp_suspend), 242 DEVMETHOD(device_resume, fxp_resume), 243 244 /* MII interface */ 245 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 246 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 247 248 { 0, 0 } 249 }; 250 251 static driver_t fxp_driver = { 252 "fxp", 253 fxp_methods, 254 sizeof(struct fxp_softc), 255 }; 256 257 static devclass_t fxp_devclass; 258 259 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 260 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 261 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 262 263 static int fxp_rnr; 264 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 265 266 /* 267 * Inline function to copy a 16-bit aligned 32-bit quantity. 268 */ 269 static __inline void 270 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 271 { 272 #ifdef __i386__ 273 *dst = *src; 274 #else 275 volatile u_int16_t *a = (volatile u_int16_t *)src; 276 volatile u_int16_t *b = (volatile u_int16_t *)dst; 277 278 b[0] = a[0]; 279 b[1] = a[1]; 280 #endif 281 } 282 283 /* 284 * Wait for the previous command to be accepted (but not necessarily 285 * completed). 286 */ 287 static __inline void 288 fxp_scb_wait(struct fxp_softc *sc) 289 { 290 int i = 10000; 291 292 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 293 DELAY(2); 294 if (i == 0) 295 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 296 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 297 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 298 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 299 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 300 } 301 302 static __inline void 303 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 304 { 305 306 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 307 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 308 fxp_scb_wait(sc); 309 } 310 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 311 } 312 313 static __inline void 314 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 315 { 316 int i = 10000; 317 318 while (!(*status & FXP_CB_STATUS_C) && --i) 319 DELAY(2); 320 if (i == 0) 321 device_printf(sc->dev, "DMA timeout\n"); 322 } 323 324 /* 325 * Return identification string if this is device is ours. 326 */ 327 static int 328 fxp_probe(device_t dev) 329 { 330 u_int16_t devid; 331 struct fxp_ident *ident; 332 333 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 334 devid = pci_get_device(dev); 335 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 336 if (ident->devid == devid) { 337 device_set_desc(dev, ident->name); 338 return (0); 339 } 340 } 341 } 342 return (ENXIO); 343 } 344 345 static void 346 fxp_powerstate_d0(device_t dev) 347 { 348 #if __FreeBSD_version >= 430002 349 u_int32_t iobase, membase, irq; 350 351 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 352 /* Save important PCI config data. */ 353 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 354 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 355 irq = pci_read_config(dev, PCIR_INTLINE, 4); 356 357 /* Reset the power state. */ 358 device_printf(dev, "chip is in D%d power mode " 359 "-- setting to D0\n", pci_get_powerstate(dev)); 360 361 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 362 363 /* Restore PCI config data. */ 364 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 365 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 366 pci_write_config(dev, PCIR_INTLINE, irq, 4); 367 } 368 #endif 369 } 370 371 static int 372 fxp_attach(device_t dev) 373 { 374 int error = 0; 375 struct fxp_softc *sc = device_get_softc(dev); 376 struct ifnet *ifp; 377 u_int32_t val; 378 u_int16_t data; 379 int i, rid, m1, m2, prefer_iomap; 380 int s; 381 382 bzero(sc, sizeof(*sc)); 383 sc->dev = dev; 384 callout_handle_init(&sc->stat_ch); 385 sysctl_ctx_init(&sc->sysctl_ctx); 386 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 387 MTX_DEF | MTX_RECURSE); 388 389 s = splimp(); 390 391 /* 392 * Enable bus mastering. Enable memory space too, in case 393 * BIOS/Prom forgot about it. 394 */ 395 val = pci_read_config(dev, PCIR_COMMAND, 2); 396 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 397 pci_write_config(dev, PCIR_COMMAND, val, 2); 398 val = pci_read_config(dev, PCIR_COMMAND, 2); 399 400 fxp_powerstate_d0(dev); 401 402 /* 403 * Figure out which we should try first - memory mapping or i/o mapping? 404 * We default to memory mapping. Then we accept an override from the 405 * command line. Then we check to see which one is enabled. 406 */ 407 m1 = PCIM_CMD_MEMEN; 408 m2 = PCIM_CMD_PORTEN; 409 prefer_iomap = 0; 410 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 411 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 412 m1 = PCIM_CMD_PORTEN; 413 m2 = PCIM_CMD_MEMEN; 414 } 415 416 if (val & m1) { 417 sc->rtp = 418 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 419 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 420 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 421 0, ~0, 1, RF_ACTIVE); 422 } 423 if (sc->mem == NULL && (val & m2)) { 424 sc->rtp = 425 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 426 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 427 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 428 0, ~0, 1, RF_ACTIVE); 429 } 430 431 if (!sc->mem) { 432 device_printf(dev, "could not map device registers\n"); 433 error = ENXIO; 434 goto fail; 435 } 436 if (bootverbose) { 437 device_printf(dev, "using %s space register mapping\n", 438 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 439 } 440 441 sc->sc_st = rman_get_bustag(sc->mem); 442 sc->sc_sh = rman_get_bushandle(sc->mem); 443 444 /* 445 * Allocate our interrupt. 446 */ 447 rid = 0; 448 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 449 RF_SHAREABLE | RF_ACTIVE); 450 if (sc->irq == NULL) { 451 device_printf(dev, "could not map interrupt\n"); 452 error = ENXIO; 453 goto fail; 454 } 455 456 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 457 fxp_intr, sc, &sc->ih); 458 if (error) { 459 device_printf(dev, "could not setup irq\n"); 460 goto fail; 461 } 462 463 /* 464 * Reset to a stable state. 465 */ 466 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 467 DELAY(10); 468 469 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 470 M_DEVBUF, M_NOWAIT | M_ZERO); 471 if (sc->cbl_base == NULL) 472 goto failmem; 473 474 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 475 M_NOWAIT | M_ZERO); 476 if (sc->fxp_stats == NULL) 477 goto failmem; 478 479 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 480 if (sc->mcsp == NULL) 481 goto failmem; 482 483 /* 484 * Pre-allocate our receive buffers. 485 */ 486 for (i = 0; i < FXP_NRFABUFS; i++) { 487 if (fxp_add_rfabuf(sc, NULL) != 0) { 488 goto failmem; 489 } 490 } 491 492 /* 493 * Find out how large of an SEEPROM we have. 494 */ 495 fxp_autosize_eeprom(sc); 496 497 /* 498 * Determine whether we must use the 503 serial interface. 499 */ 500 fxp_read_eeprom(sc, &data, 6, 1); 501 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 502 (data & FXP_PHY_SERIAL_ONLY)) 503 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 504 505 /* 506 * Create the sysctl tree 507 */ 508 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 509 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 510 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 511 if (sc->sysctl_tree == NULL) 512 goto fail; 513 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 514 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 515 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 516 "FXP driver receive interrupt microcode bundling delay"); 517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 518 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 519 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 520 "FXP driver receive interrupt microcode bundle size limit"); 521 522 /* 523 * Pull in device tunables. 524 */ 525 sc->tunable_int_delay = TUNABLE_INT_DELAY; 526 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 527 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 528 "int_delay", &sc->tunable_int_delay); 529 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 530 "bundle_max", &sc->tunable_bundle_max); 531 532 /* 533 * Find out the chip revision; lump all 82557 revs together. 534 */ 535 fxp_read_eeprom(sc, &data, 5, 1); 536 if ((data >> 8) == 1) 537 sc->revision = FXP_REV_82557; 538 else 539 sc->revision = pci_get_revid(dev); 540 541 /* 542 * Enable workarounds for certain chip revision deficiencies. 543 * 544 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 545 * some systems based a normal 82559 design, have a defect where 546 * the chip can cause a PCI protocol violation if it receives 547 * a CU_RESUME command when it is entering the IDLE state. The 548 * workaround is to disable Dynamic Standby Mode, so the chip never 549 * deasserts CLKRUN#, and always remains in an active state. 550 * 551 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 552 */ 553 i = pci_get_device(dev); 554 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 555 sc->revision >= FXP_REV_82559_A0) { 556 fxp_read_eeprom(sc, &data, 10, 1); 557 if (data & 0x02) { /* STB enable */ 558 u_int16_t cksum; 559 int i; 560 561 device_printf(dev, 562 "Disabling dynamic standby mode in EEPROM\n"); 563 data &= ~0x02; 564 fxp_write_eeprom(sc, &data, 10, 1); 565 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 566 cksum = 0; 567 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 568 fxp_read_eeprom(sc, &data, i, 1); 569 cksum += data; 570 } 571 i = (1 << sc->eeprom_size) - 1; 572 cksum = 0xBABA - cksum; 573 fxp_read_eeprom(sc, &data, i, 1); 574 fxp_write_eeprom(sc, &cksum, i, 1); 575 device_printf(dev, 576 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 577 i, data, cksum); 578 #if 1 579 /* 580 * If the user elects to continue, try the software 581 * workaround, as it is better than nothing. 582 */ 583 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 584 #endif 585 } 586 } 587 588 /* 589 * If we are not a 82557 chip, we can enable extended features. 590 */ 591 if (sc->revision != FXP_REV_82557) { 592 /* 593 * If MWI is enabled in the PCI configuration, and there 594 * is a valid cacheline size (8 or 16 dwords), then tell 595 * the board to turn on MWI. 596 */ 597 if (val & PCIM_CMD_MWRICEN && 598 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 599 sc->flags |= FXP_FLAG_MWI_ENABLE; 600 601 /* turn on the extended TxCB feature */ 602 sc->flags |= FXP_FLAG_EXT_TXCB; 603 604 /* enable reception of long frames for VLAN */ 605 sc->flags |= FXP_FLAG_LONG_PKT_EN; 606 } 607 608 /* 609 * Enable use of extended RFDs and TCBs for 82550 610 * and later chips. Note: we need extended TXCB support 611 * too, but that's already enabled by the code above. 612 * Be careful to do this only on the right devices. 613 */ 614 615 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 616 sc->rfa_size = sizeof (struct fxp_rfa); 617 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 618 sc->flags |= FXP_FLAG_EXT_RFA; 619 } else { 620 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 621 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 622 } 623 624 /* 625 * Read MAC address. 626 */ 627 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 628 device_printf(dev, "Ethernet address %6D%s\n", 629 sc->arpcom.ac_enaddr, ":", 630 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 631 if (bootverbose) { 632 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 633 pci_get_vendor(dev), pci_get_device(dev), 634 pci_get_subvendor(dev), pci_get_subdevice(dev), 635 pci_get_revid(dev)); 636 fxp_read_eeprom(sc, &data, 10, 1); 637 device_printf(dev, "Dynamic Standby mode is %s\n", 638 data & 0x02 ? "enabled" : "disabled"); 639 } 640 641 /* 642 * If this is only a 10Mbps device, then there is no MII, and 643 * the PHY will use a serial interface instead. 644 * 645 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 646 * doesn't have a programming interface of any sort. The 647 * media is sensed automatically based on how the link partner 648 * is configured. This is, in essence, manual configuration. 649 */ 650 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 651 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 652 fxp_serial_ifmedia_sts); 653 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 654 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 655 } else { 656 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 657 fxp_ifmedia_sts)) { 658 device_printf(dev, "MII without any PHY!\n"); 659 error = ENXIO; 660 goto fail; 661 } 662 } 663 664 ifp = &sc->arpcom.ac_if; 665 ifp->if_unit = device_get_unit(dev); 666 ifp->if_name = "fxp"; 667 ifp->if_output = ether_output; 668 ifp->if_baudrate = 100000000; 669 ifp->if_init = fxp_init; 670 ifp->if_softc = sc; 671 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 672 ifp->if_ioctl = fxp_ioctl; 673 ifp->if_start = fxp_start; 674 ifp->if_watchdog = fxp_watchdog; 675 676 /* Enable checksum offload for 82550 or better chips */ 677 678 if (sc->flags & FXP_FLAG_EXT_RFA) { 679 ifp->if_hwassist = FXP_CSUM_FEATURES; 680 ifp->if_capabilities = IFCAP_HWCSUM; 681 ifp->if_capenable = ifp->if_capabilities; 682 } 683 684 /* 685 * Attach the interface. 686 */ 687 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 688 689 /* 690 * Tell the upper layer(s) we support long frames. 691 */ 692 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 693 ifp->if_capabilities |= IFCAP_VLAN_MTU; 694 695 /* 696 * Let the system queue as many packets as we have available 697 * TX descriptors. 698 */ 699 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 700 701 splx(s); 702 return (0); 703 704 failmem: 705 device_printf(dev, "Failed to malloc memory\n"); 706 error = ENOMEM; 707 fail: 708 splx(s); 709 fxp_release(sc); 710 return (error); 711 } 712 713 /* 714 * release all resources 715 */ 716 static void 717 fxp_release(struct fxp_softc *sc) 718 { 719 720 bus_generic_detach(sc->dev); 721 if (sc->miibus) 722 device_delete_child(sc->dev, sc->miibus); 723 724 if (sc->cbl_base) 725 free(sc->cbl_base, M_DEVBUF); 726 if (sc->fxp_stats) 727 free(sc->fxp_stats, M_DEVBUF); 728 if (sc->mcsp) 729 free(sc->mcsp, M_DEVBUF); 730 if (sc->rfa_headm) 731 m_freem(sc->rfa_headm); 732 733 if (sc->ih) 734 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 735 if (sc->irq) 736 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 737 if (sc->mem) 738 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 739 740 sysctl_ctx_free(&sc->sysctl_ctx); 741 742 mtx_destroy(&sc->sc_mtx); 743 } 744 745 /* 746 * Detach interface. 747 */ 748 static int 749 fxp_detach(device_t dev) 750 { 751 struct fxp_softc *sc = device_get_softc(dev); 752 int s; 753 754 /* disable interrupts */ 755 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 756 757 s = splimp(); 758 759 /* 760 * Stop DMA and drop transmit queue. 761 */ 762 fxp_stop(sc); 763 764 /* 765 * Close down routes etc. 766 */ 767 ether_ifdetach(&sc->arpcom.ac_if); 768 769 /* 770 * Free all media structures. 771 */ 772 ifmedia_removeall(&sc->sc_media); 773 774 splx(s); 775 776 /* Release our allocated resources. */ 777 fxp_release(sc); 778 779 return (0); 780 } 781 782 /* 783 * Device shutdown routine. Called at system shutdown after sync. The 784 * main purpose of this routine is to shut off receiver DMA so that 785 * kernel memory doesn't get clobbered during warmboot. 786 */ 787 static int 788 fxp_shutdown(device_t dev) 789 { 790 /* 791 * Make sure that DMA is disabled prior to reboot. Not doing 792 * do could allow DMA to corrupt kernel memory during the 793 * reboot before the driver initializes. 794 */ 795 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 796 return (0); 797 } 798 799 /* 800 * Device suspend routine. Stop the interface and save some PCI 801 * settings in case the BIOS doesn't restore them properly on 802 * resume. 803 */ 804 static int 805 fxp_suspend(device_t dev) 806 { 807 struct fxp_softc *sc = device_get_softc(dev); 808 int i, s; 809 810 s = splimp(); 811 812 fxp_stop(sc); 813 814 for (i = 0; i < 5; i++) 815 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 816 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 817 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 818 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 819 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 820 821 sc->suspended = 1; 822 823 splx(s); 824 return (0); 825 } 826 827 /* 828 * Device resume routine. Restore some PCI settings in case the BIOS 829 * doesn't, re-enable busmastering, and restart the interface if 830 * appropriate. 831 */ 832 static int 833 fxp_resume(device_t dev) 834 { 835 struct fxp_softc *sc = device_get_softc(dev); 836 struct ifnet *ifp = &sc->sc_if; 837 u_int16_t pci_command; 838 int i, s; 839 840 s = splimp(); 841 842 fxp_powerstate_d0(dev); 843 844 /* better way to do this? */ 845 for (i = 0; i < 5; i++) 846 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 847 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 848 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 849 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 850 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 851 852 /* reenable busmastering */ 853 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 854 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 855 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 856 857 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 858 DELAY(10); 859 860 /* reinitialize interface if necessary */ 861 if (ifp->if_flags & IFF_UP) 862 fxp_init(sc); 863 864 sc->suspended = 0; 865 866 splx(s); 867 return (0); 868 } 869 870 static void 871 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 872 { 873 u_int16_t reg; 874 int x; 875 876 /* 877 * Shift in data. 878 */ 879 for (x = 1 << (length - 1); x; x >>= 1) { 880 if (data & x) 881 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 882 else 883 reg = FXP_EEPROM_EECS; 884 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 885 DELAY(1); 886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 887 DELAY(1); 888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 889 DELAY(1); 890 } 891 } 892 893 /* 894 * Read from the serial EEPROM. Basically, you manually shift in 895 * the read opcode (one bit at a time) and then shift in the address, 896 * and then you shift out the data (all of this one bit at a time). 897 * The word size is 16 bits, so you have to provide the address for 898 * every 16 bits of data. 899 */ 900 static u_int16_t 901 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 902 { 903 u_int16_t reg, data; 904 int x; 905 906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 907 /* 908 * Shift in read opcode. 909 */ 910 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 911 /* 912 * Shift in address. 913 */ 914 data = 0; 915 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 916 if (offset & x) 917 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 918 else 919 reg = FXP_EEPROM_EECS; 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 921 DELAY(1); 922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 923 DELAY(1); 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 925 DELAY(1); 926 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 927 data++; 928 if (autosize && reg == 0) { 929 sc->eeprom_size = data; 930 break; 931 } 932 } 933 /* 934 * Shift out data. 935 */ 936 data = 0; 937 reg = FXP_EEPROM_EECS; 938 for (x = 1 << 15; x; x >>= 1) { 939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 940 DELAY(1); 941 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 942 data |= x; 943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 944 DELAY(1); 945 } 946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 947 DELAY(1); 948 949 return (data); 950 } 951 952 static void 953 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 954 { 955 int i; 956 957 /* 958 * Erase/write enable. 959 */ 960 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 961 fxp_eeprom_shiftin(sc, 0x4, 3); 962 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 963 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 964 DELAY(1); 965 /* 966 * Shift in write opcode, address, data. 967 */ 968 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 969 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 970 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 971 fxp_eeprom_shiftin(sc, data, 16); 972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 973 DELAY(1); 974 /* 975 * Wait for EEPROM to finish up. 976 */ 977 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 978 DELAY(1); 979 for (i = 0; i < 1000; i++) { 980 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 981 break; 982 DELAY(50); 983 } 984 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 985 DELAY(1); 986 /* 987 * Erase/write disable. 988 */ 989 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 990 fxp_eeprom_shiftin(sc, 0x4, 3); 991 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 992 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 993 DELAY(1); 994 } 995 996 /* 997 * From NetBSD: 998 * 999 * Figure out EEPROM size. 1000 * 1001 * 559's can have either 64-word or 256-word EEPROMs, the 558 1002 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1003 * talks about the existance of 16 to 256 word EEPROMs. 1004 * 1005 * The only known sizes are 64 and 256, where the 256 version is used 1006 * by CardBus cards to store CIS information. 1007 * 1008 * The address is shifted in msb-to-lsb, and after the last 1009 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1010 * after which follows the actual data. We try to detect this zero, by 1011 * probing the data-out bit in the EEPROM control register just after 1012 * having shifted in a bit. If the bit is zero, we assume we've 1013 * shifted enough address bits. The data-out should be tri-state, 1014 * before this, which should translate to a logical one. 1015 */ 1016 static void 1017 fxp_autosize_eeprom(struct fxp_softc *sc) 1018 { 1019 1020 /* guess maximum size of 256 words */ 1021 sc->eeprom_size = 8; 1022 1023 /* autosize */ 1024 (void) fxp_eeprom_getword(sc, 0, 1); 1025 } 1026 1027 static void 1028 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1029 { 1030 int i; 1031 1032 for (i = 0; i < words; i++) 1033 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1034 } 1035 1036 static void 1037 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1038 { 1039 int i; 1040 1041 for (i = 0; i < words; i++) 1042 fxp_eeprom_putword(sc, offset + i, data[i]); 1043 } 1044 1045 /* 1046 * Start packet transmission on the interface. 1047 */ 1048 static void 1049 fxp_start(struct ifnet *ifp) 1050 { 1051 struct fxp_softc *sc = ifp->if_softc; 1052 struct fxp_cb_tx *txp; 1053 volatile struct fxp_tbd *bdptr; 1054 1055 /* 1056 * See if we need to suspend xmit until the multicast filter 1057 * has been reprogrammed (which can only be done at the head 1058 * of the command chain). 1059 */ 1060 if (sc->need_mcsetup) { 1061 return; 1062 } 1063 1064 txp = NULL; 1065 1066 /* 1067 * We're finished if there is nothing more to add to the list or if 1068 * we're all filled up with buffers to transmit. 1069 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1070 * a NOP command when needed. 1071 */ 1072 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1073 struct mbuf *m, *mb_head; 1074 int segment; 1075 1076 /* 1077 * Grab a packet to transmit. 1078 */ 1079 IF_DEQUEUE(&ifp->if_snd, mb_head); 1080 1081 /* 1082 * Get pointer to next available tx desc. 1083 */ 1084 txp = sc->cbl_last->next; 1085 1086 /* 1087 * If this is an 82550/82551, then we're using extended 1088 * TxCBs _and_ we're using checksum offload. This means 1089 * that the TxCB is really an IPCB. One major difference 1090 * between the two is that with plain extended TxCBs, 1091 * the bottom half of the TxCB contains two entries from 1092 * the TBD array, whereas IPCBs contain just one entry: 1093 * one entry (8 bytes) has been sacrificed for the TCP/IP 1094 * checksum offload control bits. So to make things work 1095 * right, we have to start filling in the TBD array 1096 * starting from a different place depending on whether 1097 * the chip is an 82550/82551 or not. 1098 */ 1099 1100 bdptr = &txp->tbd[0]; 1101 if (sc->flags & FXP_FLAG_EXT_RFA) 1102 bdptr++; 1103 1104 /* 1105 * Deal with TCP/IP checksum offload. Note that 1106 * in order for TCP checksum offload to work, 1107 * the pseudo header checksum must have already 1108 * been computed and stored in the checksum field 1109 * in the TCP header. The stack should have 1110 * already done this for us. 1111 */ 1112 1113 if (mb_head->m_pkthdr.csum_flags) { 1114 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1115 txp->ipcb_ip_activation_high = 1116 FXP_IPCB_HARDWAREPARSING_ENABLE; 1117 txp->ipcb_ip_schedule = 1118 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1119 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1120 txp->ipcb_ip_schedule |= 1121 FXP_IPCB_TCP_PACKET; 1122 } 1123 #ifdef FXP_IP_CSUM_WAR 1124 /* 1125 * XXX The 82550 chip appears to have trouble 1126 * dealing with IP header checksums in very small 1127 * datagrams, namely fragments from 1 to 3 bytes 1128 * in size. For example, say you want to transmit 1129 * a UDP packet of 1473 bytes. The packet will be 1130 * fragmented over two IP datagrams, the latter 1131 * containing only one byte of data. The 82550 will 1132 * botch the header checksum on the 1-byte fragment. 1133 * As long as the datagram contains 4 or more bytes 1134 * of data, you're ok. 1135 * 1136 * The following code attempts to work around this 1137 * problem: if the datagram is less than 38 bytes 1138 * in size (14 bytes ether header, 20 bytes IP header, 1139 * plus 4 bytes of data), we punt and compute the IP 1140 * header checksum by hand. This workaround doesn't 1141 * work very well, however, since it can be fooled 1142 * by things like VLAN tags and IP options that make 1143 * the header sizes/offsets vary. 1144 */ 1145 1146 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1147 if (mb_head->m_pkthdr.len < 38) { 1148 struct ip *ip; 1149 mb_head->m_data += ETHER_HDR_LEN; 1150 ip = mtod(mb_head, struct ip *); 1151 ip->ip_sum = in_cksum(mb_head, 1152 ip->ip_hl << 2); 1153 mb_head->m_data -= ETHER_HDR_LEN; 1154 } else { 1155 txp->ipcb_ip_activation_high = 1156 FXP_IPCB_HARDWAREPARSING_ENABLE; 1157 txp->ipcb_ip_schedule |= 1158 FXP_IPCB_IP_CHECKSUM_ENABLE; 1159 } 1160 } 1161 #endif 1162 } 1163 1164 /* 1165 * Go through each of the mbufs in the chain and initialize 1166 * the transmit buffer descriptors with the physical address 1167 * and size of the mbuf. 1168 */ 1169 tbdinit: 1170 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1171 if (m->m_len != 0) { 1172 if (segment == (FXP_NTXSEG - 1)) 1173 break; 1174 bdptr[segment].tb_addr = 1175 vtophys(mtod(m, vm_offset_t)); 1176 bdptr[segment].tb_size = m->m_len; 1177 segment++; 1178 } 1179 } 1180 if (m != NULL) { 1181 struct mbuf *mn; 1182 1183 /* 1184 * We ran out of segments. We have to recopy this 1185 * mbuf chain first. Bail out if we can't get the 1186 * new buffers. 1187 */ 1188 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1189 if (mn == NULL) { 1190 m_freem(mb_head); 1191 break; 1192 } 1193 if (mb_head->m_pkthdr.len > MHLEN) { 1194 MCLGET(mn, M_DONTWAIT); 1195 if ((mn->m_flags & M_EXT) == 0) { 1196 m_freem(mn); 1197 m_freem(mb_head); 1198 break; 1199 } 1200 } 1201 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1202 mtod(mn, caddr_t)); 1203 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1204 m_freem(mb_head); 1205 mb_head = mn; 1206 goto tbdinit; 1207 } 1208 1209 txp->byte_count = 0; 1210 txp->tbd_number = segment; 1211 txp->mb_head = mb_head; 1212 txp->cb_status = 0; 1213 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1214 txp->cb_command = 1215 sc->tx_cmd | FXP_CB_COMMAND_SF | 1216 FXP_CB_COMMAND_S; 1217 } else { 1218 txp->cb_command = 1219 sc->tx_cmd | FXP_CB_COMMAND_SF | 1220 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1221 /* 1222 * Set a 5 second timer just in case we don't hear 1223 * from the card again. 1224 */ 1225 ifp->if_timer = 5; 1226 } 1227 txp->tx_threshold = tx_threshold; 1228 1229 /* 1230 * Advance the end of list forward. 1231 */ 1232 1233 #ifdef __alpha__ 1234 /* 1235 * On platforms which can't access memory in 16-bit 1236 * granularities, we must prevent the card from DMA'ing 1237 * up the status while we update the command field. 1238 * This could cause us to overwrite the completion status. 1239 */ 1240 atomic_clear_short(&sc->cbl_last->cb_command, 1241 FXP_CB_COMMAND_S); 1242 #else 1243 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1244 #endif /*__alpha__*/ 1245 sc->cbl_last = txp; 1246 1247 /* 1248 * Advance the beginning of the list forward if there are 1249 * no other packets queued (when nothing is queued, cbl_first 1250 * sits on the last TxCB that was sent out). 1251 */ 1252 if (sc->tx_queued == 0) 1253 sc->cbl_first = txp; 1254 1255 sc->tx_queued++; 1256 1257 /* 1258 * Pass packet to bpf if there is a listener. 1259 */ 1260 BPF_MTAP(ifp, mb_head); 1261 } 1262 1263 /* 1264 * We're finished. If we added to the list, issue a RESUME to get DMA 1265 * going again if suspended. 1266 */ 1267 if (txp != NULL) { 1268 fxp_scb_wait(sc); 1269 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1270 } 1271 } 1272 1273 static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1274 1275 #ifdef DEVICE_POLLING 1276 static poll_handler_t fxp_poll; 1277 1278 static void 1279 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1280 { 1281 struct fxp_softc *sc = ifp->if_softc; 1282 u_int8_t statack; 1283 1284 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1285 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1286 return; 1287 } 1288 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1289 FXP_SCB_STATACK_FR; 1290 if (cmd == POLL_AND_CHECK_STATUS) { 1291 u_int8_t tmp; 1292 1293 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1294 if (tmp == 0xff || tmp == 0) 1295 return; /* nothing to do */ 1296 tmp &= ~statack; 1297 /* ack what we can */ 1298 if (tmp != 0) 1299 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1300 statack |= tmp; 1301 } 1302 fxp_intr_body(sc, statack, count); 1303 } 1304 #endif /* DEVICE_POLLING */ 1305 1306 /* 1307 * Process interface interrupts. 1308 */ 1309 static void 1310 fxp_intr(void *xsc) 1311 { 1312 struct fxp_softc *sc = xsc; 1313 u_int8_t statack; 1314 1315 #ifdef DEVICE_POLLING 1316 struct ifnet *ifp = &sc->sc_if; 1317 1318 if (ifp->if_flags & IFF_POLLING) 1319 return; 1320 if (ether_poll_register(fxp_poll, ifp)) { 1321 /* disable interrupts */ 1322 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1323 fxp_poll(ifp, 0, 1); 1324 return; 1325 } 1326 #endif 1327 1328 if (sc->suspended) { 1329 return; 1330 } 1331 1332 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1333 /* 1334 * It should not be possible to have all bits set; the 1335 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1336 * all bits are set, this may indicate that the card has 1337 * been physically ejected, so ignore it. 1338 */ 1339 if (statack == 0xff) 1340 return; 1341 1342 /* 1343 * First ACK all the interrupts in this pass. 1344 */ 1345 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1346 fxp_intr_body(sc, statack, -1); 1347 } 1348 } 1349 1350 static void 1351 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1352 { 1353 struct ifnet *ifp = &sc->sc_if; 1354 struct mbuf *m; 1355 struct fxp_rfa *rfa; 1356 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1357 1358 if (rnr) 1359 fxp_rnr++; 1360 #ifdef DEVICE_POLLING 1361 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1362 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1363 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1364 rnr = 1; 1365 } 1366 #endif 1367 1368 /* 1369 * Free any finished transmit mbuf chains. 1370 * 1371 * Handle the CNA event likt a CXTNO event. It used to 1372 * be that this event (control unit not ready) was not 1373 * encountered, but it is now with the SMPng modifications. 1374 * The exact sequence of events that occur when the interface 1375 * is brought up are different now, and if this event 1376 * goes unhandled, the configuration/rxfilter setup sequence 1377 * can stall for several seconds. The result is that no 1378 * packets go out onto the wire for about 5 to 10 seconds 1379 * after the interface is ifconfig'ed for the first time. 1380 */ 1381 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1382 struct fxp_cb_tx *txp; 1383 1384 for (txp = sc->cbl_first; sc->tx_queued && 1385 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1386 txp = txp->next) { 1387 if (txp->mb_head != NULL) { 1388 m_freem(txp->mb_head); 1389 txp->mb_head = NULL; 1390 /* clear this to reset csum offload bits */ 1391 txp->tbd[0].tb_addr = 0; 1392 } 1393 sc->tx_queued--; 1394 } 1395 sc->cbl_first = txp; 1396 ifp->if_timer = 0; 1397 if (sc->tx_queued == 0) { 1398 if (sc->need_mcsetup) 1399 fxp_mc_setup(sc); 1400 } 1401 /* 1402 * Try to start more packets transmitting. 1403 */ 1404 if (ifp->if_snd.ifq_head != NULL) 1405 fxp_start(ifp); 1406 } 1407 1408 /* 1409 * Just return if nothing happened on the receive side. 1410 */ 1411 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1412 return; 1413 1414 /* 1415 * Process receiver interrupts. If a no-resource (RNR) 1416 * condition exists, get whatever packets we can and 1417 * re-start the receiver. 1418 * 1419 * When using polling, we do not process the list to completion, 1420 * so when we get an RNR interrupt we must defer the restart 1421 * until we hit the last buffer with the C bit set. 1422 * If we run out of cycles and rfa_headm has the C bit set, 1423 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1424 * that the info will be used in the subsequent polling cycle. 1425 */ 1426 for (;;) { 1427 m = sc->rfa_headm; 1428 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1429 RFA_ALIGNMENT_FUDGE); 1430 1431 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1432 if (count >= 0 && count-- == 0) { 1433 if (rnr) { 1434 /* Defer RNR processing until the next time. */ 1435 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1436 rnr = 0; 1437 } 1438 break; 1439 } 1440 #endif /* DEVICE_POLLING */ 1441 1442 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1443 break; 1444 1445 /* 1446 * Remove first packet from the chain. 1447 */ 1448 sc->rfa_headm = m->m_next; 1449 m->m_next = NULL; 1450 1451 /* 1452 * Add a new buffer to the receive chain. 1453 * If this fails, the old buffer is recycled 1454 * instead. 1455 */ 1456 if (fxp_add_rfabuf(sc, m) == 0) { 1457 int total_len; 1458 1459 /* 1460 * Fetch packet length (the top 2 bits of 1461 * actual_size are flags set by the controller 1462 * upon completion), and drop the packet in case 1463 * of bogus length or CRC errors. 1464 */ 1465 total_len = rfa->actual_size & 0x3fff; 1466 if (total_len < sizeof(struct ether_header) || 1467 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1468 sizeof(struct fxp_rfa) || 1469 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1470 m_freem(m); 1471 continue; 1472 } 1473 1474 /* Do IP checksum checking. */ 1475 if (rfa->rfa_status & FXP_RFA_STATUS_PARSE) { 1476 if (rfa->rfax_csum_sts & 1477 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1478 m->m_pkthdr.csum_flags |= 1479 CSUM_IP_CHECKED; 1480 if (rfa->rfax_csum_sts & 1481 FXP_RFDX_CS_IP_CSUM_VALID) 1482 m->m_pkthdr.csum_flags |= 1483 CSUM_IP_VALID; 1484 if ((rfa->rfax_csum_sts & 1485 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1486 (rfa->rfax_csum_sts & 1487 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1488 m->m_pkthdr.csum_flags |= 1489 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1490 m->m_pkthdr.csum_data = 0xffff; 1491 } 1492 } 1493 1494 m->m_pkthdr.len = m->m_len = total_len; 1495 m->m_pkthdr.rcvif = ifp; 1496 1497 (*ifp->if_input)(ifp, m); 1498 } 1499 } 1500 if (rnr) { 1501 fxp_scb_wait(sc); 1502 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1503 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1504 RFA_ALIGNMENT_FUDGE); 1505 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1506 } 1507 } 1508 1509 /* 1510 * Update packet in/out/collision statistics. The i82557 doesn't 1511 * allow you to access these counters without doing a fairly 1512 * expensive DMA to get _all_ of the statistics it maintains, so 1513 * we do this operation here only once per second. The statistics 1514 * counters in the kernel are updated from the previous dump-stats 1515 * DMA and then a new dump-stats DMA is started. The on-chip 1516 * counters are zeroed when the DMA completes. If we can't start 1517 * the DMA immediately, we don't wait - we just prepare to read 1518 * them again next time. 1519 */ 1520 static void 1521 fxp_tick(void *xsc) 1522 { 1523 struct fxp_softc *sc = xsc; 1524 struct ifnet *ifp = &sc->sc_if; 1525 struct fxp_stats *sp = sc->fxp_stats; 1526 struct fxp_cb_tx *txp; 1527 int s; 1528 1529 ifp->if_opackets += sp->tx_good; 1530 ifp->if_collisions += sp->tx_total_collisions; 1531 if (sp->rx_good) { 1532 ifp->if_ipackets += sp->rx_good; 1533 sc->rx_idle_secs = 0; 1534 } else { 1535 /* 1536 * Receiver's been idle for another second. 1537 */ 1538 sc->rx_idle_secs++; 1539 } 1540 ifp->if_ierrors += 1541 sp->rx_crc_errors + 1542 sp->rx_alignment_errors + 1543 sp->rx_rnr_errors + 1544 sp->rx_overrun_errors; 1545 /* 1546 * If any transmit underruns occured, bump up the transmit 1547 * threshold by another 512 bytes (64 * 8). 1548 */ 1549 if (sp->tx_underruns) { 1550 ifp->if_oerrors += sp->tx_underruns; 1551 if (tx_threshold < 192) 1552 tx_threshold += 64; 1553 } 1554 s = splimp(); 1555 /* 1556 * Release any xmit buffers that have completed DMA. This isn't 1557 * strictly necessary to do here, but it's advantagous for mbufs 1558 * with external storage to be released in a timely manner rather 1559 * than being defered for a potentially long time. This limits 1560 * the delay to a maximum of one second. 1561 */ 1562 for (txp = sc->cbl_first; sc->tx_queued && 1563 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1564 txp = txp->next) { 1565 if (txp->mb_head != NULL) { 1566 m_freem(txp->mb_head); 1567 txp->mb_head = NULL; 1568 /* clear this to reset csum offload bits */ 1569 txp->tbd[0].tb_addr = 0; 1570 } 1571 sc->tx_queued--; 1572 } 1573 sc->cbl_first = txp; 1574 /* 1575 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1576 * then assume the receiver has locked up and attempt to clear 1577 * the condition by reprogramming the multicast filter. This is 1578 * a work-around for a bug in the 82557 where the receiver locks 1579 * up if it gets certain types of garbage in the syncronization 1580 * bits prior to the packet header. This bug is supposed to only 1581 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1582 * mode as well (perhaps due to a 10/100 speed transition). 1583 */ 1584 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1585 sc->rx_idle_secs = 0; 1586 fxp_mc_setup(sc); 1587 } 1588 /* 1589 * If there is no pending command, start another stats 1590 * dump. Otherwise punt for now. 1591 */ 1592 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1593 /* 1594 * Start another stats dump. 1595 */ 1596 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1597 } else { 1598 /* 1599 * A previous command is still waiting to be accepted. 1600 * Just zero our copy of the stats and wait for the 1601 * next timer event to update them. 1602 */ 1603 sp->tx_good = 0; 1604 sp->tx_underruns = 0; 1605 sp->tx_total_collisions = 0; 1606 1607 sp->rx_good = 0; 1608 sp->rx_crc_errors = 0; 1609 sp->rx_alignment_errors = 0; 1610 sp->rx_rnr_errors = 0; 1611 sp->rx_overrun_errors = 0; 1612 } 1613 if (sc->miibus != NULL) 1614 mii_tick(device_get_softc(sc->miibus)); 1615 splx(s); 1616 /* 1617 * Schedule another timeout one second from now. 1618 */ 1619 sc->stat_ch = timeout(fxp_tick, sc, hz); 1620 } 1621 1622 /* 1623 * Stop the interface. Cancels the statistics updater and resets 1624 * the interface. 1625 */ 1626 static void 1627 fxp_stop(struct fxp_softc *sc) 1628 { 1629 struct ifnet *ifp = &sc->sc_if; 1630 struct fxp_cb_tx *txp; 1631 int i; 1632 1633 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1634 ifp->if_timer = 0; 1635 1636 #ifdef DEVICE_POLLING 1637 ether_poll_deregister(ifp); 1638 #endif 1639 /* 1640 * Cancel stats updater. 1641 */ 1642 untimeout(fxp_tick, sc, sc->stat_ch); 1643 1644 /* 1645 * Issue software reset, which also unloads the microcode. 1646 */ 1647 sc->flags &= ~FXP_FLAG_UCODE; 1648 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1649 DELAY(50); 1650 1651 /* 1652 * Release any xmit buffers. 1653 */ 1654 txp = sc->cbl_base; 1655 if (txp != NULL) { 1656 for (i = 0; i < FXP_NTXCB; i++) { 1657 if (txp[i].mb_head != NULL) { 1658 m_freem(txp[i].mb_head); 1659 txp[i].mb_head = NULL; 1660 /* clear this to reset csum offload bits */ 1661 txp[i].tbd[0].tb_addr = 0; 1662 } 1663 } 1664 } 1665 sc->tx_queued = 0; 1666 1667 /* 1668 * Free all the receive buffers then reallocate/reinitialize 1669 */ 1670 if (sc->rfa_headm != NULL) 1671 m_freem(sc->rfa_headm); 1672 sc->rfa_headm = NULL; 1673 sc->rfa_tailm = NULL; 1674 for (i = 0; i < FXP_NRFABUFS; i++) { 1675 if (fxp_add_rfabuf(sc, NULL) != 0) { 1676 /* 1677 * This "can't happen" - we're at splimp() 1678 * and we just freed all the buffers we need 1679 * above. 1680 */ 1681 panic("fxp_stop: no buffers!"); 1682 } 1683 } 1684 } 1685 1686 /* 1687 * Watchdog/transmission transmit timeout handler. Called when a 1688 * transmission is started on the interface, but no interrupt is 1689 * received before the timeout. This usually indicates that the 1690 * card has wedged for some reason. 1691 */ 1692 static void 1693 fxp_watchdog(struct ifnet *ifp) 1694 { 1695 struct fxp_softc *sc = ifp->if_softc; 1696 1697 device_printf(sc->dev, "device timeout\n"); 1698 ifp->if_oerrors++; 1699 1700 fxp_init(sc); 1701 } 1702 1703 static void 1704 fxp_init(void *xsc) 1705 { 1706 struct fxp_softc *sc = xsc; 1707 struct ifnet *ifp = &sc->sc_if; 1708 struct fxp_cb_config *cbp; 1709 struct fxp_cb_ias *cb_ias; 1710 struct fxp_cb_tx *txp; 1711 struct fxp_cb_mcs *mcsp; 1712 int i, prm, s; 1713 1714 s = splimp(); 1715 /* 1716 * Cancel any pending I/O 1717 */ 1718 fxp_stop(sc); 1719 1720 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1721 1722 /* 1723 * Initialize base of CBL and RFA memory. Loading with zero 1724 * sets it up for regular linear addressing. 1725 */ 1726 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1727 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1728 1729 fxp_scb_wait(sc); 1730 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1731 1732 /* 1733 * Initialize base of dump-stats buffer. 1734 */ 1735 fxp_scb_wait(sc); 1736 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1737 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1738 1739 /* 1740 * Attempt to load microcode if requested. 1741 */ 1742 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1743 fxp_load_ucode(sc); 1744 1745 /* 1746 * Initialize the multicast address list. 1747 */ 1748 if (fxp_mc_addrs(sc)) { 1749 mcsp = sc->mcsp; 1750 mcsp->cb_status = 0; 1751 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1752 mcsp->link_addr = -1; 1753 /* 1754 * Start the multicast setup command. 1755 */ 1756 fxp_scb_wait(sc); 1757 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1758 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1759 /* ...and wait for it to complete. */ 1760 fxp_dma_wait(&mcsp->cb_status, sc); 1761 } 1762 1763 /* 1764 * We temporarily use memory that contains the TxCB list to 1765 * construct the config CB. The TxCB list memory is rebuilt 1766 * later. 1767 */ 1768 cbp = (struct fxp_cb_config *) sc->cbl_base; 1769 1770 /* 1771 * This bcopy is kind of disgusting, but there are a bunch of must be 1772 * zero and must be one bits in this structure and this is the easiest 1773 * way to initialize them all to proper values. 1774 */ 1775 bcopy(fxp_cb_config_template, 1776 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1777 sizeof(fxp_cb_config_template)); 1778 1779 cbp->cb_status = 0; 1780 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1781 cbp->link_addr = -1; /* (no) next command */ 1782 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 1783 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1784 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1785 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1786 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1787 cbp->type_enable = 0; /* actually reserved */ 1788 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1789 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1790 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1791 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1792 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1793 cbp->late_scb = 0; /* (don't) defer SCB update */ 1794 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1795 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1796 cbp->ci_int = 1; /* interrupt on CU idle */ 1797 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1798 cbp->ext_stats_dis = 1; /* disable extended counters */ 1799 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1800 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1801 cbp->disc_short_rx = !prm; /* discard short packets */ 1802 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1803 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1804 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1805 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1806 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1807 cbp->csma_dis = 0; /* (don't) disable link */ 1808 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1809 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1810 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1811 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1812 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1813 cbp->nsai = 1; /* (don't) disable source addr insert */ 1814 cbp->preamble_length = 2; /* (7 byte) preamble */ 1815 cbp->loopback = 0; /* (don't) loopback */ 1816 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1817 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1818 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1819 cbp->promiscuous = prm; /* promiscuous mode */ 1820 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1821 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1822 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1823 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1824 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1825 1826 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1827 cbp->padding = 1; /* (do) pad short tx packets */ 1828 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1829 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1830 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1831 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1832 /* must set wake_en in PMCSR also */ 1833 cbp->force_fdx = 0; /* (don't) force full duplex */ 1834 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1835 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1836 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1837 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 1838 1839 if (sc->revision == FXP_REV_82557) { 1840 /* 1841 * The 82557 has no hardware flow control, the values 1842 * below are the defaults for the chip. 1843 */ 1844 cbp->fc_delay_lsb = 0; 1845 cbp->fc_delay_msb = 0x40; 1846 cbp->pri_fc_thresh = 3; 1847 cbp->tx_fc_dis = 0; 1848 cbp->rx_fc_restop = 0; 1849 cbp->rx_fc_restart = 0; 1850 cbp->fc_filter = 0; 1851 cbp->pri_fc_loc = 1; 1852 } else { 1853 cbp->fc_delay_lsb = 0x1f; 1854 cbp->fc_delay_msb = 0x01; 1855 cbp->pri_fc_thresh = 3; 1856 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1857 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1858 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1859 cbp->fc_filter = !prm; /* drop FC frames to host */ 1860 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1861 } 1862 1863 /* 1864 * Start the config command/DMA. 1865 */ 1866 fxp_scb_wait(sc); 1867 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1868 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1869 /* ...and wait for it to complete. */ 1870 fxp_dma_wait(&cbp->cb_status, sc); 1871 1872 /* 1873 * Now initialize the station address. Temporarily use the TxCB 1874 * memory area like we did above for the config CB. 1875 */ 1876 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1877 cb_ias->cb_status = 0; 1878 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1879 cb_ias->link_addr = -1; 1880 bcopy(sc->arpcom.ac_enaddr, 1881 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1882 sizeof(sc->arpcom.ac_enaddr)); 1883 1884 /* 1885 * Start the IAS (Individual Address Setup) command/DMA. 1886 */ 1887 fxp_scb_wait(sc); 1888 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1889 /* ...and wait for it to complete. */ 1890 fxp_dma_wait(&cb_ias->cb_status, sc); 1891 1892 /* 1893 * Initialize transmit control block (TxCB) list. 1894 */ 1895 1896 txp = sc->cbl_base; 1897 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1898 for (i = 0; i < FXP_NTXCB; i++) { 1899 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1900 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1901 txp[i].link_addr = 1902 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1903 if (sc->flags & FXP_FLAG_EXT_TXCB) 1904 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1905 else 1906 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1907 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1908 } 1909 /* 1910 * Set the suspend flag on the first TxCB and start the control 1911 * unit. It will execute the NOP and then suspend. 1912 */ 1913 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1914 sc->cbl_first = sc->cbl_last = txp; 1915 sc->tx_queued = 1; 1916 1917 fxp_scb_wait(sc); 1918 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1919 1920 /* 1921 * Initialize receiver buffer area - RFA. 1922 */ 1923 fxp_scb_wait(sc); 1924 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1925 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1926 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1927 1928 /* 1929 * Set current media. 1930 */ 1931 if (sc->miibus != NULL) 1932 mii_mediachg(device_get_softc(sc->miibus)); 1933 1934 ifp->if_flags |= IFF_RUNNING; 1935 ifp->if_flags &= ~IFF_OACTIVE; 1936 1937 /* 1938 * Enable interrupts. 1939 */ 1940 #ifdef DEVICE_POLLING 1941 /* 1942 * ... but only do that if we are not polling. And because (presumably) 1943 * the default is interrupts on, we need to disable them explicitly! 1944 */ 1945 if ( ifp->if_flags & IFF_POLLING ) 1946 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1947 else 1948 #endif /* DEVICE_POLLING */ 1949 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1950 splx(s); 1951 1952 /* 1953 * Start stats updater. 1954 */ 1955 sc->stat_ch = timeout(fxp_tick, sc, hz); 1956 } 1957 1958 static int 1959 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1960 { 1961 1962 return (0); 1963 } 1964 1965 static void 1966 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1967 { 1968 1969 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1970 } 1971 1972 /* 1973 * Change media according to request. 1974 */ 1975 static int 1976 fxp_ifmedia_upd(struct ifnet *ifp) 1977 { 1978 struct fxp_softc *sc = ifp->if_softc; 1979 struct mii_data *mii; 1980 1981 mii = device_get_softc(sc->miibus); 1982 mii_mediachg(mii); 1983 return (0); 1984 } 1985 1986 /* 1987 * Notify the world which media we're using. 1988 */ 1989 static void 1990 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1991 { 1992 struct fxp_softc *sc = ifp->if_softc; 1993 struct mii_data *mii; 1994 1995 mii = device_get_softc(sc->miibus); 1996 mii_pollstat(mii); 1997 ifmr->ifm_active = mii->mii_media_active; 1998 ifmr->ifm_status = mii->mii_media_status; 1999 2000 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2001 sc->cu_resume_bug = 1; 2002 else 2003 sc->cu_resume_bug = 0; 2004 } 2005 2006 /* 2007 * Add a buffer to the end of the RFA buffer list. 2008 * Return 0 if successful, 1 for failure. A failure results in 2009 * adding the 'oldm' (if non-NULL) on to the end of the list - 2010 * tossing out its old contents and recycling it. 2011 * The RFA struct is stuck at the beginning of mbuf cluster and the 2012 * data pointer is fixed up to point just past it. 2013 */ 2014 static int 2015 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 2016 { 2017 u_int32_t v; 2018 struct mbuf *m; 2019 struct fxp_rfa *rfa, *p_rfa; 2020 2021 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2022 if (m == NULL) { /* try to recycle the old mbuf instead */ 2023 if (oldm == NULL) 2024 return 1; 2025 m = oldm; 2026 m->m_data = m->m_ext.ext_buf; 2027 } 2028 2029 /* 2030 * Move the data pointer up so that the incoming data packet 2031 * will be 32-bit aligned. 2032 */ 2033 m->m_data += RFA_ALIGNMENT_FUDGE; 2034 2035 /* 2036 * Get a pointer to the base of the mbuf cluster and move 2037 * data start past it. 2038 */ 2039 rfa = mtod(m, struct fxp_rfa *); 2040 m->m_data += sc->rfa_size; 2041 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - 2042 RFA_ALIGNMENT_FUDGE); 2043 2044 /* 2045 * Initialize the rest of the RFA. Note that since the RFA 2046 * is misaligned, we cannot store values directly. Instead, 2047 * we use an optimized, inline copy. 2048 */ 2049 2050 rfa->rfa_status = 0; 2051 rfa->rfa_control = FXP_RFA_CONTROL_EL; 2052 rfa->actual_size = 0; 2053 2054 v = -1; 2055 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 2056 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 2057 2058 /* 2059 * If there are other buffers already on the list, attach this 2060 * one to the end by fixing up the tail to point to this one. 2061 */ 2062 if (sc->rfa_headm != NULL) { 2063 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 2064 RFA_ALIGNMENT_FUDGE); 2065 sc->rfa_tailm->m_next = m; 2066 v = vtophys(rfa); 2067 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 2068 p_rfa->rfa_control = 0; 2069 } else { 2070 sc->rfa_headm = m; 2071 } 2072 sc->rfa_tailm = m; 2073 2074 return (m == oldm); 2075 } 2076 2077 static volatile int 2078 fxp_miibus_readreg(device_t dev, int phy, int reg) 2079 { 2080 struct fxp_softc *sc = device_get_softc(dev); 2081 int count = 10000; 2082 int value; 2083 2084 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2085 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2086 2087 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2088 && count--) 2089 DELAY(10); 2090 2091 if (count <= 0) 2092 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2093 2094 return (value & 0xffff); 2095 } 2096 2097 static void 2098 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2099 { 2100 struct fxp_softc *sc = device_get_softc(dev); 2101 int count = 10000; 2102 2103 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2104 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2105 (value & 0xffff)); 2106 2107 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2108 count--) 2109 DELAY(10); 2110 2111 if (count <= 0) 2112 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2113 } 2114 2115 static int 2116 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2117 { 2118 struct fxp_softc *sc = ifp->if_softc; 2119 struct ifreq *ifr = (struct ifreq *)data; 2120 struct mii_data *mii; 2121 int s, error = 0; 2122 2123 s = splimp(); 2124 2125 switch (command) { 2126 case SIOCSIFFLAGS: 2127 if (ifp->if_flags & IFF_ALLMULTI) 2128 sc->flags |= FXP_FLAG_ALL_MCAST; 2129 else 2130 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2131 2132 /* 2133 * If interface is marked up and not running, then start it. 2134 * If it is marked down and running, stop it. 2135 * XXX If it's up then re-initialize it. This is so flags 2136 * such as IFF_PROMISC are handled. 2137 */ 2138 if (ifp->if_flags & IFF_UP) { 2139 fxp_init(sc); 2140 } else { 2141 if (ifp->if_flags & IFF_RUNNING) 2142 fxp_stop(sc); 2143 } 2144 break; 2145 2146 case SIOCADDMULTI: 2147 case SIOCDELMULTI: 2148 if (ifp->if_flags & IFF_ALLMULTI) 2149 sc->flags |= FXP_FLAG_ALL_MCAST; 2150 else 2151 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2152 /* 2153 * Multicast list has changed; set the hardware filter 2154 * accordingly. 2155 */ 2156 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2157 fxp_mc_setup(sc); 2158 /* 2159 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2160 * again rather than else {}. 2161 */ 2162 if (sc->flags & FXP_FLAG_ALL_MCAST) 2163 fxp_init(sc); 2164 error = 0; 2165 break; 2166 2167 case SIOCSIFMEDIA: 2168 case SIOCGIFMEDIA: 2169 if (sc->miibus != NULL) { 2170 mii = device_get_softc(sc->miibus); 2171 error = ifmedia_ioctl(ifp, ifr, 2172 &mii->mii_media, command); 2173 } else { 2174 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2175 } 2176 break; 2177 2178 default: 2179 error = ether_ioctl(ifp, command, data); 2180 } 2181 splx(s); 2182 return (error); 2183 } 2184 2185 /* 2186 * Fill in the multicast address list and return number of entries. 2187 */ 2188 static int 2189 fxp_mc_addrs(struct fxp_softc *sc) 2190 { 2191 struct fxp_cb_mcs *mcsp = sc->mcsp; 2192 struct ifnet *ifp = &sc->sc_if; 2193 struct ifmultiaddr *ifma; 2194 int nmcasts; 2195 2196 nmcasts = 0; 2197 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2198 #if __FreeBSD_version < 500000 2199 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2200 #else 2201 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2202 #endif 2203 if (ifma->ifma_addr->sa_family != AF_LINK) 2204 continue; 2205 if (nmcasts >= MAXMCADDR) { 2206 sc->flags |= FXP_FLAG_ALL_MCAST; 2207 nmcasts = 0; 2208 break; 2209 } 2210 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2211 (void *)(uintptr_t)(volatile void *) 2212 &sc->mcsp->mc_addr[nmcasts][0], 6); 2213 nmcasts++; 2214 } 2215 } 2216 mcsp->mc_cnt = nmcasts * 6; 2217 return (nmcasts); 2218 } 2219 2220 /* 2221 * Program the multicast filter. 2222 * 2223 * We have an artificial restriction that the multicast setup command 2224 * must be the first command in the chain, so we take steps to ensure 2225 * this. By requiring this, it allows us to keep up the performance of 2226 * the pre-initialized command ring (esp. link pointers) by not actually 2227 * inserting the mcsetup command in the ring - i.e. its link pointer 2228 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2229 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2230 * lead into the regular TxCB ring when it completes. 2231 * 2232 * This function must be called at splimp. 2233 */ 2234 static void 2235 fxp_mc_setup(struct fxp_softc *sc) 2236 { 2237 struct fxp_cb_mcs *mcsp = sc->mcsp; 2238 struct ifnet *ifp = &sc->sc_if; 2239 int count; 2240 2241 /* 2242 * If there are queued commands, we must wait until they are all 2243 * completed. If we are already waiting, then add a NOP command 2244 * with interrupt option so that we're notified when all commands 2245 * have been completed - fxp_start() ensures that no additional 2246 * TX commands will be added when need_mcsetup is true. 2247 */ 2248 if (sc->tx_queued) { 2249 struct fxp_cb_tx *txp; 2250 2251 /* 2252 * need_mcsetup will be true if we are already waiting for the 2253 * NOP command to be completed (see below). In this case, bail. 2254 */ 2255 if (sc->need_mcsetup) 2256 return; 2257 sc->need_mcsetup = 1; 2258 2259 /* 2260 * Add a NOP command with interrupt so that we are notified 2261 * when all TX commands have been processed. 2262 */ 2263 txp = sc->cbl_last->next; 2264 txp->mb_head = NULL; 2265 txp->cb_status = 0; 2266 txp->cb_command = FXP_CB_COMMAND_NOP | 2267 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2268 /* 2269 * Advance the end of list forward. 2270 */ 2271 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2272 sc->cbl_last = txp; 2273 sc->tx_queued++; 2274 /* 2275 * Issue a resume in case the CU has just suspended. 2276 */ 2277 fxp_scb_wait(sc); 2278 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2279 /* 2280 * Set a 5 second timer just in case we don't hear from the 2281 * card again. 2282 */ 2283 ifp->if_timer = 5; 2284 2285 return; 2286 } 2287 sc->need_mcsetup = 0; 2288 2289 /* 2290 * Initialize multicast setup descriptor. 2291 */ 2292 mcsp->next = sc->cbl_base; 2293 mcsp->mb_head = NULL; 2294 mcsp->cb_status = 0; 2295 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2296 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2297 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2298 (void) fxp_mc_addrs(sc); 2299 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2300 sc->tx_queued = 1; 2301 2302 /* 2303 * Wait until command unit is not active. This should never 2304 * be the case when nothing is queued, but make sure anyway. 2305 */ 2306 count = 100; 2307 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2308 FXP_SCB_CUS_ACTIVE && --count) 2309 DELAY(10); 2310 if (count == 0) { 2311 device_printf(sc->dev, "command queue timeout\n"); 2312 return; 2313 } 2314 2315 /* 2316 * Start the multicast setup command. 2317 */ 2318 fxp_scb_wait(sc); 2319 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2320 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2321 2322 ifp->if_timer = 2; 2323 return; 2324 } 2325 2326 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2327 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2328 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2329 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2330 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2331 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2332 2333 #define UCODE(x) x, sizeof(x) 2334 2335 struct ucode { 2336 u_int32_t revision; 2337 u_int32_t *ucode; 2338 int length; 2339 u_short int_delay_offset; 2340 u_short bundle_max_offset; 2341 } ucode_table[] = { 2342 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2343 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2344 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2345 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2346 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2347 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2348 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2349 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2350 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2351 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2352 { 0, NULL, 0, 0, 0 } 2353 }; 2354 2355 static void 2356 fxp_load_ucode(struct fxp_softc *sc) 2357 { 2358 struct ucode *uc; 2359 struct fxp_cb_ucode *cbp; 2360 2361 for (uc = ucode_table; uc->ucode != NULL; uc++) 2362 if (sc->revision == uc->revision) 2363 break; 2364 if (uc->ucode == NULL) 2365 return; 2366 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2367 cbp->cb_status = 0; 2368 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2369 cbp->link_addr = -1; /* (no) next command */ 2370 memcpy(cbp->ucode, uc->ucode, uc->length); 2371 if (uc->int_delay_offset) 2372 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2373 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2374 if (uc->bundle_max_offset) 2375 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2376 sc->tunable_bundle_max; 2377 /* 2378 * Download the ucode to the chip. 2379 */ 2380 fxp_scb_wait(sc); 2381 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2382 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2383 /* ...and wait for it to complete. */ 2384 fxp_dma_wait(&cbp->cb_status, sc); 2385 device_printf(sc->dev, 2386 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2387 sc->tunable_int_delay, 2388 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2389 sc->flags |= FXP_FLAG_UCODE; 2390 } 2391 2392 static int 2393 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2394 { 2395 int error, value; 2396 2397 value = *(int *)arg1; 2398 error = sysctl_handle_int(oidp, &value, 0, req); 2399 if (error || !req->newptr) 2400 return (error); 2401 if (value < low || value > high) 2402 return (EINVAL); 2403 *(int *)arg1 = value; 2404 return (0); 2405 } 2406 2407 /* 2408 * Interrupt delay is expressed in microseconds, a multiplier is used 2409 * to convert this to the appropriate clock ticks before using. 2410 */ 2411 static int 2412 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2413 { 2414 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2415 } 2416 2417 static int 2418 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2419 { 2420 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2421 } 2422