1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/endian.h> 44 #include <sys/mbuf.h> 45 /* #include <sys/mutex.h> */ 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 55 #include <net/bpf.h> 56 #include <sys/sockio.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 69 #ifdef FXP_IP_CSUM_WAR 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/ip.h> 73 #include <machine/in_cksum.h> 74 #endif 75 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 82 #include <dev/fxp/if_fxpreg.h> 83 #include <dev/fxp/if_fxpvar.h> 84 #include <dev/fxp/rcvbundl.h> 85 86 MODULE_DEPEND(fxp, pci, 1, 1, 1); 87 MODULE_DEPEND(fxp, ether, 1, 1, 1); 88 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 89 #include "miibus_if.h" 90 91 /* 92 * NOTE! On the Alpha, we have an alignment constraint. The 93 * card DMAs the packet immediately following the RFA. However, 94 * the first thing in the packet is a 14-byte Ethernet header. 95 * This means that the packet is misaligned. To compensate, 96 * we actually offset the RFA 2 bytes into the cluster. This 97 * alignes the packet after the Ethernet header at a 32-bit 98 * boundary. HOWEVER! This means that the RFA is misaligned! 99 */ 100 #define RFA_ALIGNMENT_FUDGE 2 101 102 /* 103 * Set initial transmit threshold at 64 (512 bytes). This is 104 * increased by 64 (512 bytes) at a time, to maximum of 192 105 * (1536 bytes), if an underrun occurs. 106 */ 107 static int tx_threshold = 64; 108 109 /* 110 * The configuration byte map has several undefined fields which 111 * must be one or must be zero. Set up a template for these bits 112 * only, (assuming a 82557 chip) leaving the actual configuration 113 * to fxp_init. 114 * 115 * See struct fxp_cb_config for the bit definitions. 116 */ 117 static u_char fxp_cb_config_template[] = { 118 0x0, 0x0, /* cb_status */ 119 0x0, 0x0, /* cb_command */ 120 0x0, 0x0, 0x0, 0x0, /* link_addr */ 121 0x0, /* 0 */ 122 0x0, /* 1 */ 123 0x0, /* 2 */ 124 0x0, /* 3 */ 125 0x0, /* 4 */ 126 0x0, /* 5 */ 127 0x32, /* 6 */ 128 0x0, /* 7 */ 129 0x0, /* 8 */ 130 0x0, /* 9 */ 131 0x6, /* 10 */ 132 0x0, /* 11 */ 133 0x0, /* 12 */ 134 0x0, /* 13 */ 135 0xf2, /* 14 */ 136 0x48, /* 15 */ 137 0x0, /* 16 */ 138 0x40, /* 17 */ 139 0xf0, /* 18 */ 140 0x0, /* 19 */ 141 0x3f, /* 20 */ 142 0x5 /* 21 */ 143 }; 144 145 struct fxp_ident { 146 uint16_t devid; 147 int16_t revid; /* -1 matches anything */ 148 char *name; 149 }; 150 151 /* 152 * Claim various Intel PCI device identifiers for this driver. The 153 * sub-vendor and sub-device field are extensively used to identify 154 * particular variants, but we don't currently differentiate between 155 * them. 156 */ 157 static struct fxp_ident fxp_ident_table[] = { 158 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 159 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 160 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 161 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 162 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 166 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 167 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 168 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 170 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 172 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 173 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 174 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 175 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 176 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 177 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 178 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 179 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 180 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 181 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 182 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 183 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 184 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 185 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 186 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 187 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 188 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 189 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 190 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 191 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 192 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 193 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 194 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 195 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 196 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 197 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 198 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 199 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 200 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 201 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 202 { 0, -1, NULL }, 203 }; 204 205 #ifdef FXP_IP_CSUM_WAR 206 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 207 #else 208 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 209 #endif 210 211 static int fxp_probe(device_t dev); 212 static int fxp_attach(device_t dev); 213 static int fxp_detach(device_t dev); 214 static int fxp_shutdown(device_t dev); 215 static int fxp_suspend(device_t dev); 216 static int fxp_resume(device_t dev); 217 218 static void fxp_intr(void *xsc); 219 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 220 uint8_t statack, int count); 221 static void fxp_init(void *xsc); 222 static void fxp_init_body(struct fxp_softc *sc); 223 static void fxp_tick(void *xsc); 224 static void fxp_start(struct ifnet *ifp); 225 static void fxp_start_body(struct ifnet *ifp); 226 static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 227 static void fxp_stop(struct fxp_softc *sc); 228 static void fxp_release(struct fxp_softc *sc); 229 static int fxp_ioctl(struct ifnet *ifp, u_long command, 230 caddr_t data); 231 static void fxp_watchdog(struct fxp_softc *sc); 232 static int fxp_add_rfabuf(struct fxp_softc *sc, 233 struct fxp_rx *rxp); 234 static int fxp_mc_addrs(struct fxp_softc *sc); 235 static void fxp_mc_setup(struct fxp_softc *sc); 236 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 237 int autosize); 238 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 239 uint16_t data); 240 static void fxp_autosize_eeprom(struct fxp_softc *sc); 241 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 242 int offset, int words); 243 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 244 int offset, int words); 245 static int fxp_ifmedia_upd(struct ifnet *ifp); 246 static void fxp_ifmedia_sts(struct ifnet *ifp, 247 struct ifmediareq *ifmr); 248 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 249 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 250 struct ifmediareq *ifmr); 251 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 252 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 253 int value); 254 static void fxp_load_ucode(struct fxp_softc *sc); 255 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 256 int low, int high); 257 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 258 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 259 static void fxp_scb_wait(struct fxp_softc *sc); 260 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 261 static void fxp_dma_wait(struct fxp_softc *sc, 262 volatile uint16_t *status, bus_dma_tag_t dmat, 263 bus_dmamap_t map); 264 265 static device_method_t fxp_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, fxp_probe), 268 DEVMETHOD(device_attach, fxp_attach), 269 DEVMETHOD(device_detach, fxp_detach), 270 DEVMETHOD(device_shutdown, fxp_shutdown), 271 DEVMETHOD(device_suspend, fxp_suspend), 272 DEVMETHOD(device_resume, fxp_resume), 273 274 /* MII interface */ 275 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 276 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 277 278 { 0, 0 } 279 }; 280 281 static driver_t fxp_driver = { 282 "fxp", 283 fxp_methods, 284 sizeof(struct fxp_softc), 285 }; 286 287 static devclass_t fxp_devclass; 288 289 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 290 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 291 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 292 293 static struct resource_spec fxp_res_spec_mem[] = { 294 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 295 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 296 { -1, 0 } 297 }; 298 299 static struct resource_spec fxp_res_spec_io[] = { 300 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 301 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 302 { -1, 0 } 303 }; 304 305 /* 306 * Wait for the previous command to be accepted (but not necessarily 307 * completed). 308 */ 309 static void 310 fxp_scb_wait(struct fxp_softc *sc) 311 { 312 union { 313 uint16_t w; 314 uint8_t b[2]; 315 } flowctl; 316 int i = 10000; 317 318 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 319 DELAY(2); 320 if (i == 0) { 321 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 322 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 323 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 324 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 325 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 326 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 327 } 328 } 329 330 static void 331 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 332 { 333 334 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 335 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 336 fxp_scb_wait(sc); 337 } 338 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 339 } 340 341 static void 342 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 343 bus_dma_tag_t dmat, bus_dmamap_t map) 344 { 345 int i = 10000; 346 347 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 348 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 349 DELAY(2); 350 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 351 } 352 if (i == 0) 353 device_printf(sc->dev, "DMA timeout\n"); 354 } 355 356 /* 357 * Return identification string if this device is ours. 358 */ 359 static int 360 fxp_probe(device_t dev) 361 { 362 uint16_t devid; 363 uint8_t revid; 364 struct fxp_ident *ident; 365 366 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 367 devid = pci_get_device(dev); 368 revid = pci_get_revid(dev); 369 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 370 if (ident->devid == devid && 371 (ident->revid == revid || ident->revid == -1)) { 372 device_set_desc(dev, ident->name); 373 return (BUS_PROBE_DEFAULT); 374 } 375 } 376 } 377 return (ENXIO); 378 } 379 380 static void 381 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 382 { 383 uint32_t *addr; 384 385 if (error) 386 return; 387 388 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 389 addr = arg; 390 *addr = segs->ds_addr; 391 } 392 393 static int 394 fxp_attach(device_t dev) 395 { 396 struct fxp_softc *sc; 397 struct fxp_cb_tx *tcbp; 398 struct fxp_tx *txp; 399 struct fxp_rx *rxp; 400 struct ifnet *ifp; 401 uint32_t val; 402 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 403 u_char eaddr[ETHER_ADDR_LEN]; 404 int i, prefer_iomap; 405 int error; 406 407 error = 0; 408 sc = device_get_softc(dev); 409 sc->dev = dev; 410 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 411 MTX_DEF); 412 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 413 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 414 fxp_serial_ifmedia_sts); 415 416 ifp = sc->ifp = if_alloc(IFT_ETHER); 417 if (ifp == NULL) { 418 device_printf(dev, "can not if_alloc()\n"); 419 error = ENOSPC; 420 goto fail; 421 } 422 423 /* 424 * Enable bus mastering. 425 */ 426 pci_enable_busmaster(dev); 427 val = pci_read_config(dev, PCIR_COMMAND, 2); 428 429 /* 430 * Figure out which we should try first - memory mapping or i/o mapping? 431 * We default to memory mapping. Then we accept an override from the 432 * command line. Then we check to see which one is enabled. 433 */ 434 prefer_iomap = 0; 435 resource_int_value(device_get_name(dev), device_get_unit(dev), 436 "prefer_iomap", &prefer_iomap); 437 if (prefer_iomap) 438 sc->fxp_spec = fxp_res_spec_io; 439 else 440 sc->fxp_spec = fxp_res_spec_mem; 441 442 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 443 if (error) { 444 if (sc->fxp_spec == fxp_res_spec_mem) 445 sc->fxp_spec = fxp_res_spec_io; 446 else 447 sc->fxp_spec = fxp_res_spec_mem; 448 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 449 } 450 if (error) { 451 device_printf(dev, "could not allocate resources\n"); 452 error = ENXIO; 453 goto fail; 454 } 455 456 if (bootverbose) { 457 device_printf(dev, "using %s space register mapping\n", 458 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 459 } 460 461 /* 462 * Reset to a stable state. 463 */ 464 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 465 DELAY(10); 466 467 /* 468 * Find out how large of an SEEPROM we have. 469 */ 470 fxp_autosize_eeprom(sc); 471 472 /* 473 * Find out the chip revision; lump all 82557 revs together. 474 */ 475 fxp_read_eeprom(sc, &data, 5, 1); 476 if ((data >> 8) == 1) 477 sc->revision = FXP_REV_82557; 478 else 479 sc->revision = pci_get_revid(dev); 480 481 /* 482 * Determine whether we must use the 503 serial interface. 483 */ 484 fxp_read_eeprom(sc, &data, 6, 1); 485 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 486 && (data & FXP_PHY_SERIAL_ONLY)) 487 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 488 489 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 490 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 491 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 492 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 493 "FXP driver receive interrupt microcode bundling delay"); 494 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 495 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 496 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 497 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 498 "FXP driver receive interrupt microcode bundle size limit"); 499 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 501 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 502 "FXP RNR events"); 503 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 505 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 506 "FXP flow control disabled"); 507 508 /* 509 * Pull in device tunables. 510 */ 511 sc->tunable_int_delay = TUNABLE_INT_DELAY; 512 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 513 sc->tunable_noflow = 1; 514 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 515 "int_delay", &sc->tunable_int_delay); 516 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 517 "bundle_max", &sc->tunable_bundle_max); 518 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 519 "noflow", &sc->tunable_noflow); 520 sc->rnr = 0; 521 522 /* 523 * Enable workarounds for certain chip revision deficiencies. 524 * 525 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 526 * some systems based a normal 82559 design, have a defect where 527 * the chip can cause a PCI protocol violation if it receives 528 * a CU_RESUME command when it is entering the IDLE state. The 529 * workaround is to disable Dynamic Standby Mode, so the chip never 530 * deasserts CLKRUN#, and always remains in an active state. 531 * 532 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 533 */ 534 i = pci_get_device(dev); 535 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 536 sc->revision >= FXP_REV_82559_A0) { 537 fxp_read_eeprom(sc, &data, 10, 1); 538 if (data & 0x02) { /* STB enable */ 539 uint16_t cksum; 540 int i; 541 542 device_printf(dev, 543 "Disabling dynamic standby mode in EEPROM\n"); 544 data &= ~0x02; 545 fxp_write_eeprom(sc, &data, 10, 1); 546 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 547 cksum = 0; 548 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 549 fxp_read_eeprom(sc, &data, i, 1); 550 cksum += data; 551 } 552 i = (1 << sc->eeprom_size) - 1; 553 cksum = 0xBABA - cksum; 554 fxp_read_eeprom(sc, &data, i, 1); 555 fxp_write_eeprom(sc, &cksum, i, 1); 556 device_printf(dev, 557 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 558 i, data, cksum); 559 #if 1 560 /* 561 * If the user elects to continue, try the software 562 * workaround, as it is better than nothing. 563 */ 564 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 565 #endif 566 } 567 } 568 569 /* 570 * If we are not a 82557 chip, we can enable extended features. 571 */ 572 if (sc->revision != FXP_REV_82557) { 573 /* 574 * If MWI is enabled in the PCI configuration, and there 575 * is a valid cacheline size (8 or 16 dwords), then tell 576 * the board to turn on MWI. 577 */ 578 if (val & PCIM_CMD_MWRICEN && 579 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 580 sc->flags |= FXP_FLAG_MWI_ENABLE; 581 582 /* turn on the extended TxCB feature */ 583 sc->flags |= FXP_FLAG_EXT_TXCB; 584 585 /* enable reception of long frames for VLAN */ 586 sc->flags |= FXP_FLAG_LONG_PKT_EN; 587 } else { 588 /* a hack to get long VLAN frames on a 82557 */ 589 sc->flags |= FXP_FLAG_SAVE_BAD; 590 } 591 592 /* 593 * Enable use of extended RFDs and TCBs for 82550 594 * and later chips. Note: we need extended TXCB support 595 * too, but that's already enabled by the code above. 596 * Be careful to do this only on the right devices. 597 */ 598 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 599 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 600 || sc->revision == FXP_REV_82551_10) { 601 sc->rfa_size = sizeof (struct fxp_rfa); 602 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 603 sc->flags |= FXP_FLAG_EXT_RFA; 604 } else { 605 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 606 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 607 } 608 609 /* 610 * Allocate DMA tags and DMA safe memory. 611 */ 612 sc->maxtxseg = FXP_NTXSEG; 613 if (sc->flags & FXP_FLAG_EXT_RFA) 614 sc->maxtxseg--; 615 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 616 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 617 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 618 &sc->fxp_mtag); 619 if (error) { 620 device_printf(dev, "could not allocate dma tag\n"); 621 goto fail; 622 } 623 624 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 625 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 626 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 627 &sc->fxp_stag); 628 if (error) { 629 device_printf(dev, "could not allocate dma tag\n"); 630 goto fail; 631 } 632 633 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 634 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 635 if (error) 636 goto fail; 637 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 638 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 639 if (error) { 640 device_printf(dev, "could not map the stats buffer\n"); 641 goto fail; 642 } 643 644 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 645 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 646 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 647 if (error) { 648 device_printf(dev, "could not allocate dma tag\n"); 649 goto fail; 650 } 651 652 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 653 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 654 if (error) 655 goto fail; 656 657 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 658 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 659 &sc->fxp_desc.cbl_addr, 0); 660 if (error) { 661 device_printf(dev, "could not map DMA memory\n"); 662 goto fail; 663 } 664 665 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 666 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 667 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 668 &sc->mcs_tag); 669 if (error) { 670 device_printf(dev, "could not allocate dma tag\n"); 671 goto fail; 672 } 673 674 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 675 BUS_DMA_NOWAIT, &sc->mcs_map); 676 if (error) 677 goto fail; 678 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 679 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 680 if (error) { 681 device_printf(dev, "can't map the multicast setup command\n"); 682 goto fail; 683 } 684 685 /* 686 * Pre-allocate the TX DMA maps and setup the pointers to 687 * the TX command blocks. 688 */ 689 txp = sc->fxp_desc.tx_list; 690 tcbp = sc->fxp_desc.cbl_list; 691 for (i = 0; i < FXP_NTXCB; i++) { 692 txp[i].tx_cb = tcbp + i; 693 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 694 if (error) { 695 device_printf(dev, "can't create DMA map for TX\n"); 696 goto fail; 697 } 698 } 699 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 700 if (error) { 701 device_printf(dev, "can't create spare DMA map\n"); 702 goto fail; 703 } 704 705 /* 706 * Pre-allocate our receive buffers. 707 */ 708 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 709 for (i = 0; i < FXP_NRFABUFS; i++) { 710 rxp = &sc->fxp_desc.rx_list[i]; 711 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 712 if (error) { 713 device_printf(dev, "can't create DMA map for RX\n"); 714 goto fail; 715 } 716 if (fxp_add_rfabuf(sc, rxp) != 0) { 717 error = ENOMEM; 718 goto fail; 719 } 720 } 721 722 /* 723 * Read MAC address. 724 */ 725 fxp_read_eeprom(sc, myea, 0, 3); 726 eaddr[0] = myea[0] & 0xff; 727 eaddr[1] = myea[0] >> 8; 728 eaddr[2] = myea[1] & 0xff; 729 eaddr[3] = myea[1] >> 8; 730 eaddr[4] = myea[2] & 0xff; 731 eaddr[5] = myea[2] >> 8; 732 if (bootverbose) { 733 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 734 pci_get_vendor(dev), pci_get_device(dev), 735 pci_get_subvendor(dev), pci_get_subdevice(dev), 736 pci_get_revid(dev)); 737 fxp_read_eeprom(sc, &data, 10, 1); 738 device_printf(dev, "Dynamic Standby mode is %s\n", 739 data & 0x02 ? "enabled" : "disabled"); 740 } 741 742 /* 743 * If this is only a 10Mbps device, then there is no MII, and 744 * the PHY will use a serial interface instead. 745 * 746 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 747 * doesn't have a programming interface of any sort. The 748 * media is sensed automatically based on how the link partner 749 * is configured. This is, in essence, manual configuration. 750 */ 751 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 752 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 753 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 754 } else { 755 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 756 fxp_ifmedia_sts)) { 757 device_printf(dev, "MII without any PHY!\n"); 758 error = ENXIO; 759 goto fail; 760 } 761 } 762 763 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 764 ifp->if_init = fxp_init; 765 ifp->if_softc = sc; 766 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 767 ifp->if_ioctl = fxp_ioctl; 768 ifp->if_start = fxp_start; 769 770 ifp->if_capabilities = ifp->if_capenable = 0; 771 772 /* Enable checksum offload for 82550 or better chips */ 773 if (sc->flags & FXP_FLAG_EXT_RFA) { 774 ifp->if_hwassist = FXP_CSUM_FEATURES; 775 ifp->if_capabilities |= IFCAP_HWCSUM; 776 ifp->if_capenable |= IFCAP_HWCSUM; 777 } 778 779 #ifdef DEVICE_POLLING 780 /* Inform the world we support polling. */ 781 ifp->if_capabilities |= IFCAP_POLLING; 782 #endif 783 784 /* 785 * Attach the interface. 786 */ 787 ether_ifattach(ifp, eaddr); 788 789 /* 790 * Tell the upper layer(s) we support long frames. 791 * Must appear after the call to ether_ifattach() because 792 * ether_ifattach() sets ifi_hdrlen to the default value. 793 */ 794 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 795 ifp->if_capabilities |= IFCAP_VLAN_MTU; 796 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 797 798 /* 799 * Let the system queue as many packets as we have available 800 * TX descriptors. 801 */ 802 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 803 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 804 IFQ_SET_READY(&ifp->if_snd); 805 806 /* 807 * Hook our interrupt after all initialization is complete. 808 */ 809 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 810 fxp_intr, sc, &sc->ih); 811 if (error) { 812 device_printf(dev, "could not setup irq\n"); 813 ether_ifdetach(sc->ifp); 814 goto fail; 815 } 816 817 fail: 818 if (error) 819 fxp_release(sc); 820 return (error); 821 } 822 823 /* 824 * Release all resources. The softc lock should not be held and the 825 * interrupt should already be torn down. 826 */ 827 static void 828 fxp_release(struct fxp_softc *sc) 829 { 830 struct fxp_rx *rxp; 831 struct fxp_tx *txp; 832 int i; 833 834 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 835 KASSERT(sc->ih == NULL, 836 ("fxp_release() called with intr handle still active")); 837 if (sc->miibus) 838 device_delete_child(sc->dev, sc->miibus); 839 bus_generic_detach(sc->dev); 840 ifmedia_removeall(&sc->sc_media); 841 if (sc->fxp_desc.cbl_list) { 842 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 843 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 844 sc->cbl_map); 845 } 846 if (sc->fxp_stats) { 847 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 848 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 849 } 850 if (sc->mcsp) { 851 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 852 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 853 } 854 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 855 if (sc->fxp_mtag) { 856 for (i = 0; i < FXP_NRFABUFS; i++) { 857 rxp = &sc->fxp_desc.rx_list[i]; 858 if (rxp->rx_mbuf != NULL) { 859 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 860 BUS_DMASYNC_POSTREAD); 861 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 862 m_freem(rxp->rx_mbuf); 863 } 864 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 865 } 866 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 867 for (i = 0; i < FXP_NTXCB; i++) { 868 txp = &sc->fxp_desc.tx_list[i]; 869 if (txp->tx_mbuf != NULL) { 870 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 871 BUS_DMASYNC_POSTWRITE); 872 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 873 m_freem(txp->tx_mbuf); 874 } 875 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 876 } 877 bus_dma_tag_destroy(sc->fxp_mtag); 878 } 879 if (sc->fxp_stag) 880 bus_dma_tag_destroy(sc->fxp_stag); 881 if (sc->cbl_tag) 882 bus_dma_tag_destroy(sc->cbl_tag); 883 if (sc->mcs_tag) 884 bus_dma_tag_destroy(sc->mcs_tag); 885 if (sc->ifp) 886 if_free(sc->ifp); 887 888 mtx_destroy(&sc->sc_mtx); 889 } 890 891 /* 892 * Detach interface. 893 */ 894 static int 895 fxp_detach(device_t dev) 896 { 897 struct fxp_softc *sc = device_get_softc(dev); 898 899 #ifdef DEVICE_POLLING 900 if (sc->ifp->if_capenable & IFCAP_POLLING) 901 ether_poll_deregister(sc->ifp); 902 #endif 903 904 FXP_LOCK(sc); 905 sc->suspended = 1; /* Do same thing as we do for suspend */ 906 /* 907 * Stop DMA and drop transmit queue, but disable interrupts first. 908 */ 909 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 910 fxp_stop(sc); 911 FXP_UNLOCK(sc); 912 callout_drain(&sc->stat_ch); 913 914 /* 915 * Close down routes etc. 916 */ 917 ether_ifdetach(sc->ifp); 918 919 /* 920 * Unhook interrupt before dropping lock. This is to prevent 921 * races with fxp_intr(). 922 */ 923 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 924 sc->ih = NULL; 925 926 /* Release our allocated resources. */ 927 fxp_release(sc); 928 return (0); 929 } 930 931 /* 932 * Device shutdown routine. Called at system shutdown after sync. The 933 * main purpose of this routine is to shut off receiver DMA so that 934 * kernel memory doesn't get clobbered during warmboot. 935 */ 936 static int 937 fxp_shutdown(device_t dev) 938 { 939 struct fxp_softc *sc = device_get_softc(dev); 940 941 /* 942 * Make sure that DMA is disabled prior to reboot. Not doing 943 * do could allow DMA to corrupt kernel memory during the 944 * reboot before the driver initializes. 945 */ 946 FXP_LOCK(sc); 947 fxp_stop(sc); 948 FXP_UNLOCK(sc); 949 return (0); 950 } 951 952 /* 953 * Device suspend routine. Stop the interface and save some PCI 954 * settings in case the BIOS doesn't restore them properly on 955 * resume. 956 */ 957 static int 958 fxp_suspend(device_t dev) 959 { 960 struct fxp_softc *sc = device_get_softc(dev); 961 962 FXP_LOCK(sc); 963 964 fxp_stop(sc); 965 966 sc->suspended = 1; 967 968 FXP_UNLOCK(sc); 969 return (0); 970 } 971 972 /* 973 * Device resume routine. re-enable busmastering, and restart the interface if 974 * appropriate. 975 */ 976 static int 977 fxp_resume(device_t dev) 978 { 979 struct fxp_softc *sc = device_get_softc(dev); 980 struct ifnet *ifp = sc->ifp; 981 982 FXP_LOCK(sc); 983 984 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 985 DELAY(10); 986 987 /* reinitialize interface if necessary */ 988 if (ifp->if_flags & IFF_UP) 989 fxp_init_body(sc); 990 991 sc->suspended = 0; 992 993 FXP_UNLOCK(sc); 994 return (0); 995 } 996 997 static void 998 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 999 { 1000 uint16_t reg; 1001 int x; 1002 1003 /* 1004 * Shift in data. 1005 */ 1006 for (x = 1 << (length - 1); x; x >>= 1) { 1007 if (data & x) 1008 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1009 else 1010 reg = FXP_EEPROM_EECS; 1011 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1012 DELAY(1); 1013 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1014 DELAY(1); 1015 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1016 DELAY(1); 1017 } 1018 } 1019 1020 /* 1021 * Read from the serial EEPROM. Basically, you manually shift in 1022 * the read opcode (one bit at a time) and then shift in the address, 1023 * and then you shift out the data (all of this one bit at a time). 1024 * The word size is 16 bits, so you have to provide the address for 1025 * every 16 bits of data. 1026 */ 1027 static uint16_t 1028 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1029 { 1030 uint16_t reg, data; 1031 int x; 1032 1033 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1034 /* 1035 * Shift in read opcode. 1036 */ 1037 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1038 /* 1039 * Shift in address. 1040 */ 1041 data = 0; 1042 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1043 if (offset & x) 1044 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1045 else 1046 reg = FXP_EEPROM_EECS; 1047 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1048 DELAY(1); 1049 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1050 DELAY(1); 1051 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1052 DELAY(1); 1053 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1054 data++; 1055 if (autosize && reg == 0) { 1056 sc->eeprom_size = data; 1057 break; 1058 } 1059 } 1060 /* 1061 * Shift out data. 1062 */ 1063 data = 0; 1064 reg = FXP_EEPROM_EECS; 1065 for (x = 1 << 15; x; x >>= 1) { 1066 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1067 DELAY(1); 1068 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1069 data |= x; 1070 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1071 DELAY(1); 1072 } 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1074 DELAY(1); 1075 1076 return (data); 1077 } 1078 1079 static void 1080 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1081 { 1082 int i; 1083 1084 /* 1085 * Erase/write enable. 1086 */ 1087 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1088 fxp_eeprom_shiftin(sc, 0x4, 3); 1089 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1091 DELAY(1); 1092 /* 1093 * Shift in write opcode, address, data. 1094 */ 1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1096 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1097 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1098 fxp_eeprom_shiftin(sc, data, 16); 1099 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1100 DELAY(1); 1101 /* 1102 * Wait for EEPROM to finish up. 1103 */ 1104 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1105 DELAY(1); 1106 for (i = 0; i < 1000; i++) { 1107 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1108 break; 1109 DELAY(50); 1110 } 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1112 DELAY(1); 1113 /* 1114 * Erase/write disable. 1115 */ 1116 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1117 fxp_eeprom_shiftin(sc, 0x4, 3); 1118 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1119 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1120 DELAY(1); 1121 } 1122 1123 /* 1124 * From NetBSD: 1125 * 1126 * Figure out EEPROM size. 1127 * 1128 * 559's can have either 64-word or 256-word EEPROMs, the 558 1129 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1130 * talks about the existance of 16 to 256 word EEPROMs. 1131 * 1132 * The only known sizes are 64 and 256, where the 256 version is used 1133 * by CardBus cards to store CIS information. 1134 * 1135 * The address is shifted in msb-to-lsb, and after the last 1136 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1137 * after which follows the actual data. We try to detect this zero, by 1138 * probing the data-out bit in the EEPROM control register just after 1139 * having shifted in a bit. If the bit is zero, we assume we've 1140 * shifted enough address bits. The data-out should be tri-state, 1141 * before this, which should translate to a logical one. 1142 */ 1143 static void 1144 fxp_autosize_eeprom(struct fxp_softc *sc) 1145 { 1146 1147 /* guess maximum size of 256 words */ 1148 sc->eeprom_size = 8; 1149 1150 /* autosize */ 1151 (void) fxp_eeprom_getword(sc, 0, 1); 1152 } 1153 1154 static void 1155 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1156 { 1157 int i; 1158 1159 for (i = 0; i < words; i++) 1160 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1161 } 1162 1163 static void 1164 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1165 { 1166 int i; 1167 1168 for (i = 0; i < words; i++) 1169 fxp_eeprom_putword(sc, offset + i, data[i]); 1170 } 1171 1172 /* 1173 * Grab the softc lock and call the real fxp_start_body() routine 1174 */ 1175 static void 1176 fxp_start(struct ifnet *ifp) 1177 { 1178 struct fxp_softc *sc = ifp->if_softc; 1179 1180 FXP_LOCK(sc); 1181 fxp_start_body(ifp); 1182 FXP_UNLOCK(sc); 1183 } 1184 1185 /* 1186 * Start packet transmission on the interface. 1187 * This routine must be called with the softc lock held, and is an 1188 * internal entry point only. 1189 */ 1190 static void 1191 fxp_start_body(struct ifnet *ifp) 1192 { 1193 struct fxp_softc *sc = ifp->if_softc; 1194 struct mbuf *mb_head; 1195 int error, txqueued; 1196 1197 FXP_LOCK_ASSERT(sc, MA_OWNED); 1198 1199 /* 1200 * See if we need to suspend xmit until the multicast filter 1201 * has been reprogrammed (which can only be done at the head 1202 * of the command chain). 1203 */ 1204 if (sc->need_mcsetup) 1205 return; 1206 1207 /* 1208 * We're finished if there is nothing more to add to the list or if 1209 * we're all filled up with buffers to transmit. 1210 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1211 * a NOP command when needed. 1212 */ 1213 txqueued = 0; 1214 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1215 sc->tx_queued < FXP_NTXCB - 1) { 1216 1217 /* 1218 * Grab a packet to transmit. 1219 */ 1220 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1221 if (mb_head == NULL) 1222 break; 1223 1224 error = fxp_encap(sc, mb_head); 1225 if (error) 1226 break; 1227 txqueued = 1; 1228 } 1229 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1230 1231 /* 1232 * We're finished. If we added to the list, issue a RESUME to get DMA 1233 * going again if suspended. 1234 */ 1235 if (txqueued) { 1236 fxp_scb_wait(sc); 1237 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1238 } 1239 } 1240 1241 static int 1242 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1243 { 1244 struct ifnet *ifp; 1245 struct mbuf *m; 1246 struct fxp_tx *txp; 1247 struct fxp_cb_tx *cbp; 1248 bus_dma_segment_t segs[FXP_NTXSEG]; 1249 int chainlen, error, i, nseg; 1250 1251 FXP_LOCK_ASSERT(sc, MA_OWNED); 1252 ifp = sc->ifp; 1253 1254 /* 1255 * Get pointer to next available tx desc. 1256 */ 1257 txp = sc->fxp_desc.tx_last->tx_next; 1258 1259 /* 1260 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1261 * Ethernet Controller Family Open Source Software 1262 * Developer Manual says: 1263 * Using software parsing is only allowed with legal 1264 * TCP/IP or UDP/IP packets. 1265 * ... 1266 * For all other datagrams, hardware parsing must 1267 * be used. 1268 * Software parsing appears to truncate ICMP and 1269 * fragmented UDP packets that contain one to three 1270 * bytes in the second (and final) mbuf of the packet. 1271 */ 1272 if (sc->flags & FXP_FLAG_EXT_RFA) 1273 txp->tx_cb->ipcb_ip_activation_high = 1274 FXP_IPCB_HARDWAREPARSING_ENABLE; 1275 1276 /* 1277 * Deal with TCP/IP checksum offload. Note that 1278 * in order for TCP checksum offload to work, 1279 * the pseudo header checksum must have already 1280 * been computed and stored in the checksum field 1281 * in the TCP header. The stack should have 1282 * already done this for us. 1283 */ 1284 if (m_head->m_pkthdr.csum_flags) { 1285 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1286 txp->tx_cb->ipcb_ip_schedule = 1287 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1288 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1289 txp->tx_cb->ipcb_ip_schedule |= 1290 FXP_IPCB_TCP_PACKET; 1291 } 1292 1293 #ifdef FXP_IP_CSUM_WAR 1294 /* 1295 * XXX The 82550 chip appears to have trouble 1296 * dealing with IP header checksums in very small 1297 * datagrams, namely fragments from 1 to 3 bytes 1298 * in size. For example, say you want to transmit 1299 * a UDP packet of 1473 bytes. The packet will be 1300 * fragmented over two IP datagrams, the latter 1301 * containing only one byte of data. The 82550 will 1302 * botch the header checksum on the 1-byte fragment. 1303 * As long as the datagram contains 4 or more bytes 1304 * of data, you're ok. 1305 * 1306 * The following code attempts to work around this 1307 * problem: if the datagram is less than 38 bytes 1308 * in size (14 bytes ether header, 20 bytes IP header, 1309 * plus 4 bytes of data), we punt and compute the IP 1310 * header checksum by hand. This workaround doesn't 1311 * work very well, however, since it can be fooled 1312 * by things like VLAN tags and IP options that make 1313 * the header sizes/offsets vary. 1314 */ 1315 1316 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1317 if (m_head->m_pkthdr.len < 38) { 1318 struct ip *ip; 1319 m_head->m_data += ETHER_HDR_LEN; 1320 ip = mtod(mb_head, struct ip *); 1321 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1322 m_head->m_data -= ETHER_HDR_LEN; 1323 } else { 1324 txp->tx_cb->ipcb_ip_activation_high = 1325 FXP_IPCB_HARDWAREPARSING_ENABLE; 1326 txp->tx_cb->ipcb_ip_schedule |= 1327 FXP_IPCB_IP_CHECKSUM_ENABLE; 1328 } 1329 } 1330 #endif 1331 } 1332 1333 chainlen = 0; 1334 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1335 chainlen++; 1336 if (chainlen > sc->maxtxseg) { 1337 struct mbuf *mn; 1338 1339 /* 1340 * We ran out of segments. We have to recopy this 1341 * mbuf chain first. Bail out if we can't get the 1342 * new buffers. 1343 */ 1344 mn = m_defrag(m_head, M_DONTWAIT); 1345 if (mn == NULL) { 1346 m_freem(m_head); 1347 return (-1); 1348 } else { 1349 m_head = mn; 1350 } 1351 } 1352 1353 /* 1354 * Go through each of the mbufs in the chain and initialize 1355 * the transmit buffer descriptors with the physical address 1356 * and size of the mbuf. 1357 */ 1358 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1359 m_head, segs, &nseg, 0); 1360 if (error) { 1361 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1362 m_freem(m_head); 1363 return (-1); 1364 } 1365 1366 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1367 1368 cbp = txp->tx_cb; 1369 for (i = 0; i < nseg; i++) { 1370 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1371 /* 1372 * If this is an 82550/82551, then we're using extended 1373 * TxCBs _and_ we're using checksum offload. This means 1374 * that the TxCB is really an IPCB. One major difference 1375 * between the two is that with plain extended TxCBs, 1376 * the bottom half of the TxCB contains two entries from 1377 * the TBD array, whereas IPCBs contain just one entry: 1378 * one entry (8 bytes) has been sacrificed for the TCP/IP 1379 * checksum offload control bits. So to make things work 1380 * right, we have to start filling in the TBD array 1381 * starting from a different place depending on whether 1382 * the chip is an 82550/82551 or not. 1383 */ 1384 if (sc->flags & FXP_FLAG_EXT_RFA) { 1385 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1386 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1387 } else { 1388 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1389 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1390 } 1391 } 1392 cbp->tbd_number = nseg; 1393 1394 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1395 txp->tx_mbuf = m_head; 1396 txp->tx_cb->cb_status = 0; 1397 txp->tx_cb->byte_count = 0; 1398 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1399 txp->tx_cb->cb_command = 1400 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1401 FXP_CB_COMMAND_S); 1402 } else { 1403 txp->tx_cb->cb_command = 1404 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1405 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1406 /* 1407 * Set a 5 second timer just in case we don't hear 1408 * from the card again. 1409 */ 1410 sc->watchdog_timer = 5; 1411 } 1412 txp->tx_cb->tx_threshold = tx_threshold; 1413 1414 /* 1415 * Advance the end of list forward. 1416 */ 1417 1418 #ifdef __alpha__ 1419 /* 1420 * On platforms which can't access memory in 16-bit 1421 * granularities, we must prevent the card from DMA'ing 1422 * up the status while we update the command field. 1423 * This could cause us to overwrite the completion status. 1424 * XXX This is probably bogus and we're _not_ looking 1425 * for atomicity here. 1426 */ 1427 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1428 htole16(FXP_CB_COMMAND_S)); 1429 #else 1430 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1431 #endif /*__alpha__*/ 1432 sc->fxp_desc.tx_last = txp; 1433 1434 /* 1435 * Advance the beginning of the list forward if there are 1436 * no other packets queued (when nothing is queued, tx_first 1437 * sits on the last TxCB that was sent out). 1438 */ 1439 if (sc->tx_queued == 0) 1440 sc->fxp_desc.tx_first = txp; 1441 1442 sc->tx_queued++; 1443 1444 /* 1445 * Pass packet to bpf if there is a listener. 1446 */ 1447 BPF_MTAP(ifp, m_head); 1448 return (0); 1449 } 1450 1451 #ifdef DEVICE_POLLING 1452 static poll_handler_t fxp_poll; 1453 1454 static void 1455 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1456 { 1457 struct fxp_softc *sc = ifp->if_softc; 1458 uint8_t statack; 1459 1460 FXP_LOCK(sc); 1461 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1462 FXP_UNLOCK(sc); 1463 return; 1464 } 1465 1466 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1467 FXP_SCB_STATACK_FR; 1468 if (cmd == POLL_AND_CHECK_STATUS) { 1469 uint8_t tmp; 1470 1471 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1472 if (tmp == 0xff || tmp == 0) { 1473 FXP_UNLOCK(sc); 1474 return; /* nothing to do */ 1475 } 1476 tmp &= ~statack; 1477 /* ack what we can */ 1478 if (tmp != 0) 1479 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1480 statack |= tmp; 1481 } 1482 fxp_intr_body(sc, ifp, statack, count); 1483 FXP_UNLOCK(sc); 1484 } 1485 #endif /* DEVICE_POLLING */ 1486 1487 /* 1488 * Process interface interrupts. 1489 */ 1490 static void 1491 fxp_intr(void *xsc) 1492 { 1493 struct fxp_softc *sc = xsc; 1494 struct ifnet *ifp = sc->ifp; 1495 uint8_t statack; 1496 1497 FXP_LOCK(sc); 1498 if (sc->suspended) { 1499 FXP_UNLOCK(sc); 1500 return; 1501 } 1502 1503 #ifdef DEVICE_POLLING 1504 if (ifp->if_capenable & IFCAP_POLLING) { 1505 FXP_UNLOCK(sc); 1506 return; 1507 } 1508 #endif 1509 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1510 /* 1511 * It should not be possible to have all bits set; the 1512 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1513 * all bits are set, this may indicate that the card has 1514 * been physically ejected, so ignore it. 1515 */ 1516 if (statack == 0xff) { 1517 FXP_UNLOCK(sc); 1518 return; 1519 } 1520 1521 /* 1522 * First ACK all the interrupts in this pass. 1523 */ 1524 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1525 fxp_intr_body(sc, ifp, statack, -1); 1526 } 1527 FXP_UNLOCK(sc); 1528 } 1529 1530 static void 1531 fxp_txeof(struct fxp_softc *sc) 1532 { 1533 struct fxp_tx *txp; 1534 1535 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1536 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1537 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1538 txp = txp->tx_next) { 1539 if (txp->tx_mbuf != NULL) { 1540 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1541 BUS_DMASYNC_POSTWRITE); 1542 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1543 m_freem(txp->tx_mbuf); 1544 txp->tx_mbuf = NULL; 1545 /* clear this to reset csum offload bits */ 1546 txp->tx_cb->tbd[0].tb_addr = 0; 1547 } 1548 sc->tx_queued--; 1549 } 1550 sc->fxp_desc.tx_first = txp; 1551 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1552 } 1553 1554 static void 1555 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1556 int count) 1557 { 1558 struct mbuf *m; 1559 struct fxp_rx *rxp; 1560 struct fxp_rfa *rfa; 1561 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1562 int fxp_rc = 0; 1563 1564 FXP_LOCK_ASSERT(sc, MA_OWNED); 1565 if (rnr) 1566 sc->rnr++; 1567 #ifdef DEVICE_POLLING 1568 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1569 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1570 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1571 rnr = 1; 1572 } 1573 #endif 1574 1575 /* 1576 * Free any finished transmit mbuf chains. 1577 * 1578 * Handle the CNA event likt a CXTNO event. It used to 1579 * be that this event (control unit not ready) was not 1580 * encountered, but it is now with the SMPng modifications. 1581 * The exact sequence of events that occur when the interface 1582 * is brought up are different now, and if this event 1583 * goes unhandled, the configuration/rxfilter setup sequence 1584 * can stall for several seconds. The result is that no 1585 * packets go out onto the wire for about 5 to 10 seconds 1586 * after the interface is ifconfig'ed for the first time. 1587 */ 1588 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1589 fxp_txeof(sc); 1590 1591 sc->watchdog_timer = 0; 1592 if (sc->tx_queued == 0) { 1593 if (sc->need_mcsetup) 1594 fxp_mc_setup(sc); 1595 } 1596 /* 1597 * Try to start more packets transmitting. 1598 */ 1599 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1600 fxp_start_body(ifp); 1601 } 1602 1603 /* 1604 * Just return if nothing happened on the receive side. 1605 */ 1606 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1607 return; 1608 1609 /* 1610 * Process receiver interrupts. If a no-resource (RNR) 1611 * condition exists, get whatever packets we can and 1612 * re-start the receiver. 1613 * 1614 * When using polling, we do not process the list to completion, 1615 * so when we get an RNR interrupt we must defer the restart 1616 * until we hit the last buffer with the C bit set. 1617 * If we run out of cycles and rfa_headm has the C bit set, 1618 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1619 * that the info will be used in the subsequent polling cycle. 1620 */ 1621 for (;;) { 1622 rxp = sc->fxp_desc.rx_head; 1623 m = rxp->rx_mbuf; 1624 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1625 RFA_ALIGNMENT_FUDGE); 1626 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1627 BUS_DMASYNC_POSTREAD); 1628 1629 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1630 if (count >= 0 && count-- == 0) { 1631 if (rnr) { 1632 /* Defer RNR processing until the next time. */ 1633 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1634 rnr = 0; 1635 } 1636 break; 1637 } 1638 #endif /* DEVICE_POLLING */ 1639 1640 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1641 break; 1642 1643 /* 1644 * Advance head forward. 1645 */ 1646 sc->fxp_desc.rx_head = rxp->rx_next; 1647 1648 /* 1649 * Add a new buffer to the receive chain. 1650 * If this fails, the old buffer is recycled 1651 * instead. 1652 */ 1653 fxp_rc = fxp_add_rfabuf(sc, rxp); 1654 if (fxp_rc == 0) { 1655 int total_len; 1656 1657 /* 1658 * Fetch packet length (the top 2 bits of 1659 * actual_size are flags set by the controller 1660 * upon completion), and drop the packet in case 1661 * of bogus length or CRC errors. 1662 */ 1663 total_len = le16toh(rfa->actual_size) & 0x3fff; 1664 if (total_len < sizeof(struct ether_header) || 1665 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1666 sc->rfa_size || 1667 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1668 m_freem(m); 1669 continue; 1670 } 1671 1672 /* Do IP checksum checking. */ 1673 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1674 if (rfa->rfax_csum_sts & 1675 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1676 m->m_pkthdr.csum_flags |= 1677 CSUM_IP_CHECKED; 1678 if (rfa->rfax_csum_sts & 1679 FXP_RFDX_CS_IP_CSUM_VALID) 1680 m->m_pkthdr.csum_flags |= 1681 CSUM_IP_VALID; 1682 if ((rfa->rfax_csum_sts & 1683 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1684 (rfa->rfax_csum_sts & 1685 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1686 m->m_pkthdr.csum_flags |= 1687 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1688 m->m_pkthdr.csum_data = 0xffff; 1689 } 1690 } 1691 1692 m->m_pkthdr.len = m->m_len = total_len; 1693 m->m_pkthdr.rcvif = ifp; 1694 1695 /* 1696 * Drop locks before calling if_input() since it 1697 * may re-enter fxp_start() in the netisr case. 1698 * This would result in a lock reversal. Better 1699 * performance might be obtained by chaining all 1700 * packets received, dropping the lock, and then 1701 * calling if_input() on each one. 1702 */ 1703 FXP_UNLOCK(sc); 1704 (*ifp->if_input)(ifp, m); 1705 FXP_LOCK(sc); 1706 } else if (fxp_rc == ENOBUFS) { 1707 rnr = 0; 1708 break; 1709 } 1710 } 1711 if (rnr) { 1712 fxp_scb_wait(sc); 1713 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1714 sc->fxp_desc.rx_head->rx_addr); 1715 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1716 } 1717 } 1718 1719 /* 1720 * Update packet in/out/collision statistics. The i82557 doesn't 1721 * allow you to access these counters without doing a fairly 1722 * expensive DMA to get _all_ of the statistics it maintains, so 1723 * we do this operation here only once per second. The statistics 1724 * counters in the kernel are updated from the previous dump-stats 1725 * DMA and then a new dump-stats DMA is started. The on-chip 1726 * counters are zeroed when the DMA completes. If we can't start 1727 * the DMA immediately, we don't wait - we just prepare to read 1728 * them again next time. 1729 */ 1730 static void 1731 fxp_tick(void *xsc) 1732 { 1733 struct fxp_softc *sc = xsc; 1734 struct ifnet *ifp = sc->ifp; 1735 struct fxp_stats *sp = sc->fxp_stats; 1736 1737 FXP_LOCK_ASSERT(sc, MA_OWNED); 1738 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1739 ifp->if_opackets += le32toh(sp->tx_good); 1740 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1741 if (sp->rx_good) { 1742 ifp->if_ipackets += le32toh(sp->rx_good); 1743 sc->rx_idle_secs = 0; 1744 } else { 1745 /* 1746 * Receiver's been idle for another second. 1747 */ 1748 sc->rx_idle_secs++; 1749 } 1750 ifp->if_ierrors += 1751 le32toh(sp->rx_crc_errors) + 1752 le32toh(sp->rx_alignment_errors) + 1753 le32toh(sp->rx_rnr_errors) + 1754 le32toh(sp->rx_overrun_errors); 1755 /* 1756 * If any transmit underruns occured, bump up the transmit 1757 * threshold by another 512 bytes (64 * 8). 1758 */ 1759 if (sp->tx_underruns) { 1760 ifp->if_oerrors += le32toh(sp->tx_underruns); 1761 if (tx_threshold < 192) 1762 tx_threshold += 64; 1763 } 1764 1765 /* 1766 * Release any xmit buffers that have completed DMA. This isn't 1767 * strictly necessary to do here, but it's advantagous for mbufs 1768 * with external storage to be released in a timely manner rather 1769 * than being defered for a potentially long time. This limits 1770 * the delay to a maximum of one second. 1771 */ 1772 fxp_txeof(sc); 1773 1774 /* 1775 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1776 * then assume the receiver has locked up and attempt to clear 1777 * the condition by reprogramming the multicast filter. This is 1778 * a work-around for a bug in the 82557 where the receiver locks 1779 * up if it gets certain types of garbage in the syncronization 1780 * bits prior to the packet header. This bug is supposed to only 1781 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1782 * mode as well (perhaps due to a 10/100 speed transition). 1783 */ 1784 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1785 sc->rx_idle_secs = 0; 1786 fxp_mc_setup(sc); 1787 } 1788 /* 1789 * If there is no pending command, start another stats 1790 * dump. Otherwise punt for now. 1791 */ 1792 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1793 /* 1794 * Start another stats dump. 1795 */ 1796 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1797 BUS_DMASYNC_PREREAD); 1798 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1799 } else { 1800 /* 1801 * A previous command is still waiting to be accepted. 1802 * Just zero our copy of the stats and wait for the 1803 * next timer event to update them. 1804 */ 1805 sp->tx_good = 0; 1806 sp->tx_underruns = 0; 1807 sp->tx_total_collisions = 0; 1808 1809 sp->rx_good = 0; 1810 sp->rx_crc_errors = 0; 1811 sp->rx_alignment_errors = 0; 1812 sp->rx_rnr_errors = 0; 1813 sp->rx_overrun_errors = 0; 1814 } 1815 if (sc->miibus != NULL) 1816 mii_tick(device_get_softc(sc->miibus)); 1817 1818 /* 1819 * Check that chip hasn't hung. 1820 */ 1821 fxp_watchdog(sc); 1822 1823 /* 1824 * Schedule another timeout one second from now. 1825 */ 1826 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1827 } 1828 1829 /* 1830 * Stop the interface. Cancels the statistics updater and resets 1831 * the interface. 1832 */ 1833 static void 1834 fxp_stop(struct fxp_softc *sc) 1835 { 1836 struct ifnet *ifp = sc->ifp; 1837 struct fxp_tx *txp; 1838 int i; 1839 1840 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1841 sc->watchdog_timer = 0; 1842 1843 /* 1844 * Cancel stats updater. 1845 */ 1846 callout_stop(&sc->stat_ch); 1847 1848 /* 1849 * Issue software reset, which also unloads the microcode. 1850 */ 1851 sc->flags &= ~FXP_FLAG_UCODE; 1852 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1853 DELAY(50); 1854 1855 /* 1856 * Release any xmit buffers. 1857 */ 1858 txp = sc->fxp_desc.tx_list; 1859 if (txp != NULL) { 1860 for (i = 0; i < FXP_NTXCB; i++) { 1861 if (txp[i].tx_mbuf != NULL) { 1862 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1863 BUS_DMASYNC_POSTWRITE); 1864 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1865 m_freem(txp[i].tx_mbuf); 1866 txp[i].tx_mbuf = NULL; 1867 /* clear this to reset csum offload bits */ 1868 txp[i].tx_cb->tbd[0].tb_addr = 0; 1869 } 1870 } 1871 } 1872 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1873 sc->tx_queued = 0; 1874 } 1875 1876 /* 1877 * Watchdog/transmission transmit timeout handler. Called when a 1878 * transmission is started on the interface, but no interrupt is 1879 * received before the timeout. This usually indicates that the 1880 * card has wedged for some reason. 1881 */ 1882 static void 1883 fxp_watchdog(struct fxp_softc *sc) 1884 { 1885 1886 FXP_LOCK_ASSERT(sc, MA_OWNED); 1887 1888 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1889 return; 1890 1891 device_printf(sc->dev, "device timeout\n"); 1892 sc->ifp->if_oerrors++; 1893 1894 fxp_init_body(sc); 1895 } 1896 1897 /* 1898 * Acquire locks and then call the real initialization function. This 1899 * is necessary because ether_ioctl() calls if_init() and this would 1900 * result in mutex recursion if the mutex was held. 1901 */ 1902 static void 1903 fxp_init(void *xsc) 1904 { 1905 struct fxp_softc *sc = xsc; 1906 1907 FXP_LOCK(sc); 1908 fxp_init_body(sc); 1909 FXP_UNLOCK(sc); 1910 } 1911 1912 /* 1913 * Perform device initialization. This routine must be called with the 1914 * softc lock held. 1915 */ 1916 static void 1917 fxp_init_body(struct fxp_softc *sc) 1918 { 1919 struct ifnet *ifp = sc->ifp; 1920 struct fxp_cb_config *cbp; 1921 struct fxp_cb_ias *cb_ias; 1922 struct fxp_cb_tx *tcbp; 1923 struct fxp_tx *txp; 1924 struct fxp_cb_mcs *mcsp; 1925 int i, prm; 1926 1927 FXP_LOCK_ASSERT(sc, MA_OWNED); 1928 /* 1929 * Cancel any pending I/O 1930 */ 1931 fxp_stop(sc); 1932 1933 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1934 1935 /* 1936 * Initialize base of CBL and RFA memory. Loading with zero 1937 * sets it up for regular linear addressing. 1938 */ 1939 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1940 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1941 1942 fxp_scb_wait(sc); 1943 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1944 1945 /* 1946 * Initialize base of dump-stats buffer. 1947 */ 1948 fxp_scb_wait(sc); 1949 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1950 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1951 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1952 1953 /* 1954 * Attempt to load microcode if requested. 1955 */ 1956 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1957 fxp_load_ucode(sc); 1958 1959 /* 1960 * Initialize the multicast address list. 1961 */ 1962 if (fxp_mc_addrs(sc)) { 1963 mcsp = sc->mcsp; 1964 mcsp->cb_status = 0; 1965 mcsp->cb_command = 1966 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1967 mcsp->link_addr = 0xffffffff; 1968 /* 1969 * Start the multicast setup command. 1970 */ 1971 fxp_scb_wait(sc); 1972 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1973 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1974 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1975 /* ...and wait for it to complete. */ 1976 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1977 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1978 BUS_DMASYNC_POSTWRITE); 1979 } 1980 1981 /* 1982 * We temporarily use memory that contains the TxCB list to 1983 * construct the config CB. The TxCB list memory is rebuilt 1984 * later. 1985 */ 1986 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1987 1988 /* 1989 * This bcopy is kind of disgusting, but there are a bunch of must be 1990 * zero and must be one bits in this structure and this is the easiest 1991 * way to initialize them all to proper values. 1992 */ 1993 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1994 1995 cbp->cb_status = 0; 1996 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1997 FXP_CB_COMMAND_EL); 1998 cbp->link_addr = 0xffffffff; /* (no) next command */ 1999 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2000 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2001 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2002 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2003 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2004 cbp->type_enable = 0; /* actually reserved */ 2005 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2006 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2007 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2008 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2009 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2010 cbp->late_scb = 0; /* (don't) defer SCB update */ 2011 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2012 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2013 cbp->ci_int = 1; /* interrupt on CU idle */ 2014 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2015 cbp->ext_stats_dis = 1; /* disable extended counters */ 2016 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2017 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2018 cbp->disc_short_rx = !prm; /* discard short packets */ 2019 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2020 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2021 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2022 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2023 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2024 cbp->csma_dis = 0; /* (don't) disable link */ 2025 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2026 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2027 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2028 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2029 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2030 cbp->nsai = 1; /* (don't) disable source addr insert */ 2031 cbp->preamble_length = 2; /* (7 byte) preamble */ 2032 cbp->loopback = 0; /* (don't) loopback */ 2033 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2034 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2035 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2036 cbp->promiscuous = prm; /* promiscuous mode */ 2037 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2038 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2039 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2040 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2041 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2042 2043 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2044 cbp->padding = 1; /* (do) pad short tx packets */ 2045 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2046 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2047 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2048 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2049 /* must set wake_en in PMCSR also */ 2050 cbp->force_fdx = 0; /* (don't) force full duplex */ 2051 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2052 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2053 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2054 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2055 2056 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2057 /* 2058 * The 82557 has no hardware flow control, the values 2059 * below are the defaults for the chip. 2060 */ 2061 cbp->fc_delay_lsb = 0; 2062 cbp->fc_delay_msb = 0x40; 2063 cbp->pri_fc_thresh = 3; 2064 cbp->tx_fc_dis = 0; 2065 cbp->rx_fc_restop = 0; 2066 cbp->rx_fc_restart = 0; 2067 cbp->fc_filter = 0; 2068 cbp->pri_fc_loc = 1; 2069 } else { 2070 cbp->fc_delay_lsb = 0x1f; 2071 cbp->fc_delay_msb = 0x01; 2072 cbp->pri_fc_thresh = 3; 2073 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2074 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2075 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2076 cbp->fc_filter = !prm; /* drop FC frames to host */ 2077 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2078 } 2079 2080 /* 2081 * Start the config command/DMA. 2082 */ 2083 fxp_scb_wait(sc); 2084 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2085 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2086 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2087 /* ...and wait for it to complete. */ 2088 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2089 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2090 2091 /* 2092 * Now initialize the station address. Temporarily use the TxCB 2093 * memory area like we did above for the config CB. 2094 */ 2095 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2096 cb_ias->cb_status = 0; 2097 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2098 cb_ias->link_addr = 0xffffffff; 2099 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2100 2101 /* 2102 * Start the IAS (Individual Address Setup) command/DMA. 2103 */ 2104 fxp_scb_wait(sc); 2105 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2106 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2107 /* ...and wait for it to complete. */ 2108 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2109 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2110 2111 /* 2112 * Initialize transmit control block (TxCB) list. 2113 */ 2114 txp = sc->fxp_desc.tx_list; 2115 tcbp = sc->fxp_desc.cbl_list; 2116 bzero(tcbp, FXP_TXCB_SZ); 2117 for (i = 0; i < FXP_NTXCB; i++) { 2118 txp[i].tx_mbuf = NULL; 2119 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2120 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2121 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2122 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2123 if (sc->flags & FXP_FLAG_EXT_TXCB) 2124 tcbp[i].tbd_array_addr = 2125 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2126 else 2127 tcbp[i].tbd_array_addr = 2128 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2129 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2130 } 2131 /* 2132 * Set the suspend flag on the first TxCB and start the control 2133 * unit. It will execute the NOP and then suspend. 2134 */ 2135 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2136 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2137 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2138 sc->tx_queued = 1; 2139 2140 fxp_scb_wait(sc); 2141 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2142 2143 /* 2144 * Initialize receiver buffer area - RFA. 2145 */ 2146 fxp_scb_wait(sc); 2147 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2149 2150 /* 2151 * Set current media. 2152 */ 2153 if (sc->miibus != NULL) 2154 mii_mediachg(device_get_softc(sc->miibus)); 2155 2156 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2157 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2158 2159 /* 2160 * Enable interrupts. 2161 */ 2162 #ifdef DEVICE_POLLING 2163 /* 2164 * ... but only do that if we are not polling. And because (presumably) 2165 * the default is interrupts on, we need to disable them explicitly! 2166 */ 2167 if (ifp->if_capenable & IFCAP_POLLING ) 2168 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2169 else 2170 #endif /* DEVICE_POLLING */ 2171 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2172 2173 /* 2174 * Start stats updater. 2175 */ 2176 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2177 } 2178 2179 static int 2180 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2181 { 2182 2183 return (0); 2184 } 2185 2186 static void 2187 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2188 { 2189 2190 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2191 } 2192 2193 /* 2194 * Change media according to request. 2195 */ 2196 static int 2197 fxp_ifmedia_upd(struct ifnet *ifp) 2198 { 2199 struct fxp_softc *sc = ifp->if_softc; 2200 struct mii_data *mii; 2201 2202 mii = device_get_softc(sc->miibus); 2203 FXP_LOCK(sc); 2204 if (mii->mii_instance) { 2205 struct mii_softc *miisc; 2206 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2207 mii_phy_reset(miisc); 2208 } 2209 mii_mediachg(mii); 2210 FXP_UNLOCK(sc); 2211 return (0); 2212 } 2213 2214 /* 2215 * Notify the world which media we're using. 2216 */ 2217 static void 2218 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2219 { 2220 struct fxp_softc *sc = ifp->if_softc; 2221 struct mii_data *mii; 2222 2223 mii = device_get_softc(sc->miibus); 2224 FXP_LOCK(sc); 2225 mii_pollstat(mii); 2226 ifmr->ifm_active = mii->mii_media_active; 2227 ifmr->ifm_status = mii->mii_media_status; 2228 2229 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2230 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2231 sc->cu_resume_bug = 1; 2232 else 2233 sc->cu_resume_bug = 0; 2234 FXP_UNLOCK(sc); 2235 } 2236 2237 /* 2238 * Add a buffer to the end of the RFA buffer list. 2239 * Return 0 if successful, 1 for failure. A failure results in 2240 * adding the 'oldm' (if non-NULL) on to the end of the list - 2241 * tossing out its old contents and recycling it. 2242 * The RFA struct is stuck at the beginning of mbuf cluster and the 2243 * data pointer is fixed up to point just past it. 2244 */ 2245 static int 2246 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2247 { 2248 struct mbuf *m; 2249 struct fxp_rfa *rfa, *p_rfa; 2250 struct fxp_rx *p_rx; 2251 bus_dmamap_t tmp_map; 2252 int error; 2253 2254 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2255 if (m == NULL) 2256 return (ENOBUFS); 2257 2258 /* 2259 * Move the data pointer up so that the incoming data packet 2260 * will be 32-bit aligned. 2261 */ 2262 m->m_data += RFA_ALIGNMENT_FUDGE; 2263 2264 /* 2265 * Get a pointer to the base of the mbuf cluster and move 2266 * data start past it. 2267 */ 2268 rfa = mtod(m, struct fxp_rfa *); 2269 m->m_data += sc->rfa_size; 2270 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2271 2272 rfa->rfa_status = 0; 2273 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2274 rfa->actual_size = 0; 2275 2276 /* 2277 * Initialize the rest of the RFA. Note that since the RFA 2278 * is misaligned, we cannot store values directly. We're thus 2279 * using the le32enc() function which handles endianness and 2280 * is also alignment-safe. 2281 */ 2282 le32enc(&rfa->link_addr, 0xffffffff); 2283 le32enc(&rfa->rbd_addr, 0xffffffff); 2284 2285 /* Map the RFA into DMA memory. */ 2286 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2287 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2288 &rxp->rx_addr, 0); 2289 if (error) { 2290 m_freem(m); 2291 return (error); 2292 } 2293 2294 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2295 tmp_map = sc->spare_map; 2296 sc->spare_map = rxp->rx_map; 2297 rxp->rx_map = tmp_map; 2298 rxp->rx_mbuf = m; 2299 2300 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2301 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2302 2303 /* 2304 * If there are other buffers already on the list, attach this 2305 * one to the end by fixing up the tail to point to this one. 2306 */ 2307 if (sc->fxp_desc.rx_head != NULL) { 2308 p_rx = sc->fxp_desc.rx_tail; 2309 p_rfa = (struct fxp_rfa *) 2310 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2311 p_rx->rx_next = rxp; 2312 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2313 p_rfa->rfa_control = 0; 2314 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2315 BUS_DMASYNC_PREWRITE); 2316 } else { 2317 rxp->rx_next = NULL; 2318 sc->fxp_desc.rx_head = rxp; 2319 } 2320 sc->fxp_desc.rx_tail = rxp; 2321 return (0); 2322 } 2323 2324 static volatile int 2325 fxp_miibus_readreg(device_t dev, int phy, int reg) 2326 { 2327 struct fxp_softc *sc = device_get_softc(dev); 2328 int count = 10000; 2329 int value; 2330 2331 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2332 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2333 2334 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2335 && count--) 2336 DELAY(10); 2337 2338 if (count <= 0) 2339 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2340 2341 return (value & 0xffff); 2342 } 2343 2344 static void 2345 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2346 { 2347 struct fxp_softc *sc = device_get_softc(dev); 2348 int count = 10000; 2349 2350 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2351 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2352 (value & 0xffff)); 2353 2354 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2355 count--) 2356 DELAY(10); 2357 2358 if (count <= 0) 2359 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2360 } 2361 2362 static int 2363 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2364 { 2365 struct fxp_softc *sc = ifp->if_softc; 2366 struct ifreq *ifr = (struct ifreq *)data; 2367 struct mii_data *mii; 2368 int flag, mask, error = 0; 2369 2370 switch (command) { 2371 case SIOCSIFFLAGS: 2372 FXP_LOCK(sc); 2373 if (ifp->if_flags & IFF_ALLMULTI) 2374 sc->flags |= FXP_FLAG_ALL_MCAST; 2375 else 2376 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2377 2378 /* 2379 * If interface is marked up and not running, then start it. 2380 * If it is marked down and running, stop it. 2381 * XXX If it's up then re-initialize it. This is so flags 2382 * such as IFF_PROMISC are handled. 2383 */ 2384 if (ifp->if_flags & IFF_UP) { 2385 fxp_init_body(sc); 2386 } else { 2387 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2388 fxp_stop(sc); 2389 } 2390 FXP_UNLOCK(sc); 2391 break; 2392 2393 case SIOCADDMULTI: 2394 case SIOCDELMULTI: 2395 FXP_LOCK(sc); 2396 if (ifp->if_flags & IFF_ALLMULTI) 2397 sc->flags |= FXP_FLAG_ALL_MCAST; 2398 else 2399 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2400 /* 2401 * Multicast list has changed; set the hardware filter 2402 * accordingly. 2403 */ 2404 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2405 fxp_mc_setup(sc); 2406 /* 2407 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2408 * again rather than else {}. 2409 */ 2410 if (sc->flags & FXP_FLAG_ALL_MCAST) 2411 fxp_init_body(sc); 2412 FXP_UNLOCK(sc); 2413 error = 0; 2414 break; 2415 2416 case SIOCSIFMEDIA: 2417 case SIOCGIFMEDIA: 2418 if (sc->miibus != NULL) { 2419 mii = device_get_softc(sc->miibus); 2420 error = ifmedia_ioctl(ifp, ifr, 2421 &mii->mii_media, command); 2422 } else { 2423 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2424 } 2425 break; 2426 2427 case SIOCSIFCAP: 2428 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2429 #ifdef DEVICE_POLLING 2430 if (mask & IFCAP_POLLING) { 2431 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2432 error = ether_poll_register(fxp_poll, ifp); 2433 if (error) 2434 return(error); 2435 FXP_LOCK(sc); 2436 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2437 FXP_SCB_INTR_DISABLE); 2438 ifp->if_capenable |= IFCAP_POLLING; 2439 FXP_UNLOCK(sc); 2440 } else { 2441 error = ether_poll_deregister(ifp); 2442 /* Enable interrupts in any case */ 2443 FXP_LOCK(sc); 2444 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2445 ifp->if_capenable &= ~IFCAP_POLLING; 2446 FXP_UNLOCK(sc); 2447 } 2448 } 2449 #endif 2450 if (mask & IFCAP_VLAN_MTU) { 2451 FXP_LOCK(sc); 2452 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2453 if (sc->revision != FXP_REV_82557) 2454 flag = FXP_FLAG_LONG_PKT_EN; 2455 else /* a hack to get long frames on the old chip */ 2456 flag = FXP_FLAG_SAVE_BAD; 2457 sc->flags ^= flag; 2458 if (ifp->if_flags & IFF_UP) 2459 fxp_init_body(sc); 2460 FXP_UNLOCK(sc); 2461 } 2462 break; 2463 2464 default: 2465 error = ether_ioctl(ifp, command, data); 2466 } 2467 return (error); 2468 } 2469 2470 /* 2471 * Fill in the multicast address list and return number of entries. 2472 */ 2473 static int 2474 fxp_mc_addrs(struct fxp_softc *sc) 2475 { 2476 struct fxp_cb_mcs *mcsp = sc->mcsp; 2477 struct ifnet *ifp = sc->ifp; 2478 struct ifmultiaddr *ifma; 2479 int nmcasts; 2480 2481 nmcasts = 0; 2482 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2483 IF_ADDR_LOCK(ifp); 2484 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2485 if (ifma->ifma_addr->sa_family != AF_LINK) 2486 continue; 2487 if (nmcasts >= MAXMCADDR) { 2488 sc->flags |= FXP_FLAG_ALL_MCAST; 2489 nmcasts = 0; 2490 break; 2491 } 2492 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2493 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2494 nmcasts++; 2495 } 2496 IF_ADDR_UNLOCK(ifp); 2497 } 2498 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2499 return (nmcasts); 2500 } 2501 2502 /* 2503 * Program the multicast filter. 2504 * 2505 * We have an artificial restriction that the multicast setup command 2506 * must be the first command in the chain, so we take steps to ensure 2507 * this. By requiring this, it allows us to keep up the performance of 2508 * the pre-initialized command ring (esp. link pointers) by not actually 2509 * inserting the mcsetup command in the ring - i.e. its link pointer 2510 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2511 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2512 * lead into the regular TxCB ring when it completes. 2513 * 2514 * This function must be called at splimp. 2515 */ 2516 static void 2517 fxp_mc_setup(struct fxp_softc *sc) 2518 { 2519 struct fxp_cb_mcs *mcsp = sc->mcsp; 2520 struct fxp_tx *txp; 2521 int count; 2522 2523 FXP_LOCK_ASSERT(sc, MA_OWNED); 2524 /* 2525 * If there are queued commands, we must wait until they are all 2526 * completed. If we are already waiting, then add a NOP command 2527 * with interrupt option so that we're notified when all commands 2528 * have been completed - fxp_start() ensures that no additional 2529 * TX commands will be added when need_mcsetup is true. 2530 */ 2531 if (sc->tx_queued) { 2532 /* 2533 * need_mcsetup will be true if we are already waiting for the 2534 * NOP command to be completed (see below). In this case, bail. 2535 */ 2536 if (sc->need_mcsetup) 2537 return; 2538 sc->need_mcsetup = 1; 2539 2540 /* 2541 * Add a NOP command with interrupt so that we are notified 2542 * when all TX commands have been processed. 2543 */ 2544 txp = sc->fxp_desc.tx_last->tx_next; 2545 txp->tx_mbuf = NULL; 2546 txp->tx_cb->cb_status = 0; 2547 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2548 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2549 /* 2550 * Advance the end of list forward. 2551 */ 2552 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2553 htole16(~FXP_CB_COMMAND_S); 2554 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2555 sc->fxp_desc.tx_last = txp; 2556 sc->tx_queued++; 2557 /* 2558 * Issue a resume in case the CU has just suspended. 2559 */ 2560 fxp_scb_wait(sc); 2561 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2562 /* 2563 * Set a 5 second timer just in case we don't hear from the 2564 * card again. 2565 */ 2566 sc->watchdog_timer = 5; 2567 2568 return; 2569 } 2570 sc->need_mcsetup = 0; 2571 2572 /* 2573 * Initialize multicast setup descriptor. 2574 */ 2575 mcsp->cb_status = 0; 2576 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2577 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2578 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2579 txp = &sc->fxp_desc.mcs_tx; 2580 txp->tx_mbuf = NULL; 2581 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2582 txp->tx_next = sc->fxp_desc.tx_list; 2583 (void) fxp_mc_addrs(sc); 2584 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2585 sc->tx_queued = 1; 2586 2587 /* 2588 * Wait until command unit is not active. This should never 2589 * be the case when nothing is queued, but make sure anyway. 2590 */ 2591 count = 100; 2592 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2593 FXP_SCB_CUS_ACTIVE && --count) 2594 DELAY(10); 2595 if (count == 0) { 2596 device_printf(sc->dev, "command queue timeout\n"); 2597 return; 2598 } 2599 2600 /* 2601 * Start the multicast setup command. 2602 */ 2603 fxp_scb_wait(sc); 2604 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2605 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2606 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2607 2608 sc->watchdog_timer = 2; 2609 return; 2610 } 2611 2612 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2613 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2614 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2615 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2616 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2617 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2618 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2619 2620 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2621 2622 struct ucode { 2623 uint32_t revision; 2624 uint32_t *ucode; 2625 int length; 2626 u_short int_delay_offset; 2627 u_short bundle_max_offset; 2628 } ucode_table[] = { 2629 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2630 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2631 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2632 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2633 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2634 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2635 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2636 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2637 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2638 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2639 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2640 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2641 { 0, NULL, 0, 0, 0 } 2642 }; 2643 2644 static void 2645 fxp_load_ucode(struct fxp_softc *sc) 2646 { 2647 struct ucode *uc; 2648 struct fxp_cb_ucode *cbp; 2649 int i; 2650 2651 for (uc = ucode_table; uc->ucode != NULL; uc++) 2652 if (sc->revision == uc->revision) 2653 break; 2654 if (uc->ucode == NULL) 2655 return; 2656 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2657 cbp->cb_status = 0; 2658 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2659 cbp->link_addr = 0xffffffff; /* (no) next command */ 2660 for (i = 0; i < uc->length; i++) 2661 cbp->ucode[i] = htole32(uc->ucode[i]); 2662 if (uc->int_delay_offset) 2663 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2664 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2665 if (uc->bundle_max_offset) 2666 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2667 htole16(sc->tunable_bundle_max); 2668 /* 2669 * Download the ucode to the chip. 2670 */ 2671 fxp_scb_wait(sc); 2672 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2673 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2674 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2675 /* ...and wait for it to complete. */ 2676 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2677 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2678 device_printf(sc->dev, 2679 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2680 sc->tunable_int_delay, 2681 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2682 sc->flags |= FXP_FLAG_UCODE; 2683 } 2684 2685 static int 2686 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2687 { 2688 int error, value; 2689 2690 value = *(int *)arg1; 2691 error = sysctl_handle_int(oidp, &value, 0, req); 2692 if (error || !req->newptr) 2693 return (error); 2694 if (value < low || value > high) 2695 return (EINVAL); 2696 *(int *)arg1 = value; 2697 return (0); 2698 } 2699 2700 /* 2701 * Interrupt delay is expressed in microseconds, a multiplier is used 2702 * to convert this to the appropriate clock ticks before using. 2703 */ 2704 static int 2705 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2706 { 2707 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2708 } 2709 2710 static int 2711 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2712 { 2713 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2714 } 2715