1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Modifications to support media selection: 6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 67 #include <pci/pcivar.h> 68 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 69 #include <pci/if_fxpreg.h> 70 #include <pci/if_fxpvar.h> 71 72 #ifdef __alpha__ /* XXX */ 73 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 74 #undef vtophys 75 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) 76 #endif /* __alpha__ */ 77 78 /* 79 * NOTE! On the Alpha, we have an alignment constraint. The 80 * card DMAs the packet immediately following the RFA. However, 81 * the first thing in the packet is a 14-byte Ethernet header. 82 * This means that the packet is misaligned. To compensate, 83 * we actually offset the RFA 2 bytes into the cluster. This 84 * alignes the packet after the Ethernet header at a 32-bit 85 * boundary. HOWEVER! This means that the RFA is misaligned! 86 */ 87 #define RFA_ALIGNMENT_FUDGE 2 88 89 /* 90 * Inline function to copy a 16-bit aligned 32-bit quantity. 91 */ 92 static __inline void fxp_lwcopy __P((volatile u_int32_t *, 93 volatile u_int32_t *)); 94 static __inline void 95 fxp_lwcopy(src, dst) 96 volatile u_int32_t *src, *dst; 97 { 98 #ifdef __i386__ 99 *dst = *src; 100 #else 101 volatile u_int16_t *a = (volatile u_int16_t *)src; 102 volatile u_int16_t *b = (volatile u_int16_t *)dst; 103 104 b[0] = a[0]; 105 b[1] = a[1]; 106 #endif 107 } 108 109 /* 110 * Template for default configuration parameters. 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x80, 0x2, /* cb_command */ 116 0xff, 0xff, 0xff, 0xff, /* link_addr */ 117 0x16, /* 0 */ 118 0x8, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x80, /* 5 */ 123 0xb2, /* 6 */ 124 0x3, /* 7 */ 125 0x1, /* 8 */ 126 0x0, /* 9 */ 127 0x26, /* 10 */ 128 0x0, /* 11 */ 129 0x60, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf3, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 /* Supported media types. */ 142 struct fxp_supported_media { 143 const int fsm_phy; /* PHY type */ 144 const int *fsm_media; /* the media array */ 145 const int fsm_nmedia; /* the number of supported media */ 146 const int fsm_defmedia; /* default media for this PHY */ 147 }; 148 149 static const int fxp_media_standard[] = { 150 IFM_ETHER|IFM_10_T, 151 IFM_ETHER|IFM_10_T|IFM_FDX, 152 IFM_ETHER|IFM_100_TX, 153 IFM_ETHER|IFM_100_TX|IFM_FDX, 154 IFM_ETHER|IFM_AUTO, 155 }; 156 #define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO) 157 158 static const int fxp_media_default[] = { 159 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */ 160 }; 161 #define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL) 162 163 static const struct fxp_supported_media fxp_media[] = { 164 { FXP_PHY_DP83840, fxp_media_standard, 165 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 166 FXP_MEDIA_STANDARD_DEFMEDIA }, 167 { FXP_PHY_DP83840A, fxp_media_standard, 168 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 169 FXP_MEDIA_STANDARD_DEFMEDIA }, 170 { FXP_PHY_82553A, fxp_media_standard, 171 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 172 FXP_MEDIA_STANDARD_DEFMEDIA }, 173 { FXP_PHY_82553C, fxp_media_standard, 174 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 175 FXP_MEDIA_STANDARD_DEFMEDIA }, 176 { FXP_PHY_82555, fxp_media_standard, 177 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 178 FXP_MEDIA_STANDARD_DEFMEDIA }, 179 { FXP_PHY_82555B, fxp_media_standard, 180 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 181 FXP_MEDIA_STANDARD_DEFMEDIA }, 182 { FXP_PHY_80C24, fxp_media_default, 183 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]), 184 FXP_MEDIA_DEFAULT_DEFMEDIA }, 185 }; 186 #define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0])) 187 188 static int fxp_mediachange __P((struct ifnet *)); 189 static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *)); 190 static void fxp_set_media __P((struct fxp_softc *, int)); 191 static __inline void fxp_scb_wait __P((struct fxp_softc *)); 192 static __inline void fxp_dma_wait __P((volatile u_int16_t *, struct fxp_softc *sc)); 193 static void fxp_intr __P((void *)); 194 static void fxp_start __P((struct ifnet *)); 195 static int fxp_ioctl __P((struct ifnet *, 196 u_long, caddr_t)); 197 static void fxp_init __P((void *)); 198 static void fxp_stop __P((struct fxp_softc *)); 199 static void fxp_watchdog __P((struct ifnet *)); 200 static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *)); 201 static int fxp_mdi_read __P((struct fxp_softc *, int, int)); 202 static void fxp_mdi_write __P((struct fxp_softc *, int, int, int)); 203 static void fxp_autosize_eeprom __P((struct fxp_softc *)); 204 static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, 205 int, int)); 206 static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *)); 207 static void fxp_stats_update __P((void *)); 208 static void fxp_mc_setup __P((struct fxp_softc *)); 209 210 /* 211 * Set initial transmit threshold at 64 (512 bytes). This is 212 * increased by 64 (512 bytes) at a time, to maximum of 192 213 * (1536 bytes), if an underrun occurs. 214 */ 215 static int tx_threshold = 64; 216 217 /* 218 * Number of transmit control blocks. This determines the number 219 * of transmit buffers that can be chained in the CB list. 220 * This must be a power of two. 221 */ 222 #define FXP_NTXCB 128 223 224 /* 225 * Number of completed TX commands at which point an interrupt 226 * will be generated to garbage collect the attached buffers. 227 * Must be at least one less than FXP_NTXCB, and should be 228 * enough less so that the transmitter doesn't becomes idle 229 * during the buffer rundown (which would reduce performance). 230 */ 231 #define FXP_CXINT_THRESH 120 232 233 /* 234 * TxCB list index mask. This is used to do list wrap-around. 235 */ 236 #define FXP_TXCB_MASK (FXP_NTXCB - 1) 237 238 /* 239 * Number of receive frame area buffers. These are large so chose 240 * wisely. 241 */ 242 #define FXP_NRFABUFS 64 243 244 /* 245 * Maximum number of seconds that the receiver can be idle before we 246 * assume it's dead and attempt to reset it by reprogramming the 247 * multicast filter. This is part of a work-around for a bug in the 248 * NIC. See fxp_stats_update(). 249 */ 250 #define FXP_MAX_RX_IDLE 15 251 252 /* 253 * Wait for the previous command to be accepted (but not necessarily 254 * completed). 255 */ 256 static __inline void 257 fxp_scb_wait(sc) 258 struct fxp_softc *sc; 259 { 260 int i = 10000; 261 262 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 263 DELAY(2); 264 if (i == 0) 265 printf("fxp%d: SCB timeout\n", FXP_UNIT(sc)); 266 } 267 268 static __inline void 269 fxp_dma_wait(status, sc) 270 volatile u_int16_t *status; 271 struct fxp_softc *sc; 272 { 273 int i = 10000; 274 275 while (!(*status & FXP_CB_STATUS_C) && --i) 276 DELAY(2); 277 if (i == 0) 278 printf("fxp%d: DMA timeout\n", FXP_UNIT(sc)); 279 } 280 281 /* 282 * Return identification string if this is device is ours. 283 */ 284 static int 285 fxp_probe(device_t dev) 286 { 287 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 288 switch (pci_get_device(dev)) { 289 290 case FXP_DEVICEID_i82557: 291 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet"); 292 return 0; 293 case FXP_DEVICEID_i82559: 294 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet"); 295 return 0; 296 case FXP_DEVICEID_i82559ER: 297 device_set_desc(dev, "Intel Embedded 10/100 Ethernet"); 298 return 0; 299 case FXP_DEVICEID_i82562: 300 device_set_desc(dev, "Intel PLC 10/100 Ethernet"); 301 return 0; 302 default: 303 break; 304 } 305 } 306 307 return ENXIO; 308 } 309 310 static int 311 fxp_attach(device_t dev) 312 { 313 int error = 0; 314 struct fxp_softc *sc = device_get_softc(dev); 315 struct ifnet *ifp; 316 u_int32_t val; 317 int rid, m1, m2, ebitmap; 318 319 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 320 callout_handle_init(&sc->stat_ch); 321 322 FXP_LOCK(sc); 323 324 /* 325 * Enable bus mastering. Enable memory space too, in case 326 * BIOS/Prom forgot about it. 327 */ 328 val = pci_read_config(dev, PCIR_COMMAND, 2); 329 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 330 pci_write_config(dev, PCIR_COMMAND, val, 2); 331 val = pci_read_config(dev, PCIR_COMMAND, 2); 332 333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 334 u_int32_t iobase, membase, irq; 335 336 /* Save important PCI config data. */ 337 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 338 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 339 irq = pci_read_config(dev, PCIR_INTLINE, 4); 340 341 /* Reset the power state. */ 342 device_printf(dev, "chip is in D%d power mode " 343 "-- setting to D0\n", pci_get_powerstate(dev)); 344 345 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 346 347 /* Restore PCI config data. */ 348 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 349 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 350 pci_write_config(dev, PCIR_INTLINE, irq, 4); 351 } 352 353 /* 354 * Figure out which we should try first - memory mapping or i/o mapping? 355 * We default to memory mapping. Then we accept an override from the 356 * command line. Then we check to see which one is enabled. 357 */ 358 m1 = PCIM_CMD_MEMEN; 359 m2 = PCIM_CMD_PORTEN; 360 ebitmap = 0; 361 if (getenv_int("fxp_iomap", &ebitmap)) { 362 if (ebitmap & (1 << device_get_unit(dev))) { 363 m1 = PCIM_CMD_PORTEN; 364 m2 = PCIM_CMD_MEMEN; 365 } 366 } 367 368 if (val & m1) { 369 sc->rtp = 370 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 371 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 372 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 373 0, ~0, 1, RF_ACTIVE); 374 } 375 if (sc->mem == NULL && (val & m2)) { 376 sc->rtp = 377 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 378 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 379 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 380 0, ~0, 1, RF_ACTIVE); 381 } 382 383 if (!sc->mem) { 384 device_printf(dev, "could not map device registers\n"); 385 error = ENXIO; 386 goto fail; 387 } 388 if (bootverbose) { 389 device_printf(dev, "using %s space register mapping\n", 390 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 391 } 392 393 sc->sc_st = rman_get_bustag(sc->mem); 394 sc->sc_sh = rman_get_bushandle(sc->mem); 395 396 /* 397 * Allocate our interrupt. 398 */ 399 rid = 0; 400 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 401 RF_SHAREABLE | RF_ACTIVE); 402 if (sc->irq == NULL) { 403 device_printf(dev, "could not map interrupt\n"); 404 error = ENXIO; 405 goto fail; 406 } 407 408 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 409 fxp_intr, sc, &sc->ih); 410 if (error) { 411 device_printf(dev, "could not setup irq\n"); 412 goto fail; 413 } 414 415 /* Do generic parts of attach. */ 416 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) { 417 /* Failed! */ 418 bus_teardown_intr(dev, sc->irq, sc->ih); 419 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 420 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 421 error = ENXIO; 422 goto fail; 423 } 424 425 device_printf(dev, "Ethernet address %6D%s\n", 426 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : ""); 427 428 ifp = &sc->arpcom.ac_if; 429 ifp->if_unit = device_get_unit(dev); 430 ifp->if_name = "fxp"; 431 ifp->if_output = ether_output; 432 ifp->if_baudrate = 100000000; 433 ifp->if_init = fxp_init; 434 ifp->if_softc = sc; 435 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 436 ifp->if_ioctl = fxp_ioctl; 437 ifp->if_start = fxp_start; 438 ifp->if_watchdog = fxp_watchdog; 439 440 /* 441 * Attach the interface. 442 */ 443 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 444 /* 445 * Let the system queue as many packets as we have available 446 * TX descriptors. 447 */ 448 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 449 450 FXP_UNLOCK(sc); 451 return 0; 452 453 fail: 454 FXP_UNLOCK(sc); 455 mtx_destroy(&sc->sc_mtx); 456 return error; 457 } 458 459 /* 460 * Detach interface. 461 */ 462 static int 463 fxp_detach(device_t dev) 464 { 465 struct fxp_softc *sc = device_get_softc(dev); 466 467 FXP_LOCK(sc); 468 469 /* 470 * Close down routes etc. 471 */ 472 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 473 474 /* 475 * Stop DMA and drop transmit queue. 476 */ 477 fxp_stop(sc); 478 479 /* 480 * Deallocate resources. 481 */ 482 bus_teardown_intr(dev, sc->irq, sc->ih); 483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 484 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 485 486 /* 487 * Free all the receive buffers. 488 */ 489 if (sc->rfa_headm != NULL) 490 m_freem(sc->rfa_headm); 491 492 /* 493 * Free all media structures. 494 */ 495 ifmedia_removeall(&sc->sc_media); 496 497 /* 498 * Free anciliary structures. 499 */ 500 free(sc->cbl_base, M_DEVBUF); 501 free(sc->fxp_stats, M_DEVBUF); 502 free(sc->mcsp, M_DEVBUF); 503 504 FXP_UNLOCK(sc); 505 mtx_destroy(&sc->sc_mtx); 506 507 return 0; 508 } 509 510 /* 511 * Device shutdown routine. Called at system shutdown after sync. The 512 * main purpose of this routine is to shut off receiver DMA so that 513 * kernel memory doesn't get clobbered during warmboot. 514 */ 515 static int 516 fxp_shutdown(device_t dev) 517 { 518 /* 519 * Make sure that DMA is disabled prior to reboot. Not doing 520 * do could allow DMA to corrupt kernel memory during the 521 * reboot before the driver initializes. 522 */ 523 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 524 return 0; 525 } 526 527 /* 528 * Device suspend routine. Stop the interface and save some PCI 529 * settings in case the BIOS doesn't restore them properly on 530 * resume. 531 */ 532 static int 533 fxp_suspend(device_t dev) 534 { 535 struct fxp_softc *sc = device_get_softc(dev); 536 int i; 537 538 FXP_LOCK(sc); 539 540 fxp_stop(sc); 541 542 for (i=0; i<5; i++) 543 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 544 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 545 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 546 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 547 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 548 549 sc->suspended = 1; 550 551 FXP_UNLOCK(sc); 552 553 return 0; 554 } 555 556 /* 557 * Device resume routine. Restore some PCI settings in case the BIOS 558 * doesn't, re-enable busmastering, and restart the interface if 559 * appropriate. 560 */ 561 static int 562 fxp_resume(device_t dev) 563 { 564 struct fxp_softc *sc = device_get_softc(dev); 565 struct ifnet *ifp = &sc->sc_if; 566 u_int16_t pci_command; 567 int i; 568 569 FXP_LOCK(sc); 570 571 /* better way to do this? */ 572 for (i=0; i<5; i++) 573 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 574 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 575 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 576 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 577 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 578 579 /* reenable busmastering */ 580 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 581 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 582 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 583 584 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 585 DELAY(10); 586 587 /* reinitialize interface if necessary */ 588 if (ifp->if_flags & IFF_UP) 589 fxp_init(sc); 590 591 sc->suspended = 0; 592 593 FXP_UNLOCK(sc); 594 595 return 0; 596 } 597 598 static device_method_t fxp_methods[] = { 599 /* Device interface */ 600 DEVMETHOD(device_probe, fxp_probe), 601 DEVMETHOD(device_attach, fxp_attach), 602 DEVMETHOD(device_detach, fxp_detach), 603 DEVMETHOD(device_shutdown, fxp_shutdown), 604 DEVMETHOD(device_suspend, fxp_suspend), 605 DEVMETHOD(device_resume, fxp_resume), 606 607 { 0, 0 } 608 }; 609 610 static driver_t fxp_driver = { 611 "fxp", 612 fxp_methods, 613 sizeof(struct fxp_softc), 614 }; 615 616 static devclass_t fxp_devclass; 617 618 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 619 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 620 621 /* 622 * Do generic parts of attach. 623 */ 624 static int 625 fxp_attach_common(sc, enaddr) 626 struct fxp_softc *sc; 627 u_int8_t *enaddr; 628 { 629 u_int16_t data; 630 int i, nmedia, defmedia; 631 const int *media; 632 633 /* 634 * Reset to a stable state. 635 */ 636 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 637 DELAY(10); 638 639 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 640 M_DEVBUF, M_NOWAIT | M_ZERO); 641 if (sc->cbl_base == NULL) 642 goto fail; 643 644 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 645 M_NOWAIT | M_ZERO); 646 if (sc->fxp_stats == NULL) 647 goto fail; 648 649 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 650 if (sc->mcsp == NULL) 651 goto fail; 652 653 /* 654 * Pre-allocate our receive buffers. 655 */ 656 for (i = 0; i < FXP_NRFABUFS; i++) { 657 if (fxp_add_rfabuf(sc, NULL) != 0) { 658 goto fail; 659 } 660 } 661 662 /* 663 * Find out how large of an SEEPROM we have. 664 */ 665 fxp_autosize_eeprom(sc); 666 667 /* 668 * Get info about the primary PHY 669 */ 670 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1); 671 sc->phy_primary_addr = data & 0xff; 672 sc->phy_primary_device = (data >> 8) & 0x3f; 673 sc->phy_10Mbps_only = data >> 15; 674 675 /* 676 * Read MAC address. 677 */ 678 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3); 679 680 /* 681 * Initialize the media structures. 682 */ 683 684 media = fxp_media_default; 685 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]); 686 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA; 687 688 for (i = 0; i < NFXPMEDIA; i++) { 689 if (sc->phy_primary_device == fxp_media[i].fsm_phy) { 690 media = fxp_media[i].fsm_media; 691 nmedia = fxp_media[i].fsm_nmedia; 692 defmedia = fxp_media[i].fsm_defmedia; 693 } 694 } 695 696 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus); 697 for (i = 0; i < nmedia; i++) { 698 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only) 699 continue; 700 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 701 } 702 ifmedia_set(&sc->sc_media, defmedia); 703 704 return (0); 705 706 fail: 707 printf("fxp%d: Failed to malloc memory\n", FXP_UNIT(sc)); 708 if (sc->cbl_base) 709 free(sc->cbl_base, M_DEVBUF); 710 if (sc->fxp_stats) 711 free(sc->fxp_stats, M_DEVBUF); 712 if (sc->mcsp) 713 free(sc->mcsp, M_DEVBUF); 714 /* frees entire chain */ 715 if (sc->rfa_headm) 716 m_freem(sc->rfa_headm); 717 718 return (ENOMEM); 719 } 720 721 /* 722 * From NetBSD: 723 * 724 * Figure out EEPROM size. 725 * 726 * 559's can have either 64-word or 256-word EEPROMs, the 558 727 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 728 * talks about the existance of 16 to 256 word EEPROMs. 729 * 730 * The only known sizes are 64 and 256, where the 256 version is used 731 * by CardBus cards to store CIS information. 732 * 733 * The address is shifted in msb-to-lsb, and after the last 734 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 735 * after which follows the actual data. We try to detect this zero, by 736 * probing the data-out bit in the EEPROM control register just after 737 * having shifted in a bit. If the bit is zero, we assume we've 738 * shifted enough address bits. The data-out should be tri-state, 739 * before this, which should translate to a logical one. 740 * 741 * Other ways to do this would be to try to read a register with known 742 * contents with a varying number of address bits, but no such 743 * register seem to be available. The high bits of register 10 are 01 744 * on the 558 and 559, but apparently not on the 557. 745 * 746 * The Linux driver computes a checksum on the EEPROM data, but the 747 * value of this checksum is not very well documented. 748 */ 749 static void 750 fxp_autosize_eeprom(sc) 751 struct fxp_softc *sc; 752 { 753 u_int16_t reg; 754 int x; 755 756 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 757 /* 758 * Shift in read opcode. 759 */ 760 for (x = 3; x > 0; x--) { 761 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 762 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 763 } else { 764 reg = FXP_EEPROM_EECS; 765 } 766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 767 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 768 reg | FXP_EEPROM_EESK); 769 DELAY(1); 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 771 DELAY(1); 772 } 773 /* 774 * Shift in address. 775 * Wait for the dummy zero following a correct address shift. 776 */ 777 for (x = 1; x <= 8; x++) { 778 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 779 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 780 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 781 DELAY(1); 782 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0) 783 break; 784 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 785 DELAY(1); 786 } 787 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 788 DELAY(1); 789 sc->eeprom_size = x; 790 } 791 /* 792 * Read from the serial EEPROM. Basically, you manually shift in 793 * the read opcode (one bit at a time) and then shift in the address, 794 * and then you shift out the data (all of this one bit at a time). 795 * The word size is 16 bits, so you have to provide the address for 796 * every 16 bits of data. 797 */ 798 static void 799 fxp_read_eeprom(sc, data, offset, words) 800 struct fxp_softc *sc; 801 u_short *data; 802 int offset; 803 int words; 804 { 805 u_int16_t reg; 806 int i, x; 807 808 for (i = 0; i < words; i++) { 809 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 810 /* 811 * Shift in read opcode. 812 */ 813 for (x = 3; x > 0; x--) { 814 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 815 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 816 } else { 817 reg = FXP_EEPROM_EECS; 818 } 819 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 820 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 821 reg | FXP_EEPROM_EESK); 822 DELAY(1); 823 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 824 DELAY(1); 825 } 826 /* 827 * Shift in address. 828 */ 829 for (x = sc->eeprom_size; x > 0; x--) { 830 if ((i + offset) & (1 << (x - 1))) { 831 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 832 } else { 833 reg = FXP_EEPROM_EECS; 834 } 835 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 836 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 837 reg | FXP_EEPROM_EESK); 838 DELAY(1); 839 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 840 DELAY(1); 841 } 842 reg = FXP_EEPROM_EECS; 843 data[i] = 0; 844 /* 845 * Shift out data. 846 */ 847 for (x = 16; x > 0; x--) { 848 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 849 reg | FXP_EEPROM_EESK); 850 DELAY(1); 851 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 852 FXP_EEPROM_EEDO) 853 data[i] |= (1 << (x - 1)); 854 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 855 DELAY(1); 856 } 857 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 858 DELAY(1); 859 } 860 } 861 862 /* 863 * Start packet transmission on the interface. 864 */ 865 static void 866 fxp_start(ifp) 867 struct ifnet *ifp; 868 { 869 struct fxp_softc *sc = ifp->if_softc; 870 struct fxp_cb_tx *txp; 871 872 FXP_LOCK(sc); 873 /* 874 * See if we need to suspend xmit until the multicast filter 875 * has been reprogrammed (which can only be done at the head 876 * of the command chain). 877 */ 878 if (sc->need_mcsetup) { 879 FXP_UNLOCK(sc); 880 return; 881 } 882 883 txp = NULL; 884 885 /* 886 * We're finished if there is nothing more to add to the list or if 887 * we're all filled up with buffers to transmit. 888 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 889 * a NOP command when needed. 890 */ 891 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 892 struct mbuf *m, *mb_head; 893 int segment; 894 895 /* 896 * Grab a packet to transmit. 897 */ 898 IF_DEQUEUE(&ifp->if_snd, mb_head); 899 900 /* 901 * Get pointer to next available tx desc. 902 */ 903 txp = sc->cbl_last->next; 904 905 /* 906 * Go through each of the mbufs in the chain and initialize 907 * the transmit buffer descriptors with the physical address 908 * and size of the mbuf. 909 */ 910 tbdinit: 911 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 912 if (m->m_len != 0) { 913 if (segment == FXP_NTXSEG) 914 break; 915 txp->tbd[segment].tb_addr = 916 vtophys(mtod(m, vm_offset_t)); 917 txp->tbd[segment].tb_size = m->m_len; 918 segment++; 919 } 920 } 921 if (m != NULL) { 922 struct mbuf *mn; 923 924 /* 925 * We ran out of segments. We have to recopy this mbuf 926 * chain first. Bail out if we can't get the new buffers. 927 */ 928 MGETHDR(mn, M_DONTWAIT, MT_DATA); 929 if (mn == NULL) { 930 m_freem(mb_head); 931 break; 932 } 933 if (mb_head->m_pkthdr.len > MHLEN) { 934 MCLGET(mn, M_DONTWAIT); 935 if ((mn->m_flags & M_EXT) == 0) { 936 m_freem(mn); 937 m_freem(mb_head); 938 break; 939 } 940 } 941 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 942 mtod(mn, caddr_t)); 943 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 944 m_freem(mb_head); 945 mb_head = mn; 946 goto tbdinit; 947 } 948 949 txp->tbd_number = segment; 950 txp->mb_head = mb_head; 951 txp->cb_status = 0; 952 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 953 txp->cb_command = 954 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S; 955 } else { 956 txp->cb_command = 957 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 958 /* 959 * Set a 5 second timer just in case we don't hear from the 960 * card again. 961 */ 962 ifp->if_timer = 5; 963 } 964 txp->tx_threshold = tx_threshold; 965 966 /* 967 * Advance the end of list forward. 968 */ 969 970 #ifdef __alpha__ 971 /* 972 * On platforms which can't access memory in 16-bit 973 * granularities, we must prevent the card from DMA'ing 974 * up the status while we update the command field. 975 * This could cause us to overwrite the completion status. 976 */ 977 atomic_clear_short(&sc->cbl_last->cb_command, 978 FXP_CB_COMMAND_S); 979 #else 980 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 981 #endif /*__alpha__*/ 982 sc->cbl_last = txp; 983 984 /* 985 * Advance the beginning of the list forward if there are 986 * no other packets queued (when nothing is queued, cbl_first 987 * sits on the last TxCB that was sent out). 988 */ 989 if (sc->tx_queued == 0) 990 sc->cbl_first = txp; 991 992 sc->tx_queued++; 993 994 /* 995 * Pass packet to bpf if there is a listener. 996 */ 997 if (ifp->if_bpf) 998 bpf_mtap(ifp, mb_head); 999 } 1000 1001 /* 1002 * We're finished. If we added to the list, issue a RESUME to get DMA 1003 * going again if suspended. 1004 */ 1005 if (txp != NULL) { 1006 fxp_scb_wait(sc); 1007 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1008 } 1009 FXP_UNLOCK(sc); 1010 } 1011 1012 /* 1013 * Process interface interrupts. 1014 */ 1015 static void 1016 fxp_intr(arg) 1017 void *arg; 1018 { 1019 struct fxp_softc *sc = arg; 1020 struct ifnet *ifp = &sc->sc_if; 1021 u_int8_t statack; 1022 1023 FXP_LOCK(sc); 1024 1025 if (sc->suspended) { 1026 FXP_UNLOCK(sc); 1027 return; 1028 } 1029 1030 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1031 /* 1032 * First ACK all the interrupts in this pass. 1033 */ 1034 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1035 1036 /* 1037 * Free any finished transmit mbuf chains. 1038 * 1039 * Handle the CNA event likt a CXTNO event. It used to 1040 * be that this event (control unit not ready) was not 1041 * encountered, but it is now with the SMPng modifications. 1042 * The exact sequence of events that occur when the interface 1043 * is brought up are different now, and if this event 1044 * goes unhandled, the configuration/rxfilter setup sequence 1045 * can stall for several seconds. The result is that no 1046 * packets go out onto the wire for about 5 to 10 seconds 1047 * after the interface is ifconfig'ed for the first time. 1048 */ 1049 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1050 struct fxp_cb_tx *txp; 1051 1052 for (txp = sc->cbl_first; sc->tx_queued && 1053 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1054 txp = txp->next) { 1055 if (txp->mb_head != NULL) { 1056 m_freem(txp->mb_head); 1057 txp->mb_head = NULL; 1058 } 1059 sc->tx_queued--; 1060 } 1061 sc->cbl_first = txp; 1062 ifp->if_timer = 0; 1063 if (sc->tx_queued == 0) { 1064 if (sc->need_mcsetup) 1065 fxp_mc_setup(sc); 1066 } 1067 /* 1068 * Try to start more packets transmitting. 1069 */ 1070 if (ifp->if_snd.ifq_head != NULL) 1071 fxp_start(ifp); 1072 } 1073 /* 1074 * Process receiver interrupts. If a no-resource (RNR) 1075 * condition exists, get whatever packets we can and 1076 * re-start the receiver. 1077 */ 1078 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1079 struct mbuf *m; 1080 struct fxp_rfa *rfa; 1081 rcvloop: 1082 m = sc->rfa_headm; 1083 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1084 RFA_ALIGNMENT_FUDGE); 1085 1086 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1087 /* 1088 * Remove first packet from the chain. 1089 */ 1090 sc->rfa_headm = m->m_next; 1091 m->m_next = NULL; 1092 1093 /* 1094 * Add a new buffer to the receive chain. 1095 * If this fails, the old buffer is recycled 1096 * instead. 1097 */ 1098 if (fxp_add_rfabuf(sc, m) == 0) { 1099 struct ether_header *eh; 1100 int total_len; 1101 1102 total_len = rfa->actual_size & 1103 (MCLBYTES - 1); 1104 if (total_len < 1105 sizeof(struct ether_header)) { 1106 m_freem(m); 1107 goto rcvloop; 1108 } 1109 m->m_pkthdr.rcvif = ifp; 1110 m->m_pkthdr.len = m->m_len = total_len; 1111 eh = mtod(m, struct ether_header *); 1112 m->m_data += 1113 sizeof(struct ether_header); 1114 m->m_len -= 1115 sizeof(struct ether_header); 1116 m->m_pkthdr.len = m->m_len; 1117 ether_input(ifp, eh, m); 1118 } 1119 goto rcvloop; 1120 } 1121 if (statack & FXP_SCB_STATACK_RNR) { 1122 fxp_scb_wait(sc); 1123 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1124 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1125 RFA_ALIGNMENT_FUDGE); 1126 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1127 FXP_SCB_COMMAND_RU_START); 1128 } 1129 } 1130 } 1131 FXP_UNLOCK(sc); 1132 } 1133 1134 /* 1135 * Update packet in/out/collision statistics. The i82557 doesn't 1136 * allow you to access these counters without doing a fairly 1137 * expensive DMA to get _all_ of the statistics it maintains, so 1138 * we do this operation here only once per second. The statistics 1139 * counters in the kernel are updated from the previous dump-stats 1140 * DMA and then a new dump-stats DMA is started. The on-chip 1141 * counters are zeroed when the DMA completes. If we can't start 1142 * the DMA immediately, we don't wait - we just prepare to read 1143 * them again next time. 1144 */ 1145 static void 1146 fxp_stats_update(arg) 1147 void *arg; 1148 { 1149 struct fxp_softc *sc = arg; 1150 struct ifnet *ifp = &sc->sc_if; 1151 struct fxp_stats *sp = sc->fxp_stats; 1152 struct fxp_cb_tx *txp; 1153 1154 ifp->if_opackets += sp->tx_good; 1155 ifp->if_collisions += sp->tx_total_collisions; 1156 if (sp->rx_good) { 1157 ifp->if_ipackets += sp->rx_good; 1158 sc->rx_idle_secs = 0; 1159 } else { 1160 /* 1161 * Receiver's been idle for another second. 1162 */ 1163 sc->rx_idle_secs++; 1164 } 1165 ifp->if_ierrors += 1166 sp->rx_crc_errors + 1167 sp->rx_alignment_errors + 1168 sp->rx_rnr_errors + 1169 sp->rx_overrun_errors; 1170 /* 1171 * If any transmit underruns occured, bump up the transmit 1172 * threshold by another 512 bytes (64 * 8). 1173 */ 1174 if (sp->tx_underruns) { 1175 ifp->if_oerrors += sp->tx_underruns; 1176 if (tx_threshold < 192) 1177 tx_threshold += 64; 1178 } 1179 FXP_LOCK(sc); 1180 /* 1181 * Release any xmit buffers that have completed DMA. This isn't 1182 * strictly necessary to do here, but it's advantagous for mbufs 1183 * with external storage to be released in a timely manner rather 1184 * than being defered for a potentially long time. This limits 1185 * the delay to a maximum of one second. 1186 */ 1187 for (txp = sc->cbl_first; sc->tx_queued && 1188 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1189 txp = txp->next) { 1190 if (txp->mb_head != NULL) { 1191 m_freem(txp->mb_head); 1192 txp->mb_head = NULL; 1193 } 1194 sc->tx_queued--; 1195 } 1196 sc->cbl_first = txp; 1197 /* 1198 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1199 * then assume the receiver has locked up and attempt to clear 1200 * the condition by reprogramming the multicast filter. This is 1201 * a work-around for a bug in the 82557 where the receiver locks 1202 * up if it gets certain types of garbage in the syncronization 1203 * bits prior to the packet header. This bug is supposed to only 1204 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1205 * mode as well (perhaps due to a 10/100 speed transition). 1206 */ 1207 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1208 sc->rx_idle_secs = 0; 1209 fxp_mc_setup(sc); 1210 } 1211 /* 1212 * If there is no pending command, start another stats 1213 * dump. Otherwise punt for now. 1214 */ 1215 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1216 /* 1217 * Start another stats dump. 1218 */ 1219 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1220 FXP_SCB_COMMAND_CU_DUMPRESET); 1221 } else { 1222 /* 1223 * A previous command is still waiting to be accepted. 1224 * Just zero our copy of the stats and wait for the 1225 * next timer event to update them. 1226 */ 1227 sp->tx_good = 0; 1228 sp->tx_underruns = 0; 1229 sp->tx_total_collisions = 0; 1230 1231 sp->rx_good = 0; 1232 sp->rx_crc_errors = 0; 1233 sp->rx_alignment_errors = 0; 1234 sp->rx_rnr_errors = 0; 1235 sp->rx_overrun_errors = 0; 1236 } 1237 FXP_UNLOCK(sc); 1238 /* 1239 * Schedule another timeout one second from now. 1240 */ 1241 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1242 } 1243 1244 /* 1245 * Stop the interface. Cancels the statistics updater and resets 1246 * the interface. 1247 */ 1248 static void 1249 fxp_stop(sc) 1250 struct fxp_softc *sc; 1251 { 1252 struct ifnet *ifp = &sc->sc_if; 1253 struct fxp_cb_tx *txp; 1254 int i; 1255 1256 FXP_LOCK(sc); 1257 1258 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1259 ifp->if_timer = 0; 1260 1261 /* 1262 * Cancel stats updater. 1263 */ 1264 untimeout(fxp_stats_update, sc, sc->stat_ch); 1265 1266 /* 1267 * Issue software reset 1268 */ 1269 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1270 DELAY(10); 1271 1272 /* 1273 * Release any xmit buffers. 1274 */ 1275 txp = sc->cbl_base; 1276 if (txp != NULL) { 1277 for (i = 0; i < FXP_NTXCB; i++) { 1278 if (txp[i].mb_head != NULL) { 1279 m_freem(txp[i].mb_head); 1280 txp[i].mb_head = NULL; 1281 } 1282 } 1283 } 1284 sc->tx_queued = 0; 1285 1286 /* 1287 * Free all the receive buffers then reallocate/reinitialize 1288 */ 1289 if (sc->rfa_headm != NULL) 1290 m_freem(sc->rfa_headm); 1291 sc->rfa_headm = NULL; 1292 sc->rfa_tailm = NULL; 1293 for (i = 0; i < FXP_NRFABUFS; i++) { 1294 if (fxp_add_rfabuf(sc, NULL) != 0) { 1295 /* 1296 * This "can't happen" - we're at splimp() 1297 * and we just freed all the buffers we need 1298 * above. 1299 */ 1300 panic("fxp_stop: no buffers!"); 1301 } 1302 } 1303 1304 FXP_UNLOCK(sc); 1305 } 1306 1307 /* 1308 * Watchdog/transmission transmit timeout handler. Called when a 1309 * transmission is started on the interface, but no interrupt is 1310 * received before the timeout. This usually indicates that the 1311 * card has wedged for some reason. 1312 */ 1313 static void 1314 fxp_watchdog(ifp) 1315 struct ifnet *ifp; 1316 { 1317 struct fxp_softc *sc = ifp->if_softc; 1318 1319 printf("fxp%d: device timeout\n", FXP_UNIT(sc)); 1320 ifp->if_oerrors++; 1321 1322 fxp_init(sc); 1323 } 1324 1325 static void 1326 fxp_init(xsc) 1327 void *xsc; 1328 { 1329 struct fxp_softc *sc = xsc; 1330 struct ifnet *ifp = &sc->sc_if; 1331 struct fxp_cb_config *cbp; 1332 struct fxp_cb_ias *cb_ias; 1333 struct fxp_cb_tx *txp; 1334 int i, prm; 1335 1336 FXP_LOCK(sc); 1337 /* 1338 * Cancel any pending I/O 1339 */ 1340 fxp_stop(sc); 1341 1342 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1343 1344 /* 1345 * Initialize base of CBL and RFA memory. Loading with zero 1346 * sets it up for regular linear addressing. 1347 */ 1348 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1349 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1350 1351 fxp_scb_wait(sc); 1352 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1353 1354 /* 1355 * Initialize base of dump-stats buffer. 1356 */ 1357 fxp_scb_wait(sc); 1358 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1359 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1360 1361 /* 1362 * We temporarily use memory that contains the TxCB list to 1363 * construct the config CB. The TxCB list memory is rebuilt 1364 * later. 1365 */ 1366 cbp = (struct fxp_cb_config *) sc->cbl_base; 1367 1368 /* 1369 * This bcopy is kind of disgusting, but there are a bunch of must be 1370 * zero and must be one bits in this structure and this is the easiest 1371 * way to initialize them all to proper values. 1372 */ 1373 bcopy(fxp_cb_config_template, 1374 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1375 sizeof(fxp_cb_config_template)); 1376 1377 cbp->cb_status = 0; 1378 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1379 cbp->link_addr = -1; /* (no) next command */ 1380 cbp->byte_count = 22; /* (22) bytes to config */ 1381 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1382 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1383 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1384 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1385 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1386 cbp->dma_bce = 0; /* (disable) dma max counters */ 1387 cbp->late_scb = 0; /* (don't) defer SCB update */ 1388 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1389 cbp->ci_int = 1; /* interrupt on CU idle */ 1390 cbp->save_bf = prm; /* save bad frames */ 1391 cbp->disc_short_rx = !prm; /* discard short packets */ 1392 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1393 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1394 cbp->nsai = 1; /* (don't) disable source addr insert */ 1395 cbp->preamble_length = 2; /* (7 byte) preamble */ 1396 cbp->loopback = 0; /* (don't) loopback */ 1397 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1398 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1399 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1400 cbp->promiscuous = prm; /* promiscuous mode */ 1401 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1402 cbp->crscdt = 0; /* (CRS only) */ 1403 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1404 cbp->padding = 1; /* (do) pad short tx packets */ 1405 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1406 cbp->force_fdx = 0; /* (don't) force full duplex */ 1407 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1408 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1409 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */ 1410 1411 /* 1412 * Start the config command/DMA. 1413 */ 1414 fxp_scb_wait(sc); 1415 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1416 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1417 /* ...and wait for it to complete. */ 1418 fxp_dma_wait(&cbp->cb_status, sc); 1419 1420 /* 1421 * Now initialize the station address. Temporarily use the TxCB 1422 * memory area like we did above for the config CB. 1423 */ 1424 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1425 cb_ias->cb_status = 0; 1426 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1427 cb_ias->link_addr = -1; 1428 bcopy(sc->arpcom.ac_enaddr, 1429 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1430 sizeof(sc->arpcom.ac_enaddr)); 1431 1432 /* 1433 * Start the IAS (Individual Address Setup) command/DMA. 1434 */ 1435 fxp_scb_wait(sc); 1436 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1437 /* ...and wait for it to complete. */ 1438 fxp_dma_wait(&cb_ias->cb_status, sc); 1439 1440 /* 1441 * Initialize transmit control block (TxCB) list. 1442 */ 1443 1444 txp = sc->cbl_base; 1445 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1446 for (i = 0; i < FXP_NTXCB; i++) { 1447 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1448 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1449 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1450 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1451 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1452 } 1453 /* 1454 * Set the suspend flag on the first TxCB and start the control 1455 * unit. It will execute the NOP and then suspend. 1456 */ 1457 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1458 sc->cbl_first = sc->cbl_last = txp; 1459 sc->tx_queued = 1; 1460 1461 fxp_scb_wait(sc); 1462 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1463 1464 /* 1465 * Initialize receiver buffer area - RFA. 1466 */ 1467 fxp_scb_wait(sc); 1468 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1469 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1470 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1471 1472 /* 1473 * Set current media. 1474 */ 1475 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 1476 1477 ifp->if_flags |= IFF_RUNNING; 1478 ifp->if_flags &= ~IFF_OACTIVE; 1479 FXP_UNLOCK(sc); 1480 1481 /* 1482 * Start stats updater. 1483 */ 1484 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1485 } 1486 1487 static void 1488 fxp_set_media(sc, media) 1489 struct fxp_softc *sc; 1490 int media; 1491 { 1492 1493 switch (sc->phy_primary_device) { 1494 case FXP_PHY_DP83840: 1495 case FXP_PHY_DP83840A: 1496 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR, 1497 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) | 1498 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */ 1499 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */ 1500 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */ 1501 /* fall through */ 1502 case FXP_PHY_82553A: 1503 case FXP_PHY_82553C: /* untested */ 1504 case FXP_PHY_82555: 1505 case FXP_PHY_82555B: 1506 if (IFM_SUBTYPE(media) != IFM_AUTO) { 1507 int flags; 1508 1509 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ? 1510 FXP_PHY_BMCR_SPEED_100M : 0; 1511 flags |= (media & IFM_FDX) ? 1512 FXP_PHY_BMCR_FULLDUPLEX : 0; 1513 fxp_mdi_write(sc, sc->phy_primary_addr, 1514 FXP_PHY_BMCR, 1515 (fxp_mdi_read(sc, sc->phy_primary_addr, 1516 FXP_PHY_BMCR) & 1517 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M | 1518 FXP_PHY_BMCR_FULLDUPLEX)) | flags); 1519 } else { 1520 fxp_mdi_write(sc, sc->phy_primary_addr, 1521 FXP_PHY_BMCR, 1522 (fxp_mdi_read(sc, sc->phy_primary_addr, 1523 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN)); 1524 } 1525 break; 1526 /* 1527 * The Seeq 80c24 doesn't have a PHY programming interface, so do 1528 * nothing. 1529 */ 1530 case FXP_PHY_80C24: 1531 break; 1532 default: 1533 printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n", 1534 FXP_UNIT(sc), sc->phy_primary_device, 1535 sc->phy_primary_addr); 1536 } 1537 } 1538 1539 /* 1540 * Change media according to request. 1541 */ 1542 int 1543 fxp_mediachange(ifp) 1544 struct ifnet *ifp; 1545 { 1546 struct fxp_softc *sc = ifp->if_softc; 1547 struct ifmedia *ifm = &sc->sc_media; 1548 1549 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1550 return (EINVAL); 1551 1552 fxp_set_media(sc, ifm->ifm_media); 1553 return (0); 1554 } 1555 1556 /* 1557 * Notify the world which media we're using. 1558 */ 1559 void 1560 fxp_mediastatus(ifp, ifmr) 1561 struct ifnet *ifp; 1562 struct ifmediareq *ifmr; 1563 { 1564 struct fxp_softc *sc = ifp->if_softc; 1565 int flags, stsflags; 1566 1567 switch (sc->phy_primary_device) { 1568 case FXP_PHY_82555: 1569 case FXP_PHY_82555B: 1570 case FXP_PHY_DP83840: 1571 case FXP_PHY_DP83840A: 1572 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */ 1573 ifmr->ifm_active = IFM_ETHER; 1574 /* 1575 * the following is not an error. 1576 * You need to read this register twice to get current 1577 * status. This is correct documented behaviour, the 1578 * first read gets latched values. 1579 */ 1580 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1581 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1582 if (stsflags & FXP_PHY_STS_LINK_STS) 1583 ifmr->ifm_status |= IFM_ACTIVE; 1584 1585 /* 1586 * If we are in auto mode, then try report the result. 1587 */ 1588 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR); 1589 if (flags & FXP_PHY_BMCR_AUTOEN) { 1590 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */ 1591 if (stsflags & FXP_PHY_STS_AUTO_DONE) { 1592 /* 1593 * Intel and National parts report 1594 * differently on what they found. 1595 */ 1596 if ((sc->phy_primary_device == FXP_PHY_82555) 1597 || (sc->phy_primary_device == FXP_PHY_82555B)) { 1598 flags = fxp_mdi_read(sc, 1599 sc->phy_primary_addr, 1600 FXP_PHY_USC); 1601 1602 if (flags & FXP_PHY_USC_SPEED) 1603 ifmr->ifm_active |= IFM_100_TX; 1604 else 1605 ifmr->ifm_active |= IFM_10_T; 1606 1607 if (flags & FXP_PHY_USC_DUPLEX) 1608 ifmr->ifm_active |= IFM_FDX; 1609 } else { /* it's National. only know speed */ 1610 flags = fxp_mdi_read(sc, 1611 sc->phy_primary_addr, 1612 FXP_DP83840_PAR); 1613 1614 if (flags & FXP_DP83840_PAR_SPEED_10) 1615 ifmr->ifm_active |= IFM_10_T; 1616 else 1617 ifmr->ifm_active |= IFM_100_TX; 1618 } 1619 } 1620 } else { /* in manual mode.. just report what we were set to */ 1621 if (flags & FXP_PHY_BMCR_SPEED_100M) 1622 ifmr->ifm_active |= IFM_100_TX; 1623 else 1624 ifmr->ifm_active |= IFM_10_T; 1625 1626 if (flags & FXP_PHY_BMCR_FULLDUPLEX) 1627 ifmr->ifm_active |= IFM_FDX; 1628 } 1629 break; 1630 1631 case FXP_PHY_80C24: 1632 default: 1633 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */ 1634 } 1635 } 1636 1637 /* 1638 * Add a buffer to the end of the RFA buffer list. 1639 * Return 0 if successful, 1 for failure. A failure results in 1640 * adding the 'oldm' (if non-NULL) on to the end of the list - 1641 * tossing out its old contents and recycling it. 1642 * The RFA struct is stuck at the beginning of mbuf cluster and the 1643 * data pointer is fixed up to point just past it. 1644 */ 1645 static int 1646 fxp_add_rfabuf(sc, oldm) 1647 struct fxp_softc *sc; 1648 struct mbuf *oldm; 1649 { 1650 u_int32_t v; 1651 struct mbuf *m; 1652 struct fxp_rfa *rfa, *p_rfa; 1653 1654 MGETHDR(m, M_DONTWAIT, MT_DATA); 1655 if (m != NULL) { 1656 MCLGET(m, M_DONTWAIT); 1657 if ((m->m_flags & M_EXT) == 0) { 1658 m_freem(m); 1659 if (oldm == NULL) 1660 return 1; 1661 m = oldm; 1662 m->m_data = m->m_ext.ext_buf; 1663 } 1664 } else { 1665 if (oldm == NULL) 1666 return 1; 1667 m = oldm; 1668 m->m_data = m->m_ext.ext_buf; 1669 } 1670 1671 /* 1672 * Move the data pointer up so that the incoming data packet 1673 * will be 32-bit aligned. 1674 */ 1675 m->m_data += RFA_ALIGNMENT_FUDGE; 1676 1677 /* 1678 * Get a pointer to the base of the mbuf cluster and move 1679 * data start past it. 1680 */ 1681 rfa = mtod(m, struct fxp_rfa *); 1682 m->m_data += sizeof(struct fxp_rfa); 1683 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1684 1685 /* 1686 * Initialize the rest of the RFA. Note that since the RFA 1687 * is misaligned, we cannot store values directly. Instead, 1688 * we use an optimized, inline copy. 1689 */ 1690 1691 rfa->rfa_status = 0; 1692 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1693 rfa->actual_size = 0; 1694 1695 v = -1; 1696 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1697 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1698 1699 /* 1700 * If there are other buffers already on the list, attach this 1701 * one to the end by fixing up the tail to point to this one. 1702 */ 1703 if (sc->rfa_headm != NULL) { 1704 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1705 RFA_ALIGNMENT_FUDGE); 1706 sc->rfa_tailm->m_next = m; 1707 v = vtophys(rfa); 1708 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1709 p_rfa->rfa_control = 0; 1710 } else { 1711 sc->rfa_headm = m; 1712 } 1713 sc->rfa_tailm = m; 1714 1715 return (m == oldm); 1716 } 1717 1718 static volatile int 1719 fxp_mdi_read(sc, phy, reg) 1720 struct fxp_softc *sc; 1721 int phy; 1722 int reg; 1723 { 1724 int count = 10000; 1725 int value; 1726 1727 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1728 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1729 1730 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1731 && count--) 1732 DELAY(10); 1733 1734 if (count <= 0) 1735 printf("fxp%d: fxp_mdi_read: timed out\n", FXP_UNIT(sc)); 1736 1737 return (value & 0xffff); 1738 } 1739 1740 static void 1741 fxp_mdi_write(sc, phy, reg, value) 1742 struct fxp_softc *sc; 1743 int phy; 1744 int reg; 1745 int value; 1746 { 1747 int count = 10000; 1748 1749 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1750 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1751 (value & 0xffff)); 1752 1753 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1754 count--) 1755 DELAY(10); 1756 1757 if (count <= 0) 1758 printf("fxp%d: fxp_mdi_write: timed out\n", FXP_UNIT(sc)); 1759 } 1760 1761 static int 1762 fxp_ioctl(ifp, command, data) 1763 struct ifnet *ifp; 1764 u_long command; 1765 caddr_t data; 1766 { 1767 struct fxp_softc *sc = ifp->if_softc; 1768 struct ifreq *ifr = (struct ifreq *)data; 1769 int error = 0; 1770 1771 FXP_LOCK(sc); 1772 1773 switch (command) { 1774 1775 case SIOCSIFADDR: 1776 case SIOCGIFADDR: 1777 case SIOCSIFMTU: 1778 error = ether_ioctl(ifp, command, data); 1779 break; 1780 1781 case SIOCSIFFLAGS: 1782 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1783 1784 /* 1785 * If interface is marked up and not running, then start it. 1786 * If it is marked down and running, stop it. 1787 * XXX If it's up then re-initialize it. This is so flags 1788 * such as IFF_PROMISC are handled. 1789 */ 1790 if (ifp->if_flags & IFF_UP) { 1791 fxp_init(sc); 1792 } else { 1793 if (ifp->if_flags & IFF_RUNNING) 1794 fxp_stop(sc); 1795 } 1796 break; 1797 1798 case SIOCADDMULTI: 1799 case SIOCDELMULTI: 1800 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1801 /* 1802 * Multicast list has changed; set the hardware filter 1803 * accordingly. 1804 */ 1805 if (!sc->all_mcasts) 1806 fxp_mc_setup(sc); 1807 /* 1808 * fxp_mc_setup() can turn on sc->all_mcasts, so check it 1809 * again rather than else {}. 1810 */ 1811 if (sc->all_mcasts) 1812 fxp_init(sc); 1813 error = 0; 1814 break; 1815 1816 case SIOCSIFMEDIA: 1817 case SIOCGIFMEDIA: 1818 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1819 break; 1820 1821 default: 1822 error = EINVAL; 1823 } 1824 FXP_UNLOCK(sc); 1825 return (error); 1826 } 1827 1828 /* 1829 * Program the multicast filter. 1830 * 1831 * We have an artificial restriction that the multicast setup command 1832 * must be the first command in the chain, so we take steps to ensure 1833 * this. By requiring this, it allows us to keep up the performance of 1834 * the pre-initialized command ring (esp. link pointers) by not actually 1835 * inserting the mcsetup command in the ring - i.e. its link pointer 1836 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1837 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1838 * lead into the regular TxCB ring when it completes. 1839 * 1840 * This function must be called at splimp. 1841 */ 1842 static void 1843 fxp_mc_setup(sc) 1844 struct fxp_softc *sc; 1845 { 1846 struct fxp_cb_mcs *mcsp = sc->mcsp; 1847 struct ifnet *ifp = &sc->sc_if; 1848 struct ifmultiaddr *ifma; 1849 int nmcasts; 1850 int count; 1851 1852 /* 1853 * If there are queued commands, we must wait until they are all 1854 * completed. If we are already waiting, then add a NOP command 1855 * with interrupt option so that we're notified when all commands 1856 * have been completed - fxp_start() ensures that no additional 1857 * TX commands will be added when need_mcsetup is true. 1858 */ 1859 if (sc->tx_queued) { 1860 struct fxp_cb_tx *txp; 1861 1862 /* 1863 * need_mcsetup will be true if we are already waiting for the 1864 * NOP command to be completed (see below). In this case, bail. 1865 */ 1866 if (sc->need_mcsetup) 1867 return; 1868 sc->need_mcsetup = 1; 1869 1870 /* 1871 * Add a NOP command with interrupt so that we are notified when all 1872 * TX commands have been processed. 1873 */ 1874 txp = sc->cbl_last->next; 1875 txp->mb_head = NULL; 1876 txp->cb_status = 0; 1877 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1878 /* 1879 * Advance the end of list forward. 1880 */ 1881 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1882 sc->cbl_last = txp; 1883 sc->tx_queued++; 1884 /* 1885 * Issue a resume in case the CU has just suspended. 1886 */ 1887 fxp_scb_wait(sc); 1888 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1889 /* 1890 * Set a 5 second timer just in case we don't hear from the 1891 * card again. 1892 */ 1893 ifp->if_timer = 5; 1894 1895 return; 1896 } 1897 sc->need_mcsetup = 0; 1898 1899 /* 1900 * Initialize multicast setup descriptor. 1901 */ 1902 mcsp->next = sc->cbl_base; 1903 mcsp->mb_head = NULL; 1904 mcsp->cb_status = 0; 1905 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1906 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1907 1908 nmcasts = 0; 1909 if (!sc->all_mcasts) { 1910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1911 if (ifma->ifma_addr->sa_family != AF_LINK) 1912 continue; 1913 if (nmcasts >= MAXMCADDR) { 1914 sc->all_mcasts = 1; 1915 nmcasts = 0; 1916 break; 1917 } 1918 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1919 (void *)(uintptr_t)(volatile void *) 1920 &sc->mcsp->mc_addr[nmcasts][0], 6); 1921 nmcasts++; 1922 } 1923 } 1924 mcsp->mc_cnt = nmcasts * 6; 1925 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1926 sc->tx_queued = 1; 1927 1928 /* 1929 * Wait until command unit is not active. This should never 1930 * be the case when nothing is queued, but make sure anyway. 1931 */ 1932 count = 100; 1933 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1934 FXP_SCB_CUS_ACTIVE && --count) 1935 DELAY(10); 1936 if (count == 0) { 1937 printf("fxp%d: command queue timeout\n", FXP_UNIT(sc)); 1938 return; 1939 } 1940 1941 /* 1942 * Start the multicast setup command. 1943 */ 1944 fxp_scb_wait(sc); 1945 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1946 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1947 1948 ifp->if_timer = 2; 1949 return; 1950 } 1951