1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 #include <sys/sockio.h> 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 57 #include <net/ethernet.h> 58 #include <net/if_arp.h> 59 60 #include <machine/clock.h> /* for DELAY */ 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #ifdef FXP_IP_CSUM_WAR 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <machine/in_cksum.h> 70 #endif 71 72 #include <pci/pcivar.h> 73 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 u_int16_t devid; 143 char *name; 144 }; 145 146 /* 147 * Claim various Intel PCI device identifiers for this driver. The 148 * sub-vendor and sub-device field are extensively used to identify 149 * particular variants, but we don't currently differentiate between 150 * them. 151 */ 152 static struct fxp_ident fxp_ident_table[] = { 153 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 154 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 155 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 164 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 170 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 171 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 172 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 173 { 0, NULL }, 174 }; 175 176 #ifdef FXP_IP_CSUM_WAR 177 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 178 #else 179 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 180 #endif 181 182 static int fxp_probe(device_t dev); 183 static int fxp_attach(device_t dev); 184 static int fxp_detach(device_t dev); 185 static int fxp_shutdown(device_t dev); 186 static int fxp_suspend(device_t dev); 187 static int fxp_resume(device_t dev); 188 189 static void fxp_intr(void *xsc); 190 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 191 u_int8_t statack, int count); 192 static void fxp_init(void *xsc); 193 static void fxp_init_body(struct fxp_softc *sc); 194 static void fxp_tick(void *xsc); 195 static void fxp_powerstate_d0(device_t dev); 196 static void fxp_start(struct ifnet *ifp); 197 static void fxp_start_body(struct ifnet *ifp); 198 static void fxp_stop(struct fxp_softc *sc); 199 static void fxp_release(struct fxp_softc *sc); 200 static int fxp_ioctl(struct ifnet *ifp, u_long command, 201 caddr_t data); 202 static void fxp_watchdog(struct ifnet *ifp); 203 static int fxp_add_rfabuf(struct fxp_softc *sc, 204 struct fxp_rx *rxp); 205 static int fxp_mc_addrs(struct fxp_softc *sc); 206 static void fxp_mc_setup(struct fxp_softc *sc); 207 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 208 int autosize); 209 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 210 u_int16_t data); 211 static void fxp_autosize_eeprom(struct fxp_softc *sc); 212 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 213 int offset, int words); 214 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 215 int offset, int words); 216 static int fxp_ifmedia_upd(struct ifnet *ifp); 217 static void fxp_ifmedia_sts(struct ifnet *ifp, 218 struct ifmediareq *ifmr); 219 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 220 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 221 struct ifmediareq *ifmr); 222 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 223 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 224 int value); 225 static void fxp_load_ucode(struct fxp_softc *sc); 226 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 227 int low, int high); 228 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 229 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 230 static __inline void fxp_scb_wait(struct fxp_softc *sc); 231 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 232 static __inline void fxp_dma_wait(struct fxp_softc *sc, 233 volatile u_int16_t *status, bus_dma_tag_t dmat, 234 bus_dmamap_t map); 235 236 static device_method_t fxp_methods[] = { 237 /* Device interface */ 238 DEVMETHOD(device_probe, fxp_probe), 239 DEVMETHOD(device_attach, fxp_attach), 240 DEVMETHOD(device_detach, fxp_detach), 241 DEVMETHOD(device_shutdown, fxp_shutdown), 242 DEVMETHOD(device_suspend, fxp_suspend), 243 DEVMETHOD(device_resume, fxp_resume), 244 245 /* MII interface */ 246 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 247 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 248 249 { 0, 0 } 250 }; 251 252 static driver_t fxp_driver = { 253 "fxp", 254 fxp_methods, 255 sizeof(struct fxp_softc), 256 }; 257 258 static devclass_t fxp_devclass; 259 260 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 261 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 262 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 263 264 static int fxp_rnr; 265 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 266 267 /* 268 * Wait for the previous command to be accepted (but not necessarily 269 * completed). 270 */ 271 static __inline void 272 fxp_scb_wait(struct fxp_softc *sc) 273 { 274 int i = 10000; 275 276 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 277 DELAY(2); 278 if (i == 0) 279 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 280 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 281 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 282 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 283 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 284 } 285 286 static __inline void 287 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 288 { 289 290 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 291 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 292 fxp_scb_wait(sc); 293 } 294 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 295 } 296 297 static __inline void 298 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 299 bus_dma_tag_t dmat, bus_dmamap_t map) 300 { 301 int i = 10000; 302 303 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 304 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 305 DELAY(2); 306 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 307 } 308 if (i == 0) 309 device_printf(sc->dev, "DMA timeout\n"); 310 } 311 312 /* 313 * Return identification string if this is device is ours. 314 */ 315 static int 316 fxp_probe(device_t dev) 317 { 318 u_int16_t devid; 319 struct fxp_ident *ident; 320 321 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 322 devid = pci_get_device(dev); 323 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 324 if (ident->devid == devid) { 325 device_set_desc(dev, ident->name); 326 return (0); 327 } 328 } 329 } 330 return (ENXIO); 331 } 332 333 static void 334 fxp_powerstate_d0(device_t dev) 335 { 336 #if __FreeBSD_version >= 430002 337 u_int32_t iobase, membase, irq; 338 339 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 340 /* Save important PCI config data. */ 341 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 342 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 343 irq = pci_read_config(dev, PCIR_INTLINE, 4); 344 345 /* Reset the power state. */ 346 device_printf(dev, "chip is in D%d power mode " 347 "-- setting to D0\n", pci_get_powerstate(dev)); 348 349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 350 351 /* Restore PCI config data. */ 352 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 353 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 354 pci_write_config(dev, PCIR_INTLINE, irq, 4); 355 } 356 #endif 357 } 358 359 static void 360 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 361 { 362 u_int32_t *addr; 363 364 if (error) 365 return; 366 367 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 368 addr = arg; 369 *addr = segs->ds_addr; 370 } 371 372 static int 373 fxp_attach(device_t dev) 374 { 375 int error = 0; 376 struct fxp_softc *sc = device_get_softc(dev); 377 struct ifnet *ifp; 378 struct fxp_rx *rxp; 379 u_int32_t val; 380 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 381 int i, rid, m1, m2, prefer_iomap, maxtxseg; 382 int s; 383 384 sc->dev = dev; 385 callout_handle_init(&sc->stat_ch); 386 sysctl_ctx_init(&sc->sysctl_ctx); 387 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 388 MTX_DEF); 389 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 390 fxp_serial_ifmedia_sts); 391 392 s = splimp(); 393 394 /* 395 * Enable bus mastering. 396 */ 397 pci_enable_busmaster(dev); 398 val = pci_read_config(dev, PCIR_COMMAND, 2); 399 400 fxp_powerstate_d0(dev); 401 402 /* 403 * Figure out which we should try first - memory mapping or i/o mapping? 404 * We default to memory mapping. Then we accept an override from the 405 * command line. Then we check to see which one is enabled. 406 */ 407 m1 = PCIM_CMD_MEMEN; 408 m2 = PCIM_CMD_PORTEN; 409 prefer_iomap = 0; 410 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 411 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 412 m1 = PCIM_CMD_PORTEN; 413 m2 = PCIM_CMD_MEMEN; 414 } 415 416 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 417 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 418 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 419 0, ~0, 1, RF_ACTIVE); 420 if (sc->mem == NULL) { 421 sc->rtp = 422 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 423 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 424 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 425 0, ~0, 1, RF_ACTIVE); 426 } 427 428 if (!sc->mem) { 429 error = ENXIO; 430 goto fail; 431 } 432 if (bootverbose) { 433 device_printf(dev, "using %s space register mapping\n", 434 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 435 } 436 437 sc->sc_st = rman_get_bustag(sc->mem); 438 sc->sc_sh = rman_get_bushandle(sc->mem); 439 440 /* 441 * Allocate our interrupt. 442 */ 443 rid = 0; 444 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 445 RF_SHAREABLE | RF_ACTIVE); 446 if (sc->irq == NULL) { 447 device_printf(dev, "could not map interrupt\n"); 448 error = ENXIO; 449 goto fail; 450 } 451 452 /* 453 * Reset to a stable state. 454 */ 455 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 456 DELAY(10); 457 458 /* 459 * Find out how large of an SEEPROM we have. 460 */ 461 fxp_autosize_eeprom(sc); 462 463 /* 464 * Determine whether we must use the 503 serial interface. 465 */ 466 fxp_read_eeprom(sc, &data, 6, 1); 467 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 468 (data & FXP_PHY_SERIAL_ONLY)) 469 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 470 471 /* 472 * Create the sysctl tree 473 */ 474 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 475 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 476 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 477 if (sc->sysctl_tree == NULL) { 478 error = ENXIO; 479 goto fail; 480 } 481 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 482 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 483 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 484 "FXP driver receive interrupt microcode bundling delay"); 485 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 486 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 487 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 488 "FXP driver receive interrupt microcode bundle size limit"); 489 490 /* 491 * Pull in device tunables. 492 */ 493 sc->tunable_int_delay = TUNABLE_INT_DELAY; 494 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 495 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 496 "int_delay", &sc->tunable_int_delay); 497 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 498 "bundle_max", &sc->tunable_bundle_max); 499 500 /* 501 * Find out the chip revision; lump all 82557 revs together. 502 */ 503 fxp_read_eeprom(sc, &data, 5, 1); 504 if ((data >> 8) == 1) 505 sc->revision = FXP_REV_82557; 506 else 507 sc->revision = pci_get_revid(dev); 508 509 /* 510 * Enable workarounds for certain chip revision deficiencies. 511 * 512 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 513 * some systems based a normal 82559 design, have a defect where 514 * the chip can cause a PCI protocol violation if it receives 515 * a CU_RESUME command when it is entering the IDLE state. The 516 * workaround is to disable Dynamic Standby Mode, so the chip never 517 * deasserts CLKRUN#, and always remains in an active state. 518 * 519 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 520 */ 521 i = pci_get_device(dev); 522 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 523 sc->revision >= FXP_REV_82559_A0) { 524 fxp_read_eeprom(sc, &data, 10, 1); 525 if (data & 0x02) { /* STB enable */ 526 u_int16_t cksum; 527 int i; 528 529 device_printf(dev, 530 "Disabling dynamic standby mode in EEPROM\n"); 531 data &= ~0x02; 532 fxp_write_eeprom(sc, &data, 10, 1); 533 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 534 cksum = 0; 535 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 536 fxp_read_eeprom(sc, &data, i, 1); 537 cksum += data; 538 } 539 i = (1 << sc->eeprom_size) - 1; 540 cksum = 0xBABA - cksum; 541 fxp_read_eeprom(sc, &data, i, 1); 542 fxp_write_eeprom(sc, &cksum, i, 1); 543 device_printf(dev, 544 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 545 i, data, cksum); 546 #if 1 547 /* 548 * If the user elects to continue, try the software 549 * workaround, as it is better than nothing. 550 */ 551 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 552 #endif 553 } 554 } 555 556 /* 557 * If we are not a 82557 chip, we can enable extended features. 558 */ 559 if (sc->revision != FXP_REV_82557) { 560 /* 561 * If MWI is enabled in the PCI configuration, and there 562 * is a valid cacheline size (8 or 16 dwords), then tell 563 * the board to turn on MWI. 564 */ 565 if (val & PCIM_CMD_MWRICEN && 566 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 567 sc->flags |= FXP_FLAG_MWI_ENABLE; 568 569 /* turn on the extended TxCB feature */ 570 sc->flags |= FXP_FLAG_EXT_TXCB; 571 572 /* enable reception of long frames for VLAN */ 573 sc->flags |= FXP_FLAG_LONG_PKT_EN; 574 } 575 576 /* 577 * Enable use of extended RFDs and TCBs for 82550 578 * and later chips. Note: we need extended TXCB support 579 * too, but that's already enabled by the code above. 580 * Be careful to do this only on the right devices. 581 */ 582 583 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C) { 584 sc->rfa_size = sizeof (struct fxp_rfa); 585 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 586 sc->flags |= FXP_FLAG_EXT_RFA; 587 } else { 588 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 589 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 590 } 591 592 /* 593 * Allocate DMA tags and DMA safe memory. 594 */ 595 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 596 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 597 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 598 maxtxseg, MCLBYTES, 0, &sc->fxp_mtag); 599 if (error) { 600 device_printf(dev, "could not allocate dma tag\n"); 601 goto fail; 602 } 603 604 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 605 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 606 sizeof(struct fxp_stats), 0, &sc->fxp_stag); 607 if (error) { 608 device_printf(dev, "could not allocate dma tag\n"); 609 goto fail; 610 } 611 612 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 613 BUS_DMA_NOWAIT, &sc->fxp_smap); 614 if (error) 615 goto fail; 616 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 617 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 618 if (error) { 619 device_printf(dev, "could not map the stats buffer\n"); 620 goto fail; 621 } 622 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 623 624 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 625 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 626 FXP_TXCB_SZ, 0, &sc->cbl_tag); 627 if (error) { 628 device_printf(dev, "could not allocate dma tag\n"); 629 goto fail; 630 } 631 632 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 633 BUS_DMA_NOWAIT, &sc->cbl_map); 634 if (error) 635 goto fail; 636 bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ); 637 638 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 639 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 640 &sc->fxp_desc.cbl_addr, 0); 641 if (error) { 642 device_printf(dev, "could not map DMA memory\n"); 643 goto fail; 644 } 645 646 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 647 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 648 sizeof(struct fxp_cb_mcs), 0, &sc->mcs_tag); 649 if (error) { 650 device_printf(dev, "could not allocate dma tag\n"); 651 goto fail; 652 } 653 654 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 655 BUS_DMA_NOWAIT, &sc->mcs_map); 656 if (error) 657 goto fail; 658 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 659 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 660 if (error) { 661 device_printf(dev, "can't map the multicast setup command\n"); 662 goto fail; 663 } 664 665 /* 666 * Pre-allocate the TX DMA maps. 667 */ 668 for (i = 0; i < FXP_NTXCB; i++) { 669 error = bus_dmamap_create(sc->fxp_mtag, 0, 670 &sc->fxp_desc.tx_list[i].tx_map); 671 if (error) { 672 device_printf(dev, "can't create DMA map for TX\n"); 673 goto fail; 674 } 675 } 676 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 677 if (error) { 678 device_printf(dev, "can't create spare DMA map\n"); 679 goto fail; 680 } 681 682 /* 683 * Pre-allocate our receive buffers. 684 */ 685 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 686 for (i = 0; i < FXP_NRFABUFS; i++) { 687 rxp = &sc->fxp_desc.rx_list[i]; 688 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 689 if (error) { 690 device_printf(dev, "can't create DMA map for RX\n"); 691 goto fail; 692 } 693 if (fxp_add_rfabuf(sc, rxp) != 0) { 694 error = ENOMEM; 695 goto fail; 696 } 697 } 698 699 /* 700 * Read MAC address. 701 */ 702 fxp_read_eeprom(sc, myea, 0, 3); 703 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 704 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 705 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 706 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 707 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 708 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 709 device_printf(dev, "Ethernet address %6D%s\n", 710 sc->arpcom.ac_enaddr, ":", 711 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 712 if (bootverbose) { 713 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 714 pci_get_vendor(dev), pci_get_device(dev), 715 pci_get_subvendor(dev), pci_get_subdevice(dev), 716 pci_get_revid(dev)); 717 fxp_read_eeprom(sc, &data, 10, 1); 718 device_printf(dev, "Dynamic Standby mode is %s\n", 719 data & 0x02 ? "enabled" : "disabled"); 720 } 721 722 /* 723 * If this is only a 10Mbps device, then there is no MII, and 724 * the PHY will use a serial interface instead. 725 * 726 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 727 * doesn't have a programming interface of any sort. The 728 * media is sensed automatically based on how the link partner 729 * is configured. This is, in essence, manual configuration. 730 */ 731 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 732 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 733 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 734 } else { 735 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 736 fxp_ifmedia_sts)) { 737 device_printf(dev, "MII without any PHY!\n"); 738 error = ENXIO; 739 goto fail; 740 } 741 } 742 743 ifp = &sc->arpcom.ac_if; 744 ifp->if_unit = device_get_unit(dev); 745 ifp->if_name = "fxp"; 746 ifp->if_output = ether_output; 747 ifp->if_baudrate = 100000000; 748 ifp->if_init = fxp_init; 749 ifp->if_softc = sc; 750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 751 ifp->if_ioctl = fxp_ioctl; 752 ifp->if_start = fxp_start; 753 ifp->if_watchdog = fxp_watchdog; 754 755 /* Enable checksum offload for 82550 or better chips */ 756 if (sc->flags & FXP_FLAG_EXT_RFA) { 757 ifp->if_hwassist = FXP_CSUM_FEATURES; 758 ifp->if_capabilities = IFCAP_HWCSUM; 759 ifp->if_capenable = ifp->if_capabilities; 760 } 761 762 /* 763 * Attach the interface. 764 */ 765 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 766 767 /* 768 * Tell the upper layer(s) we support long frames. 769 */ 770 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 771 ifp->if_capabilities |= IFCAP_VLAN_MTU; 772 773 /* 774 * Let the system queue as many packets as we have available 775 * TX descriptors. 776 */ 777 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 778 779 /* 780 * Hook our interrupt after all initialization is complete. 781 * XXX This driver has been tested with the INTR_MPSAFFE flag set 782 * however, ifp and its functions are not fully locked so MPSAFE 783 * should not be used unless you can handle potential data loss. 784 */ 785 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/, 786 fxp_intr, sc, &sc->ih); 787 if (error) { 788 device_printf(dev, "could not setup irq\n"); 789 ether_ifdetach(&sc->arpcom.ac_if); 790 goto fail; 791 } 792 793 fail: 794 splx(s); 795 if (error) 796 fxp_release(sc); 797 return (error); 798 } 799 800 /* 801 * Release all resources. The softc lock should not be held and the 802 * interrupt should already be torn down. 803 */ 804 static void 805 fxp_release(struct fxp_softc *sc) 806 { 807 struct fxp_rx *rxp; 808 struct fxp_tx *txp; 809 int i; 810 811 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 812 if (sc->ih) 813 panic("fxp_release() called with intr handle still active"); 814 if (sc->miibus) 815 device_delete_child(sc->dev, sc->miibus); 816 bus_generic_detach(sc->dev); 817 ifmedia_removeall(&sc->sc_media); 818 if (sc->fxp_desc.cbl_list) { 819 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 820 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 821 sc->cbl_map); 822 } 823 if (sc->fxp_stats) { 824 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 825 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 826 } 827 if (sc->mcsp) { 828 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 829 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 830 } 831 if (sc->irq) 832 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 833 if (sc->mem) 834 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 835 if (sc->fxp_mtag) { 836 for (i = 0; i < FXP_NRFABUFS; i++) { 837 rxp = &sc->fxp_desc.rx_list[i]; 838 if (rxp->rx_mbuf != NULL) { 839 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 840 BUS_DMASYNC_POSTREAD); 841 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 842 m_freem(rxp->rx_mbuf); 843 } 844 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 845 } 846 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 847 bus_dma_tag_destroy(sc->fxp_mtag); 848 } 849 if (sc->fxp_stag) { 850 for (i = 0; i < FXP_NTXCB; i++) { 851 txp = &sc->fxp_desc.tx_list[i]; 852 if (txp->tx_mbuf != NULL) { 853 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 854 BUS_DMASYNC_POSTWRITE); 855 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 856 m_freem(txp->tx_mbuf); 857 } 858 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 859 } 860 bus_dma_tag_destroy(sc->fxp_stag); 861 } 862 if (sc->cbl_tag) 863 bus_dma_tag_destroy(sc->cbl_tag); 864 if (sc->mcs_tag) 865 bus_dma_tag_destroy(sc->mcs_tag); 866 867 sysctl_ctx_free(&sc->sysctl_ctx); 868 869 mtx_destroy(&sc->sc_mtx); 870 } 871 872 /* 873 * Detach interface. 874 */ 875 static int 876 fxp_detach(device_t dev) 877 { 878 struct fxp_softc *sc = device_get_softc(dev); 879 int s; 880 881 FXP_LOCK(sc); 882 s = splimp(); 883 /* 884 * Close down routes etc. 885 */ 886 ether_ifdetach(&sc->arpcom.ac_if); 887 888 /* 889 * Stop DMA and drop transmit queue. 890 */ 891 if (bus_child_present(dev)) { 892 /* disable interrupts */ 893 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 894 fxp_stop(sc); 895 } 896 897 /* 898 * Unhook interrupt before dropping lock. This is to prevent 899 * races with fxp_intr(). 900 */ 901 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 902 sc->ih = NULL; 903 904 FXP_UNLOCK(sc); 905 splx(s); 906 907 /* Release our allocated resources. */ 908 fxp_release(sc); 909 return (0); 910 } 911 912 /* 913 * Device shutdown routine. Called at system shutdown after sync. The 914 * main purpose of this routine is to shut off receiver DMA so that 915 * kernel memory doesn't get clobbered during warmboot. 916 */ 917 static int 918 fxp_shutdown(device_t dev) 919 { 920 /* 921 * Make sure that DMA is disabled prior to reboot. Not doing 922 * do could allow DMA to corrupt kernel memory during the 923 * reboot before the driver initializes. 924 */ 925 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 926 return (0); 927 } 928 929 /* 930 * Device suspend routine. Stop the interface and save some PCI 931 * settings in case the BIOS doesn't restore them properly on 932 * resume. 933 */ 934 static int 935 fxp_suspend(device_t dev) 936 { 937 struct fxp_softc *sc = device_get_softc(dev); 938 int i, s; 939 940 FXP_LOCK(sc); 941 s = splimp(); 942 943 fxp_stop(sc); 944 945 for (i = 0; i < 5; i++) 946 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 947 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 948 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 949 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 950 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 951 952 sc->suspended = 1; 953 954 FXP_UNLOCK(sc); 955 splx(s); 956 return (0); 957 } 958 959 /* 960 * Device resume routine. Restore some PCI settings in case the BIOS 961 * doesn't, re-enable busmastering, and restart the interface if 962 * appropriate. 963 */ 964 static int 965 fxp_resume(device_t dev) 966 { 967 struct fxp_softc *sc = device_get_softc(dev); 968 struct ifnet *ifp = &sc->sc_if; 969 u_int16_t pci_command; 970 int i, s; 971 972 FXP_LOCK(sc); 973 s = splimp(); 974 975 fxp_powerstate_d0(dev); 976 977 /* better way to do this? */ 978 for (i = 0; i < 5; i++) 979 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 980 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 981 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 982 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 983 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 984 985 /* reenable busmastering */ 986 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 987 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 988 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 989 990 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 991 DELAY(10); 992 993 /* reinitialize interface if necessary */ 994 if (ifp->if_flags & IFF_UP) 995 fxp_init_body(sc); 996 997 sc->suspended = 0; 998 999 FXP_UNLOCK(sc); 1000 splx(s); 1001 return (0); 1002 } 1003 1004 static void 1005 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1006 { 1007 u_int16_t reg; 1008 int x; 1009 1010 /* 1011 * Shift in data. 1012 */ 1013 for (x = 1 << (length - 1); x; x >>= 1) { 1014 if (data & x) 1015 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1016 else 1017 reg = FXP_EEPROM_EECS; 1018 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1019 DELAY(1); 1020 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1021 DELAY(1); 1022 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1023 DELAY(1); 1024 } 1025 } 1026 1027 /* 1028 * Read from the serial EEPROM. Basically, you manually shift in 1029 * the read opcode (one bit at a time) and then shift in the address, 1030 * and then you shift out the data (all of this one bit at a time). 1031 * The word size is 16 bits, so you have to provide the address for 1032 * every 16 bits of data. 1033 */ 1034 static u_int16_t 1035 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1036 { 1037 u_int16_t reg, data; 1038 int x; 1039 1040 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1041 /* 1042 * Shift in read opcode. 1043 */ 1044 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1045 /* 1046 * Shift in address. 1047 */ 1048 data = 0; 1049 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1050 if (offset & x) 1051 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1052 else 1053 reg = FXP_EEPROM_EECS; 1054 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1055 DELAY(1); 1056 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1057 DELAY(1); 1058 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1059 DELAY(1); 1060 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1061 data++; 1062 if (autosize && reg == 0) { 1063 sc->eeprom_size = data; 1064 break; 1065 } 1066 } 1067 /* 1068 * Shift out data. 1069 */ 1070 data = 0; 1071 reg = FXP_EEPROM_EECS; 1072 for (x = 1 << 15; x; x >>= 1) { 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1074 DELAY(1); 1075 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1076 data |= x; 1077 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1078 DELAY(1); 1079 } 1080 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1081 DELAY(1); 1082 1083 return (data); 1084 } 1085 1086 static void 1087 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1088 { 1089 int i; 1090 1091 /* 1092 * Erase/write enable. 1093 */ 1094 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1095 fxp_eeprom_shiftin(sc, 0x4, 3); 1096 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1098 DELAY(1); 1099 /* 1100 * Shift in write opcode, address, data. 1101 */ 1102 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1103 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1104 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1105 fxp_eeprom_shiftin(sc, data, 16); 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1107 DELAY(1); 1108 /* 1109 * Wait for EEPROM to finish up. 1110 */ 1111 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1112 DELAY(1); 1113 for (i = 0; i < 1000; i++) { 1114 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1115 break; 1116 DELAY(50); 1117 } 1118 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1119 DELAY(1); 1120 /* 1121 * Erase/write disable. 1122 */ 1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1124 fxp_eeprom_shiftin(sc, 0x4, 3); 1125 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1127 DELAY(1); 1128 } 1129 1130 /* 1131 * From NetBSD: 1132 * 1133 * Figure out EEPROM size. 1134 * 1135 * 559's can have either 64-word or 256-word EEPROMs, the 558 1136 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1137 * talks about the existance of 16 to 256 word EEPROMs. 1138 * 1139 * The only known sizes are 64 and 256, where the 256 version is used 1140 * by CardBus cards to store CIS information. 1141 * 1142 * The address is shifted in msb-to-lsb, and after the last 1143 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1144 * after which follows the actual data. We try to detect this zero, by 1145 * probing the data-out bit in the EEPROM control register just after 1146 * having shifted in a bit. If the bit is zero, we assume we've 1147 * shifted enough address bits. The data-out should be tri-state, 1148 * before this, which should translate to a logical one. 1149 */ 1150 static void 1151 fxp_autosize_eeprom(struct fxp_softc *sc) 1152 { 1153 1154 /* guess maximum size of 256 words */ 1155 sc->eeprom_size = 8; 1156 1157 /* autosize */ 1158 (void) fxp_eeprom_getword(sc, 0, 1); 1159 } 1160 1161 static void 1162 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1163 { 1164 int i; 1165 1166 for (i = 0; i < words; i++) 1167 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1168 } 1169 1170 static void 1171 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1172 { 1173 int i; 1174 1175 for (i = 0; i < words; i++) 1176 fxp_eeprom_putword(sc, offset + i, data[i]); 1177 } 1178 1179 static void 1180 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1181 bus_size_t mapsize, int error) 1182 { 1183 struct fxp_softc *sc; 1184 struct fxp_cb_tx *txp; 1185 int i; 1186 1187 if (error) 1188 return; 1189 1190 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1191 1192 sc = arg; 1193 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1194 for (i = 0; i < nseg; i++) { 1195 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1196 /* 1197 * If this is an 82550/82551, then we're using extended 1198 * TxCBs _and_ we're using checksum offload. This means 1199 * that the TxCB is really an IPCB. One major difference 1200 * between the two is that with plain extended TxCBs, 1201 * the bottom half of the TxCB contains two entries from 1202 * the TBD array, whereas IPCBs contain just one entry: 1203 * one entry (8 bytes) has been sacrificed for the TCP/IP 1204 * checksum offload control bits. So to make things work 1205 * right, we have to start filling in the TBD array 1206 * starting from a different place depending on whether 1207 * the chip is an 82550/82551 or not. 1208 */ 1209 if (sc->flags & FXP_FLAG_EXT_RFA) { 1210 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1211 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1212 } else { 1213 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1214 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1215 } 1216 } 1217 txp->tbd_number = nseg; 1218 } 1219 1220 /* 1221 * Grab the softc lock and call the real fxp_start_body() routine 1222 */ 1223 static void 1224 fxp_start(struct ifnet *ifp) 1225 { 1226 struct fxp_softc *sc = ifp->if_softc; 1227 1228 FXP_LOCK(sc); 1229 fxp_start_body(ifp); 1230 FXP_UNLOCK(sc); 1231 } 1232 1233 /* 1234 * Start packet transmission on the interface. 1235 * This routine must be called with the softc lock held, and is an 1236 * internal entry point only. 1237 */ 1238 static void 1239 fxp_start_body(struct ifnet *ifp) 1240 { 1241 struct fxp_softc *sc = ifp->if_softc; 1242 struct fxp_tx *txp; 1243 struct mbuf *mb_head; 1244 int error; 1245 1246 mtx_assert(&sc->sc_mtx, MA_OWNED); 1247 /* 1248 * See if we need to suspend xmit until the multicast filter 1249 * has been reprogrammed (which can only be done at the head 1250 * of the command chain). 1251 */ 1252 if (sc->need_mcsetup) { 1253 return; 1254 } 1255 1256 txp = NULL; 1257 1258 /* 1259 * We're finished if there is nothing more to add to the list or if 1260 * we're all filled up with buffers to transmit. 1261 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1262 * a NOP command when needed. 1263 */ 1264 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1265 1266 /* 1267 * Grab a packet to transmit. 1268 */ 1269 IF_DEQUEUE(&ifp->if_snd, mb_head); 1270 1271 /* 1272 * Get pointer to next available tx desc. 1273 */ 1274 txp = sc->fxp_desc.tx_last->tx_next; 1275 1276 /* 1277 * Deal with TCP/IP checksum offload. Note that 1278 * in order for TCP checksum offload to work, 1279 * the pseudo header checksum must have already 1280 * been computed and stored in the checksum field 1281 * in the TCP header. The stack should have 1282 * already done this for us. 1283 */ 1284 1285 if (mb_head->m_pkthdr.csum_flags) { 1286 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1287 txp->tx_cb->ipcb_ip_activation_high = 1288 FXP_IPCB_HARDWAREPARSING_ENABLE; 1289 txp->tx_cb->ipcb_ip_schedule = 1290 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1291 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1292 txp->tx_cb->ipcb_ip_schedule |= 1293 FXP_IPCB_TCP_PACKET; 1294 } 1295 #ifdef FXP_IP_CSUM_WAR 1296 /* 1297 * XXX The 82550 chip appears to have trouble 1298 * dealing with IP header checksums in very small 1299 * datagrams, namely fragments from 1 to 3 bytes 1300 * in size. For example, say you want to transmit 1301 * a UDP packet of 1473 bytes. The packet will be 1302 * fragmented over two IP datagrams, the latter 1303 * containing only one byte of data. The 82550 will 1304 * botch the header checksum on the 1-byte fragment. 1305 * As long as the datagram contains 4 or more bytes 1306 * of data, you're ok. 1307 * 1308 * The following code attempts to work around this 1309 * problem: if the datagram is less than 38 bytes 1310 * in size (14 bytes ether header, 20 bytes IP header, 1311 * plus 4 bytes of data), we punt and compute the IP 1312 * header checksum by hand. This workaround doesn't 1313 * work very well, however, since it can be fooled 1314 * by things like VLAN tags and IP options that make 1315 * the header sizes/offsets vary. 1316 */ 1317 1318 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1319 if (mb_head->m_pkthdr.len < 38) { 1320 struct ip *ip; 1321 mb_head->m_data += ETHER_HDR_LEN; 1322 ip = mtod(mb_head, struct ip *); 1323 ip->ip_sum = in_cksum(mb_head, 1324 ip->ip_hl << 2); 1325 mb_head->m_data -= ETHER_HDR_LEN; 1326 } else { 1327 txp->tx_cb->ipcb_ip_activation_high = 1328 FXP_IPCB_HARDWAREPARSING_ENABLE; 1329 txp->tx_cb->ipcb_ip_schedule |= 1330 FXP_IPCB_IP_CHECKSUM_ENABLE; 1331 } 1332 } 1333 #endif 1334 } 1335 1336 /* 1337 * Go through each of the mbufs in the chain and initialize 1338 * the transmit buffer descriptors with the physical address 1339 * and size of the mbuf. 1340 */ 1341 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1342 mb_head, fxp_dma_map_txbuf, sc, 0); 1343 1344 if (error && error != EFBIG) { 1345 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1346 error); 1347 m_freem(mb_head); 1348 break; 1349 } 1350 1351 if (error) { 1352 struct mbuf *mn; 1353 1354 /* 1355 * We ran out of segments. We have to recopy this 1356 * mbuf chain first. Bail out if we can't get the 1357 * new buffers. 1358 */ 1359 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1360 if (mn == NULL) { 1361 m_freem(mb_head); 1362 break; 1363 } 1364 if (mb_head->m_pkthdr.len > MHLEN) { 1365 MCLGET(mn, M_DONTWAIT); 1366 if ((mn->m_flags & M_EXT) == 0) { 1367 m_freem(mn); 1368 m_freem(mb_head); 1369 break; 1370 } 1371 } 1372 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1373 mtod(mn, caddr_t)); 1374 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1375 m_freem(mb_head); 1376 mb_head = mn; 1377 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1378 mb_head, fxp_dma_map_txbuf, sc, 0); 1379 if (error) { 1380 device_printf(sc->dev, 1381 "can't map mbuf (error %d)\n", error); 1382 m_freem(mb_head); 1383 break; 1384 } 1385 } 1386 1387 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1388 BUS_DMASYNC_PREWRITE); 1389 1390 txp->tx_mbuf = mb_head; 1391 txp->tx_cb->cb_status = 0; 1392 txp->tx_cb->byte_count = 0; 1393 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1394 txp->tx_cb->cb_command = 1395 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1396 FXP_CB_COMMAND_S); 1397 } else { 1398 txp->tx_cb->cb_command = 1399 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1400 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1401 /* 1402 * Set a 5 second timer just in case we don't hear 1403 * from the card again. 1404 */ 1405 ifp->if_timer = 5; 1406 } 1407 txp->tx_cb->tx_threshold = tx_threshold; 1408 1409 /* 1410 * Advance the end of list forward. 1411 */ 1412 1413 #ifdef __alpha__ 1414 /* 1415 * On platforms which can't access memory in 16-bit 1416 * granularities, we must prevent the card from DMA'ing 1417 * up the status while we update the command field. 1418 * This could cause us to overwrite the completion status. 1419 * XXX This is probably bogus and we're _not_ looking 1420 * for atomicity here. 1421 */ 1422 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1423 htole16(FXP_CB_COMMAND_S)); 1424 #else 1425 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1426 htole16(~FXP_CB_COMMAND_S); 1427 #endif /*__alpha__*/ 1428 sc->fxp_desc.tx_last = txp; 1429 1430 /* 1431 * Advance the beginning of the list forward if there are 1432 * no other packets queued (when nothing is queued, tx_first 1433 * sits on the last TxCB that was sent out). 1434 */ 1435 if (sc->tx_queued == 0) 1436 sc->fxp_desc.tx_first = txp; 1437 1438 sc->tx_queued++; 1439 1440 /* 1441 * Pass packet to bpf if there is a listener. 1442 */ 1443 BPF_MTAP(ifp, mb_head); 1444 } 1445 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1446 1447 /* 1448 * We're finished. If we added to the list, issue a RESUME to get DMA 1449 * going again if suspended. 1450 */ 1451 if (txp != NULL) { 1452 fxp_scb_wait(sc); 1453 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1454 } 1455 } 1456 1457 #ifdef DEVICE_POLLING 1458 static poll_handler_t fxp_poll; 1459 1460 static void 1461 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1462 { 1463 struct fxp_softc *sc = ifp->if_softc; 1464 u_int8_t statack; 1465 1466 FXP_LOCK(sc); 1467 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1468 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1469 FXP_UNLOCK(sc); 1470 return; 1471 } 1472 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1473 FXP_SCB_STATACK_FR; 1474 if (cmd == POLL_AND_CHECK_STATUS) { 1475 u_int8_t tmp; 1476 1477 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1478 if (tmp == 0xff || tmp == 0) { 1479 FXP_UNLOCK(sc); 1480 return; /* nothing to do */ 1481 } 1482 tmp &= ~statack; 1483 /* ack what we can */ 1484 if (tmp != 0) 1485 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1486 statack |= tmp; 1487 } 1488 fxp_intr_body(sc, ifp, statack, count); 1489 FXP_UNLOCK(sc); 1490 } 1491 #endif /* DEVICE_POLLING */ 1492 1493 /* 1494 * Process interface interrupts. 1495 */ 1496 static void 1497 fxp_intr(void *xsc) 1498 { 1499 struct fxp_softc *sc = xsc; 1500 struct ifnet *ifp = &sc->sc_if; 1501 u_int8_t statack; 1502 1503 FXP_LOCK(sc); 1504 #ifdef DEVICE_POLLING 1505 if (ifp->if_flags & IFF_POLLING) { 1506 FXP_UNLOCK(sc); 1507 return; 1508 } 1509 if (ether_poll_register(fxp_poll, ifp)) { 1510 /* disable interrupts */ 1511 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1512 fxp_poll(ifp, 0, 1); 1513 FXP_UNLOCK(sc); 1514 return; 1515 } 1516 #endif 1517 1518 if (sc->suspended) { 1519 FXP_UNLOCK(sc); 1520 return; 1521 } 1522 1523 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1524 /* 1525 * It should not be possible to have all bits set; the 1526 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1527 * all bits are set, this may indicate that the card has 1528 * been physically ejected, so ignore it. 1529 */ 1530 if (statack == 0xff) { 1531 FXP_UNLOCK(sc); 1532 return; 1533 } 1534 1535 /* 1536 * First ACK all the interrupts in this pass. 1537 */ 1538 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1539 fxp_intr_body(sc, ifp, statack, -1); 1540 } 1541 FXP_UNLOCK(sc); 1542 } 1543 1544 static void 1545 fxp_txeof(struct fxp_softc *sc) 1546 { 1547 struct fxp_tx *txp; 1548 1549 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1550 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1551 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1552 txp = txp->tx_next) { 1553 if (txp->tx_mbuf != NULL) { 1554 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1555 BUS_DMASYNC_POSTWRITE); 1556 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1557 m_freem(txp->tx_mbuf); 1558 txp->tx_mbuf = NULL; 1559 /* clear this to reset csum offload bits */ 1560 txp->tx_cb->tbd[0].tb_addr = 0; 1561 } 1562 sc->tx_queued--; 1563 } 1564 sc->fxp_desc.tx_first = txp; 1565 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1566 } 1567 1568 static void 1569 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1570 int count) 1571 { 1572 struct mbuf *m; 1573 struct fxp_rx *rxp; 1574 struct fxp_rfa *rfa; 1575 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1576 1577 mtx_assert(&sc->sc_mtx, MA_OWNED); 1578 if (rnr) 1579 fxp_rnr++; 1580 #ifdef DEVICE_POLLING 1581 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1582 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1583 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1584 rnr = 1; 1585 } 1586 #endif 1587 1588 /* 1589 * Free any finished transmit mbuf chains. 1590 * 1591 * Handle the CNA event likt a CXTNO event. It used to 1592 * be that this event (control unit not ready) was not 1593 * encountered, but it is now with the SMPng modifications. 1594 * The exact sequence of events that occur when the interface 1595 * is brought up are different now, and if this event 1596 * goes unhandled, the configuration/rxfilter setup sequence 1597 * can stall for several seconds. The result is that no 1598 * packets go out onto the wire for about 5 to 10 seconds 1599 * after the interface is ifconfig'ed for the first time. 1600 */ 1601 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1602 fxp_txeof(sc); 1603 1604 ifp->if_timer = 0; 1605 if (sc->tx_queued == 0) { 1606 if (sc->need_mcsetup) 1607 fxp_mc_setup(sc); 1608 } 1609 /* 1610 * Try to start more packets transmitting. 1611 */ 1612 if (ifp->if_snd.ifq_head != NULL) 1613 fxp_start_body(ifp); 1614 } 1615 1616 /* 1617 * Just return if nothing happened on the receive side. 1618 */ 1619 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1620 return; 1621 1622 /* 1623 * Process receiver interrupts. If a no-resource (RNR) 1624 * condition exists, get whatever packets we can and 1625 * re-start the receiver. 1626 * 1627 * When using polling, we do not process the list to completion, 1628 * so when we get an RNR interrupt we must defer the restart 1629 * until we hit the last buffer with the C bit set. 1630 * If we run out of cycles and rfa_headm has the C bit set, 1631 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1632 * that the info will be used in the subsequent polling cycle. 1633 */ 1634 for (;;) { 1635 rxp = sc->fxp_desc.rx_head; 1636 m = rxp->rx_mbuf; 1637 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1638 RFA_ALIGNMENT_FUDGE); 1639 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1640 BUS_DMASYNC_POSTREAD); 1641 1642 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1643 if (count >= 0 && count-- == 0) { 1644 if (rnr) { 1645 /* Defer RNR processing until the next time. */ 1646 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1647 rnr = 0; 1648 } 1649 break; 1650 } 1651 #endif /* DEVICE_POLLING */ 1652 1653 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1654 break; 1655 1656 /* 1657 * Advance head forward. 1658 */ 1659 sc->fxp_desc.rx_head = rxp->rx_next; 1660 1661 /* 1662 * Add a new buffer to the receive chain. 1663 * If this fails, the old buffer is recycled 1664 * instead. 1665 */ 1666 if (fxp_add_rfabuf(sc, rxp) == 0) { 1667 int total_len; 1668 1669 /* 1670 * Fetch packet length (the top 2 bits of 1671 * actual_size are flags set by the controller 1672 * upon completion), and drop the packet in case 1673 * of bogus length or CRC errors. 1674 */ 1675 total_len = le16toh(rfa->actual_size) & 0x3fff; 1676 if (total_len < sizeof(struct ether_header) || 1677 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1678 sc->rfa_size || 1679 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1680 m_freem(m); 1681 continue; 1682 } 1683 1684 /* Do IP checksum checking. */ 1685 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1686 if (rfa->rfax_csum_sts & 1687 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1688 m->m_pkthdr.csum_flags |= 1689 CSUM_IP_CHECKED; 1690 if (rfa->rfax_csum_sts & 1691 FXP_RFDX_CS_IP_CSUM_VALID) 1692 m->m_pkthdr.csum_flags |= 1693 CSUM_IP_VALID; 1694 if ((rfa->rfax_csum_sts & 1695 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1696 (rfa->rfax_csum_sts & 1697 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1698 m->m_pkthdr.csum_flags |= 1699 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1700 m->m_pkthdr.csum_data = 0xffff; 1701 } 1702 } 1703 1704 m->m_pkthdr.len = m->m_len = total_len; 1705 m->m_pkthdr.rcvif = ifp; 1706 1707 (*ifp->if_input)(ifp, m); 1708 } 1709 } 1710 if (rnr) { 1711 fxp_scb_wait(sc); 1712 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1713 sc->fxp_desc.rx_head->rx_addr); 1714 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1715 } 1716 } 1717 1718 /* 1719 * Update packet in/out/collision statistics. The i82557 doesn't 1720 * allow you to access these counters without doing a fairly 1721 * expensive DMA to get _all_ of the statistics it maintains, so 1722 * we do this operation here only once per second. The statistics 1723 * counters in the kernel are updated from the previous dump-stats 1724 * DMA and then a new dump-stats DMA is started. The on-chip 1725 * counters are zeroed when the DMA completes. If we can't start 1726 * the DMA immediately, we don't wait - we just prepare to read 1727 * them again next time. 1728 */ 1729 static void 1730 fxp_tick(void *xsc) 1731 { 1732 struct fxp_softc *sc = xsc; 1733 struct ifnet *ifp = &sc->sc_if; 1734 struct fxp_stats *sp = sc->fxp_stats; 1735 int s; 1736 1737 FXP_LOCK(sc); 1738 s = splimp(); 1739 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1740 ifp->if_opackets += le32toh(sp->tx_good); 1741 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1742 if (sp->rx_good) { 1743 ifp->if_ipackets += le32toh(sp->rx_good); 1744 sc->rx_idle_secs = 0; 1745 } else { 1746 /* 1747 * Receiver's been idle for another second. 1748 */ 1749 sc->rx_idle_secs++; 1750 } 1751 ifp->if_ierrors += 1752 le32toh(sp->rx_crc_errors) + 1753 le32toh(sp->rx_alignment_errors) + 1754 le32toh(sp->rx_rnr_errors) + 1755 le32toh(sp->rx_overrun_errors); 1756 /* 1757 * If any transmit underruns occured, bump up the transmit 1758 * threshold by another 512 bytes (64 * 8). 1759 */ 1760 if (sp->tx_underruns) { 1761 ifp->if_oerrors += le32toh(sp->tx_underruns); 1762 if (tx_threshold < 192) 1763 tx_threshold += 64; 1764 } 1765 1766 /* 1767 * Release any xmit buffers that have completed DMA. This isn't 1768 * strictly necessary to do here, but it's advantagous for mbufs 1769 * with external storage to be released in a timely manner rather 1770 * than being defered for a potentially long time. This limits 1771 * the delay to a maximum of one second. 1772 */ 1773 fxp_txeof(sc); 1774 1775 /* 1776 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1777 * then assume the receiver has locked up and attempt to clear 1778 * the condition by reprogramming the multicast filter. This is 1779 * a work-around for a bug in the 82557 where the receiver locks 1780 * up if it gets certain types of garbage in the syncronization 1781 * bits prior to the packet header. This bug is supposed to only 1782 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1783 * mode as well (perhaps due to a 10/100 speed transition). 1784 */ 1785 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1786 sc->rx_idle_secs = 0; 1787 fxp_mc_setup(sc); 1788 } 1789 /* 1790 * If there is no pending command, start another stats 1791 * dump. Otherwise punt for now. 1792 */ 1793 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1794 /* 1795 * Start another stats dump. 1796 */ 1797 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1798 BUS_DMASYNC_PREREAD); 1799 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1800 } else { 1801 /* 1802 * A previous command is still waiting to be accepted. 1803 * Just zero our copy of the stats and wait for the 1804 * next timer event to update them. 1805 */ 1806 sp->tx_good = 0; 1807 sp->tx_underruns = 0; 1808 sp->tx_total_collisions = 0; 1809 1810 sp->rx_good = 0; 1811 sp->rx_crc_errors = 0; 1812 sp->rx_alignment_errors = 0; 1813 sp->rx_rnr_errors = 0; 1814 sp->rx_overrun_errors = 0; 1815 } 1816 if (sc->miibus != NULL) 1817 mii_tick(device_get_softc(sc->miibus)); 1818 1819 /* 1820 * Schedule another timeout one second from now. 1821 */ 1822 sc->stat_ch = timeout(fxp_tick, sc, hz); 1823 FXP_UNLOCK(sc); 1824 splx(s); 1825 } 1826 1827 /* 1828 * Stop the interface. Cancels the statistics updater and resets 1829 * the interface. 1830 */ 1831 static void 1832 fxp_stop(struct fxp_softc *sc) 1833 { 1834 struct ifnet *ifp = &sc->sc_if; 1835 struct fxp_tx *txp; 1836 int i; 1837 1838 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1839 ifp->if_timer = 0; 1840 1841 #ifdef DEVICE_POLLING 1842 ether_poll_deregister(ifp); 1843 #endif 1844 /* 1845 * Cancel stats updater. 1846 */ 1847 untimeout(fxp_tick, sc, sc->stat_ch); 1848 1849 /* 1850 * Issue software reset, which also unloads the microcode. 1851 */ 1852 sc->flags &= ~FXP_FLAG_UCODE; 1853 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1854 DELAY(50); 1855 1856 /* 1857 * Release any xmit buffers. 1858 */ 1859 txp = sc->fxp_desc.tx_list; 1860 if (txp != NULL) { 1861 for (i = 0; i < FXP_NTXCB; i++) { 1862 if (txp[i].tx_mbuf != NULL) { 1863 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1864 BUS_DMASYNC_POSTWRITE); 1865 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1866 m_freem(txp[i].tx_mbuf); 1867 txp[i].tx_mbuf = NULL; 1868 /* clear this to reset csum offload bits */ 1869 txp[i].tx_cb->tbd[0].tb_addr = 0; 1870 } 1871 } 1872 } 1873 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1874 sc->tx_queued = 0; 1875 } 1876 1877 /* 1878 * Watchdog/transmission transmit timeout handler. Called when a 1879 * transmission is started on the interface, but no interrupt is 1880 * received before the timeout. This usually indicates that the 1881 * card has wedged for some reason. 1882 */ 1883 static void 1884 fxp_watchdog(struct ifnet *ifp) 1885 { 1886 struct fxp_softc *sc = ifp->if_softc; 1887 1888 FXP_LOCK(sc); 1889 device_printf(sc->dev, "device timeout\n"); 1890 ifp->if_oerrors++; 1891 1892 fxp_init_body(sc); 1893 FXP_UNLOCK(sc); 1894 } 1895 1896 /* 1897 * Acquire locks and then call the real initialization function. This 1898 * is necessary because ether_ioctl() calls if_init() and this would 1899 * result in mutex recursion if the mutex was held. 1900 */ 1901 static void 1902 fxp_init(void *xsc) 1903 { 1904 struct fxp_softc *sc = xsc; 1905 1906 FXP_LOCK(sc); 1907 fxp_init_body(sc); 1908 FXP_UNLOCK(sc); 1909 } 1910 1911 /* 1912 * Perform device initialization. This routine must be called with the 1913 * softc lock held. 1914 */ 1915 static void 1916 fxp_init_body(struct fxp_softc *sc) 1917 { 1918 struct ifnet *ifp = &sc->sc_if; 1919 struct fxp_cb_config *cbp; 1920 struct fxp_cb_ias *cb_ias; 1921 struct fxp_cb_tx *tcbp; 1922 struct fxp_tx *txp; 1923 struct fxp_cb_mcs *mcsp; 1924 int i, prm, s; 1925 1926 mtx_assert(&sc->sc_mtx, MA_OWNED); 1927 s = splimp(); 1928 /* 1929 * Cancel any pending I/O 1930 */ 1931 fxp_stop(sc); 1932 1933 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1934 1935 /* 1936 * Initialize base of CBL and RFA memory. Loading with zero 1937 * sets it up for regular linear addressing. 1938 */ 1939 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1940 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1941 1942 fxp_scb_wait(sc); 1943 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1944 1945 /* 1946 * Initialize base of dump-stats buffer. 1947 */ 1948 fxp_scb_wait(sc); 1949 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1950 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1951 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1952 1953 /* 1954 * Attempt to load microcode if requested. 1955 */ 1956 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1957 fxp_load_ucode(sc); 1958 1959 /* 1960 * Initialize the multicast address list. 1961 */ 1962 if (fxp_mc_addrs(sc)) { 1963 mcsp = sc->mcsp; 1964 mcsp->cb_status = 0; 1965 mcsp->cb_command = 1966 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1967 mcsp->link_addr = 0xffffffff; 1968 /* 1969 * Start the multicast setup command. 1970 */ 1971 fxp_scb_wait(sc); 1972 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1973 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1974 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1975 /* ...and wait for it to complete. */ 1976 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1977 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1978 BUS_DMASYNC_POSTWRITE); 1979 } 1980 1981 /* 1982 * We temporarily use memory that contains the TxCB list to 1983 * construct the config CB. The TxCB list memory is rebuilt 1984 * later. 1985 */ 1986 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1987 1988 /* 1989 * This bcopy is kind of disgusting, but there are a bunch of must be 1990 * zero and must be one bits in this structure and this is the easiest 1991 * way to initialize them all to proper values. 1992 */ 1993 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1994 1995 cbp->cb_status = 0; 1996 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1997 FXP_CB_COMMAND_EL); 1998 cbp->link_addr = 0xffffffff; /* (no) next command */ 1999 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2000 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2001 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2002 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2003 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2004 cbp->type_enable = 0; /* actually reserved */ 2005 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2006 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2007 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2008 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2009 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2010 cbp->late_scb = 0; /* (don't) defer SCB update */ 2011 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2012 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2013 cbp->ci_int = 1; /* interrupt on CU idle */ 2014 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2015 cbp->ext_stats_dis = 1; /* disable extended counters */ 2016 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2017 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2018 cbp->disc_short_rx = !prm; /* discard short packets */ 2019 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2020 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2021 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2022 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2023 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2024 cbp->csma_dis = 0; /* (don't) disable link */ 2025 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2026 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2027 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2028 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2029 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2030 cbp->nsai = 1; /* (don't) disable source addr insert */ 2031 cbp->preamble_length = 2; /* (7 byte) preamble */ 2032 cbp->loopback = 0; /* (don't) loopback */ 2033 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2034 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2035 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2036 cbp->promiscuous = prm; /* promiscuous mode */ 2037 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2038 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2039 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2040 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2041 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2042 2043 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2044 cbp->padding = 1; /* (do) pad short tx packets */ 2045 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2046 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2047 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2048 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2049 /* must set wake_en in PMCSR also */ 2050 cbp->force_fdx = 0; /* (don't) force full duplex */ 2051 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2052 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2053 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2054 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2055 2056 if (sc->revision == FXP_REV_82557) { 2057 /* 2058 * The 82557 has no hardware flow control, the values 2059 * below are the defaults for the chip. 2060 */ 2061 cbp->fc_delay_lsb = 0; 2062 cbp->fc_delay_msb = 0x40; 2063 cbp->pri_fc_thresh = 3; 2064 cbp->tx_fc_dis = 0; 2065 cbp->rx_fc_restop = 0; 2066 cbp->rx_fc_restart = 0; 2067 cbp->fc_filter = 0; 2068 cbp->pri_fc_loc = 1; 2069 } else { 2070 cbp->fc_delay_lsb = 0x1f; 2071 cbp->fc_delay_msb = 0x01; 2072 cbp->pri_fc_thresh = 3; 2073 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2074 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2075 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2076 cbp->fc_filter = !prm; /* drop FC frames to host */ 2077 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2078 } 2079 2080 /* 2081 * Start the config command/DMA. 2082 */ 2083 fxp_scb_wait(sc); 2084 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2085 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2086 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2087 /* ...and wait for it to complete. */ 2088 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2089 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2090 2091 /* 2092 * Now initialize the station address. Temporarily use the TxCB 2093 * memory area like we did above for the config CB. 2094 */ 2095 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2096 cb_ias->cb_status = 0; 2097 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2098 cb_ias->link_addr = 0xffffffff; 2099 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2100 sizeof(sc->arpcom.ac_enaddr)); 2101 2102 /* 2103 * Start the IAS (Individual Address Setup) command/DMA. 2104 */ 2105 fxp_scb_wait(sc); 2106 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2107 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2108 /* ...and wait for it to complete. */ 2109 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2110 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2111 2112 /* 2113 * Initialize transmit control block (TxCB) list. 2114 */ 2115 txp = sc->fxp_desc.tx_list; 2116 tcbp = sc->fxp_desc.cbl_list; 2117 bzero(tcbp, FXP_TXCB_SZ); 2118 for (i = 0; i < FXP_NTXCB; i++) { 2119 txp[i].tx_cb = tcbp + i; 2120 txp[i].tx_mbuf = NULL; 2121 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2122 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2123 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2124 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2125 if (sc->flags & FXP_FLAG_EXT_TXCB) 2126 tcbp[i].tbd_array_addr = 2127 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2128 else 2129 tcbp[i].tbd_array_addr = 2130 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2131 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2132 } 2133 /* 2134 * Set the suspend flag on the first TxCB and start the control 2135 * unit. It will execute the NOP and then suspend. 2136 */ 2137 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2138 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2139 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2140 sc->tx_queued = 1; 2141 2142 fxp_scb_wait(sc); 2143 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2144 2145 /* 2146 * Initialize receiver buffer area - RFA. 2147 */ 2148 fxp_scb_wait(sc); 2149 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2150 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2151 2152 /* 2153 * Set current media. 2154 */ 2155 if (sc->miibus != NULL) 2156 mii_mediachg(device_get_softc(sc->miibus)); 2157 2158 ifp->if_flags |= IFF_RUNNING; 2159 ifp->if_flags &= ~IFF_OACTIVE; 2160 2161 /* 2162 * Enable interrupts. 2163 */ 2164 #ifdef DEVICE_POLLING 2165 /* 2166 * ... but only do that if we are not polling. And because (presumably) 2167 * the default is interrupts on, we need to disable them explicitly! 2168 */ 2169 if ( ifp->if_flags & IFF_POLLING ) 2170 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2171 else 2172 #endif /* DEVICE_POLLING */ 2173 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2174 2175 /* 2176 * Start stats updater. 2177 */ 2178 sc->stat_ch = timeout(fxp_tick, sc, hz); 2179 splx(s); 2180 } 2181 2182 static int 2183 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2184 { 2185 2186 return (0); 2187 } 2188 2189 static void 2190 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2191 { 2192 2193 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2194 } 2195 2196 /* 2197 * Change media according to request. 2198 */ 2199 static int 2200 fxp_ifmedia_upd(struct ifnet *ifp) 2201 { 2202 struct fxp_softc *sc = ifp->if_softc; 2203 struct mii_data *mii; 2204 2205 mii = device_get_softc(sc->miibus); 2206 mii_mediachg(mii); 2207 return (0); 2208 } 2209 2210 /* 2211 * Notify the world which media we're using. 2212 */ 2213 static void 2214 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2215 { 2216 struct fxp_softc *sc = ifp->if_softc; 2217 struct mii_data *mii; 2218 2219 mii = device_get_softc(sc->miibus); 2220 mii_pollstat(mii); 2221 ifmr->ifm_active = mii->mii_media_active; 2222 ifmr->ifm_status = mii->mii_media_status; 2223 2224 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2225 sc->cu_resume_bug = 1; 2226 else 2227 sc->cu_resume_bug = 0; 2228 } 2229 2230 /* 2231 * Add a buffer to the end of the RFA buffer list. 2232 * Return 0 if successful, 1 for failure. A failure results in 2233 * adding the 'oldm' (if non-NULL) on to the end of the list - 2234 * tossing out its old contents and recycling it. 2235 * The RFA struct is stuck at the beginning of mbuf cluster and the 2236 * data pointer is fixed up to point just past it. 2237 */ 2238 static int 2239 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2240 { 2241 struct mbuf *m; 2242 struct fxp_rfa *rfa, *p_rfa; 2243 struct fxp_rx *p_rx; 2244 bus_dmamap_t tmp_map; 2245 int error; 2246 2247 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2248 if (m == NULL) 2249 return (ENOBUFS); 2250 2251 /* 2252 * Move the data pointer up so that the incoming data packet 2253 * will be 32-bit aligned. 2254 */ 2255 m->m_data += RFA_ALIGNMENT_FUDGE; 2256 2257 /* 2258 * Get a pointer to the base of the mbuf cluster and move 2259 * data start past it. 2260 */ 2261 rfa = mtod(m, struct fxp_rfa *); 2262 m->m_data += sc->rfa_size; 2263 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2264 2265 /* 2266 * Initialize the rest of the RFA. Note that since the RFA 2267 * is misaligned, we cannot store values directly. Instead, 2268 * we use an optimized, inline copy. 2269 */ 2270 2271 rfa->rfa_status = 0; 2272 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2273 rfa->actual_size = 0; 2274 2275 le32enc(&rfa->link_addr, 0xffffffff); 2276 le32enc(&rfa->rbd_addr, 0xffffffff); 2277 2278 /* Map the RFA into DMA memory. */ 2279 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2280 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2281 &rxp->rx_addr, 0); 2282 if (error) { 2283 m_freem(m); 2284 return (error); 2285 } 2286 2287 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2288 tmp_map = sc->spare_map; 2289 sc->spare_map = rxp->rx_map; 2290 rxp->rx_map = tmp_map; 2291 rxp->rx_mbuf = m; 2292 2293 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2294 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2295 2296 /* 2297 * If there are other buffers already on the list, attach this 2298 * one to the end by fixing up the tail to point to this one. 2299 */ 2300 if (sc->fxp_desc.rx_head != NULL) { 2301 p_rx = sc->fxp_desc.rx_tail; 2302 p_rfa = (struct fxp_rfa *) 2303 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2304 p_rx->rx_next = rxp; 2305 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2306 p_rfa->rfa_control = 0; 2307 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2308 BUS_DMASYNC_PREWRITE); 2309 } else { 2310 rxp->rx_next = NULL; 2311 sc->fxp_desc.rx_head = rxp; 2312 } 2313 sc->fxp_desc.rx_tail = rxp; 2314 return (0); 2315 } 2316 2317 static volatile int 2318 fxp_miibus_readreg(device_t dev, int phy, int reg) 2319 { 2320 struct fxp_softc *sc = device_get_softc(dev); 2321 int count = 10000; 2322 int value; 2323 2324 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2325 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2326 2327 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2328 && count--) 2329 DELAY(10); 2330 2331 if (count <= 0) 2332 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2333 2334 return (value & 0xffff); 2335 } 2336 2337 static void 2338 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2339 { 2340 struct fxp_softc *sc = device_get_softc(dev); 2341 int count = 10000; 2342 2343 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2344 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2345 (value & 0xffff)); 2346 2347 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2348 count--) 2349 DELAY(10); 2350 2351 if (count <= 0) 2352 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2353 } 2354 2355 static int 2356 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2357 { 2358 struct fxp_softc *sc = ifp->if_softc; 2359 struct ifreq *ifr = (struct ifreq *)data; 2360 struct mii_data *mii; 2361 int s, error = 0; 2362 2363 FXP_LOCK(sc); 2364 s = splimp(); 2365 2366 switch (command) { 2367 case SIOCSIFFLAGS: 2368 if (ifp->if_flags & IFF_ALLMULTI) 2369 sc->flags |= FXP_FLAG_ALL_MCAST; 2370 else 2371 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2372 2373 /* 2374 * If interface is marked up and not running, then start it. 2375 * If it is marked down and running, stop it. 2376 * XXX If it's up then re-initialize it. This is so flags 2377 * such as IFF_PROMISC are handled. 2378 */ 2379 if (ifp->if_flags & IFF_UP) { 2380 fxp_init_body(sc); 2381 } else { 2382 if (ifp->if_flags & IFF_RUNNING) 2383 fxp_stop(sc); 2384 } 2385 break; 2386 2387 case SIOCADDMULTI: 2388 case SIOCDELMULTI: 2389 if (ifp->if_flags & IFF_ALLMULTI) 2390 sc->flags |= FXP_FLAG_ALL_MCAST; 2391 else 2392 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2393 /* 2394 * Multicast list has changed; set the hardware filter 2395 * accordingly. 2396 */ 2397 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2398 fxp_mc_setup(sc); 2399 /* 2400 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2401 * again rather than else {}. 2402 */ 2403 if (sc->flags & FXP_FLAG_ALL_MCAST) 2404 fxp_init_body(sc); 2405 error = 0; 2406 break; 2407 2408 case SIOCSIFMEDIA: 2409 case SIOCGIFMEDIA: 2410 if (sc->miibus != NULL) { 2411 mii = device_get_softc(sc->miibus); 2412 error = ifmedia_ioctl(ifp, ifr, 2413 &mii->mii_media, command); 2414 } else { 2415 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2416 } 2417 break; 2418 2419 default: 2420 /* 2421 * ether_ioctl() will eventually call fxp_start() which 2422 * will result in mutex recursion so drop it first. 2423 */ 2424 FXP_UNLOCK(sc); 2425 error = ether_ioctl(ifp, command, data); 2426 } 2427 if (mtx_owned(&sc->sc_mtx)) 2428 FXP_UNLOCK(sc); 2429 splx(s); 2430 return (error); 2431 } 2432 2433 /* 2434 * Fill in the multicast address list and return number of entries. 2435 */ 2436 static int 2437 fxp_mc_addrs(struct fxp_softc *sc) 2438 { 2439 struct fxp_cb_mcs *mcsp = sc->mcsp; 2440 struct ifnet *ifp = &sc->sc_if; 2441 struct ifmultiaddr *ifma; 2442 int nmcasts; 2443 2444 nmcasts = 0; 2445 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2446 #if __FreeBSD_version < 500000 2447 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2448 #else 2449 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2450 #endif 2451 if (ifma->ifma_addr->sa_family != AF_LINK) 2452 continue; 2453 if (nmcasts >= MAXMCADDR) { 2454 sc->flags |= FXP_FLAG_ALL_MCAST; 2455 nmcasts = 0; 2456 break; 2457 } 2458 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2459 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2460 nmcasts++; 2461 } 2462 } 2463 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2464 return (nmcasts); 2465 } 2466 2467 /* 2468 * Program the multicast filter. 2469 * 2470 * We have an artificial restriction that the multicast setup command 2471 * must be the first command in the chain, so we take steps to ensure 2472 * this. By requiring this, it allows us to keep up the performance of 2473 * the pre-initialized command ring (esp. link pointers) by not actually 2474 * inserting the mcsetup command in the ring - i.e. its link pointer 2475 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2476 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2477 * lead into the regular TxCB ring when it completes. 2478 * 2479 * This function must be called at splimp. 2480 */ 2481 static void 2482 fxp_mc_setup(struct fxp_softc *sc) 2483 { 2484 struct fxp_cb_mcs *mcsp = sc->mcsp; 2485 struct ifnet *ifp = &sc->sc_if; 2486 struct fxp_tx *txp; 2487 int count; 2488 2489 /* 2490 * If there are queued commands, we must wait until they are all 2491 * completed. If we are already waiting, then add a NOP command 2492 * with interrupt option so that we're notified when all commands 2493 * have been completed - fxp_start() ensures that no additional 2494 * TX commands will be added when need_mcsetup is true. 2495 */ 2496 if (sc->tx_queued) { 2497 /* 2498 * need_mcsetup will be true if we are already waiting for the 2499 * NOP command to be completed (see below). In this case, bail. 2500 */ 2501 if (sc->need_mcsetup) 2502 return; 2503 sc->need_mcsetup = 1; 2504 2505 /* 2506 * Add a NOP command with interrupt so that we are notified 2507 * when all TX commands have been processed. 2508 */ 2509 txp = sc->fxp_desc.tx_last->tx_next; 2510 txp->tx_mbuf = NULL; 2511 txp->tx_cb->cb_status = 0; 2512 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2513 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2514 /* 2515 * Advance the end of list forward. 2516 */ 2517 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2518 htole16(~FXP_CB_COMMAND_S); 2519 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2520 sc->fxp_desc.tx_last = txp; 2521 sc->tx_queued++; 2522 /* 2523 * Issue a resume in case the CU has just suspended. 2524 */ 2525 fxp_scb_wait(sc); 2526 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2527 /* 2528 * Set a 5 second timer just in case we don't hear from the 2529 * card again. 2530 */ 2531 ifp->if_timer = 5; 2532 2533 return; 2534 } 2535 sc->need_mcsetup = 0; 2536 2537 /* 2538 * Initialize multicast setup descriptor. 2539 */ 2540 mcsp->cb_status = 0; 2541 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2542 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2543 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2544 txp = &sc->fxp_desc.mcs_tx; 2545 txp->tx_mbuf = NULL; 2546 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2547 txp->tx_next = sc->fxp_desc.tx_list; 2548 (void) fxp_mc_addrs(sc); 2549 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2550 sc->tx_queued = 1; 2551 2552 /* 2553 * Wait until command unit is not active. This should never 2554 * be the case when nothing is queued, but make sure anyway. 2555 */ 2556 count = 100; 2557 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2558 FXP_SCB_CUS_ACTIVE && --count) 2559 DELAY(10); 2560 if (count == 0) { 2561 device_printf(sc->dev, "command queue timeout\n"); 2562 return; 2563 } 2564 2565 /* 2566 * Start the multicast setup command. 2567 */ 2568 fxp_scb_wait(sc); 2569 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2570 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2571 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2572 2573 ifp->if_timer = 2; 2574 return; 2575 } 2576 2577 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2578 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2579 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2580 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2581 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2582 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2583 2584 #define UCODE(x) x, sizeof(x) 2585 2586 struct ucode { 2587 u_int32_t revision; 2588 u_int32_t *ucode; 2589 int length; 2590 u_short int_delay_offset; 2591 u_short bundle_max_offset; 2592 } ucode_table[] = { 2593 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2594 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2595 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2596 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2597 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2598 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2599 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2600 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2601 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2602 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2603 { 0, NULL, 0, 0, 0 } 2604 }; 2605 2606 static void 2607 fxp_load_ucode(struct fxp_softc *sc) 2608 { 2609 struct ucode *uc; 2610 struct fxp_cb_ucode *cbp; 2611 2612 for (uc = ucode_table; uc->ucode != NULL; uc++) 2613 if (sc->revision == uc->revision) 2614 break; 2615 if (uc->ucode == NULL) 2616 return; 2617 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2618 cbp->cb_status = 0; 2619 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2620 cbp->link_addr = 0xffffffff; /* (no) next command */ 2621 memcpy(cbp->ucode, uc->ucode, uc->length); 2622 if (uc->int_delay_offset) 2623 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2624 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2625 if (uc->bundle_max_offset) 2626 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2627 htole16(sc->tunable_bundle_max); 2628 /* 2629 * Download the ucode to the chip. 2630 */ 2631 fxp_scb_wait(sc); 2632 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2633 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2634 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2635 /* ...and wait for it to complete. */ 2636 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2637 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2638 device_printf(sc->dev, 2639 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2640 sc->tunable_int_delay, 2641 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2642 sc->flags |= FXP_FLAG_UCODE; 2643 } 2644 2645 static int 2646 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2647 { 2648 int error, value; 2649 2650 value = *(int *)arg1; 2651 error = sysctl_handle_int(oidp, &value, 0, req); 2652 if (error || !req->newptr) 2653 return (error); 2654 if (value < low || value > high) 2655 return (EINVAL); 2656 *(int *)arg1 = value; 2657 return (0); 2658 } 2659 2660 /* 2661 * Interrupt delay is expressed in microseconds, a multiplier is used 2662 * to convert this to the appropriate clock ticks before using. 2663 */ 2664 static int 2665 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2666 { 2667 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2668 } 2669 2670 static int 2671 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2672 { 2673 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2674 } 2675