1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 #include <sys/sockio.h> 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 57 #include <net/ethernet.h> 58 #include <net/if_arp.h> 59 60 #include <machine/clock.h> /* for DELAY */ 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #ifdef FXP_IP_CSUM_WAR 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <machine/in_cksum.h> 70 #endif 71 72 #include <pci/pcivar.h> 73 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 u_int16_t devid; 143 char *name; 144 }; 145 146 /* 147 * Claim various Intel PCI device identifiers for this driver. The 148 * sub-vendor and sub-device field are extensively used to identify 149 * particular variants, but we don't currently differentiate between 150 * them. 151 */ 152 static struct fxp_ident fxp_ident_table[] = { 153 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 154 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 155 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 156 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 158 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 160 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 163 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 164 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 165 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 168 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x1050, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 170 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 171 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 172 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 173 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 174 { 0, NULL }, 175 }; 176 177 #ifdef FXP_IP_CSUM_WAR 178 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 179 #else 180 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 181 #endif 182 183 static int fxp_probe(device_t dev); 184 static int fxp_attach(device_t dev); 185 static int fxp_detach(device_t dev); 186 static int fxp_shutdown(device_t dev); 187 static int fxp_suspend(device_t dev); 188 static int fxp_resume(device_t dev); 189 190 static void fxp_intr(void *xsc); 191 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 192 u_int8_t statack, int count); 193 static void fxp_init(void *xsc); 194 static void fxp_init_body(struct fxp_softc *sc); 195 static void fxp_tick(void *xsc); 196 #ifndef BURN_BRIDGES 197 static void fxp_powerstate_d0(device_t dev); 198 #endif 199 static void fxp_start(struct ifnet *ifp); 200 static void fxp_start_body(struct ifnet *ifp); 201 static void fxp_stop(struct fxp_softc *sc); 202 static void fxp_release(struct fxp_softc *sc); 203 static int fxp_ioctl(struct ifnet *ifp, u_long command, 204 caddr_t data); 205 static void fxp_watchdog(struct ifnet *ifp); 206 static int fxp_add_rfabuf(struct fxp_softc *sc, 207 struct fxp_rx *rxp); 208 static int fxp_mc_addrs(struct fxp_softc *sc); 209 static void fxp_mc_setup(struct fxp_softc *sc); 210 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 211 int autosize); 212 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 213 u_int16_t data); 214 static void fxp_autosize_eeprom(struct fxp_softc *sc); 215 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 216 int offset, int words); 217 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 218 int offset, int words); 219 static int fxp_ifmedia_upd(struct ifnet *ifp); 220 static void fxp_ifmedia_sts(struct ifnet *ifp, 221 struct ifmediareq *ifmr); 222 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 223 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 224 struct ifmediareq *ifmr); 225 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 226 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 227 int value); 228 static void fxp_load_ucode(struct fxp_softc *sc); 229 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 230 int low, int high); 231 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 232 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 233 static __inline void fxp_scb_wait(struct fxp_softc *sc); 234 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 235 static __inline void fxp_dma_wait(struct fxp_softc *sc, 236 volatile u_int16_t *status, bus_dma_tag_t dmat, 237 bus_dmamap_t map); 238 239 static device_method_t fxp_methods[] = { 240 /* Device interface */ 241 DEVMETHOD(device_probe, fxp_probe), 242 DEVMETHOD(device_attach, fxp_attach), 243 DEVMETHOD(device_detach, fxp_detach), 244 DEVMETHOD(device_shutdown, fxp_shutdown), 245 DEVMETHOD(device_suspend, fxp_suspend), 246 DEVMETHOD(device_resume, fxp_resume), 247 248 /* MII interface */ 249 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 250 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 251 252 { 0, 0 } 253 }; 254 255 static driver_t fxp_driver = { 256 "fxp", 257 fxp_methods, 258 sizeof(struct fxp_softc), 259 }; 260 261 static devclass_t fxp_devclass; 262 263 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 264 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 265 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 266 267 static int fxp_rnr; 268 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 269 270 static int fxp_noflow; 271 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 272 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 273 274 /* 275 * Wait for the previous command to be accepted (but not necessarily 276 * completed). 277 */ 278 static __inline void 279 fxp_scb_wait(struct fxp_softc *sc) 280 { 281 int i = 10000; 282 283 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 284 DELAY(2); 285 if (i == 0) 286 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 287 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 288 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 289 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 290 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 291 } 292 293 static __inline void 294 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 295 { 296 297 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 298 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 299 fxp_scb_wait(sc); 300 } 301 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 302 } 303 304 static __inline void 305 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 306 bus_dma_tag_t dmat, bus_dmamap_t map) 307 { 308 int i = 10000; 309 310 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 311 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 312 DELAY(2); 313 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 314 } 315 if (i == 0) 316 device_printf(sc->dev, "DMA timeout\n"); 317 } 318 319 /* 320 * Return identification string if this is device is ours. 321 */ 322 static int 323 fxp_probe(device_t dev) 324 { 325 u_int16_t devid; 326 struct fxp_ident *ident; 327 328 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 329 devid = pci_get_device(dev); 330 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 331 if (ident->devid == devid) { 332 device_set_desc(dev, ident->name); 333 return (0); 334 } 335 } 336 } 337 return (ENXIO); 338 } 339 340 #ifndef BURN_BRIDGES 341 static void 342 fxp_powerstate_d0(device_t dev) 343 { 344 #if __FreeBSD_version >= 430002 345 u_int32_t iobase, membase, irq; 346 347 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 348 /* Save important PCI config data. */ 349 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 350 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 351 irq = pci_read_config(dev, PCIR_INTLINE, 4); 352 353 /* Reset the power state. */ 354 device_printf(dev, "chip is in D%d power mode " 355 "-- setting to D0\n", pci_get_powerstate(dev)); 356 357 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 358 359 /* Restore PCI config data. */ 360 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 361 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 362 pci_write_config(dev, PCIR_INTLINE, irq, 4); 363 } 364 #endif 365 } 366 #endif 367 368 static void 369 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 370 { 371 u_int32_t *addr; 372 373 if (error) 374 return; 375 376 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 377 addr = arg; 378 *addr = segs->ds_addr; 379 } 380 381 static int 382 fxp_attach(device_t dev) 383 { 384 int error = 0; 385 struct fxp_softc *sc = device_get_softc(dev); 386 struct ifnet *ifp; 387 struct fxp_rx *rxp; 388 u_int32_t val; 389 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 390 int i, rid, m1, m2, prefer_iomap, maxtxseg; 391 int s, ipcbxmit_disable; 392 393 sc->dev = dev; 394 callout_handle_init(&sc->stat_ch); 395 sysctl_ctx_init(&sc->sysctl_ctx); 396 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 397 MTX_DEF); 398 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 399 fxp_serial_ifmedia_sts); 400 401 s = splimp(); 402 403 /* 404 * Enable bus mastering. 405 */ 406 pci_enable_busmaster(dev); 407 val = pci_read_config(dev, PCIR_COMMAND, 2); 408 #ifndef BURN_BRIDGES 409 fxp_powerstate_d0(dev); 410 #endif 411 /* 412 * Figure out which we should try first - memory mapping or i/o mapping? 413 * We default to memory mapping. Then we accept an override from the 414 * command line. Then we check to see which one is enabled. 415 */ 416 m1 = PCIM_CMD_MEMEN; 417 m2 = PCIM_CMD_PORTEN; 418 prefer_iomap = 0; 419 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 420 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 421 m1 = PCIM_CMD_PORTEN; 422 m2 = PCIM_CMD_MEMEN; 423 } 424 425 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 426 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 427 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 428 0, ~0, 1, RF_ACTIVE); 429 if (sc->mem == NULL) { 430 sc->rtp = 431 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 432 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 433 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 434 0, ~0, 1, RF_ACTIVE); 435 } 436 437 if (!sc->mem) { 438 error = ENXIO; 439 goto fail; 440 } 441 if (bootverbose) { 442 device_printf(dev, "using %s space register mapping\n", 443 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 444 } 445 446 sc->sc_st = rman_get_bustag(sc->mem); 447 sc->sc_sh = rman_get_bushandle(sc->mem); 448 449 /* 450 * Allocate our interrupt. 451 */ 452 rid = 0; 453 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 454 RF_SHAREABLE | RF_ACTIVE); 455 if (sc->irq == NULL) { 456 device_printf(dev, "could not map interrupt\n"); 457 error = ENXIO; 458 goto fail; 459 } 460 461 /* 462 * Reset to a stable state. 463 */ 464 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 465 DELAY(10); 466 467 /* 468 * Find out how large of an SEEPROM we have. 469 */ 470 fxp_autosize_eeprom(sc); 471 472 /* 473 * Determine whether we must use the 503 serial interface. 474 */ 475 fxp_read_eeprom(sc, &data, 6, 1); 476 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 477 (data & FXP_PHY_SERIAL_ONLY)) 478 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 479 480 /* 481 * Create the sysctl tree 482 */ 483 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 484 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 485 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 486 if (sc->sysctl_tree == NULL) { 487 error = ENXIO; 488 goto fail; 489 } 490 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 491 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 492 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 493 "FXP driver receive interrupt microcode bundling delay"); 494 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 495 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 496 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 497 "FXP driver receive interrupt microcode bundle size limit"); 498 499 /* 500 * Pull in device tunables. 501 */ 502 sc->tunable_int_delay = TUNABLE_INT_DELAY; 503 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 504 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 505 "int_delay", &sc->tunable_int_delay); 506 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "bundle_max", &sc->tunable_bundle_max); 508 509 /* 510 * Find out the chip revision; lump all 82557 revs together. 511 */ 512 fxp_read_eeprom(sc, &data, 5, 1); 513 if ((data >> 8) == 1) 514 sc->revision = FXP_REV_82557; 515 else 516 sc->revision = pci_get_revid(dev); 517 518 /* 519 * Enable workarounds for certain chip revision deficiencies. 520 * 521 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 522 * some systems based a normal 82559 design, have a defect where 523 * the chip can cause a PCI protocol violation if it receives 524 * a CU_RESUME command when it is entering the IDLE state. The 525 * workaround is to disable Dynamic Standby Mode, so the chip never 526 * deasserts CLKRUN#, and always remains in an active state. 527 * 528 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 529 */ 530 i = pci_get_device(dev); 531 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 532 sc->revision >= FXP_REV_82559_A0) { 533 fxp_read_eeprom(sc, &data, 10, 1); 534 if (data & 0x02) { /* STB enable */ 535 u_int16_t cksum; 536 int i; 537 538 device_printf(dev, 539 "Disabling dynamic standby mode in EEPROM\n"); 540 data &= ~0x02; 541 fxp_write_eeprom(sc, &data, 10, 1); 542 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 543 cksum = 0; 544 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 545 fxp_read_eeprom(sc, &data, i, 1); 546 cksum += data; 547 } 548 i = (1 << sc->eeprom_size) - 1; 549 cksum = 0xBABA - cksum; 550 fxp_read_eeprom(sc, &data, i, 1); 551 fxp_write_eeprom(sc, &cksum, i, 1); 552 device_printf(dev, 553 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 554 i, data, cksum); 555 #if 1 556 /* 557 * If the user elects to continue, try the software 558 * workaround, as it is better than nothing. 559 */ 560 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 561 #endif 562 } 563 } 564 565 /* 566 * If we are not a 82557 chip, we can enable extended features. 567 */ 568 if (sc->revision != FXP_REV_82557) { 569 /* 570 * If MWI is enabled in the PCI configuration, and there 571 * is a valid cacheline size (8 or 16 dwords), then tell 572 * the board to turn on MWI. 573 */ 574 if (val & PCIM_CMD_MWRICEN && 575 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 576 sc->flags |= FXP_FLAG_MWI_ENABLE; 577 578 /* turn on the extended TxCB feature */ 579 sc->flags |= FXP_FLAG_EXT_TXCB; 580 581 /* enable reception of long frames for VLAN */ 582 sc->flags |= FXP_FLAG_LONG_PKT_EN; 583 } 584 585 /* 586 * Enable use of extended RFDs and TCBs for 82550 587 * and later chips. Note: we need extended TXCB support 588 * too, but that's already enabled by the code above. 589 * Be careful to do this only on the right devices. 590 * 591 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 592 * truncate packets that end with an mbuf containing 1 to 3 bytes 593 * when used with this feature enabled in the previous version of the 594 * driver. This problem appears to be fixed now that the driver 595 * always sets the hardware parse bit in the IPCB structure, which 596 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 597 * Source Software Developer Manual" says is necessary in the 598 * cases where packet truncation was observed. 599 * 600 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 601 * allows this feature to be disabled at boot time. 602 * 603 * If fxp is not compiled into the kernel, this feature may also 604 * be disabled at run time: 605 * # kldunload fxp 606 * # kenv hint.fxp.0.ipcbxmit_disable=1 607 * # kldload fxp 608 */ 609 610 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 611 &ipcbxmit_disable) != 0) 612 ipcbxmit_disable = 0; 613 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 614 sc->revision == FXP_REV_82550_C)) { 615 sc->rfa_size = sizeof (struct fxp_rfa); 616 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 617 sc->flags |= FXP_FLAG_EXT_RFA; 618 } else { 619 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 620 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 621 } 622 623 /* 624 * Allocate DMA tags and DMA safe memory. 625 */ 626 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 627 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 628 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 629 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 630 if (error) { 631 device_printf(dev, "could not allocate dma tag\n"); 632 goto fail; 633 } 634 635 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 636 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 637 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 638 &sc->fxp_stag); 639 if (error) { 640 device_printf(dev, "could not allocate dma tag\n"); 641 goto fail; 642 } 643 644 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 645 BUS_DMA_NOWAIT, &sc->fxp_smap); 646 if (error) 647 goto fail; 648 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 649 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 650 if (error) { 651 device_printf(dev, "could not map the stats buffer\n"); 652 goto fail; 653 } 654 bzero(sc->fxp_stats, sizeof(struct fxp_stats)); 655 656 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 657 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 658 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 659 if (error) { 660 device_printf(dev, "could not allocate dma tag\n"); 661 goto fail; 662 } 663 664 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 665 BUS_DMA_NOWAIT, &sc->cbl_map); 666 if (error) 667 goto fail; 668 bzero(sc->fxp_desc.cbl_list, FXP_TXCB_SZ); 669 670 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 671 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 672 &sc->fxp_desc.cbl_addr, 0); 673 if (error) { 674 device_printf(dev, "could not map DMA memory\n"); 675 goto fail; 676 } 677 678 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 679 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 680 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 681 &sc->mcs_tag); 682 if (error) { 683 device_printf(dev, "could not allocate dma tag\n"); 684 goto fail; 685 } 686 687 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 688 BUS_DMA_NOWAIT, &sc->mcs_map); 689 if (error) 690 goto fail; 691 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 692 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 693 if (error) { 694 device_printf(dev, "can't map the multicast setup command\n"); 695 goto fail; 696 } 697 698 /* 699 * Pre-allocate the TX DMA maps. 700 */ 701 for (i = 0; i < FXP_NTXCB; i++) { 702 error = bus_dmamap_create(sc->fxp_mtag, 0, 703 &sc->fxp_desc.tx_list[i].tx_map); 704 if (error) { 705 device_printf(dev, "can't create DMA map for TX\n"); 706 goto fail; 707 } 708 } 709 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 710 if (error) { 711 device_printf(dev, "can't create spare DMA map\n"); 712 goto fail; 713 } 714 715 /* 716 * Pre-allocate our receive buffers. 717 */ 718 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 719 for (i = 0; i < FXP_NRFABUFS; i++) { 720 rxp = &sc->fxp_desc.rx_list[i]; 721 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 722 if (error) { 723 device_printf(dev, "can't create DMA map for RX\n"); 724 goto fail; 725 } 726 if (fxp_add_rfabuf(sc, rxp) != 0) { 727 error = ENOMEM; 728 goto fail; 729 } 730 } 731 732 /* 733 * Read MAC address. 734 */ 735 fxp_read_eeprom(sc, myea, 0, 3); 736 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 737 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 738 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 739 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 740 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 741 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 742 device_printf(dev, "Ethernet address %6D%s\n", 743 sc->arpcom.ac_enaddr, ":", 744 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 745 if (bootverbose) { 746 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 747 pci_get_vendor(dev), pci_get_device(dev), 748 pci_get_subvendor(dev), pci_get_subdevice(dev), 749 pci_get_revid(dev)); 750 fxp_read_eeprom(sc, &data, 10, 1); 751 device_printf(dev, "Dynamic Standby mode is %s\n", 752 data & 0x02 ? "enabled" : "disabled"); 753 } 754 755 /* 756 * If this is only a 10Mbps device, then there is no MII, and 757 * the PHY will use a serial interface instead. 758 * 759 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 760 * doesn't have a programming interface of any sort. The 761 * media is sensed automatically based on how the link partner 762 * is configured. This is, in essence, manual configuration. 763 */ 764 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 765 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 766 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 767 } else { 768 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 769 fxp_ifmedia_sts)) { 770 device_printf(dev, "MII without any PHY!\n"); 771 error = ENXIO; 772 goto fail; 773 } 774 } 775 776 ifp = &sc->arpcom.ac_if; 777 ifp->if_unit = device_get_unit(dev); 778 ifp->if_name = "fxp"; 779 ifp->if_output = ether_output; 780 ifp->if_baudrate = 100000000; 781 ifp->if_init = fxp_init; 782 ifp->if_softc = sc; 783 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 784 ifp->if_ioctl = fxp_ioctl; 785 ifp->if_start = fxp_start; 786 ifp->if_watchdog = fxp_watchdog; 787 788 /* Enable checksum offload for 82550 or better chips */ 789 if (sc->flags & FXP_FLAG_EXT_RFA) { 790 ifp->if_hwassist = FXP_CSUM_FEATURES; 791 ifp->if_capabilities = IFCAP_HWCSUM; 792 ifp->if_capenable = ifp->if_capabilities; 793 } 794 795 /* 796 * Attach the interface. 797 */ 798 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 799 800 /* 801 * Tell the upper layer(s) we support long frames. 802 */ 803 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 804 ifp->if_capabilities |= IFCAP_VLAN_MTU; 805 806 /* 807 * Let the system queue as many packets as we have available 808 * TX descriptors. 809 */ 810 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 811 812 /* 813 * Hook our interrupt after all initialization is complete. 814 * XXX This driver has been tested with the INTR_MPSAFFE flag set 815 * however, ifp and its functions are not fully locked so MPSAFE 816 * should not be used unless you can handle potential data loss. 817 */ 818 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/, 819 fxp_intr, sc, &sc->ih); 820 if (error) { 821 device_printf(dev, "could not setup irq\n"); 822 ether_ifdetach(&sc->arpcom.ac_if); 823 goto fail; 824 } 825 826 fail: 827 splx(s); 828 if (error) 829 fxp_release(sc); 830 return (error); 831 } 832 833 /* 834 * Release all resources. The softc lock should not be held and the 835 * interrupt should already be torn down. 836 */ 837 static void 838 fxp_release(struct fxp_softc *sc) 839 { 840 struct fxp_rx *rxp; 841 struct fxp_tx *txp; 842 int i; 843 844 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 845 if (sc->ih) 846 panic("fxp_release() called with intr handle still active"); 847 if (sc->miibus) 848 device_delete_child(sc->dev, sc->miibus); 849 bus_generic_detach(sc->dev); 850 ifmedia_removeall(&sc->sc_media); 851 if (sc->fxp_desc.cbl_list) { 852 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 853 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 854 sc->cbl_map); 855 } 856 if (sc->fxp_stats) { 857 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 858 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 859 } 860 if (sc->mcsp) { 861 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 862 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 863 } 864 if (sc->irq) 865 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 866 if (sc->mem) 867 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 868 if (sc->fxp_mtag) { 869 for (i = 0; i < FXP_NRFABUFS; i++) { 870 rxp = &sc->fxp_desc.rx_list[i]; 871 if (rxp->rx_mbuf != NULL) { 872 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 873 BUS_DMASYNC_POSTREAD); 874 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 875 m_freem(rxp->rx_mbuf); 876 } 877 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 878 } 879 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 880 bus_dma_tag_destroy(sc->fxp_mtag); 881 } 882 if (sc->fxp_stag) { 883 for (i = 0; i < FXP_NTXCB; i++) { 884 txp = &sc->fxp_desc.tx_list[i]; 885 if (txp->tx_mbuf != NULL) { 886 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 887 BUS_DMASYNC_POSTWRITE); 888 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 889 m_freem(txp->tx_mbuf); 890 } 891 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 892 } 893 bus_dma_tag_destroy(sc->fxp_stag); 894 } 895 if (sc->cbl_tag) 896 bus_dma_tag_destroy(sc->cbl_tag); 897 if (sc->mcs_tag) 898 bus_dma_tag_destroy(sc->mcs_tag); 899 900 sysctl_ctx_free(&sc->sysctl_ctx); 901 902 mtx_destroy(&sc->sc_mtx); 903 } 904 905 /* 906 * Detach interface. 907 */ 908 static int 909 fxp_detach(device_t dev) 910 { 911 struct fxp_softc *sc = device_get_softc(dev); 912 int s; 913 914 FXP_LOCK(sc); 915 s = splimp(); 916 917 sc->suspended = 1; /* Do same thing as we do for suspend */ 918 /* 919 * Close down routes etc. 920 */ 921 ether_ifdetach(&sc->arpcom.ac_if); 922 923 /* 924 * Stop DMA and drop transmit queue, but disable interrupts first. 925 */ 926 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 927 fxp_stop(sc); 928 FXP_UNLOCK(sc); 929 930 /* 931 * Unhook interrupt before dropping lock. This is to prevent 932 * races with fxp_intr(). 933 */ 934 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 935 sc->ih = NULL; 936 937 splx(s); 938 939 /* Release our allocated resources. */ 940 fxp_release(sc); 941 return (0); 942 } 943 944 /* 945 * Device shutdown routine. Called at system shutdown after sync. The 946 * main purpose of this routine is to shut off receiver DMA so that 947 * kernel memory doesn't get clobbered during warmboot. 948 */ 949 static int 950 fxp_shutdown(device_t dev) 951 { 952 /* 953 * Make sure that DMA is disabled prior to reboot. Not doing 954 * do could allow DMA to corrupt kernel memory during the 955 * reboot before the driver initializes. 956 */ 957 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 958 return (0); 959 } 960 961 /* 962 * Device suspend routine. Stop the interface and save some PCI 963 * settings in case the BIOS doesn't restore them properly on 964 * resume. 965 */ 966 static int 967 fxp_suspend(device_t dev) 968 { 969 struct fxp_softc *sc = device_get_softc(dev); 970 int i, s; 971 972 FXP_LOCK(sc); 973 s = splimp(); 974 975 fxp_stop(sc); 976 977 for (i = 0; i < 5; i++) 978 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 979 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 980 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 981 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 982 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 983 984 sc->suspended = 1; 985 986 FXP_UNLOCK(sc); 987 splx(s); 988 return (0); 989 } 990 991 /* 992 * Device resume routine. Restore some PCI settings in case the BIOS 993 * doesn't, re-enable busmastering, and restart the interface if 994 * appropriate. 995 */ 996 static int 997 fxp_resume(device_t dev) 998 { 999 struct fxp_softc *sc = device_get_softc(dev); 1000 struct ifnet *ifp = &sc->sc_if; 1001 u_int16_t pci_command; 1002 int i, s; 1003 1004 FXP_LOCK(sc); 1005 s = splimp(); 1006 #ifndef BURN_BRIDGES 1007 fxp_powerstate_d0(dev); 1008 #endif 1009 /* better way to do this? */ 1010 for (i = 0; i < 5; i++) 1011 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1012 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1013 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1014 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1015 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1016 1017 /* reenable busmastering */ 1018 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1019 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1020 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1021 1022 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1023 DELAY(10); 1024 1025 /* reinitialize interface if necessary */ 1026 if (ifp->if_flags & IFF_UP) 1027 fxp_init_body(sc); 1028 1029 sc->suspended = 0; 1030 1031 FXP_UNLOCK(sc); 1032 splx(s); 1033 return (0); 1034 } 1035 1036 static void 1037 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1038 { 1039 u_int16_t reg; 1040 int x; 1041 1042 /* 1043 * Shift in data. 1044 */ 1045 for (x = 1 << (length - 1); x; x >>= 1) { 1046 if (data & x) 1047 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1048 else 1049 reg = FXP_EEPROM_EECS; 1050 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1051 DELAY(1); 1052 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1053 DELAY(1); 1054 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1055 DELAY(1); 1056 } 1057 } 1058 1059 /* 1060 * Read from the serial EEPROM. Basically, you manually shift in 1061 * the read opcode (one bit at a time) and then shift in the address, 1062 * and then you shift out the data (all of this one bit at a time). 1063 * The word size is 16 bits, so you have to provide the address for 1064 * every 16 bits of data. 1065 */ 1066 static u_int16_t 1067 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1068 { 1069 u_int16_t reg, data; 1070 int x; 1071 1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1073 /* 1074 * Shift in read opcode. 1075 */ 1076 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1077 /* 1078 * Shift in address. 1079 */ 1080 data = 0; 1081 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1082 if (offset & x) 1083 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1084 else 1085 reg = FXP_EEPROM_EECS; 1086 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1087 DELAY(1); 1088 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1089 DELAY(1); 1090 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1091 DELAY(1); 1092 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1093 data++; 1094 if (autosize && reg == 0) { 1095 sc->eeprom_size = data; 1096 break; 1097 } 1098 } 1099 /* 1100 * Shift out data. 1101 */ 1102 data = 0; 1103 reg = FXP_EEPROM_EECS; 1104 for (x = 1 << 15; x; x >>= 1) { 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1106 DELAY(1); 1107 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1108 data |= x; 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1110 DELAY(1); 1111 } 1112 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1113 DELAY(1); 1114 1115 return (data); 1116 } 1117 1118 static void 1119 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1120 { 1121 int i; 1122 1123 /* 1124 * Erase/write enable. 1125 */ 1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1127 fxp_eeprom_shiftin(sc, 0x4, 3); 1128 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1130 DELAY(1); 1131 /* 1132 * Shift in write opcode, address, data. 1133 */ 1134 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1135 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1136 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1137 fxp_eeprom_shiftin(sc, data, 16); 1138 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1139 DELAY(1); 1140 /* 1141 * Wait for EEPROM to finish up. 1142 */ 1143 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1144 DELAY(1); 1145 for (i = 0; i < 1000; i++) { 1146 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1147 break; 1148 DELAY(50); 1149 } 1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1151 DELAY(1); 1152 /* 1153 * Erase/write disable. 1154 */ 1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1156 fxp_eeprom_shiftin(sc, 0x4, 3); 1157 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1158 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1159 DELAY(1); 1160 } 1161 1162 /* 1163 * From NetBSD: 1164 * 1165 * Figure out EEPROM size. 1166 * 1167 * 559's can have either 64-word or 256-word EEPROMs, the 558 1168 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1169 * talks about the existance of 16 to 256 word EEPROMs. 1170 * 1171 * The only known sizes are 64 and 256, where the 256 version is used 1172 * by CardBus cards to store CIS information. 1173 * 1174 * The address is shifted in msb-to-lsb, and after the last 1175 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1176 * after which follows the actual data. We try to detect this zero, by 1177 * probing the data-out bit in the EEPROM control register just after 1178 * having shifted in a bit. If the bit is zero, we assume we've 1179 * shifted enough address bits. The data-out should be tri-state, 1180 * before this, which should translate to a logical one. 1181 */ 1182 static void 1183 fxp_autosize_eeprom(struct fxp_softc *sc) 1184 { 1185 1186 /* guess maximum size of 256 words */ 1187 sc->eeprom_size = 8; 1188 1189 /* autosize */ 1190 (void) fxp_eeprom_getword(sc, 0, 1); 1191 } 1192 1193 static void 1194 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1195 { 1196 int i; 1197 1198 for (i = 0; i < words; i++) 1199 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1200 } 1201 1202 static void 1203 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1204 { 1205 int i; 1206 1207 for (i = 0; i < words; i++) 1208 fxp_eeprom_putword(sc, offset + i, data[i]); 1209 } 1210 1211 static void 1212 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1213 bus_size_t mapsize, int error) 1214 { 1215 struct fxp_softc *sc; 1216 struct fxp_cb_tx *txp; 1217 int i; 1218 1219 if (error) 1220 return; 1221 1222 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1223 1224 sc = arg; 1225 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1226 for (i = 0; i < nseg; i++) { 1227 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1228 /* 1229 * If this is an 82550/82551, then we're using extended 1230 * TxCBs _and_ we're using checksum offload. This means 1231 * that the TxCB is really an IPCB. One major difference 1232 * between the two is that with plain extended TxCBs, 1233 * the bottom half of the TxCB contains two entries from 1234 * the TBD array, whereas IPCBs contain just one entry: 1235 * one entry (8 bytes) has been sacrificed for the TCP/IP 1236 * checksum offload control bits. So to make things work 1237 * right, we have to start filling in the TBD array 1238 * starting from a different place depending on whether 1239 * the chip is an 82550/82551 or not. 1240 */ 1241 if (sc->flags & FXP_FLAG_EXT_RFA) { 1242 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1243 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1244 } else { 1245 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1246 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1247 } 1248 } 1249 txp->tbd_number = nseg; 1250 } 1251 1252 /* 1253 * Grab the softc lock and call the real fxp_start_body() routine 1254 */ 1255 static void 1256 fxp_start(struct ifnet *ifp) 1257 { 1258 struct fxp_softc *sc = ifp->if_softc; 1259 1260 FXP_LOCK(sc); 1261 fxp_start_body(ifp); 1262 FXP_UNLOCK(sc); 1263 } 1264 1265 /* 1266 * Start packet transmission on the interface. 1267 * This routine must be called with the softc lock held, and is an 1268 * internal entry point only. 1269 */ 1270 static void 1271 fxp_start_body(struct ifnet *ifp) 1272 { 1273 struct fxp_softc *sc = ifp->if_softc; 1274 struct fxp_tx *txp; 1275 struct mbuf *mb_head; 1276 int error; 1277 1278 mtx_assert(&sc->sc_mtx, MA_OWNED); 1279 /* 1280 * See if we need to suspend xmit until the multicast filter 1281 * has been reprogrammed (which can only be done at the head 1282 * of the command chain). 1283 */ 1284 if (sc->need_mcsetup) { 1285 return; 1286 } 1287 1288 txp = NULL; 1289 1290 /* 1291 * We're finished if there is nothing more to add to the list or if 1292 * we're all filled up with buffers to transmit. 1293 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1294 * a NOP command when needed. 1295 */ 1296 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1297 1298 /* 1299 * Grab a packet to transmit. 1300 */ 1301 IF_DEQUEUE(&ifp->if_snd, mb_head); 1302 1303 /* 1304 * Get pointer to next available tx desc. 1305 */ 1306 txp = sc->fxp_desc.tx_last->tx_next; 1307 1308 /* 1309 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1310 * Ethernet Controller Family Open Source Software 1311 * Developer Manual says: 1312 * Using software parsing is only allowed with legal 1313 * TCP/IP or UDP/IP packets. 1314 * ... 1315 * For all other datagrams, hardware parsing must 1316 * be used. 1317 * Software parsing appears to truncate ICMP and 1318 * fragmented UDP packets that contain one to three 1319 * bytes in the second (and final) mbuf of the packet. 1320 */ 1321 if (sc->flags & FXP_FLAG_EXT_RFA) 1322 txp->tx_cb->ipcb_ip_activation_high = 1323 FXP_IPCB_HARDWAREPARSING_ENABLE; 1324 1325 /* 1326 * Deal with TCP/IP checksum offload. Note that 1327 * in order for TCP checksum offload to work, 1328 * the pseudo header checksum must have already 1329 * been computed and stored in the checksum field 1330 * in the TCP header. The stack should have 1331 * already done this for us. 1332 */ 1333 1334 if (mb_head->m_pkthdr.csum_flags) { 1335 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1336 txp->tx_cb->ipcb_ip_schedule = 1337 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1338 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1339 txp->tx_cb->ipcb_ip_schedule |= 1340 FXP_IPCB_TCP_PACKET; 1341 } 1342 #ifdef FXP_IP_CSUM_WAR 1343 /* 1344 * XXX The 82550 chip appears to have trouble 1345 * dealing with IP header checksums in very small 1346 * datagrams, namely fragments from 1 to 3 bytes 1347 * in size. For example, say you want to transmit 1348 * a UDP packet of 1473 bytes. The packet will be 1349 * fragmented over two IP datagrams, the latter 1350 * containing only one byte of data. The 82550 will 1351 * botch the header checksum on the 1-byte fragment. 1352 * As long as the datagram contains 4 or more bytes 1353 * of data, you're ok. 1354 * 1355 * The following code attempts to work around this 1356 * problem: if the datagram is less than 38 bytes 1357 * in size (14 bytes ether header, 20 bytes IP header, 1358 * plus 4 bytes of data), we punt and compute the IP 1359 * header checksum by hand. This workaround doesn't 1360 * work very well, however, since it can be fooled 1361 * by things like VLAN tags and IP options that make 1362 * the header sizes/offsets vary. 1363 */ 1364 1365 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1366 if (mb_head->m_pkthdr.len < 38) { 1367 struct ip *ip; 1368 mb_head->m_data += ETHER_HDR_LEN; 1369 ip = mtod(mb_head, struct ip *); 1370 ip->ip_sum = in_cksum(mb_head, 1371 ip->ip_hl << 2); 1372 mb_head->m_data -= ETHER_HDR_LEN; 1373 } else { 1374 txp->tx_cb->ipcb_ip_activation_high = 1375 FXP_IPCB_HARDWAREPARSING_ENABLE; 1376 txp->tx_cb->ipcb_ip_schedule |= 1377 FXP_IPCB_IP_CHECKSUM_ENABLE; 1378 } 1379 } 1380 #endif 1381 } 1382 1383 /* 1384 * Go through each of the mbufs in the chain and initialize 1385 * the transmit buffer descriptors with the physical address 1386 * and size of the mbuf. 1387 */ 1388 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1389 mb_head, fxp_dma_map_txbuf, sc, 0); 1390 1391 if (error && error != EFBIG) { 1392 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1393 error); 1394 m_freem(mb_head); 1395 break; 1396 } 1397 1398 if (error) { 1399 struct mbuf *mn; 1400 1401 /* 1402 * We ran out of segments. We have to recopy this 1403 * mbuf chain first. Bail out if we can't get the 1404 * new buffers. 1405 */ 1406 mn = m_defrag(mb_head, M_DONTWAIT); 1407 if (mn == NULL) { 1408 m_freem(mb_head); 1409 break; 1410 } else { 1411 mb_head = mn; 1412 } 1413 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1414 mb_head, fxp_dma_map_txbuf, sc, 0); 1415 if (error) { 1416 device_printf(sc->dev, 1417 "can't map mbuf (error %d)\n", error); 1418 m_freem(mb_head); 1419 break; 1420 } 1421 } 1422 1423 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1424 BUS_DMASYNC_PREWRITE); 1425 1426 txp->tx_mbuf = mb_head; 1427 txp->tx_cb->cb_status = 0; 1428 txp->tx_cb->byte_count = 0; 1429 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1430 txp->tx_cb->cb_command = 1431 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1432 FXP_CB_COMMAND_S); 1433 } else { 1434 txp->tx_cb->cb_command = 1435 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1436 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1437 /* 1438 * Set a 5 second timer just in case we don't hear 1439 * from the card again. 1440 */ 1441 ifp->if_timer = 5; 1442 } 1443 txp->tx_cb->tx_threshold = tx_threshold; 1444 1445 /* 1446 * Advance the end of list forward. 1447 */ 1448 1449 #ifdef __alpha__ 1450 /* 1451 * On platforms which can't access memory in 16-bit 1452 * granularities, we must prevent the card from DMA'ing 1453 * up the status while we update the command field. 1454 * This could cause us to overwrite the completion status. 1455 * XXX This is probably bogus and we're _not_ looking 1456 * for atomicity here. 1457 */ 1458 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1459 htole16(FXP_CB_COMMAND_S)); 1460 #else 1461 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1462 htole16(~FXP_CB_COMMAND_S); 1463 #endif /*__alpha__*/ 1464 sc->fxp_desc.tx_last = txp; 1465 1466 /* 1467 * Advance the beginning of the list forward if there are 1468 * no other packets queued (when nothing is queued, tx_first 1469 * sits on the last TxCB that was sent out). 1470 */ 1471 if (sc->tx_queued == 0) 1472 sc->fxp_desc.tx_first = txp; 1473 1474 sc->tx_queued++; 1475 1476 /* 1477 * Pass packet to bpf if there is a listener. 1478 */ 1479 BPF_MTAP(ifp, mb_head); 1480 } 1481 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1482 1483 /* 1484 * We're finished. If we added to the list, issue a RESUME to get DMA 1485 * going again if suspended. 1486 */ 1487 if (txp != NULL) { 1488 fxp_scb_wait(sc); 1489 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1490 } 1491 } 1492 1493 #ifdef DEVICE_POLLING 1494 static poll_handler_t fxp_poll; 1495 1496 static void 1497 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1498 { 1499 struct fxp_softc *sc = ifp->if_softc; 1500 u_int8_t statack; 1501 1502 FXP_LOCK(sc); 1503 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1504 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1505 FXP_UNLOCK(sc); 1506 return; 1507 } 1508 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1509 FXP_SCB_STATACK_FR; 1510 if (cmd == POLL_AND_CHECK_STATUS) { 1511 u_int8_t tmp; 1512 1513 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1514 if (tmp == 0xff || tmp == 0) { 1515 FXP_UNLOCK(sc); 1516 return; /* nothing to do */ 1517 } 1518 tmp &= ~statack; 1519 /* ack what we can */ 1520 if (tmp != 0) 1521 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1522 statack |= tmp; 1523 } 1524 fxp_intr_body(sc, ifp, statack, count); 1525 FXP_UNLOCK(sc); 1526 } 1527 #endif /* DEVICE_POLLING */ 1528 1529 /* 1530 * Process interface interrupts. 1531 */ 1532 static void 1533 fxp_intr(void *xsc) 1534 { 1535 struct fxp_softc *sc = xsc; 1536 struct ifnet *ifp = &sc->sc_if; 1537 u_int8_t statack; 1538 1539 FXP_LOCK(sc); 1540 if (sc->suspended) { 1541 FXP_UNLOCK(sc); 1542 return; 1543 } 1544 1545 #ifdef DEVICE_POLLING 1546 if (ifp->if_flags & IFF_POLLING) { 1547 FXP_UNLOCK(sc); 1548 return; 1549 } 1550 if (ether_poll_register(fxp_poll, ifp)) { 1551 /* disable interrupts */ 1552 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1553 fxp_poll(ifp, 0, 1); 1554 FXP_UNLOCK(sc); 1555 return; 1556 } 1557 #endif 1558 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1559 /* 1560 * It should not be possible to have all bits set; the 1561 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1562 * all bits are set, this may indicate that the card has 1563 * been physically ejected, so ignore it. 1564 */ 1565 if (statack == 0xff) { 1566 FXP_UNLOCK(sc); 1567 return; 1568 } 1569 1570 /* 1571 * First ACK all the interrupts in this pass. 1572 */ 1573 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1574 fxp_intr_body(sc, ifp, statack, -1); 1575 } 1576 FXP_UNLOCK(sc); 1577 } 1578 1579 static void 1580 fxp_txeof(struct fxp_softc *sc) 1581 { 1582 struct fxp_tx *txp; 1583 1584 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1585 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1586 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1587 txp = txp->tx_next) { 1588 if (txp->tx_mbuf != NULL) { 1589 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1590 BUS_DMASYNC_POSTWRITE); 1591 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1592 m_freem(txp->tx_mbuf); 1593 txp->tx_mbuf = NULL; 1594 /* clear this to reset csum offload bits */ 1595 txp->tx_cb->tbd[0].tb_addr = 0; 1596 } 1597 sc->tx_queued--; 1598 } 1599 sc->fxp_desc.tx_first = txp; 1600 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1601 } 1602 1603 static void 1604 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1605 int count) 1606 { 1607 struct mbuf *m; 1608 struct fxp_rx *rxp; 1609 struct fxp_rfa *rfa; 1610 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1611 1612 mtx_assert(&sc->sc_mtx, MA_OWNED); 1613 if (rnr) 1614 fxp_rnr++; 1615 #ifdef DEVICE_POLLING 1616 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1617 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1618 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1619 rnr = 1; 1620 } 1621 #endif 1622 1623 /* 1624 * Free any finished transmit mbuf chains. 1625 * 1626 * Handle the CNA event likt a CXTNO event. It used to 1627 * be that this event (control unit not ready) was not 1628 * encountered, but it is now with the SMPng modifications. 1629 * The exact sequence of events that occur when the interface 1630 * is brought up are different now, and if this event 1631 * goes unhandled, the configuration/rxfilter setup sequence 1632 * can stall for several seconds. The result is that no 1633 * packets go out onto the wire for about 5 to 10 seconds 1634 * after the interface is ifconfig'ed for the first time. 1635 */ 1636 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1637 fxp_txeof(sc); 1638 1639 ifp->if_timer = 0; 1640 if (sc->tx_queued == 0) { 1641 if (sc->need_mcsetup) 1642 fxp_mc_setup(sc); 1643 } 1644 /* 1645 * Try to start more packets transmitting. 1646 */ 1647 if (ifp->if_snd.ifq_head != NULL) 1648 fxp_start_body(ifp); 1649 } 1650 1651 /* 1652 * Just return if nothing happened on the receive side. 1653 */ 1654 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1655 return; 1656 1657 /* 1658 * Process receiver interrupts. If a no-resource (RNR) 1659 * condition exists, get whatever packets we can and 1660 * re-start the receiver. 1661 * 1662 * When using polling, we do not process the list to completion, 1663 * so when we get an RNR interrupt we must defer the restart 1664 * until we hit the last buffer with the C bit set. 1665 * If we run out of cycles and rfa_headm has the C bit set, 1666 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1667 * that the info will be used in the subsequent polling cycle. 1668 */ 1669 for (;;) { 1670 rxp = sc->fxp_desc.rx_head; 1671 m = rxp->rx_mbuf; 1672 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1673 RFA_ALIGNMENT_FUDGE); 1674 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1675 BUS_DMASYNC_POSTREAD); 1676 1677 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1678 if (count >= 0 && count-- == 0) { 1679 if (rnr) { 1680 /* Defer RNR processing until the next time. */ 1681 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1682 rnr = 0; 1683 } 1684 break; 1685 } 1686 #endif /* DEVICE_POLLING */ 1687 1688 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1689 break; 1690 1691 /* 1692 * Advance head forward. 1693 */ 1694 sc->fxp_desc.rx_head = rxp->rx_next; 1695 1696 /* 1697 * Add a new buffer to the receive chain. 1698 * If this fails, the old buffer is recycled 1699 * instead. 1700 */ 1701 if (fxp_add_rfabuf(sc, rxp) == 0) { 1702 int total_len; 1703 1704 /* 1705 * Fetch packet length (the top 2 bits of 1706 * actual_size are flags set by the controller 1707 * upon completion), and drop the packet in case 1708 * of bogus length or CRC errors. 1709 */ 1710 total_len = le16toh(rfa->actual_size) & 0x3fff; 1711 if (total_len < sizeof(struct ether_header) || 1712 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1713 sc->rfa_size || 1714 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1715 m_freem(m); 1716 continue; 1717 } 1718 1719 /* Do IP checksum checking. */ 1720 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1721 if (rfa->rfax_csum_sts & 1722 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1723 m->m_pkthdr.csum_flags |= 1724 CSUM_IP_CHECKED; 1725 if (rfa->rfax_csum_sts & 1726 FXP_RFDX_CS_IP_CSUM_VALID) 1727 m->m_pkthdr.csum_flags |= 1728 CSUM_IP_VALID; 1729 if ((rfa->rfax_csum_sts & 1730 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1731 (rfa->rfax_csum_sts & 1732 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1733 m->m_pkthdr.csum_flags |= 1734 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1735 m->m_pkthdr.csum_data = 0xffff; 1736 } 1737 } 1738 1739 m->m_pkthdr.len = m->m_len = total_len; 1740 m->m_pkthdr.rcvif = ifp; 1741 1742 /* 1743 * Drop locks before calling if_input() since it 1744 * may re-enter fxp_start() in the netisr case. 1745 * This would result in a lock reversal. Better 1746 * performance might be obtained by chaining all 1747 * packets received, dropping the lock, and then 1748 * calling if_input() on each one. 1749 */ 1750 FXP_UNLOCK(sc); 1751 (*ifp->if_input)(ifp, m); 1752 FXP_LOCK(sc); 1753 } 1754 } 1755 if (rnr) { 1756 fxp_scb_wait(sc); 1757 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1758 sc->fxp_desc.rx_head->rx_addr); 1759 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1760 } 1761 } 1762 1763 /* 1764 * Update packet in/out/collision statistics. The i82557 doesn't 1765 * allow you to access these counters without doing a fairly 1766 * expensive DMA to get _all_ of the statistics it maintains, so 1767 * we do this operation here only once per second. The statistics 1768 * counters in the kernel are updated from the previous dump-stats 1769 * DMA and then a new dump-stats DMA is started. The on-chip 1770 * counters are zeroed when the DMA completes. If we can't start 1771 * the DMA immediately, we don't wait - we just prepare to read 1772 * them again next time. 1773 */ 1774 static void 1775 fxp_tick(void *xsc) 1776 { 1777 struct fxp_softc *sc = xsc; 1778 struct ifnet *ifp = &sc->sc_if; 1779 struct fxp_stats *sp = sc->fxp_stats; 1780 int s; 1781 1782 FXP_LOCK(sc); 1783 s = splimp(); 1784 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1785 ifp->if_opackets += le32toh(sp->tx_good); 1786 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1787 if (sp->rx_good) { 1788 ifp->if_ipackets += le32toh(sp->rx_good); 1789 sc->rx_idle_secs = 0; 1790 } else { 1791 /* 1792 * Receiver's been idle for another second. 1793 */ 1794 sc->rx_idle_secs++; 1795 } 1796 ifp->if_ierrors += 1797 le32toh(sp->rx_crc_errors) + 1798 le32toh(sp->rx_alignment_errors) + 1799 le32toh(sp->rx_rnr_errors) + 1800 le32toh(sp->rx_overrun_errors); 1801 /* 1802 * If any transmit underruns occured, bump up the transmit 1803 * threshold by another 512 bytes (64 * 8). 1804 */ 1805 if (sp->tx_underruns) { 1806 ifp->if_oerrors += le32toh(sp->tx_underruns); 1807 if (tx_threshold < 192) 1808 tx_threshold += 64; 1809 } 1810 1811 /* 1812 * Release any xmit buffers that have completed DMA. This isn't 1813 * strictly necessary to do here, but it's advantagous for mbufs 1814 * with external storage to be released in a timely manner rather 1815 * than being defered for a potentially long time. This limits 1816 * the delay to a maximum of one second. 1817 */ 1818 fxp_txeof(sc); 1819 1820 /* 1821 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1822 * then assume the receiver has locked up and attempt to clear 1823 * the condition by reprogramming the multicast filter. This is 1824 * a work-around for a bug in the 82557 where the receiver locks 1825 * up if it gets certain types of garbage in the syncronization 1826 * bits prior to the packet header. This bug is supposed to only 1827 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1828 * mode as well (perhaps due to a 10/100 speed transition). 1829 */ 1830 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1831 sc->rx_idle_secs = 0; 1832 fxp_mc_setup(sc); 1833 } 1834 /* 1835 * If there is no pending command, start another stats 1836 * dump. Otherwise punt for now. 1837 */ 1838 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1839 /* 1840 * Start another stats dump. 1841 */ 1842 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1843 BUS_DMASYNC_PREREAD); 1844 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1845 } else { 1846 /* 1847 * A previous command is still waiting to be accepted. 1848 * Just zero our copy of the stats and wait for the 1849 * next timer event to update them. 1850 */ 1851 sp->tx_good = 0; 1852 sp->tx_underruns = 0; 1853 sp->tx_total_collisions = 0; 1854 1855 sp->rx_good = 0; 1856 sp->rx_crc_errors = 0; 1857 sp->rx_alignment_errors = 0; 1858 sp->rx_rnr_errors = 0; 1859 sp->rx_overrun_errors = 0; 1860 } 1861 if (sc->miibus != NULL) 1862 mii_tick(device_get_softc(sc->miibus)); 1863 1864 /* 1865 * Schedule another timeout one second from now. 1866 */ 1867 sc->stat_ch = timeout(fxp_tick, sc, hz); 1868 FXP_UNLOCK(sc); 1869 splx(s); 1870 } 1871 1872 /* 1873 * Stop the interface. Cancels the statistics updater and resets 1874 * the interface. 1875 */ 1876 static void 1877 fxp_stop(struct fxp_softc *sc) 1878 { 1879 struct ifnet *ifp = &sc->sc_if; 1880 struct fxp_tx *txp; 1881 int i; 1882 1883 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1884 ifp->if_timer = 0; 1885 1886 #ifdef DEVICE_POLLING 1887 ether_poll_deregister(ifp); 1888 #endif 1889 /* 1890 * Cancel stats updater. 1891 */ 1892 untimeout(fxp_tick, sc, sc->stat_ch); 1893 1894 /* 1895 * Issue software reset, which also unloads the microcode. 1896 */ 1897 sc->flags &= ~FXP_FLAG_UCODE; 1898 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1899 DELAY(50); 1900 1901 /* 1902 * Release any xmit buffers. 1903 */ 1904 txp = sc->fxp_desc.tx_list; 1905 if (txp != NULL) { 1906 for (i = 0; i < FXP_NTXCB; i++) { 1907 if (txp[i].tx_mbuf != NULL) { 1908 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1909 BUS_DMASYNC_POSTWRITE); 1910 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1911 m_freem(txp[i].tx_mbuf); 1912 txp[i].tx_mbuf = NULL; 1913 /* clear this to reset csum offload bits */ 1914 txp[i].tx_cb->tbd[0].tb_addr = 0; 1915 } 1916 } 1917 } 1918 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1919 sc->tx_queued = 0; 1920 } 1921 1922 /* 1923 * Watchdog/transmission transmit timeout handler. Called when a 1924 * transmission is started on the interface, but no interrupt is 1925 * received before the timeout. This usually indicates that the 1926 * card has wedged for some reason. 1927 */ 1928 static void 1929 fxp_watchdog(struct ifnet *ifp) 1930 { 1931 struct fxp_softc *sc = ifp->if_softc; 1932 1933 FXP_LOCK(sc); 1934 device_printf(sc->dev, "device timeout\n"); 1935 ifp->if_oerrors++; 1936 1937 fxp_init_body(sc); 1938 FXP_UNLOCK(sc); 1939 } 1940 1941 /* 1942 * Acquire locks and then call the real initialization function. This 1943 * is necessary because ether_ioctl() calls if_init() and this would 1944 * result in mutex recursion if the mutex was held. 1945 */ 1946 static void 1947 fxp_init(void *xsc) 1948 { 1949 struct fxp_softc *sc = xsc; 1950 1951 FXP_LOCK(sc); 1952 fxp_init_body(sc); 1953 FXP_UNLOCK(sc); 1954 } 1955 1956 /* 1957 * Perform device initialization. This routine must be called with the 1958 * softc lock held. 1959 */ 1960 static void 1961 fxp_init_body(struct fxp_softc *sc) 1962 { 1963 struct ifnet *ifp = &sc->sc_if; 1964 struct fxp_cb_config *cbp; 1965 struct fxp_cb_ias *cb_ias; 1966 struct fxp_cb_tx *tcbp; 1967 struct fxp_tx *txp; 1968 struct fxp_cb_mcs *mcsp; 1969 int i, prm, s; 1970 1971 mtx_assert(&sc->sc_mtx, MA_OWNED); 1972 s = splimp(); 1973 /* 1974 * Cancel any pending I/O 1975 */ 1976 fxp_stop(sc); 1977 1978 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1979 1980 /* 1981 * Initialize base of CBL and RFA memory. Loading with zero 1982 * sets it up for regular linear addressing. 1983 */ 1984 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1985 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1986 1987 fxp_scb_wait(sc); 1988 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1989 1990 /* 1991 * Initialize base of dump-stats buffer. 1992 */ 1993 fxp_scb_wait(sc); 1994 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1995 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1996 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1997 1998 /* 1999 * Attempt to load microcode if requested. 2000 */ 2001 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2002 fxp_load_ucode(sc); 2003 2004 /* 2005 * Initialize the multicast address list. 2006 */ 2007 if (fxp_mc_addrs(sc)) { 2008 mcsp = sc->mcsp; 2009 mcsp->cb_status = 0; 2010 mcsp->cb_command = 2011 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2012 mcsp->link_addr = 0xffffffff; 2013 /* 2014 * Start the multicast setup command. 2015 */ 2016 fxp_scb_wait(sc); 2017 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2018 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2019 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2020 /* ...and wait for it to complete. */ 2021 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2022 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2023 BUS_DMASYNC_POSTWRITE); 2024 } 2025 2026 /* 2027 * We temporarily use memory that contains the TxCB list to 2028 * construct the config CB. The TxCB list memory is rebuilt 2029 * later. 2030 */ 2031 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2032 2033 /* 2034 * This bcopy is kind of disgusting, but there are a bunch of must be 2035 * zero and must be one bits in this structure and this is the easiest 2036 * way to initialize them all to proper values. 2037 */ 2038 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2039 2040 cbp->cb_status = 0; 2041 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2042 FXP_CB_COMMAND_EL); 2043 cbp->link_addr = 0xffffffff; /* (no) next command */ 2044 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2045 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2046 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2047 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2048 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2049 cbp->type_enable = 0; /* actually reserved */ 2050 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2051 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2052 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2053 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2054 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2055 cbp->late_scb = 0; /* (don't) defer SCB update */ 2056 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2057 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2058 cbp->ci_int = 1; /* interrupt on CU idle */ 2059 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2060 cbp->ext_stats_dis = 1; /* disable extended counters */ 2061 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2062 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2063 cbp->disc_short_rx = !prm; /* discard short packets */ 2064 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2065 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2066 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2067 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2068 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2069 cbp->csma_dis = 0; /* (don't) disable link */ 2070 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2071 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2072 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2073 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2074 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2075 cbp->nsai = 1; /* (don't) disable source addr insert */ 2076 cbp->preamble_length = 2; /* (7 byte) preamble */ 2077 cbp->loopback = 0; /* (don't) loopback */ 2078 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2079 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2080 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2081 cbp->promiscuous = prm; /* promiscuous mode */ 2082 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2083 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2084 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2085 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2086 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2087 2088 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2089 cbp->padding = 1; /* (do) pad short tx packets */ 2090 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2091 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2092 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2093 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2094 /* must set wake_en in PMCSR also */ 2095 cbp->force_fdx = 0; /* (don't) force full duplex */ 2096 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2097 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2098 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2099 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2100 2101 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2102 /* 2103 * The 82557 has no hardware flow control, the values 2104 * below are the defaults for the chip. 2105 */ 2106 cbp->fc_delay_lsb = 0; 2107 cbp->fc_delay_msb = 0x40; 2108 cbp->pri_fc_thresh = 3; 2109 cbp->tx_fc_dis = 0; 2110 cbp->rx_fc_restop = 0; 2111 cbp->rx_fc_restart = 0; 2112 cbp->fc_filter = 0; 2113 cbp->pri_fc_loc = 1; 2114 } else { 2115 cbp->fc_delay_lsb = 0x1f; 2116 cbp->fc_delay_msb = 0x01; 2117 cbp->pri_fc_thresh = 3; 2118 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2119 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2120 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2121 cbp->fc_filter = !prm; /* drop FC frames to host */ 2122 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2123 } 2124 2125 /* 2126 * Start the config command/DMA. 2127 */ 2128 fxp_scb_wait(sc); 2129 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2130 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2131 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2132 /* ...and wait for it to complete. */ 2133 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2134 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2135 2136 /* 2137 * Now initialize the station address. Temporarily use the TxCB 2138 * memory area like we did above for the config CB. 2139 */ 2140 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2141 cb_ias->cb_status = 0; 2142 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2143 cb_ias->link_addr = 0xffffffff; 2144 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2145 sizeof(sc->arpcom.ac_enaddr)); 2146 2147 /* 2148 * Start the IAS (Individual Address Setup) command/DMA. 2149 */ 2150 fxp_scb_wait(sc); 2151 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2152 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2153 /* ...and wait for it to complete. */ 2154 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2155 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2156 2157 /* 2158 * Initialize transmit control block (TxCB) list. 2159 */ 2160 txp = sc->fxp_desc.tx_list; 2161 tcbp = sc->fxp_desc.cbl_list; 2162 bzero(tcbp, FXP_TXCB_SZ); 2163 for (i = 0; i < FXP_NTXCB; i++) { 2164 txp[i].tx_cb = tcbp + i; 2165 txp[i].tx_mbuf = NULL; 2166 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2167 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2168 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2169 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2170 if (sc->flags & FXP_FLAG_EXT_TXCB) 2171 tcbp[i].tbd_array_addr = 2172 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2173 else 2174 tcbp[i].tbd_array_addr = 2175 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2176 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2177 } 2178 /* 2179 * Set the suspend flag on the first TxCB and start the control 2180 * unit. It will execute the NOP and then suspend. 2181 */ 2182 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2183 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2184 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2185 sc->tx_queued = 1; 2186 2187 fxp_scb_wait(sc); 2188 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2189 2190 /* 2191 * Initialize receiver buffer area - RFA. 2192 */ 2193 fxp_scb_wait(sc); 2194 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2195 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2196 2197 /* 2198 * Set current media. 2199 */ 2200 if (sc->miibus != NULL) 2201 mii_mediachg(device_get_softc(sc->miibus)); 2202 2203 ifp->if_flags |= IFF_RUNNING; 2204 ifp->if_flags &= ~IFF_OACTIVE; 2205 2206 /* 2207 * Enable interrupts. 2208 */ 2209 #ifdef DEVICE_POLLING 2210 /* 2211 * ... but only do that if we are not polling. And because (presumably) 2212 * the default is interrupts on, we need to disable them explicitly! 2213 */ 2214 if ( ifp->if_flags & IFF_POLLING ) 2215 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2216 else 2217 #endif /* DEVICE_POLLING */ 2218 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2219 2220 /* 2221 * Start stats updater. 2222 */ 2223 sc->stat_ch = timeout(fxp_tick, sc, hz); 2224 splx(s); 2225 } 2226 2227 static int 2228 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2229 { 2230 2231 return (0); 2232 } 2233 2234 static void 2235 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2236 { 2237 2238 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2239 } 2240 2241 /* 2242 * Change media according to request. 2243 */ 2244 static int 2245 fxp_ifmedia_upd(struct ifnet *ifp) 2246 { 2247 struct fxp_softc *sc = ifp->if_softc; 2248 struct mii_data *mii; 2249 2250 mii = device_get_softc(sc->miibus); 2251 mii_mediachg(mii); 2252 return (0); 2253 } 2254 2255 /* 2256 * Notify the world which media we're using. 2257 */ 2258 static void 2259 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2260 { 2261 struct fxp_softc *sc = ifp->if_softc; 2262 struct mii_data *mii; 2263 2264 mii = device_get_softc(sc->miibus); 2265 mii_pollstat(mii); 2266 ifmr->ifm_active = mii->mii_media_active; 2267 ifmr->ifm_status = mii->mii_media_status; 2268 2269 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2270 sc->cu_resume_bug = 1; 2271 else 2272 sc->cu_resume_bug = 0; 2273 } 2274 2275 /* 2276 * Add a buffer to the end of the RFA buffer list. 2277 * Return 0 if successful, 1 for failure. A failure results in 2278 * adding the 'oldm' (if non-NULL) on to the end of the list - 2279 * tossing out its old contents and recycling it. 2280 * The RFA struct is stuck at the beginning of mbuf cluster and the 2281 * data pointer is fixed up to point just past it. 2282 */ 2283 static int 2284 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2285 { 2286 struct mbuf *m; 2287 struct fxp_rfa *rfa, *p_rfa; 2288 struct fxp_rx *p_rx; 2289 bus_dmamap_t tmp_map; 2290 int error; 2291 2292 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2293 if (m == NULL) 2294 return (ENOBUFS); 2295 2296 /* 2297 * Move the data pointer up so that the incoming data packet 2298 * will be 32-bit aligned. 2299 */ 2300 m->m_data += RFA_ALIGNMENT_FUDGE; 2301 2302 /* 2303 * Get a pointer to the base of the mbuf cluster and move 2304 * data start past it. 2305 */ 2306 rfa = mtod(m, struct fxp_rfa *); 2307 m->m_data += sc->rfa_size; 2308 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2309 2310 /* 2311 * Initialize the rest of the RFA. Note that since the RFA 2312 * is misaligned, we cannot store values directly. Instead, 2313 * we use an optimized, inline copy. 2314 */ 2315 2316 rfa->rfa_status = 0; 2317 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2318 rfa->actual_size = 0; 2319 2320 le32enc(&rfa->link_addr, 0xffffffff); 2321 le32enc(&rfa->rbd_addr, 0xffffffff); 2322 2323 /* Map the RFA into DMA memory. */ 2324 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2325 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2326 &rxp->rx_addr, 0); 2327 if (error) { 2328 m_freem(m); 2329 return (error); 2330 } 2331 2332 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2333 tmp_map = sc->spare_map; 2334 sc->spare_map = rxp->rx_map; 2335 rxp->rx_map = tmp_map; 2336 rxp->rx_mbuf = m; 2337 2338 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2339 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2340 2341 /* 2342 * If there are other buffers already on the list, attach this 2343 * one to the end by fixing up the tail to point to this one. 2344 */ 2345 if (sc->fxp_desc.rx_head != NULL) { 2346 p_rx = sc->fxp_desc.rx_tail; 2347 p_rfa = (struct fxp_rfa *) 2348 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2349 p_rx->rx_next = rxp; 2350 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2351 p_rfa->rfa_control = 0; 2352 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2353 BUS_DMASYNC_PREWRITE); 2354 } else { 2355 rxp->rx_next = NULL; 2356 sc->fxp_desc.rx_head = rxp; 2357 } 2358 sc->fxp_desc.rx_tail = rxp; 2359 return (0); 2360 } 2361 2362 static volatile int 2363 fxp_miibus_readreg(device_t dev, int phy, int reg) 2364 { 2365 struct fxp_softc *sc = device_get_softc(dev); 2366 int count = 10000; 2367 int value; 2368 2369 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2370 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2371 2372 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2373 && count--) 2374 DELAY(10); 2375 2376 if (count <= 0) 2377 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2378 2379 return (value & 0xffff); 2380 } 2381 2382 static void 2383 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2384 { 2385 struct fxp_softc *sc = device_get_softc(dev); 2386 int count = 10000; 2387 2388 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2389 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2390 (value & 0xffff)); 2391 2392 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2393 count--) 2394 DELAY(10); 2395 2396 if (count <= 0) 2397 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2398 } 2399 2400 static int 2401 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2402 { 2403 struct fxp_softc *sc = ifp->if_softc; 2404 struct ifreq *ifr = (struct ifreq *)data; 2405 struct mii_data *mii; 2406 int s, error = 0; 2407 2408 /* 2409 * Detaching causes us to call ioctl with the mutex owned. Preclude 2410 * that by saying we're busy if the lock is already held. 2411 */ 2412 if (mtx_owned(&sc->sc_mtx)) 2413 return (EBUSY); 2414 2415 FXP_LOCK(sc); 2416 s = splimp(); 2417 2418 switch (command) { 2419 case SIOCSIFFLAGS: 2420 if (ifp->if_flags & IFF_ALLMULTI) 2421 sc->flags |= FXP_FLAG_ALL_MCAST; 2422 else 2423 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2424 2425 /* 2426 * If interface is marked up and not running, then start it. 2427 * If it is marked down and running, stop it. 2428 * XXX If it's up then re-initialize it. This is so flags 2429 * such as IFF_PROMISC are handled. 2430 */ 2431 if (ifp->if_flags & IFF_UP) { 2432 fxp_init_body(sc); 2433 } else { 2434 if (ifp->if_flags & IFF_RUNNING) 2435 fxp_stop(sc); 2436 } 2437 break; 2438 2439 case SIOCADDMULTI: 2440 case SIOCDELMULTI: 2441 if (ifp->if_flags & IFF_ALLMULTI) 2442 sc->flags |= FXP_FLAG_ALL_MCAST; 2443 else 2444 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2445 /* 2446 * Multicast list has changed; set the hardware filter 2447 * accordingly. 2448 */ 2449 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2450 fxp_mc_setup(sc); 2451 /* 2452 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2453 * again rather than else {}. 2454 */ 2455 if (sc->flags & FXP_FLAG_ALL_MCAST) 2456 fxp_init_body(sc); 2457 error = 0; 2458 break; 2459 2460 case SIOCSIFMEDIA: 2461 case SIOCGIFMEDIA: 2462 if (sc->miibus != NULL) { 2463 mii = device_get_softc(sc->miibus); 2464 error = ifmedia_ioctl(ifp, ifr, 2465 &mii->mii_media, command); 2466 } else { 2467 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2468 } 2469 break; 2470 2471 default: 2472 /* 2473 * ether_ioctl() will eventually call fxp_start() which 2474 * will result in mutex recursion so drop it first. 2475 */ 2476 FXP_UNLOCK(sc); 2477 error = ether_ioctl(ifp, command, data); 2478 } 2479 if (mtx_owned(&sc->sc_mtx)) 2480 FXP_UNLOCK(sc); 2481 splx(s); 2482 return (error); 2483 } 2484 2485 /* 2486 * Fill in the multicast address list and return number of entries. 2487 */ 2488 static int 2489 fxp_mc_addrs(struct fxp_softc *sc) 2490 { 2491 struct fxp_cb_mcs *mcsp = sc->mcsp; 2492 struct ifnet *ifp = &sc->sc_if; 2493 struct ifmultiaddr *ifma; 2494 int nmcasts; 2495 2496 nmcasts = 0; 2497 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2498 #if __FreeBSD_version < 500000 2499 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2500 #else 2501 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2502 #endif 2503 if (ifma->ifma_addr->sa_family != AF_LINK) 2504 continue; 2505 if (nmcasts >= MAXMCADDR) { 2506 sc->flags |= FXP_FLAG_ALL_MCAST; 2507 nmcasts = 0; 2508 break; 2509 } 2510 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2511 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2512 nmcasts++; 2513 } 2514 } 2515 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2516 return (nmcasts); 2517 } 2518 2519 /* 2520 * Program the multicast filter. 2521 * 2522 * We have an artificial restriction that the multicast setup command 2523 * must be the first command in the chain, so we take steps to ensure 2524 * this. By requiring this, it allows us to keep up the performance of 2525 * the pre-initialized command ring (esp. link pointers) by not actually 2526 * inserting the mcsetup command in the ring - i.e. its link pointer 2527 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2528 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2529 * lead into the regular TxCB ring when it completes. 2530 * 2531 * This function must be called at splimp. 2532 */ 2533 static void 2534 fxp_mc_setup(struct fxp_softc *sc) 2535 { 2536 struct fxp_cb_mcs *mcsp = sc->mcsp; 2537 struct ifnet *ifp = &sc->sc_if; 2538 struct fxp_tx *txp; 2539 int count; 2540 2541 /* 2542 * If there are queued commands, we must wait until they are all 2543 * completed. If we are already waiting, then add a NOP command 2544 * with interrupt option so that we're notified when all commands 2545 * have been completed - fxp_start() ensures that no additional 2546 * TX commands will be added when need_mcsetup is true. 2547 */ 2548 if (sc->tx_queued) { 2549 /* 2550 * need_mcsetup will be true if we are already waiting for the 2551 * NOP command to be completed (see below). In this case, bail. 2552 */ 2553 if (sc->need_mcsetup) 2554 return; 2555 sc->need_mcsetup = 1; 2556 2557 /* 2558 * Add a NOP command with interrupt so that we are notified 2559 * when all TX commands have been processed. 2560 */ 2561 txp = sc->fxp_desc.tx_last->tx_next; 2562 txp->tx_mbuf = NULL; 2563 txp->tx_cb->cb_status = 0; 2564 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2565 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2566 /* 2567 * Advance the end of list forward. 2568 */ 2569 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2570 htole16(~FXP_CB_COMMAND_S); 2571 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2572 sc->fxp_desc.tx_last = txp; 2573 sc->tx_queued++; 2574 /* 2575 * Issue a resume in case the CU has just suspended. 2576 */ 2577 fxp_scb_wait(sc); 2578 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2579 /* 2580 * Set a 5 second timer just in case we don't hear from the 2581 * card again. 2582 */ 2583 ifp->if_timer = 5; 2584 2585 return; 2586 } 2587 sc->need_mcsetup = 0; 2588 2589 /* 2590 * Initialize multicast setup descriptor. 2591 */ 2592 mcsp->cb_status = 0; 2593 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2594 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2595 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2596 txp = &sc->fxp_desc.mcs_tx; 2597 txp->tx_mbuf = NULL; 2598 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2599 txp->tx_next = sc->fxp_desc.tx_list; 2600 (void) fxp_mc_addrs(sc); 2601 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2602 sc->tx_queued = 1; 2603 2604 /* 2605 * Wait until command unit is not active. This should never 2606 * be the case when nothing is queued, but make sure anyway. 2607 */ 2608 count = 100; 2609 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2610 FXP_SCB_CUS_ACTIVE && --count) 2611 DELAY(10); 2612 if (count == 0) { 2613 device_printf(sc->dev, "command queue timeout\n"); 2614 return; 2615 } 2616 2617 /* 2618 * Start the multicast setup command. 2619 */ 2620 fxp_scb_wait(sc); 2621 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2622 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2623 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2624 2625 ifp->if_timer = 2; 2626 return; 2627 } 2628 2629 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2630 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2631 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2632 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2633 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2634 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2635 2636 #define UCODE(x) x, sizeof(x) 2637 2638 struct ucode { 2639 u_int32_t revision; 2640 u_int32_t *ucode; 2641 int length; 2642 u_short int_delay_offset; 2643 u_short bundle_max_offset; 2644 } ucode_table[] = { 2645 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2646 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2647 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2648 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2649 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2650 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2651 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2652 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2653 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2654 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2655 { 0, NULL, 0, 0, 0 } 2656 }; 2657 2658 static void 2659 fxp_load_ucode(struct fxp_softc *sc) 2660 { 2661 struct ucode *uc; 2662 struct fxp_cb_ucode *cbp; 2663 2664 for (uc = ucode_table; uc->ucode != NULL; uc++) 2665 if (sc->revision == uc->revision) 2666 break; 2667 if (uc->ucode == NULL) 2668 return; 2669 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2670 cbp->cb_status = 0; 2671 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2672 cbp->link_addr = 0xffffffff; /* (no) next command */ 2673 memcpy(cbp->ucode, uc->ucode, uc->length); 2674 if (uc->int_delay_offset) 2675 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2676 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2677 if (uc->bundle_max_offset) 2678 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2679 htole16(sc->tunable_bundle_max); 2680 /* 2681 * Download the ucode to the chip. 2682 */ 2683 fxp_scb_wait(sc); 2684 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2685 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2686 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2687 /* ...and wait for it to complete. */ 2688 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2689 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2690 device_printf(sc->dev, 2691 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2692 sc->tunable_int_delay, 2693 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2694 sc->flags |= FXP_FLAG_UCODE; 2695 } 2696 2697 static int 2698 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2699 { 2700 int error, value; 2701 2702 value = *(int *)arg1; 2703 error = sysctl_handle_int(oidp, &value, 0, req); 2704 if (error || !req->newptr) 2705 return (error); 2706 if (value < low || value > high) 2707 return (EINVAL); 2708 *(int *)arg1 = value; 2709 return (0); 2710 } 2711 2712 /* 2713 * Interrupt delay is expressed in microseconds, a multiplier is used 2714 * to convert this to the appropriate clock ticks before using. 2715 */ 2716 static int 2717 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2718 { 2719 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2720 } 2721 2722 static int 2723 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2724 { 2725 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2726 } 2727