1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 #include <sys/sockio.h> 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 57 #include <net/ethernet.h> 58 #include <net/if_arp.h> 59 60 #include <machine/clock.h> /* for DELAY */ 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #ifdef FXP_IP_CSUM_WAR 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <machine/in_cksum.h> 70 #endif 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 u_int16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145 }; 146 147 /* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153 static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 172 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 190 { 0, -1, NULL }, 191 }; 192 193 #ifdef FXP_IP_CSUM_WAR 194 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 195 #else 196 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 197 #endif 198 199 static int fxp_probe(device_t dev); 200 static int fxp_attach(device_t dev); 201 static int fxp_detach(device_t dev); 202 static int fxp_shutdown(device_t dev); 203 static int fxp_suspend(device_t dev); 204 static int fxp_resume(device_t dev); 205 206 static void fxp_intr(void *xsc); 207 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 208 u_int8_t statack, int count); 209 static void fxp_init(void *xsc); 210 static void fxp_init_body(struct fxp_softc *sc); 211 static void fxp_tick(void *xsc); 212 #ifndef BURN_BRIDGES 213 static void fxp_powerstate_d0(device_t dev); 214 #endif 215 static void fxp_start(struct ifnet *ifp); 216 static void fxp_start_body(struct ifnet *ifp); 217 static void fxp_stop(struct fxp_softc *sc); 218 static void fxp_release(struct fxp_softc *sc); 219 static int fxp_ioctl(struct ifnet *ifp, u_long command, 220 caddr_t data); 221 static void fxp_watchdog(struct ifnet *ifp); 222 static int fxp_add_rfabuf(struct fxp_softc *sc, 223 struct fxp_rx *rxp); 224 static int fxp_mc_addrs(struct fxp_softc *sc); 225 static void fxp_mc_setup(struct fxp_softc *sc); 226 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 227 int autosize); 228 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 229 u_int16_t data); 230 static void fxp_autosize_eeprom(struct fxp_softc *sc); 231 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 232 int offset, int words); 233 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235 static int fxp_ifmedia_upd(struct ifnet *ifp); 236 static void fxp_ifmedia_sts(struct ifnet *ifp, 237 struct ifmediareq *ifmr); 238 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 239 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 240 struct ifmediareq *ifmr); 241 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 242 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 243 int value); 244 static void fxp_load_ucode(struct fxp_softc *sc); 245 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 246 int low, int high); 247 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 248 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 249 static void fxp_scb_wait(struct fxp_softc *sc); 250 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 251 static void fxp_dma_wait(struct fxp_softc *sc, 252 volatile u_int16_t *status, bus_dma_tag_t dmat, 253 bus_dmamap_t map); 254 255 static device_method_t fxp_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, fxp_probe), 258 DEVMETHOD(device_attach, fxp_attach), 259 DEVMETHOD(device_detach, fxp_detach), 260 DEVMETHOD(device_shutdown, fxp_shutdown), 261 DEVMETHOD(device_suspend, fxp_suspend), 262 DEVMETHOD(device_resume, fxp_resume), 263 264 /* MII interface */ 265 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 266 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 267 268 { 0, 0 } 269 }; 270 271 static driver_t fxp_driver = { 272 "fxp", 273 fxp_methods, 274 sizeof(struct fxp_softc), 275 }; 276 277 static devclass_t fxp_devclass; 278 279 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 280 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 281 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 282 283 static int fxp_rnr; 284 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 285 286 static int fxp_noflow; 287 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 288 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 289 290 /* 291 * Wait for the previous command to be accepted (but not necessarily 292 * completed). 293 */ 294 static void 295 fxp_scb_wait(struct fxp_softc *sc) 296 { 297 int i = 10000; 298 299 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 300 DELAY(2); 301 if (i == 0) 302 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 303 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 304 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 305 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 306 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 307 } 308 309 static void 310 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 311 { 312 313 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 314 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 315 fxp_scb_wait(sc); 316 } 317 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 318 } 319 320 static void 321 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 322 bus_dma_tag_t dmat, bus_dmamap_t map) 323 { 324 int i = 10000; 325 326 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 327 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 328 DELAY(2); 329 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 330 } 331 if (i == 0) 332 device_printf(sc->dev, "DMA timeout\n"); 333 } 334 335 /* 336 * Return identification string if this device is ours. 337 */ 338 static int 339 fxp_probe(device_t dev) 340 { 341 u_int16_t devid; 342 u_int8_t revid; 343 struct fxp_ident *ident; 344 345 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 346 devid = pci_get_device(dev); 347 revid = pci_get_revid(dev); 348 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 349 if (ident->devid == devid && 350 (ident->revid == revid || ident->revid == -1)) { 351 device_set_desc(dev, ident->name); 352 return (0); 353 } 354 } 355 } 356 return (ENXIO); 357 } 358 359 #ifndef BURN_BRIDGES 360 static void 361 fxp_powerstate_d0(device_t dev) 362 { 363 #if __FreeBSD_version >= 430002 364 u_int32_t iobase, membase, irq; 365 366 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 367 /* Save important PCI config data. */ 368 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 369 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 370 irq = pci_read_config(dev, PCIR_INTLINE, 4); 371 372 /* Reset the power state. */ 373 device_printf(dev, "chip is in D%d power mode " 374 "-- setting to D0\n", pci_get_powerstate(dev)); 375 376 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 377 378 /* Restore PCI config data. */ 379 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 380 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 381 pci_write_config(dev, PCIR_INTLINE, irq, 4); 382 } 383 #endif 384 } 385 #endif 386 387 static void 388 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 389 { 390 u_int32_t *addr; 391 392 if (error) 393 return; 394 395 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 396 addr = arg; 397 *addr = segs->ds_addr; 398 } 399 400 static int 401 fxp_attach(device_t dev) 402 { 403 int error = 0; 404 struct fxp_softc *sc = device_get_softc(dev); 405 struct ifnet *ifp; 406 struct fxp_rx *rxp; 407 u_int32_t val; 408 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 409 int i, rid, m1, m2, prefer_iomap, maxtxseg; 410 int s, ipcbxmit_disable; 411 412 sc->dev = dev; 413 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 414 sysctl_ctx_init(&sc->sysctl_ctx); 415 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 416 MTX_DEF); 417 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 418 fxp_serial_ifmedia_sts); 419 420 s = splimp(); 421 422 /* 423 * Enable bus mastering. 424 */ 425 pci_enable_busmaster(dev); 426 val = pci_read_config(dev, PCIR_COMMAND, 2); 427 #ifndef BURN_BRIDGES 428 fxp_powerstate_d0(dev); 429 #endif 430 /* 431 * Figure out which we should try first - memory mapping or i/o mapping? 432 * We default to memory mapping. Then we accept an override from the 433 * command line. Then we check to see which one is enabled. 434 */ 435 m1 = PCIM_CMD_MEMEN; 436 m2 = PCIM_CMD_PORTEN; 437 prefer_iomap = 0; 438 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 439 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 440 m1 = PCIM_CMD_PORTEN; 441 m2 = PCIM_CMD_MEMEN; 442 } 443 444 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 445 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 446 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 447 if (sc->mem == NULL) { 448 sc->rtp = 449 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 450 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 451 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 452 RF_ACTIVE); 453 } 454 455 if (!sc->mem) { 456 error = ENXIO; 457 goto fail; 458 } 459 if (bootverbose) { 460 device_printf(dev, "using %s space register mapping\n", 461 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 462 } 463 464 sc->sc_st = rman_get_bustag(sc->mem); 465 sc->sc_sh = rman_get_bushandle(sc->mem); 466 467 /* 468 * Allocate our interrupt. 469 */ 470 rid = 0; 471 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 472 RF_SHAREABLE | RF_ACTIVE); 473 if (sc->irq == NULL) { 474 device_printf(dev, "could not map interrupt\n"); 475 error = ENXIO; 476 goto fail; 477 } 478 479 /* 480 * Reset to a stable state. 481 */ 482 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 483 DELAY(10); 484 485 /* 486 * Find out how large of an SEEPROM we have. 487 */ 488 fxp_autosize_eeprom(sc); 489 490 /* 491 * Determine whether we must use the 503 serial interface. 492 */ 493 fxp_read_eeprom(sc, &data, 6, 1); 494 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 495 (data & FXP_PHY_SERIAL_ONLY)) 496 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 497 498 /* 499 * Create the sysctl tree 500 */ 501 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 502 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 503 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 504 if (sc->sysctl_tree == NULL) { 505 error = ENXIO; 506 goto fail; 507 } 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 510 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 511 "FXP driver receive interrupt microcode bundling delay"); 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 515 "FXP driver receive interrupt microcode bundle size limit"); 516 517 /* 518 * Pull in device tunables. 519 */ 520 sc->tunable_int_delay = TUNABLE_INT_DELAY; 521 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 522 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 523 "int_delay", &sc->tunable_int_delay); 524 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 525 "bundle_max", &sc->tunable_bundle_max); 526 527 /* 528 * Find out the chip revision; lump all 82557 revs together. 529 */ 530 fxp_read_eeprom(sc, &data, 5, 1); 531 if ((data >> 8) == 1) 532 sc->revision = FXP_REV_82557; 533 else 534 sc->revision = pci_get_revid(dev); 535 536 /* 537 * Enable workarounds for certain chip revision deficiencies. 538 * 539 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 540 * some systems based a normal 82559 design, have a defect where 541 * the chip can cause a PCI protocol violation if it receives 542 * a CU_RESUME command when it is entering the IDLE state. The 543 * workaround is to disable Dynamic Standby Mode, so the chip never 544 * deasserts CLKRUN#, and always remains in an active state. 545 * 546 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 547 */ 548 i = pci_get_device(dev); 549 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 550 sc->revision >= FXP_REV_82559_A0) { 551 fxp_read_eeprom(sc, &data, 10, 1); 552 if (data & 0x02) { /* STB enable */ 553 u_int16_t cksum; 554 int i; 555 556 device_printf(dev, 557 "Disabling dynamic standby mode in EEPROM\n"); 558 data &= ~0x02; 559 fxp_write_eeprom(sc, &data, 10, 1); 560 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 561 cksum = 0; 562 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 563 fxp_read_eeprom(sc, &data, i, 1); 564 cksum += data; 565 } 566 i = (1 << sc->eeprom_size) - 1; 567 cksum = 0xBABA - cksum; 568 fxp_read_eeprom(sc, &data, i, 1); 569 fxp_write_eeprom(sc, &cksum, i, 1); 570 device_printf(dev, 571 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 572 i, data, cksum); 573 #if 1 574 /* 575 * If the user elects to continue, try the software 576 * workaround, as it is better than nothing. 577 */ 578 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 579 #endif 580 } 581 } 582 583 /* 584 * If we are not a 82557 chip, we can enable extended features. 585 */ 586 if (sc->revision != FXP_REV_82557) { 587 /* 588 * If MWI is enabled in the PCI configuration, and there 589 * is a valid cacheline size (8 or 16 dwords), then tell 590 * the board to turn on MWI. 591 */ 592 if (val & PCIM_CMD_MWRICEN && 593 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 594 sc->flags |= FXP_FLAG_MWI_ENABLE; 595 596 /* turn on the extended TxCB feature */ 597 sc->flags |= FXP_FLAG_EXT_TXCB; 598 } 599 600 /* 601 * Enable use of extended RFDs and TCBs for 82550 602 * and later chips. Note: we need extended TXCB support 603 * too, but that's already enabled by the code above. 604 * Be careful to do this only on the right devices. 605 * 606 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 607 * truncate packets that end with an mbuf containing 1 to 3 bytes 608 * when used with this feature enabled in the previous version of the 609 * driver. This problem appears to be fixed now that the driver 610 * always sets the hardware parse bit in the IPCB structure, which 611 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 612 * Source Software Developer Manual" says is necessary in the 613 * cases where packet truncation was observed. 614 * 615 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 616 * allows this feature to be disabled at boot time. 617 * 618 * If fxp is not compiled into the kernel, this feature may also 619 * be disabled at run time: 620 * # kldunload fxp 621 * # kenv hint.fxp.0.ipcbxmit_disable=1 622 * # kldload fxp 623 */ 624 625 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 626 &ipcbxmit_disable) != 0) 627 ipcbxmit_disable = 0; 628 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 629 sc->revision == FXP_REV_82550_C)) { 630 sc->rfa_size = sizeof (struct fxp_rfa); 631 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 632 sc->flags |= FXP_FLAG_EXT_RFA; 633 } else { 634 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 635 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 636 } 637 638 /* 639 * Allocate DMA tags and DMA safe memory. 640 */ 641 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 642 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 643 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 644 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 645 if (error) { 646 device_printf(dev, "could not allocate dma tag\n"); 647 goto fail; 648 } 649 650 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 651 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 652 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 653 &sc->fxp_stag); 654 if (error) { 655 device_printf(dev, "could not allocate dma tag\n"); 656 goto fail; 657 } 658 659 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 660 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 661 if (error) 662 goto fail; 663 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 664 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 665 if (error) { 666 device_printf(dev, "could not map the stats buffer\n"); 667 goto fail; 668 } 669 670 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 671 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 672 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 673 if (error) { 674 device_printf(dev, "could not allocate dma tag\n"); 675 goto fail; 676 } 677 678 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 679 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 680 if (error) 681 goto fail; 682 683 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 684 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 685 &sc->fxp_desc.cbl_addr, 0); 686 if (error) { 687 device_printf(dev, "could not map DMA memory\n"); 688 goto fail; 689 } 690 691 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 692 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 693 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 694 &sc->mcs_tag); 695 if (error) { 696 device_printf(dev, "could not allocate dma tag\n"); 697 goto fail; 698 } 699 700 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 701 BUS_DMA_NOWAIT, &sc->mcs_map); 702 if (error) 703 goto fail; 704 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 705 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 706 if (error) { 707 device_printf(dev, "can't map the multicast setup command\n"); 708 goto fail; 709 } 710 711 /* 712 * Pre-allocate the TX DMA maps. 713 */ 714 for (i = 0; i < FXP_NTXCB; i++) { 715 error = bus_dmamap_create(sc->fxp_mtag, 0, 716 &sc->fxp_desc.tx_list[i].tx_map); 717 if (error) { 718 device_printf(dev, "can't create DMA map for TX\n"); 719 goto fail; 720 } 721 } 722 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 723 if (error) { 724 device_printf(dev, "can't create spare DMA map\n"); 725 goto fail; 726 } 727 728 /* 729 * Pre-allocate our receive buffers. 730 */ 731 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 732 for (i = 0; i < FXP_NRFABUFS; i++) { 733 rxp = &sc->fxp_desc.rx_list[i]; 734 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 735 if (error) { 736 device_printf(dev, "can't create DMA map for RX\n"); 737 goto fail; 738 } 739 if (fxp_add_rfabuf(sc, rxp) != 0) { 740 error = ENOMEM; 741 goto fail; 742 } 743 } 744 745 /* 746 * Read MAC address. 747 */ 748 fxp_read_eeprom(sc, myea, 0, 3); 749 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 750 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 751 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 752 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 753 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 754 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 755 if (bootverbose) { 756 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 757 pci_get_vendor(dev), pci_get_device(dev), 758 pci_get_subvendor(dev), pci_get_subdevice(dev), 759 pci_get_revid(dev)); 760 fxp_read_eeprom(sc, &data, 10, 1); 761 device_printf(dev, "Dynamic Standby mode is %s\n", 762 data & 0x02 ? "enabled" : "disabled"); 763 } 764 765 /* 766 * If this is only a 10Mbps device, then there is no MII, and 767 * the PHY will use a serial interface instead. 768 * 769 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 770 * doesn't have a programming interface of any sort. The 771 * media is sensed automatically based on how the link partner 772 * is configured. This is, in essence, manual configuration. 773 */ 774 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 775 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 776 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 777 } else { 778 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 779 fxp_ifmedia_sts)) { 780 device_printf(dev, "MII without any PHY!\n"); 781 error = ENXIO; 782 goto fail; 783 } 784 } 785 786 ifp = &sc->arpcom.ac_if; 787 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 788 ifp->if_baudrate = 100000000; 789 ifp->if_init = fxp_init; 790 ifp->if_softc = sc; 791 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 792 ifp->if_ioctl = fxp_ioctl; 793 ifp->if_start = fxp_start; 794 ifp->if_watchdog = fxp_watchdog; 795 796 ifp->if_capabilities = ifp->if_capenable = 0; 797 798 /* Enable checksum offload for 82550 or better chips */ 799 if (sc->flags & FXP_FLAG_EXT_RFA) { 800 ifp->if_hwassist = FXP_CSUM_FEATURES; 801 ifp->if_capabilities |= IFCAP_HWCSUM; 802 ifp->if_capenable |= IFCAP_HWCSUM; 803 } 804 805 #ifdef DEVICE_POLLING 806 /* Inform the world we support polling. */ 807 ifp->if_capabilities |= IFCAP_POLLING; 808 ifp->if_capenable |= IFCAP_POLLING; 809 #endif 810 811 /* 812 * Attach the interface. 813 */ 814 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 815 816 /* 817 * Tell the upper layer(s) we support long frames. 818 * Must appear after the call to ether_ifattach() because 819 * ether_ifattach() sets ifi_hdrlen to the default value. 820 */ 821 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 822 ifp->if_capabilities |= IFCAP_VLAN_MTU; 823 /* this driver lets vlan(4) control the bit in if_capenable via ioctl */ 824 825 /* 826 * Let the system queue as many packets as we have available 827 * TX descriptors. 828 */ 829 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 830 831 /* 832 * Hook our interrupt after all initialization is complete. 833 * XXX This driver has been tested with the INTR_MPSAFFE flag set 834 * however, ifp and its functions are not fully locked so MPSAFE 835 * should not be used unless you can handle potential data loss. 836 */ 837 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 838 fxp_intr, sc, &sc->ih); 839 if (error) { 840 device_printf(dev, "could not setup irq\n"); 841 ether_ifdetach(&sc->arpcom.ac_if); 842 goto fail; 843 } 844 845 fail: 846 splx(s); 847 if (error) 848 fxp_release(sc); 849 return (error); 850 } 851 852 /* 853 * Release all resources. The softc lock should not be held and the 854 * interrupt should already be torn down. 855 */ 856 static void 857 fxp_release(struct fxp_softc *sc) 858 { 859 struct fxp_rx *rxp; 860 struct fxp_tx *txp; 861 int i; 862 863 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 864 KASSERT(sc->ih == NULL, 865 ("fxp_release() called with intr handle still active")); 866 if (sc->miibus) 867 device_delete_child(sc->dev, sc->miibus); 868 bus_generic_detach(sc->dev); 869 ifmedia_removeall(&sc->sc_media); 870 if (sc->fxp_desc.cbl_list) { 871 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 872 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 873 sc->cbl_map); 874 } 875 if (sc->fxp_stats) { 876 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 877 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 878 } 879 if (sc->mcsp) { 880 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 881 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 882 } 883 if (sc->irq) 884 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 885 if (sc->mem) 886 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 887 if (sc->fxp_mtag) { 888 for (i = 0; i < FXP_NRFABUFS; i++) { 889 rxp = &sc->fxp_desc.rx_list[i]; 890 if (rxp->rx_mbuf != NULL) { 891 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 892 BUS_DMASYNC_POSTREAD); 893 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 894 m_freem(rxp->rx_mbuf); 895 } 896 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 897 } 898 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 899 bus_dma_tag_destroy(sc->fxp_mtag); 900 } 901 if (sc->fxp_stag) { 902 for (i = 0; i < FXP_NTXCB; i++) { 903 txp = &sc->fxp_desc.tx_list[i]; 904 if (txp->tx_mbuf != NULL) { 905 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 906 BUS_DMASYNC_POSTWRITE); 907 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 908 m_freem(txp->tx_mbuf); 909 } 910 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 911 } 912 bus_dma_tag_destroy(sc->fxp_stag); 913 } 914 if (sc->cbl_tag) 915 bus_dma_tag_destroy(sc->cbl_tag); 916 if (sc->mcs_tag) 917 bus_dma_tag_destroy(sc->mcs_tag); 918 919 sysctl_ctx_free(&sc->sysctl_ctx); 920 921 mtx_destroy(&sc->sc_mtx); 922 } 923 924 /* 925 * Detach interface. 926 */ 927 static int 928 fxp_detach(device_t dev) 929 { 930 struct fxp_softc *sc = device_get_softc(dev); 931 int s; 932 933 FXP_LOCK(sc); 934 s = splimp(); 935 936 sc->suspended = 1; /* Do same thing as we do for suspend */ 937 /* 938 * Close down routes etc. 939 */ 940 ether_ifdetach(&sc->arpcom.ac_if); 941 942 /* 943 * Stop DMA and drop transmit queue, but disable interrupts first. 944 */ 945 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 946 fxp_stop(sc); 947 FXP_UNLOCK(sc); 948 949 /* 950 * Unhook interrupt before dropping lock. This is to prevent 951 * races with fxp_intr(). 952 */ 953 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 954 sc->ih = NULL; 955 956 splx(s); 957 958 /* Release our allocated resources. */ 959 fxp_release(sc); 960 return (0); 961 } 962 963 /* 964 * Device shutdown routine. Called at system shutdown after sync. The 965 * main purpose of this routine is to shut off receiver DMA so that 966 * kernel memory doesn't get clobbered during warmboot. 967 */ 968 static int 969 fxp_shutdown(device_t dev) 970 { 971 /* 972 * Make sure that DMA is disabled prior to reboot. Not doing 973 * do could allow DMA to corrupt kernel memory during the 974 * reboot before the driver initializes. 975 */ 976 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 977 return (0); 978 } 979 980 /* 981 * Device suspend routine. Stop the interface and save some PCI 982 * settings in case the BIOS doesn't restore them properly on 983 * resume. 984 */ 985 static int 986 fxp_suspend(device_t dev) 987 { 988 struct fxp_softc *sc = device_get_softc(dev); 989 int i, s; 990 991 FXP_LOCK(sc); 992 s = splimp(); 993 994 fxp_stop(sc); 995 996 for (i = 0; i < 5; i++) 997 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 998 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 999 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1000 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1001 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1002 1003 sc->suspended = 1; 1004 1005 FXP_UNLOCK(sc); 1006 splx(s); 1007 return (0); 1008 } 1009 1010 /* 1011 * Device resume routine. Restore some PCI settings in case the BIOS 1012 * doesn't, re-enable busmastering, and restart the interface if 1013 * appropriate. 1014 */ 1015 static int 1016 fxp_resume(device_t dev) 1017 { 1018 struct fxp_softc *sc = device_get_softc(dev); 1019 struct ifnet *ifp = &sc->sc_if; 1020 u_int16_t pci_command; 1021 int i, s; 1022 1023 FXP_LOCK(sc); 1024 s = splimp(); 1025 #ifndef BURN_BRIDGES 1026 fxp_powerstate_d0(dev); 1027 #endif 1028 /* better way to do this? */ 1029 for (i = 0; i < 5; i++) 1030 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1031 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1032 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1033 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1034 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1035 1036 /* reenable busmastering */ 1037 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1038 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1039 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1040 1041 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1042 DELAY(10); 1043 1044 /* reinitialize interface if necessary */ 1045 if (ifp->if_flags & IFF_UP) 1046 fxp_init_body(sc); 1047 1048 sc->suspended = 0; 1049 1050 FXP_UNLOCK(sc); 1051 splx(s); 1052 return (0); 1053 } 1054 1055 static void 1056 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1057 { 1058 u_int16_t reg; 1059 int x; 1060 1061 /* 1062 * Shift in data. 1063 */ 1064 for (x = 1 << (length - 1); x; x >>= 1) { 1065 if (data & x) 1066 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1067 else 1068 reg = FXP_EEPROM_EECS; 1069 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1070 DELAY(1); 1071 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1072 DELAY(1); 1073 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1074 DELAY(1); 1075 } 1076 } 1077 1078 /* 1079 * Read from the serial EEPROM. Basically, you manually shift in 1080 * the read opcode (one bit at a time) and then shift in the address, 1081 * and then you shift out the data (all of this one bit at a time). 1082 * The word size is 16 bits, so you have to provide the address for 1083 * every 16 bits of data. 1084 */ 1085 static u_int16_t 1086 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1087 { 1088 u_int16_t reg, data; 1089 int x; 1090 1091 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1092 /* 1093 * Shift in read opcode. 1094 */ 1095 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1096 /* 1097 * Shift in address. 1098 */ 1099 data = 0; 1100 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1101 if (offset & x) 1102 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1103 else 1104 reg = FXP_EEPROM_EECS; 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1106 DELAY(1); 1107 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1108 DELAY(1); 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1110 DELAY(1); 1111 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1112 data++; 1113 if (autosize && reg == 0) { 1114 sc->eeprom_size = data; 1115 break; 1116 } 1117 } 1118 /* 1119 * Shift out data. 1120 */ 1121 data = 0; 1122 reg = FXP_EEPROM_EECS; 1123 for (x = 1 << 15; x; x >>= 1) { 1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1125 DELAY(1); 1126 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1127 data |= x; 1128 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1129 DELAY(1); 1130 } 1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1132 DELAY(1); 1133 1134 return (data); 1135 } 1136 1137 static void 1138 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1139 { 1140 int i; 1141 1142 /* 1143 * Erase/write enable. 1144 */ 1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1146 fxp_eeprom_shiftin(sc, 0x4, 3); 1147 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1149 DELAY(1); 1150 /* 1151 * Shift in write opcode, address, data. 1152 */ 1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1154 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1155 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1156 fxp_eeprom_shiftin(sc, data, 16); 1157 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1158 DELAY(1); 1159 /* 1160 * Wait for EEPROM to finish up. 1161 */ 1162 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1163 DELAY(1); 1164 for (i = 0; i < 1000; i++) { 1165 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1166 break; 1167 DELAY(50); 1168 } 1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1170 DELAY(1); 1171 /* 1172 * Erase/write disable. 1173 */ 1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1175 fxp_eeprom_shiftin(sc, 0x4, 3); 1176 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1178 DELAY(1); 1179 } 1180 1181 /* 1182 * From NetBSD: 1183 * 1184 * Figure out EEPROM size. 1185 * 1186 * 559's can have either 64-word or 256-word EEPROMs, the 558 1187 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1188 * talks about the existance of 16 to 256 word EEPROMs. 1189 * 1190 * The only known sizes are 64 and 256, where the 256 version is used 1191 * by CardBus cards to store CIS information. 1192 * 1193 * The address is shifted in msb-to-lsb, and after the last 1194 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1195 * after which follows the actual data. We try to detect this zero, by 1196 * probing the data-out bit in the EEPROM control register just after 1197 * having shifted in a bit. If the bit is zero, we assume we've 1198 * shifted enough address bits. The data-out should be tri-state, 1199 * before this, which should translate to a logical one. 1200 */ 1201 static void 1202 fxp_autosize_eeprom(struct fxp_softc *sc) 1203 { 1204 1205 /* guess maximum size of 256 words */ 1206 sc->eeprom_size = 8; 1207 1208 /* autosize */ 1209 (void) fxp_eeprom_getword(sc, 0, 1); 1210 } 1211 1212 static void 1213 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1214 { 1215 int i; 1216 1217 for (i = 0; i < words; i++) 1218 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1219 } 1220 1221 static void 1222 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1223 { 1224 int i; 1225 1226 for (i = 0; i < words; i++) 1227 fxp_eeprom_putword(sc, offset + i, data[i]); 1228 } 1229 1230 static void 1231 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1232 bus_size_t mapsize, int error) 1233 { 1234 struct fxp_softc *sc; 1235 struct fxp_cb_tx *txp; 1236 int i; 1237 1238 if (error) 1239 return; 1240 1241 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1242 1243 sc = arg; 1244 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1245 for (i = 0; i < nseg; i++) { 1246 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1247 /* 1248 * If this is an 82550/82551, then we're using extended 1249 * TxCBs _and_ we're using checksum offload. This means 1250 * that the TxCB is really an IPCB. One major difference 1251 * between the two is that with plain extended TxCBs, 1252 * the bottom half of the TxCB contains two entries from 1253 * the TBD array, whereas IPCBs contain just one entry: 1254 * one entry (8 bytes) has been sacrificed for the TCP/IP 1255 * checksum offload control bits. So to make things work 1256 * right, we have to start filling in the TBD array 1257 * starting from a different place depending on whether 1258 * the chip is an 82550/82551 or not. 1259 */ 1260 if (sc->flags & FXP_FLAG_EXT_RFA) { 1261 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1262 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1263 } else { 1264 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1265 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1266 } 1267 } 1268 txp->tbd_number = nseg; 1269 } 1270 1271 /* 1272 * Grab the softc lock and call the real fxp_start_body() routine 1273 */ 1274 static void 1275 fxp_start(struct ifnet *ifp) 1276 { 1277 struct fxp_softc *sc = ifp->if_softc; 1278 1279 FXP_LOCK(sc); 1280 fxp_start_body(ifp); 1281 FXP_UNLOCK(sc); 1282 } 1283 1284 /* 1285 * Start packet transmission on the interface. 1286 * This routine must be called with the softc lock held, and is an 1287 * internal entry point only. 1288 */ 1289 static void 1290 fxp_start_body(struct ifnet *ifp) 1291 { 1292 struct fxp_softc *sc = ifp->if_softc; 1293 struct fxp_tx *txp; 1294 struct mbuf *mb_head; 1295 int error; 1296 1297 mtx_assert(&sc->sc_mtx, MA_OWNED); 1298 /* 1299 * See if we need to suspend xmit until the multicast filter 1300 * has been reprogrammed (which can only be done at the head 1301 * of the command chain). 1302 */ 1303 if (sc->need_mcsetup) { 1304 return; 1305 } 1306 1307 txp = NULL; 1308 1309 /* 1310 * We're finished if there is nothing more to add to the list or if 1311 * we're all filled up with buffers to transmit. 1312 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1313 * a NOP command when needed. 1314 */ 1315 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1316 1317 /* 1318 * Grab a packet to transmit. 1319 */ 1320 IF_DEQUEUE(&ifp->if_snd, mb_head); 1321 1322 /* 1323 * Get pointer to next available tx desc. 1324 */ 1325 txp = sc->fxp_desc.tx_last->tx_next; 1326 1327 /* 1328 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1329 * Ethernet Controller Family Open Source Software 1330 * Developer Manual says: 1331 * Using software parsing is only allowed with legal 1332 * TCP/IP or UDP/IP packets. 1333 * ... 1334 * For all other datagrams, hardware parsing must 1335 * be used. 1336 * Software parsing appears to truncate ICMP and 1337 * fragmented UDP packets that contain one to three 1338 * bytes in the second (and final) mbuf of the packet. 1339 */ 1340 if (sc->flags & FXP_FLAG_EXT_RFA) 1341 txp->tx_cb->ipcb_ip_activation_high = 1342 FXP_IPCB_HARDWAREPARSING_ENABLE; 1343 1344 /* 1345 * Deal with TCP/IP checksum offload. Note that 1346 * in order for TCP checksum offload to work, 1347 * the pseudo header checksum must have already 1348 * been computed and stored in the checksum field 1349 * in the TCP header. The stack should have 1350 * already done this for us. 1351 */ 1352 1353 if (mb_head->m_pkthdr.csum_flags) { 1354 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1355 txp->tx_cb->ipcb_ip_schedule = 1356 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1357 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1358 txp->tx_cb->ipcb_ip_schedule |= 1359 FXP_IPCB_TCP_PACKET; 1360 } 1361 #ifdef FXP_IP_CSUM_WAR 1362 /* 1363 * XXX The 82550 chip appears to have trouble 1364 * dealing with IP header checksums in very small 1365 * datagrams, namely fragments from 1 to 3 bytes 1366 * in size. For example, say you want to transmit 1367 * a UDP packet of 1473 bytes. The packet will be 1368 * fragmented over two IP datagrams, the latter 1369 * containing only one byte of data. The 82550 will 1370 * botch the header checksum on the 1-byte fragment. 1371 * As long as the datagram contains 4 or more bytes 1372 * of data, you're ok. 1373 * 1374 * The following code attempts to work around this 1375 * problem: if the datagram is less than 38 bytes 1376 * in size (14 bytes ether header, 20 bytes IP header, 1377 * plus 4 bytes of data), we punt and compute the IP 1378 * header checksum by hand. This workaround doesn't 1379 * work very well, however, since it can be fooled 1380 * by things like VLAN tags and IP options that make 1381 * the header sizes/offsets vary. 1382 */ 1383 1384 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1385 if (mb_head->m_pkthdr.len < 38) { 1386 struct ip *ip; 1387 mb_head->m_data += ETHER_HDR_LEN; 1388 ip = mtod(mb_head, struct ip *); 1389 ip->ip_sum = in_cksum(mb_head, 1390 ip->ip_hl << 2); 1391 mb_head->m_data -= ETHER_HDR_LEN; 1392 } else { 1393 txp->tx_cb->ipcb_ip_activation_high = 1394 FXP_IPCB_HARDWAREPARSING_ENABLE; 1395 txp->tx_cb->ipcb_ip_schedule |= 1396 FXP_IPCB_IP_CHECKSUM_ENABLE; 1397 } 1398 } 1399 #endif 1400 } 1401 1402 /* 1403 * Go through each of the mbufs in the chain and initialize 1404 * the transmit buffer descriptors with the physical address 1405 * and size of the mbuf. 1406 */ 1407 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1408 mb_head, fxp_dma_map_txbuf, sc, 0); 1409 1410 if (error && error != EFBIG) { 1411 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1412 error); 1413 m_freem(mb_head); 1414 break; 1415 } 1416 1417 if (error) { 1418 struct mbuf *mn; 1419 1420 /* 1421 * We ran out of segments. We have to recopy this 1422 * mbuf chain first. Bail out if we can't get the 1423 * new buffers. 1424 */ 1425 mn = m_defrag(mb_head, M_DONTWAIT); 1426 if (mn == NULL) { 1427 m_freem(mb_head); 1428 break; 1429 } else { 1430 mb_head = mn; 1431 } 1432 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1433 mb_head, fxp_dma_map_txbuf, sc, 0); 1434 if (error) { 1435 device_printf(sc->dev, 1436 "can't map mbuf (error %d)\n", error); 1437 m_freem(mb_head); 1438 break; 1439 } 1440 } 1441 1442 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1443 BUS_DMASYNC_PREWRITE); 1444 1445 txp->tx_mbuf = mb_head; 1446 txp->tx_cb->cb_status = 0; 1447 txp->tx_cb->byte_count = 0; 1448 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1449 txp->tx_cb->cb_command = 1450 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1451 FXP_CB_COMMAND_S); 1452 } else { 1453 txp->tx_cb->cb_command = 1454 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1455 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1456 /* 1457 * Set a 5 second timer just in case we don't hear 1458 * from the card again. 1459 */ 1460 ifp->if_timer = 5; 1461 } 1462 txp->tx_cb->tx_threshold = tx_threshold; 1463 1464 /* 1465 * Advance the end of list forward. 1466 */ 1467 1468 #ifdef __alpha__ 1469 /* 1470 * On platforms which can't access memory in 16-bit 1471 * granularities, we must prevent the card from DMA'ing 1472 * up the status while we update the command field. 1473 * This could cause us to overwrite the completion status. 1474 * XXX This is probably bogus and we're _not_ looking 1475 * for atomicity here. 1476 */ 1477 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1478 htole16(FXP_CB_COMMAND_S)); 1479 #else 1480 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1481 htole16(~FXP_CB_COMMAND_S); 1482 #endif /*__alpha__*/ 1483 sc->fxp_desc.tx_last = txp; 1484 1485 /* 1486 * Advance the beginning of the list forward if there are 1487 * no other packets queued (when nothing is queued, tx_first 1488 * sits on the last TxCB that was sent out). 1489 */ 1490 if (sc->tx_queued == 0) 1491 sc->fxp_desc.tx_first = txp; 1492 1493 sc->tx_queued++; 1494 1495 /* 1496 * Pass packet to bpf if there is a listener. 1497 */ 1498 BPF_MTAP(ifp, mb_head); 1499 } 1500 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1501 1502 /* 1503 * We're finished. If we added to the list, issue a RESUME to get DMA 1504 * going again if suspended. 1505 */ 1506 if (txp != NULL) { 1507 fxp_scb_wait(sc); 1508 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1509 } 1510 } 1511 1512 #ifdef DEVICE_POLLING 1513 static poll_handler_t fxp_poll; 1514 1515 static void 1516 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1517 { 1518 struct fxp_softc *sc = ifp->if_softc; 1519 u_int8_t statack; 1520 1521 FXP_LOCK(sc); 1522 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1523 ether_poll_deregister(ifp); 1524 cmd = POLL_DEREGISTER; 1525 } 1526 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1527 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1528 FXP_UNLOCK(sc); 1529 return; 1530 } 1531 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1532 FXP_SCB_STATACK_FR; 1533 if (cmd == POLL_AND_CHECK_STATUS) { 1534 u_int8_t tmp; 1535 1536 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1537 if (tmp == 0xff || tmp == 0) { 1538 FXP_UNLOCK(sc); 1539 return; /* nothing to do */ 1540 } 1541 tmp &= ~statack; 1542 /* ack what we can */ 1543 if (tmp != 0) 1544 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1545 statack |= tmp; 1546 } 1547 fxp_intr_body(sc, ifp, statack, count); 1548 FXP_UNLOCK(sc); 1549 } 1550 #endif /* DEVICE_POLLING */ 1551 1552 /* 1553 * Process interface interrupts. 1554 */ 1555 static void 1556 fxp_intr(void *xsc) 1557 { 1558 struct fxp_softc *sc = xsc; 1559 struct ifnet *ifp = &sc->sc_if; 1560 u_int8_t statack; 1561 1562 FXP_LOCK(sc); 1563 if (sc->suspended) { 1564 FXP_UNLOCK(sc); 1565 return; 1566 } 1567 1568 #ifdef DEVICE_POLLING 1569 if (ifp->if_flags & IFF_POLLING) { 1570 FXP_UNLOCK(sc); 1571 return; 1572 } 1573 if ((ifp->if_capenable & IFCAP_POLLING) && 1574 ether_poll_register(fxp_poll, ifp)) { 1575 /* disable interrupts */ 1576 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1577 FXP_UNLOCK(sc); 1578 fxp_poll(ifp, 0, 1); 1579 return; 1580 } 1581 #endif 1582 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1583 /* 1584 * It should not be possible to have all bits set; the 1585 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1586 * all bits are set, this may indicate that the card has 1587 * been physically ejected, so ignore it. 1588 */ 1589 if (statack == 0xff) { 1590 FXP_UNLOCK(sc); 1591 return; 1592 } 1593 1594 /* 1595 * First ACK all the interrupts in this pass. 1596 */ 1597 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1598 fxp_intr_body(sc, ifp, statack, -1); 1599 } 1600 FXP_UNLOCK(sc); 1601 } 1602 1603 static void 1604 fxp_txeof(struct fxp_softc *sc) 1605 { 1606 struct fxp_tx *txp; 1607 1608 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1609 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1610 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1611 txp = txp->tx_next) { 1612 if (txp->tx_mbuf != NULL) { 1613 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1614 BUS_DMASYNC_POSTWRITE); 1615 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1616 m_freem(txp->tx_mbuf); 1617 txp->tx_mbuf = NULL; 1618 /* clear this to reset csum offload bits */ 1619 txp->tx_cb->tbd[0].tb_addr = 0; 1620 } 1621 sc->tx_queued--; 1622 } 1623 sc->fxp_desc.tx_first = txp; 1624 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1625 } 1626 1627 static void 1628 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1629 int count) 1630 { 1631 struct mbuf *m; 1632 struct fxp_rx *rxp; 1633 struct fxp_rfa *rfa; 1634 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1635 1636 mtx_assert(&sc->sc_mtx, MA_OWNED); 1637 if (rnr) 1638 fxp_rnr++; 1639 #ifdef DEVICE_POLLING 1640 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1641 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1642 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1643 rnr = 1; 1644 } 1645 #endif 1646 1647 /* 1648 * Free any finished transmit mbuf chains. 1649 * 1650 * Handle the CNA event likt a CXTNO event. It used to 1651 * be that this event (control unit not ready) was not 1652 * encountered, but it is now with the SMPng modifications. 1653 * The exact sequence of events that occur when the interface 1654 * is brought up are different now, and if this event 1655 * goes unhandled, the configuration/rxfilter setup sequence 1656 * can stall for several seconds. The result is that no 1657 * packets go out onto the wire for about 5 to 10 seconds 1658 * after the interface is ifconfig'ed for the first time. 1659 */ 1660 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1661 fxp_txeof(sc); 1662 1663 ifp->if_timer = 0; 1664 if (sc->tx_queued == 0) { 1665 if (sc->need_mcsetup) 1666 fxp_mc_setup(sc); 1667 } 1668 /* 1669 * Try to start more packets transmitting. 1670 */ 1671 if (ifp->if_snd.ifq_head != NULL) 1672 fxp_start_body(ifp); 1673 } 1674 1675 /* 1676 * Just return if nothing happened on the receive side. 1677 */ 1678 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1679 return; 1680 1681 /* 1682 * Process receiver interrupts. If a no-resource (RNR) 1683 * condition exists, get whatever packets we can and 1684 * re-start the receiver. 1685 * 1686 * When using polling, we do not process the list to completion, 1687 * so when we get an RNR interrupt we must defer the restart 1688 * until we hit the last buffer with the C bit set. 1689 * If we run out of cycles and rfa_headm has the C bit set, 1690 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1691 * that the info will be used in the subsequent polling cycle. 1692 */ 1693 for (;;) { 1694 rxp = sc->fxp_desc.rx_head; 1695 m = rxp->rx_mbuf; 1696 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1697 RFA_ALIGNMENT_FUDGE); 1698 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1699 BUS_DMASYNC_POSTREAD); 1700 1701 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1702 if (count >= 0 && count-- == 0) { 1703 if (rnr) { 1704 /* Defer RNR processing until the next time. */ 1705 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1706 rnr = 0; 1707 } 1708 break; 1709 } 1710 #endif /* DEVICE_POLLING */ 1711 1712 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1713 break; 1714 1715 /* 1716 * Advance head forward. 1717 */ 1718 sc->fxp_desc.rx_head = rxp->rx_next; 1719 1720 /* 1721 * Add a new buffer to the receive chain. 1722 * If this fails, the old buffer is recycled 1723 * instead. 1724 */ 1725 if (fxp_add_rfabuf(sc, rxp) == 0) { 1726 int total_len; 1727 1728 /* 1729 * Fetch packet length (the top 2 bits of 1730 * actual_size are flags set by the controller 1731 * upon completion), and drop the packet in case 1732 * of bogus length or CRC errors. 1733 */ 1734 total_len = le16toh(rfa->actual_size) & 0x3fff; 1735 if (total_len < sizeof(struct ether_header) || 1736 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1737 sc->rfa_size || 1738 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1739 m_freem(m); 1740 continue; 1741 } 1742 1743 /* Do IP checksum checking. */ 1744 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1745 if (rfa->rfax_csum_sts & 1746 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1747 m->m_pkthdr.csum_flags |= 1748 CSUM_IP_CHECKED; 1749 if (rfa->rfax_csum_sts & 1750 FXP_RFDX_CS_IP_CSUM_VALID) 1751 m->m_pkthdr.csum_flags |= 1752 CSUM_IP_VALID; 1753 if ((rfa->rfax_csum_sts & 1754 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1755 (rfa->rfax_csum_sts & 1756 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1757 m->m_pkthdr.csum_flags |= 1758 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1759 m->m_pkthdr.csum_data = 0xffff; 1760 } 1761 } 1762 1763 m->m_pkthdr.len = m->m_len = total_len; 1764 m->m_pkthdr.rcvif = ifp; 1765 1766 /* 1767 * Drop locks before calling if_input() since it 1768 * may re-enter fxp_start() in the netisr case. 1769 * This would result in a lock reversal. Better 1770 * performance might be obtained by chaining all 1771 * packets received, dropping the lock, and then 1772 * calling if_input() on each one. 1773 */ 1774 FXP_UNLOCK(sc); 1775 (*ifp->if_input)(ifp, m); 1776 FXP_LOCK(sc); 1777 } 1778 } 1779 if (rnr) { 1780 fxp_scb_wait(sc); 1781 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1782 sc->fxp_desc.rx_head->rx_addr); 1783 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1784 } 1785 } 1786 1787 /* 1788 * Update packet in/out/collision statistics. The i82557 doesn't 1789 * allow you to access these counters without doing a fairly 1790 * expensive DMA to get _all_ of the statistics it maintains, so 1791 * we do this operation here only once per second. The statistics 1792 * counters in the kernel are updated from the previous dump-stats 1793 * DMA and then a new dump-stats DMA is started. The on-chip 1794 * counters are zeroed when the DMA completes. If we can't start 1795 * the DMA immediately, we don't wait - we just prepare to read 1796 * them again next time. 1797 */ 1798 static void 1799 fxp_tick(void *xsc) 1800 { 1801 struct fxp_softc *sc = xsc; 1802 struct ifnet *ifp = &sc->sc_if; 1803 struct fxp_stats *sp = sc->fxp_stats; 1804 int s; 1805 1806 FXP_LOCK(sc); 1807 s = splimp(); 1808 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1809 ifp->if_opackets += le32toh(sp->tx_good); 1810 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1811 if (sp->rx_good) { 1812 ifp->if_ipackets += le32toh(sp->rx_good); 1813 sc->rx_idle_secs = 0; 1814 } else { 1815 /* 1816 * Receiver's been idle for another second. 1817 */ 1818 sc->rx_idle_secs++; 1819 } 1820 ifp->if_ierrors += 1821 le32toh(sp->rx_crc_errors) + 1822 le32toh(sp->rx_alignment_errors) + 1823 le32toh(sp->rx_rnr_errors) + 1824 le32toh(sp->rx_overrun_errors); 1825 /* 1826 * If any transmit underruns occured, bump up the transmit 1827 * threshold by another 512 bytes (64 * 8). 1828 */ 1829 if (sp->tx_underruns) { 1830 ifp->if_oerrors += le32toh(sp->tx_underruns); 1831 if (tx_threshold < 192) 1832 tx_threshold += 64; 1833 } 1834 1835 /* 1836 * Release any xmit buffers that have completed DMA. This isn't 1837 * strictly necessary to do here, but it's advantagous for mbufs 1838 * with external storage to be released in a timely manner rather 1839 * than being defered for a potentially long time. This limits 1840 * the delay to a maximum of one second. 1841 */ 1842 fxp_txeof(sc); 1843 1844 /* 1845 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1846 * then assume the receiver has locked up and attempt to clear 1847 * the condition by reprogramming the multicast filter. This is 1848 * a work-around for a bug in the 82557 where the receiver locks 1849 * up if it gets certain types of garbage in the syncronization 1850 * bits prior to the packet header. This bug is supposed to only 1851 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1852 * mode as well (perhaps due to a 10/100 speed transition). 1853 */ 1854 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1855 sc->rx_idle_secs = 0; 1856 fxp_mc_setup(sc); 1857 } 1858 /* 1859 * If there is no pending command, start another stats 1860 * dump. Otherwise punt for now. 1861 */ 1862 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1863 /* 1864 * Start another stats dump. 1865 */ 1866 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1867 BUS_DMASYNC_PREREAD); 1868 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1869 } else { 1870 /* 1871 * A previous command is still waiting to be accepted. 1872 * Just zero our copy of the stats and wait for the 1873 * next timer event to update them. 1874 */ 1875 sp->tx_good = 0; 1876 sp->tx_underruns = 0; 1877 sp->tx_total_collisions = 0; 1878 1879 sp->rx_good = 0; 1880 sp->rx_crc_errors = 0; 1881 sp->rx_alignment_errors = 0; 1882 sp->rx_rnr_errors = 0; 1883 sp->rx_overrun_errors = 0; 1884 } 1885 if (sc->miibus != NULL) 1886 mii_tick(device_get_softc(sc->miibus)); 1887 1888 /* 1889 * Schedule another timeout one second from now. 1890 */ 1891 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1892 FXP_UNLOCK(sc); 1893 splx(s); 1894 } 1895 1896 /* 1897 * Stop the interface. Cancels the statistics updater and resets 1898 * the interface. 1899 */ 1900 static void 1901 fxp_stop(struct fxp_softc *sc) 1902 { 1903 struct ifnet *ifp = &sc->sc_if; 1904 struct fxp_tx *txp; 1905 int i; 1906 1907 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1908 ifp->if_timer = 0; 1909 1910 #ifdef DEVICE_POLLING 1911 ether_poll_deregister(ifp); 1912 #endif 1913 /* 1914 * Cancel stats updater. 1915 */ 1916 callout_stop(&sc->stat_ch); 1917 1918 /* 1919 * Issue software reset, which also unloads the microcode. 1920 */ 1921 sc->flags &= ~FXP_FLAG_UCODE; 1922 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1923 DELAY(50); 1924 1925 /* 1926 * Release any xmit buffers. 1927 */ 1928 txp = sc->fxp_desc.tx_list; 1929 if (txp != NULL) { 1930 for (i = 0; i < FXP_NTXCB; i++) { 1931 if (txp[i].tx_mbuf != NULL) { 1932 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1933 BUS_DMASYNC_POSTWRITE); 1934 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1935 m_freem(txp[i].tx_mbuf); 1936 txp[i].tx_mbuf = NULL; 1937 /* clear this to reset csum offload bits */ 1938 txp[i].tx_cb->tbd[0].tb_addr = 0; 1939 } 1940 } 1941 } 1942 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1943 sc->tx_queued = 0; 1944 } 1945 1946 /* 1947 * Watchdog/transmission transmit timeout handler. Called when a 1948 * transmission is started on the interface, but no interrupt is 1949 * received before the timeout. This usually indicates that the 1950 * card has wedged for some reason. 1951 */ 1952 static void 1953 fxp_watchdog(struct ifnet *ifp) 1954 { 1955 struct fxp_softc *sc = ifp->if_softc; 1956 1957 FXP_LOCK(sc); 1958 device_printf(sc->dev, "device timeout\n"); 1959 ifp->if_oerrors++; 1960 1961 fxp_init_body(sc); 1962 FXP_UNLOCK(sc); 1963 } 1964 1965 /* 1966 * Acquire locks and then call the real initialization function. This 1967 * is necessary because ether_ioctl() calls if_init() and this would 1968 * result in mutex recursion if the mutex was held. 1969 */ 1970 static void 1971 fxp_init(void *xsc) 1972 { 1973 struct fxp_softc *sc = xsc; 1974 1975 FXP_LOCK(sc); 1976 fxp_init_body(sc); 1977 FXP_UNLOCK(sc); 1978 } 1979 1980 /* 1981 * Perform device initialization. This routine must be called with the 1982 * softc lock held. 1983 */ 1984 static void 1985 fxp_init_body(struct fxp_softc *sc) 1986 { 1987 struct ifnet *ifp = &sc->sc_if; 1988 struct fxp_cb_config *cbp; 1989 struct fxp_cb_ias *cb_ias; 1990 struct fxp_cb_tx *tcbp; 1991 struct fxp_tx *txp; 1992 struct fxp_cb_mcs *mcsp; 1993 int i, prm, s; 1994 1995 mtx_assert(&sc->sc_mtx, MA_OWNED); 1996 s = splimp(); 1997 /* 1998 * Cancel any pending I/O 1999 */ 2000 fxp_stop(sc); 2001 2002 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2003 2004 /* 2005 * Initialize base of CBL and RFA memory. Loading with zero 2006 * sets it up for regular linear addressing. 2007 */ 2008 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2009 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2010 2011 fxp_scb_wait(sc); 2012 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2013 2014 /* 2015 * Initialize base of dump-stats buffer. 2016 */ 2017 fxp_scb_wait(sc); 2018 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2019 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2020 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2021 2022 /* 2023 * Attempt to load microcode if requested. 2024 */ 2025 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2026 fxp_load_ucode(sc); 2027 2028 /* 2029 * Initialize the multicast address list. 2030 */ 2031 if (fxp_mc_addrs(sc)) { 2032 mcsp = sc->mcsp; 2033 mcsp->cb_status = 0; 2034 mcsp->cb_command = 2035 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2036 mcsp->link_addr = 0xffffffff; 2037 /* 2038 * Start the multicast setup command. 2039 */ 2040 fxp_scb_wait(sc); 2041 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2042 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2043 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2044 /* ...and wait for it to complete. */ 2045 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2046 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2047 BUS_DMASYNC_POSTWRITE); 2048 } 2049 2050 /* 2051 * We temporarily use memory that contains the TxCB list to 2052 * construct the config CB. The TxCB list memory is rebuilt 2053 * later. 2054 */ 2055 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2056 2057 /* 2058 * This bcopy is kind of disgusting, but there are a bunch of must be 2059 * zero and must be one bits in this structure and this is the easiest 2060 * way to initialize them all to proper values. 2061 */ 2062 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2063 2064 cbp->cb_status = 0; 2065 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2066 FXP_CB_COMMAND_EL); 2067 cbp->link_addr = 0xffffffff; /* (no) next command */ 2068 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2069 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2070 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2071 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2072 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2073 cbp->type_enable = 0; /* actually reserved */ 2074 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2075 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2076 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2077 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2078 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2079 cbp->late_scb = 0; /* (don't) defer SCB update */ 2080 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2081 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2082 cbp->ci_int = 1; /* interrupt on CU idle */ 2083 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2084 cbp->ext_stats_dis = 1; /* disable extended counters */ 2085 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2086 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2087 cbp->disc_short_rx = !prm; /* discard short packets */ 2088 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2089 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2090 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2091 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2092 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2093 cbp->csma_dis = 0; /* (don't) disable link */ 2094 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2095 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2096 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2097 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2098 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2099 cbp->nsai = 1; /* (don't) disable source addr insert */ 2100 cbp->preamble_length = 2; /* (7 byte) preamble */ 2101 cbp->loopback = 0; /* (don't) loopback */ 2102 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2103 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2104 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2105 cbp->promiscuous = prm; /* promiscuous mode */ 2106 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2107 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2108 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2109 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2110 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2111 2112 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2113 cbp->padding = 1; /* (do) pad short tx packets */ 2114 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2115 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2116 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2117 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2118 /* must set wake_en in PMCSR also */ 2119 cbp->force_fdx = 0; /* (don't) force full duplex */ 2120 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2121 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2122 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2123 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2124 2125 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2126 /* 2127 * The 82557 has no hardware flow control, the values 2128 * below are the defaults for the chip. 2129 */ 2130 cbp->fc_delay_lsb = 0; 2131 cbp->fc_delay_msb = 0x40; 2132 cbp->pri_fc_thresh = 3; 2133 cbp->tx_fc_dis = 0; 2134 cbp->rx_fc_restop = 0; 2135 cbp->rx_fc_restart = 0; 2136 cbp->fc_filter = 0; 2137 cbp->pri_fc_loc = 1; 2138 } else { 2139 cbp->fc_delay_lsb = 0x1f; 2140 cbp->fc_delay_msb = 0x01; 2141 cbp->pri_fc_thresh = 3; 2142 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2143 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2144 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2145 cbp->fc_filter = !prm; /* drop FC frames to host */ 2146 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2147 } 2148 2149 /* 2150 * Start the config command/DMA. 2151 */ 2152 fxp_scb_wait(sc); 2153 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2154 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2155 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2156 /* ...and wait for it to complete. */ 2157 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2158 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2159 2160 /* 2161 * Now initialize the station address. Temporarily use the TxCB 2162 * memory area like we did above for the config CB. 2163 */ 2164 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2165 cb_ias->cb_status = 0; 2166 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2167 cb_ias->link_addr = 0xffffffff; 2168 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2169 sizeof(sc->arpcom.ac_enaddr)); 2170 2171 /* 2172 * Start the IAS (Individual Address Setup) command/DMA. 2173 */ 2174 fxp_scb_wait(sc); 2175 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2176 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2177 /* ...and wait for it to complete. */ 2178 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2179 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2180 2181 /* 2182 * Initialize transmit control block (TxCB) list. 2183 */ 2184 txp = sc->fxp_desc.tx_list; 2185 tcbp = sc->fxp_desc.cbl_list; 2186 bzero(tcbp, FXP_TXCB_SZ); 2187 for (i = 0; i < FXP_NTXCB; i++) { 2188 txp[i].tx_cb = tcbp + i; 2189 txp[i].tx_mbuf = NULL; 2190 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2191 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2192 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2193 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2194 if (sc->flags & FXP_FLAG_EXT_TXCB) 2195 tcbp[i].tbd_array_addr = 2196 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2197 else 2198 tcbp[i].tbd_array_addr = 2199 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2200 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2201 } 2202 /* 2203 * Set the suspend flag on the first TxCB and start the control 2204 * unit. It will execute the NOP and then suspend. 2205 */ 2206 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2207 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2208 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2209 sc->tx_queued = 1; 2210 2211 fxp_scb_wait(sc); 2212 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2213 2214 /* 2215 * Initialize receiver buffer area - RFA. 2216 */ 2217 fxp_scb_wait(sc); 2218 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2219 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2220 2221 /* 2222 * Set current media. 2223 */ 2224 if (sc->miibus != NULL) 2225 mii_mediachg(device_get_softc(sc->miibus)); 2226 2227 ifp->if_flags |= IFF_RUNNING; 2228 ifp->if_flags &= ~IFF_OACTIVE; 2229 2230 /* 2231 * Enable interrupts. 2232 */ 2233 #ifdef DEVICE_POLLING 2234 /* 2235 * ... but only do that if we are not polling. And because (presumably) 2236 * the default is interrupts on, we need to disable them explicitly! 2237 */ 2238 if ( ifp->if_flags & IFF_POLLING ) 2239 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2240 else 2241 #endif /* DEVICE_POLLING */ 2242 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2243 2244 /* 2245 * Start stats updater. 2246 */ 2247 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2248 splx(s); 2249 } 2250 2251 static int 2252 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2253 { 2254 2255 return (0); 2256 } 2257 2258 static void 2259 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2260 { 2261 2262 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2263 } 2264 2265 /* 2266 * Change media according to request. 2267 */ 2268 static int 2269 fxp_ifmedia_upd(struct ifnet *ifp) 2270 { 2271 struct fxp_softc *sc = ifp->if_softc; 2272 struct mii_data *mii; 2273 2274 mii = device_get_softc(sc->miibus); 2275 mii_mediachg(mii); 2276 return (0); 2277 } 2278 2279 /* 2280 * Notify the world which media we're using. 2281 */ 2282 static void 2283 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2284 { 2285 struct fxp_softc *sc = ifp->if_softc; 2286 struct mii_data *mii; 2287 2288 mii = device_get_softc(sc->miibus); 2289 mii_pollstat(mii); 2290 ifmr->ifm_active = mii->mii_media_active; 2291 ifmr->ifm_status = mii->mii_media_status; 2292 2293 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2294 sc->cu_resume_bug = 1; 2295 else 2296 sc->cu_resume_bug = 0; 2297 } 2298 2299 /* 2300 * Add a buffer to the end of the RFA buffer list. 2301 * Return 0 if successful, 1 for failure. A failure results in 2302 * adding the 'oldm' (if non-NULL) on to the end of the list - 2303 * tossing out its old contents and recycling it. 2304 * The RFA struct is stuck at the beginning of mbuf cluster and the 2305 * data pointer is fixed up to point just past it. 2306 */ 2307 static int 2308 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2309 { 2310 struct mbuf *m; 2311 struct fxp_rfa *rfa, *p_rfa; 2312 struct fxp_rx *p_rx; 2313 bus_dmamap_t tmp_map; 2314 int error; 2315 2316 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2317 if (m == NULL) 2318 return (ENOBUFS); 2319 2320 /* 2321 * Move the data pointer up so that the incoming data packet 2322 * will be 32-bit aligned. 2323 */ 2324 m->m_data += RFA_ALIGNMENT_FUDGE; 2325 2326 /* 2327 * Get a pointer to the base of the mbuf cluster and move 2328 * data start past it. 2329 */ 2330 rfa = mtod(m, struct fxp_rfa *); 2331 m->m_data += sc->rfa_size; 2332 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2333 2334 rfa->rfa_status = 0; 2335 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2336 rfa->actual_size = 0; 2337 2338 /* 2339 * Initialize the rest of the RFA. Note that since the RFA 2340 * is misaligned, we cannot store values directly. We're thus 2341 * using the le32enc() function which handles endianness and 2342 * is also alignment-safe. 2343 */ 2344 le32enc(&rfa->link_addr, 0xffffffff); 2345 le32enc(&rfa->rbd_addr, 0xffffffff); 2346 2347 /* Map the RFA into DMA memory. */ 2348 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2349 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2350 &rxp->rx_addr, 0); 2351 if (error) { 2352 m_freem(m); 2353 return (error); 2354 } 2355 2356 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2357 tmp_map = sc->spare_map; 2358 sc->spare_map = rxp->rx_map; 2359 rxp->rx_map = tmp_map; 2360 rxp->rx_mbuf = m; 2361 2362 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2364 2365 /* 2366 * If there are other buffers already on the list, attach this 2367 * one to the end by fixing up the tail to point to this one. 2368 */ 2369 if (sc->fxp_desc.rx_head != NULL) { 2370 p_rx = sc->fxp_desc.rx_tail; 2371 p_rfa = (struct fxp_rfa *) 2372 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2373 p_rx->rx_next = rxp; 2374 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2375 p_rfa->rfa_control = 0; 2376 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2377 BUS_DMASYNC_PREWRITE); 2378 } else { 2379 rxp->rx_next = NULL; 2380 sc->fxp_desc.rx_head = rxp; 2381 } 2382 sc->fxp_desc.rx_tail = rxp; 2383 return (0); 2384 } 2385 2386 static volatile int 2387 fxp_miibus_readreg(device_t dev, int phy, int reg) 2388 { 2389 struct fxp_softc *sc = device_get_softc(dev); 2390 int count = 10000; 2391 int value; 2392 2393 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2394 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2395 2396 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2397 && count--) 2398 DELAY(10); 2399 2400 if (count <= 0) 2401 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2402 2403 return (value & 0xffff); 2404 } 2405 2406 static void 2407 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2408 { 2409 struct fxp_softc *sc = device_get_softc(dev); 2410 int count = 10000; 2411 2412 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2413 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2414 (value & 0xffff)); 2415 2416 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2417 count--) 2418 DELAY(10); 2419 2420 if (count <= 0) 2421 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2422 } 2423 2424 static int 2425 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2426 { 2427 struct fxp_softc *sc = ifp->if_softc; 2428 struct ifreq *ifr = (struct ifreq *)data; 2429 struct mii_data *mii; 2430 int flag, mask, s, error = 0; 2431 2432 /* 2433 * Detaching causes us to call ioctl with the mutex owned. Preclude 2434 * that by saying we're busy if the lock is already held. 2435 */ 2436 if (mtx_owned(&sc->sc_mtx)) 2437 return (EBUSY); 2438 2439 FXP_LOCK(sc); 2440 s = splimp(); 2441 2442 switch (command) { 2443 case SIOCSIFFLAGS: 2444 if (ifp->if_flags & IFF_ALLMULTI) 2445 sc->flags |= FXP_FLAG_ALL_MCAST; 2446 else 2447 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2448 2449 /* 2450 * If interface is marked up and not running, then start it. 2451 * If it is marked down and running, stop it. 2452 * XXX If it's up then re-initialize it. This is so flags 2453 * such as IFF_PROMISC are handled. 2454 */ 2455 if (ifp->if_flags & IFF_UP) { 2456 fxp_init_body(sc); 2457 } else { 2458 if (ifp->if_flags & IFF_RUNNING) 2459 fxp_stop(sc); 2460 } 2461 break; 2462 2463 case SIOCADDMULTI: 2464 case SIOCDELMULTI: 2465 if (ifp->if_flags & IFF_ALLMULTI) 2466 sc->flags |= FXP_FLAG_ALL_MCAST; 2467 else 2468 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2469 /* 2470 * Multicast list has changed; set the hardware filter 2471 * accordingly. 2472 */ 2473 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2474 fxp_mc_setup(sc); 2475 /* 2476 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2477 * again rather than else {}. 2478 */ 2479 if (sc->flags & FXP_FLAG_ALL_MCAST) 2480 fxp_init_body(sc); 2481 error = 0; 2482 break; 2483 2484 case SIOCSIFMEDIA: 2485 case SIOCGIFMEDIA: 2486 if (sc->miibus != NULL) { 2487 mii = device_get_softc(sc->miibus); 2488 error = ifmedia_ioctl(ifp, ifr, 2489 &mii->mii_media, command); 2490 } else { 2491 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2492 } 2493 break; 2494 2495 case SIOCSIFCAP: 2496 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2497 if (mask & IFCAP_POLLING) 2498 ifp->if_capenable ^= IFCAP_POLLING; 2499 if (mask & IFCAP_VLAN_MTU) { 2500 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2501 if (sc->revision != FXP_REV_82557) 2502 flag = FXP_FLAG_LONG_PKT_EN; 2503 else /* a hack to get long frames on the old chip */ 2504 flag = FXP_FLAG_SAVE_BAD; 2505 sc->flags ^= flag; 2506 if (ifp->if_flags & IFF_UP) 2507 fxp_init_body(sc); 2508 } 2509 break; 2510 2511 default: 2512 /* 2513 * ether_ioctl() will eventually call fxp_start() which 2514 * will result in mutex recursion so drop it first. 2515 */ 2516 FXP_UNLOCK(sc); 2517 error = ether_ioctl(ifp, command, data); 2518 } 2519 if (mtx_owned(&sc->sc_mtx)) 2520 FXP_UNLOCK(sc); 2521 splx(s); 2522 return (error); 2523 } 2524 2525 /* 2526 * Fill in the multicast address list and return number of entries. 2527 */ 2528 static int 2529 fxp_mc_addrs(struct fxp_softc *sc) 2530 { 2531 struct fxp_cb_mcs *mcsp = sc->mcsp; 2532 struct ifnet *ifp = &sc->sc_if; 2533 struct ifmultiaddr *ifma; 2534 int nmcasts; 2535 2536 nmcasts = 0; 2537 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2538 #if __FreeBSD_version < 500000 2539 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2540 #else 2541 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2542 #endif 2543 if (ifma->ifma_addr->sa_family != AF_LINK) 2544 continue; 2545 if (nmcasts >= MAXMCADDR) { 2546 sc->flags |= FXP_FLAG_ALL_MCAST; 2547 nmcasts = 0; 2548 break; 2549 } 2550 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2551 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2552 nmcasts++; 2553 } 2554 } 2555 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2556 return (nmcasts); 2557 } 2558 2559 /* 2560 * Program the multicast filter. 2561 * 2562 * We have an artificial restriction that the multicast setup command 2563 * must be the first command in the chain, so we take steps to ensure 2564 * this. By requiring this, it allows us to keep up the performance of 2565 * the pre-initialized command ring (esp. link pointers) by not actually 2566 * inserting the mcsetup command in the ring - i.e. its link pointer 2567 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2568 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2569 * lead into the regular TxCB ring when it completes. 2570 * 2571 * This function must be called at splimp. 2572 */ 2573 static void 2574 fxp_mc_setup(struct fxp_softc *sc) 2575 { 2576 struct fxp_cb_mcs *mcsp = sc->mcsp; 2577 struct ifnet *ifp = &sc->sc_if; 2578 struct fxp_tx *txp; 2579 int count; 2580 2581 /* 2582 * If there are queued commands, we must wait until they are all 2583 * completed. If we are already waiting, then add a NOP command 2584 * with interrupt option so that we're notified when all commands 2585 * have been completed - fxp_start() ensures that no additional 2586 * TX commands will be added when need_mcsetup is true. 2587 */ 2588 if (sc->tx_queued) { 2589 /* 2590 * need_mcsetup will be true if we are already waiting for the 2591 * NOP command to be completed (see below). In this case, bail. 2592 */ 2593 if (sc->need_mcsetup) 2594 return; 2595 sc->need_mcsetup = 1; 2596 2597 /* 2598 * Add a NOP command with interrupt so that we are notified 2599 * when all TX commands have been processed. 2600 */ 2601 txp = sc->fxp_desc.tx_last->tx_next; 2602 txp->tx_mbuf = NULL; 2603 txp->tx_cb->cb_status = 0; 2604 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2605 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2606 /* 2607 * Advance the end of list forward. 2608 */ 2609 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2610 htole16(~FXP_CB_COMMAND_S); 2611 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2612 sc->fxp_desc.tx_last = txp; 2613 sc->tx_queued++; 2614 /* 2615 * Issue a resume in case the CU has just suspended. 2616 */ 2617 fxp_scb_wait(sc); 2618 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2619 /* 2620 * Set a 5 second timer just in case we don't hear from the 2621 * card again. 2622 */ 2623 ifp->if_timer = 5; 2624 2625 return; 2626 } 2627 sc->need_mcsetup = 0; 2628 2629 /* 2630 * Initialize multicast setup descriptor. 2631 */ 2632 mcsp->cb_status = 0; 2633 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2634 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2635 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2636 txp = &sc->fxp_desc.mcs_tx; 2637 txp->tx_mbuf = NULL; 2638 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2639 txp->tx_next = sc->fxp_desc.tx_list; 2640 (void) fxp_mc_addrs(sc); 2641 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2642 sc->tx_queued = 1; 2643 2644 /* 2645 * Wait until command unit is not active. This should never 2646 * be the case when nothing is queued, but make sure anyway. 2647 */ 2648 count = 100; 2649 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2650 FXP_SCB_CUS_ACTIVE && --count) 2651 DELAY(10); 2652 if (count == 0) { 2653 device_printf(sc->dev, "command queue timeout\n"); 2654 return; 2655 } 2656 2657 /* 2658 * Start the multicast setup command. 2659 */ 2660 fxp_scb_wait(sc); 2661 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2662 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2663 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2664 2665 ifp->if_timer = 2; 2666 return; 2667 } 2668 2669 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2670 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2671 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2672 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2673 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2674 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2675 2676 #define UCODE(x) x, sizeof(x) 2677 2678 struct ucode { 2679 u_int32_t revision; 2680 u_int32_t *ucode; 2681 int length; 2682 u_short int_delay_offset; 2683 u_short bundle_max_offset; 2684 } ucode_table[] = { 2685 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2686 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2687 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2688 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2689 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2690 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2691 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2692 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2693 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2694 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2695 { 0, NULL, 0, 0, 0 } 2696 }; 2697 2698 static void 2699 fxp_load_ucode(struct fxp_softc *sc) 2700 { 2701 struct ucode *uc; 2702 struct fxp_cb_ucode *cbp; 2703 2704 for (uc = ucode_table; uc->ucode != NULL; uc++) 2705 if (sc->revision == uc->revision) 2706 break; 2707 if (uc->ucode == NULL) 2708 return; 2709 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2710 cbp->cb_status = 0; 2711 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2712 cbp->link_addr = 0xffffffff; /* (no) next command */ 2713 memcpy(cbp->ucode, uc->ucode, uc->length); 2714 if (uc->int_delay_offset) 2715 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2716 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2717 if (uc->bundle_max_offset) 2718 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2719 htole16(sc->tunable_bundle_max); 2720 /* 2721 * Download the ucode to the chip. 2722 */ 2723 fxp_scb_wait(sc); 2724 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2725 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2726 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2727 /* ...and wait for it to complete. */ 2728 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2729 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2730 device_printf(sc->dev, 2731 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2732 sc->tunable_int_delay, 2733 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2734 sc->flags |= FXP_FLAG_UCODE; 2735 } 2736 2737 static int 2738 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2739 { 2740 int error, value; 2741 2742 value = *(int *)arg1; 2743 error = sysctl_handle_int(oidp, &value, 0, req); 2744 if (error || !req->newptr) 2745 return (error); 2746 if (value < low || value > high) 2747 return (EINVAL); 2748 *(int *)arg1 = value; 2749 return (0); 2750 } 2751 2752 /* 2753 * Interrupt delay is expressed in microseconds, a multiplier is used 2754 * to convert this to the appropriate clock ticks before using. 2755 */ 2756 static int 2757 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2758 { 2759 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2760 } 2761 2762 static int 2763 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2764 { 2765 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2766 } 2767