1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/lock.h> 48 #include <sys/module.h> 49 #include <sys/mutex.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 #include <netinet/udp.h> 69 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 #include <machine/resource.h> 73 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/fxp/if_fxpreg.h> 81 #include <dev/fxp/if_fxpvar.h> 82 #include <dev/fxp/rcvbundl.h> 83 84 MODULE_DEPEND(fxp, pci, 1, 1, 1); 85 MODULE_DEPEND(fxp, ether, 1, 1, 1); 86 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 87 #include "miibus_if.h" 88 89 /* 90 * NOTE! On the Alpha, we have an alignment constraint. The 91 * card DMAs the packet immediately following the RFA. However, 92 * the first thing in the packet is a 14-byte Ethernet header. 93 * This means that the packet is misaligned. To compensate, 94 * we actually offset the RFA 2 bytes into the cluster. This 95 * alignes the packet after the Ethernet header at a 32-bit 96 * boundary. HOWEVER! This means that the RFA is misaligned! 97 */ 98 #define RFA_ALIGNMENT_FUDGE 2 99 100 /* 101 * Set initial transmit threshold at 64 (512 bytes). This is 102 * increased by 64 (512 bytes) at a time, to maximum of 192 103 * (1536 bytes), if an underrun occurs. 104 */ 105 static int tx_threshold = 64; 106 107 /* 108 * The configuration byte map has several undefined fields which 109 * must be one or must be zero. Set up a template for these bits 110 * only, (assuming a 82557 chip) leaving the actual configuration 111 * to fxp_init. 112 * 113 * See struct fxp_cb_config for the bit definitions. 114 */ 115 static u_char fxp_cb_config_template[] = { 116 0x0, 0x0, /* cb_status */ 117 0x0, 0x0, /* cb_command */ 118 0x0, 0x0, 0x0, 0x0, /* link_addr */ 119 0x0, /* 0 */ 120 0x0, /* 1 */ 121 0x0, /* 2 */ 122 0x0, /* 3 */ 123 0x0, /* 4 */ 124 0x0, /* 5 */ 125 0x32, /* 6 */ 126 0x0, /* 7 */ 127 0x0, /* 8 */ 128 0x0, /* 9 */ 129 0x6, /* 10 */ 130 0x0, /* 11 */ 131 0x0, /* 12 */ 132 0x0, /* 13 */ 133 0xf2, /* 14 */ 134 0x48, /* 15 */ 135 0x0, /* 16 */ 136 0x40, /* 17 */ 137 0xf0, /* 18 */ 138 0x0, /* 19 */ 139 0x3f, /* 20 */ 140 0x5 /* 21 */ 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" }, 170 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 171 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 172 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 173 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" }, 174 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" }, 175 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" }, 176 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 177 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" }, 178 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" }, 181 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" }, 183 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" }, 186 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" }, 187 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0d, 0, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" }, 190 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" }, 192 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" }, 193 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 194 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 195 { 0, -1, 0, NULL }, 196 }; 197 198 #ifdef FXP_IP_CSUM_WAR 199 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 200 #else 201 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 202 #endif 203 204 static int fxp_probe(device_t dev); 205 static int fxp_attach(device_t dev); 206 static int fxp_detach(device_t dev); 207 static int fxp_shutdown(device_t dev); 208 static int fxp_suspend(device_t dev); 209 static int fxp_resume(device_t dev); 210 211 static struct fxp_ident *fxp_find_ident(device_t dev); 212 static void fxp_intr(void *xsc); 213 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 214 struct mbuf *m, uint16_t status, int pos); 215 static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 216 uint8_t statack, int count); 217 static void fxp_init(void *xsc); 218 static void fxp_init_body(struct fxp_softc *sc); 219 static void fxp_tick(void *xsc); 220 static void fxp_start(struct ifnet *ifp); 221 static void fxp_start_body(struct ifnet *ifp); 222 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 223 static void fxp_txeof(struct fxp_softc *sc); 224 static void fxp_stop(struct fxp_softc *sc); 225 static void fxp_release(struct fxp_softc *sc); 226 static int fxp_ioctl(struct ifnet *ifp, u_long command, 227 caddr_t data); 228 static void fxp_watchdog(struct fxp_softc *sc); 229 static void fxp_add_rfabuf(struct fxp_softc *sc, 230 struct fxp_rx *rxp); 231 static void fxp_discard_rfabuf(struct fxp_softc *sc, 232 struct fxp_rx *rxp); 233 static int fxp_new_rfabuf(struct fxp_softc *sc, 234 struct fxp_rx *rxp); 235 static int fxp_mc_addrs(struct fxp_softc *sc); 236 static void fxp_mc_setup(struct fxp_softc *sc); 237 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 238 int autosize); 239 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 240 uint16_t data); 241 static void fxp_autosize_eeprom(struct fxp_softc *sc); 242 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 243 int offset, int words); 244 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 245 int offset, int words); 246 static int fxp_ifmedia_upd(struct ifnet *ifp); 247 static void fxp_ifmedia_sts(struct ifnet *ifp, 248 struct ifmediareq *ifmr); 249 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 250 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 251 struct ifmediareq *ifmr); 252 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 253 static int fxp_miibus_writereg(device_t dev, int phy, int reg, 254 int value); 255 static void fxp_load_ucode(struct fxp_softc *sc); 256 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 257 int low, int high); 258 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 259 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 260 static void fxp_scb_wait(struct fxp_softc *sc); 261 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 262 static void fxp_dma_wait(struct fxp_softc *sc, 263 volatile uint16_t *status, bus_dma_tag_t dmat, 264 bus_dmamap_t map); 265 266 static device_method_t fxp_methods[] = { 267 /* Device interface */ 268 DEVMETHOD(device_probe, fxp_probe), 269 DEVMETHOD(device_attach, fxp_attach), 270 DEVMETHOD(device_detach, fxp_detach), 271 DEVMETHOD(device_shutdown, fxp_shutdown), 272 DEVMETHOD(device_suspend, fxp_suspend), 273 DEVMETHOD(device_resume, fxp_resume), 274 275 /* MII interface */ 276 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 277 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 278 279 { 0, 0 } 280 }; 281 282 static driver_t fxp_driver = { 283 "fxp", 284 fxp_methods, 285 sizeof(struct fxp_softc), 286 }; 287 288 static devclass_t fxp_devclass; 289 290 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 291 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 292 293 static struct resource_spec fxp_res_spec_mem[] = { 294 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 295 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 296 { -1, 0 } 297 }; 298 299 static struct resource_spec fxp_res_spec_io[] = { 300 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 301 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 302 { -1, 0 } 303 }; 304 305 /* 306 * Wait for the previous command to be accepted (but not necessarily 307 * completed). 308 */ 309 static void 310 fxp_scb_wait(struct fxp_softc *sc) 311 { 312 union { 313 uint16_t w; 314 uint8_t b[2]; 315 } flowctl; 316 int i = 10000; 317 318 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 319 DELAY(2); 320 if (i == 0) { 321 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 322 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 323 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 324 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 325 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 326 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 327 } 328 } 329 330 static void 331 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 332 { 333 334 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 335 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 336 fxp_scb_wait(sc); 337 } 338 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 339 } 340 341 static void 342 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 343 bus_dma_tag_t dmat, bus_dmamap_t map) 344 { 345 int i; 346 347 for (i = 10000; i > 0; i--) { 348 DELAY(2); 349 bus_dmamap_sync(dmat, map, 350 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 351 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0) 352 break; 353 } 354 if (i == 0) 355 device_printf(sc->dev, "DMA timeout\n"); 356 } 357 358 static struct fxp_ident * 359 fxp_find_ident(device_t dev) 360 { 361 uint16_t devid; 362 uint8_t revid; 363 struct fxp_ident *ident; 364 365 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 366 devid = pci_get_device(dev); 367 revid = pci_get_revid(dev); 368 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 369 if (ident->devid == devid && 370 (ident->revid == revid || ident->revid == -1)) { 371 return (ident); 372 } 373 } 374 } 375 return (NULL); 376 } 377 378 /* 379 * Return identification string if this device is ours. 380 */ 381 static int 382 fxp_probe(device_t dev) 383 { 384 struct fxp_ident *ident; 385 386 ident = fxp_find_ident(dev); 387 if (ident != NULL) { 388 device_set_desc(dev, ident->name); 389 return (BUS_PROBE_DEFAULT); 390 } 391 return (ENXIO); 392 } 393 394 static void 395 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 396 { 397 uint32_t *addr; 398 399 if (error) 400 return; 401 402 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 403 addr = arg; 404 *addr = segs->ds_addr; 405 } 406 407 static int 408 fxp_attach(device_t dev) 409 { 410 struct fxp_softc *sc; 411 struct fxp_cb_tx *tcbp; 412 struct fxp_tx *txp; 413 struct fxp_rx *rxp; 414 struct ifnet *ifp; 415 uint32_t val; 416 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 417 u_char eaddr[ETHER_ADDR_LEN]; 418 int i, pmc, prefer_iomap; 419 int error; 420 421 error = 0; 422 sc = device_get_softc(dev); 423 sc->dev = dev; 424 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 425 MTX_DEF); 426 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 427 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 428 fxp_serial_ifmedia_sts); 429 430 ifp = sc->ifp = if_alloc(IFT_ETHER); 431 if (ifp == NULL) { 432 device_printf(dev, "can not if_alloc()\n"); 433 error = ENOSPC; 434 goto fail; 435 } 436 437 /* 438 * Enable bus mastering. 439 */ 440 pci_enable_busmaster(dev); 441 val = pci_read_config(dev, PCIR_COMMAND, 2); 442 443 /* 444 * Figure out which we should try first - memory mapping or i/o mapping? 445 * We default to memory mapping. Then we accept an override from the 446 * command line. Then we check to see which one is enabled. 447 */ 448 prefer_iomap = 0; 449 resource_int_value(device_get_name(dev), device_get_unit(dev), 450 "prefer_iomap", &prefer_iomap); 451 if (prefer_iomap) 452 sc->fxp_spec = fxp_res_spec_io; 453 else 454 sc->fxp_spec = fxp_res_spec_mem; 455 456 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 457 if (error) { 458 if (sc->fxp_spec == fxp_res_spec_mem) 459 sc->fxp_spec = fxp_res_spec_io; 460 else 461 sc->fxp_spec = fxp_res_spec_mem; 462 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 463 } 464 if (error) { 465 device_printf(dev, "could not allocate resources\n"); 466 error = ENXIO; 467 goto fail; 468 } 469 470 if (bootverbose) { 471 device_printf(dev, "using %s space register mapping\n", 472 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 473 } 474 475 /* 476 * Put CU/RU idle state and prepare full reset. 477 */ 478 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 479 DELAY(10); 480 /* Full reset and disable interrupts. */ 481 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 482 DELAY(10); 483 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 484 485 /* 486 * Find out how large of an SEEPROM we have. 487 */ 488 fxp_autosize_eeprom(sc); 489 490 /* 491 * Find out the chip revision; lump all 82557 revs together. 492 */ 493 sc->ident = fxp_find_ident(dev); 494 if (sc->ident->ich > 0) { 495 /* Assume ICH controllers are 82559. */ 496 sc->revision = FXP_REV_82559_A0; 497 } else { 498 fxp_read_eeprom(sc, &data, 5, 1); 499 if ((data >> 8) == 1) 500 sc->revision = FXP_REV_82557; 501 else 502 sc->revision = pci_get_revid(dev); 503 } 504 505 /* 506 * Check availability of WOL. 82559ER does not support WOL. 507 */ 508 if (sc->revision >= FXP_REV_82558_A4 && 509 sc->revision != FXP_REV_82559S_A) { 510 fxp_read_eeprom(sc, &data, 10, 1); 511 if ((data & 0x20) != 0 && 512 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) 513 sc->flags |= FXP_FLAG_WOLCAP; 514 } 515 516 /* Receiver lock-up workaround detection. */ 517 fxp_read_eeprom(sc, &data, 3, 1); 518 if ((data & 0x03) != 0x03) { 519 sc->flags |= FXP_FLAG_RXBUG; 520 device_printf(dev, "Enabling Rx lock-up workaround\n"); 521 } 522 523 /* 524 * Determine whether we must use the 503 serial interface. 525 */ 526 fxp_read_eeprom(sc, &data, 6, 1); 527 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 528 && (data & FXP_PHY_SERIAL_ONLY)) 529 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 530 531 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 533 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 534 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 535 "FXP driver receive interrupt microcode bundling delay"); 536 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 537 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 538 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 539 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 540 "FXP driver receive interrupt microcode bundle size limit"); 541 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 542 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 543 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 544 "FXP RNR events"); 545 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 546 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 547 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 548 "FXP flow control disabled"); 549 550 /* 551 * Pull in device tunables. 552 */ 553 sc->tunable_int_delay = TUNABLE_INT_DELAY; 554 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 555 sc->tunable_noflow = 1; 556 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 557 "int_delay", &sc->tunable_int_delay); 558 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 559 "bundle_max", &sc->tunable_bundle_max); 560 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 561 "noflow", &sc->tunable_noflow); 562 sc->rnr = 0; 563 564 /* 565 * Enable workarounds for certain chip revision deficiencies. 566 * 567 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 568 * some systems based a normal 82559 design, have a defect where 569 * the chip can cause a PCI protocol violation if it receives 570 * a CU_RESUME command when it is entering the IDLE state. The 571 * workaround is to disable Dynamic Standby Mode, so the chip never 572 * deasserts CLKRUN#, and always remains in an active state. 573 * 574 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 575 */ 576 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) || 577 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) { 578 fxp_read_eeprom(sc, &data, 10, 1); 579 if (data & 0x02) { /* STB enable */ 580 uint16_t cksum; 581 int i; 582 583 device_printf(dev, 584 "Disabling dynamic standby mode in EEPROM\n"); 585 data &= ~0x02; 586 fxp_write_eeprom(sc, &data, 10, 1); 587 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 588 cksum = 0; 589 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 590 fxp_read_eeprom(sc, &data, i, 1); 591 cksum += data; 592 } 593 i = (1 << sc->eeprom_size) - 1; 594 cksum = 0xBABA - cksum; 595 fxp_read_eeprom(sc, &data, i, 1); 596 fxp_write_eeprom(sc, &cksum, i, 1); 597 device_printf(dev, 598 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 599 i, data, cksum); 600 #if 1 601 /* 602 * If the user elects to continue, try the software 603 * workaround, as it is better than nothing. 604 */ 605 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 606 #endif 607 } 608 } 609 610 /* 611 * If we are not a 82557 chip, we can enable extended features. 612 */ 613 if (sc->revision != FXP_REV_82557) { 614 /* 615 * If MWI is enabled in the PCI configuration, and there 616 * is a valid cacheline size (8 or 16 dwords), then tell 617 * the board to turn on MWI. 618 */ 619 if (val & PCIM_CMD_MWRICEN && 620 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 621 sc->flags |= FXP_FLAG_MWI_ENABLE; 622 623 /* turn on the extended TxCB feature */ 624 sc->flags |= FXP_FLAG_EXT_TXCB; 625 626 /* enable reception of long frames for VLAN */ 627 sc->flags |= FXP_FLAG_LONG_PKT_EN; 628 } else { 629 /* a hack to get long VLAN frames on a 82557 */ 630 sc->flags |= FXP_FLAG_SAVE_BAD; 631 } 632 633 /* For 82559 or later chips, Rx checksum offload is supported. */ 634 if (sc->revision >= FXP_REV_82559_A0) { 635 /* 82559ER does not support Rx checksum offloading. */ 636 if (sc->ident->devid != 0x1209) 637 sc->flags |= FXP_FLAG_82559_RXCSUM; 638 } 639 /* 640 * Enable use of extended RFDs and TCBs for 82550 641 * and later chips. Note: we need extended TXCB support 642 * too, but that's already enabled by the code above. 643 * Be careful to do this only on the right devices. 644 */ 645 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 646 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 647 || sc->revision == FXP_REV_82551_10) { 648 sc->rfa_size = sizeof (struct fxp_rfa); 649 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 650 sc->flags |= FXP_FLAG_EXT_RFA; 651 /* Use extended RFA instead of 82559 checksum mode. */ 652 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 653 } else { 654 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 655 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 656 } 657 658 /* 659 * Allocate DMA tags and DMA safe memory. 660 */ 661 sc->maxtxseg = FXP_NTXSEG; 662 sc->maxsegsize = MCLBYTES; 663 if (sc->flags & FXP_FLAG_EXT_RFA) { 664 sc->maxtxseg--; 665 sc->maxsegsize = FXP_TSO_SEGSIZE; 666 } 667 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 668 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 669 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 670 sc->maxtxseg, sc->maxsegsize, 0, 671 busdma_lock_mutex, &Giant, &sc->fxp_txmtag); 672 if (error) { 673 device_printf(dev, "could not create TX DMA tag\n"); 674 goto fail; 675 } 676 677 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 678 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 679 MCLBYTES, 1, MCLBYTES, 0, 680 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag); 681 if (error) { 682 device_printf(dev, "could not create RX DMA tag\n"); 683 goto fail; 684 } 685 686 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 687 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 688 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 689 busdma_lock_mutex, &Giant, &sc->fxp_stag); 690 if (error) { 691 device_printf(dev, "could not create stats DMA tag\n"); 692 goto fail; 693 } 694 695 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 696 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 697 if (error) { 698 device_printf(dev, "could not allocate stats DMA memory\n"); 699 goto fail; 700 } 701 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 702 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 703 if (error) { 704 device_printf(dev, "could not load the stats DMA buffer\n"); 705 goto fail; 706 } 707 708 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 709 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 710 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 711 busdma_lock_mutex, &Giant, &sc->cbl_tag); 712 if (error) { 713 device_printf(dev, "could not create TxCB DMA tag\n"); 714 goto fail; 715 } 716 717 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 718 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 719 if (error) { 720 device_printf(dev, "could not allocate TxCB DMA memory\n"); 721 goto fail; 722 } 723 724 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 725 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 726 &sc->fxp_desc.cbl_addr, 0); 727 if (error) { 728 device_printf(dev, "could not load TxCB DMA buffer\n"); 729 goto fail; 730 } 731 732 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 733 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 734 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 735 busdma_lock_mutex, &Giant, &sc->mcs_tag); 736 if (error) { 737 device_printf(dev, 738 "could not create multicast setup DMA tag\n"); 739 goto fail; 740 } 741 742 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 743 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->mcs_map); 744 if (error) { 745 device_printf(dev, 746 "could not allocate multicast setup DMA memory\n"); 747 goto fail; 748 } 749 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 750 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 751 if (error) { 752 device_printf(dev, 753 "can't load the multicast setup DMA buffer\n"); 754 goto fail; 755 } 756 757 /* 758 * Pre-allocate the TX DMA maps and setup the pointers to 759 * the TX command blocks. 760 */ 761 txp = sc->fxp_desc.tx_list; 762 tcbp = sc->fxp_desc.cbl_list; 763 for (i = 0; i < FXP_NTXCB; i++) { 764 txp[i].tx_cb = tcbp + i; 765 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map); 766 if (error) { 767 device_printf(dev, "can't create DMA map for TX\n"); 768 goto fail; 769 } 770 } 771 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map); 772 if (error) { 773 device_printf(dev, "can't create spare DMA map\n"); 774 goto fail; 775 } 776 777 /* 778 * Pre-allocate our receive buffers. 779 */ 780 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 781 for (i = 0; i < FXP_NRFABUFS; i++) { 782 rxp = &sc->fxp_desc.rx_list[i]; 783 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map); 784 if (error) { 785 device_printf(dev, "can't create DMA map for RX\n"); 786 goto fail; 787 } 788 if (fxp_new_rfabuf(sc, rxp) != 0) { 789 error = ENOMEM; 790 goto fail; 791 } 792 fxp_add_rfabuf(sc, rxp); 793 } 794 795 /* 796 * Read MAC address. 797 */ 798 fxp_read_eeprom(sc, myea, 0, 3); 799 eaddr[0] = myea[0] & 0xff; 800 eaddr[1] = myea[0] >> 8; 801 eaddr[2] = myea[1] & 0xff; 802 eaddr[3] = myea[1] >> 8; 803 eaddr[4] = myea[2] & 0xff; 804 eaddr[5] = myea[2] >> 8; 805 if (bootverbose) { 806 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 807 pci_get_vendor(dev), pci_get_device(dev), 808 pci_get_subvendor(dev), pci_get_subdevice(dev), 809 pci_get_revid(dev)); 810 fxp_read_eeprom(sc, &data, 10, 1); 811 device_printf(dev, "Dynamic Standby mode is %s\n", 812 data & 0x02 ? "enabled" : "disabled"); 813 } 814 815 /* 816 * If this is only a 10Mbps device, then there is no MII, and 817 * the PHY will use a serial interface instead. 818 * 819 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 820 * doesn't have a programming interface of any sort. The 821 * media is sensed automatically based on how the link partner 822 * is configured. This is, in essence, manual configuration. 823 */ 824 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 825 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 826 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 827 } else { 828 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 829 fxp_ifmedia_sts)) { 830 device_printf(dev, "MII without any PHY!\n"); 831 error = ENXIO; 832 goto fail; 833 } 834 } 835 836 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 837 ifp->if_init = fxp_init; 838 ifp->if_softc = sc; 839 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 840 ifp->if_ioctl = fxp_ioctl; 841 ifp->if_start = fxp_start; 842 843 ifp->if_capabilities = ifp->if_capenable = 0; 844 845 /* Enable checksum offload/TSO for 82550 or better chips */ 846 if (sc->flags & FXP_FLAG_EXT_RFA) { 847 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 848 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 849 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 850 } 851 852 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 853 ifp->if_capabilities |= IFCAP_RXCSUM; 854 ifp->if_capenable |= IFCAP_RXCSUM; 855 } 856 857 if (sc->flags & FXP_FLAG_WOLCAP) { 858 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 859 ifp->if_capenable |= IFCAP_WOL_MAGIC; 860 } 861 862 #ifdef DEVICE_POLLING 863 /* Inform the world we support polling. */ 864 ifp->if_capabilities |= IFCAP_POLLING; 865 #endif 866 867 /* 868 * Attach the interface. 869 */ 870 ether_ifattach(ifp, eaddr); 871 872 /* 873 * Tell the upper layer(s) we support long frames. 874 * Must appear after the call to ether_ifattach() because 875 * ether_ifattach() sets ifi_hdrlen to the default value. 876 */ 877 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 878 ifp->if_capabilities |= IFCAP_VLAN_MTU; 879 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 880 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 881 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | 882 IFCAP_VLAN_HWCSUM; 883 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | 884 IFCAP_VLAN_HWCSUM; 885 } 886 887 /* 888 * Let the system queue as many packets as we have available 889 * TX descriptors. 890 */ 891 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 892 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 893 IFQ_SET_READY(&ifp->if_snd); 894 895 /* 896 * Hook our interrupt after all initialization is complete. 897 */ 898 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 899 NULL, fxp_intr, sc, &sc->ih); 900 if (error) { 901 device_printf(dev, "could not setup irq\n"); 902 ether_ifdetach(sc->ifp); 903 goto fail; 904 } 905 906 /* 907 * Configure hardware to reject magic frames otherwise 908 * system will hang on recipt of magic frames. 909 */ 910 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 911 FXP_LOCK(sc); 912 /* Clear wakeup events. */ 913 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 914 fxp_init_body(sc); 915 fxp_stop(sc); 916 FXP_UNLOCK(sc); 917 } 918 919 fail: 920 if (error) 921 fxp_release(sc); 922 return (error); 923 } 924 925 /* 926 * Release all resources. The softc lock should not be held and the 927 * interrupt should already be torn down. 928 */ 929 static void 930 fxp_release(struct fxp_softc *sc) 931 { 932 struct fxp_rx *rxp; 933 struct fxp_tx *txp; 934 int i; 935 936 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 937 KASSERT(sc->ih == NULL, 938 ("fxp_release() called with intr handle still active")); 939 if (sc->miibus) 940 device_delete_child(sc->dev, sc->miibus); 941 bus_generic_detach(sc->dev); 942 ifmedia_removeall(&sc->sc_media); 943 if (sc->fxp_desc.cbl_list) { 944 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 945 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 946 sc->cbl_map); 947 } 948 if (sc->fxp_stats) { 949 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 950 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 951 } 952 if (sc->mcsp) { 953 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 954 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 955 } 956 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 957 if (sc->fxp_rxmtag) { 958 for (i = 0; i < FXP_NRFABUFS; i++) { 959 rxp = &sc->fxp_desc.rx_list[i]; 960 if (rxp->rx_mbuf != NULL) { 961 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 962 BUS_DMASYNC_POSTREAD); 963 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 964 m_freem(rxp->rx_mbuf); 965 } 966 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map); 967 } 968 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map); 969 bus_dma_tag_destroy(sc->fxp_rxmtag); 970 } 971 if (sc->fxp_txmtag) { 972 for (i = 0; i < FXP_NTXCB; i++) { 973 txp = &sc->fxp_desc.tx_list[i]; 974 if (txp->tx_mbuf != NULL) { 975 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 976 BUS_DMASYNC_POSTWRITE); 977 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 978 m_freem(txp->tx_mbuf); 979 } 980 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map); 981 } 982 bus_dma_tag_destroy(sc->fxp_txmtag); 983 } 984 if (sc->fxp_stag) 985 bus_dma_tag_destroy(sc->fxp_stag); 986 if (sc->cbl_tag) 987 bus_dma_tag_destroy(sc->cbl_tag); 988 if (sc->mcs_tag) 989 bus_dma_tag_destroy(sc->mcs_tag); 990 if (sc->ifp) 991 if_free(sc->ifp); 992 993 mtx_destroy(&sc->sc_mtx); 994 } 995 996 /* 997 * Detach interface. 998 */ 999 static int 1000 fxp_detach(device_t dev) 1001 { 1002 struct fxp_softc *sc = device_get_softc(dev); 1003 1004 #ifdef DEVICE_POLLING 1005 if (sc->ifp->if_capenable & IFCAP_POLLING) 1006 ether_poll_deregister(sc->ifp); 1007 #endif 1008 1009 FXP_LOCK(sc); 1010 /* 1011 * Stop DMA and drop transmit queue, but disable interrupts first. 1012 */ 1013 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1014 fxp_stop(sc); 1015 FXP_UNLOCK(sc); 1016 callout_drain(&sc->stat_ch); 1017 1018 /* 1019 * Close down routes etc. 1020 */ 1021 ether_ifdetach(sc->ifp); 1022 1023 /* 1024 * Unhook interrupt before dropping lock. This is to prevent 1025 * races with fxp_intr(). 1026 */ 1027 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 1028 sc->ih = NULL; 1029 1030 /* Release our allocated resources. */ 1031 fxp_release(sc); 1032 return (0); 1033 } 1034 1035 /* 1036 * Device shutdown routine. Called at system shutdown after sync. The 1037 * main purpose of this routine is to shut off receiver DMA so that 1038 * kernel memory doesn't get clobbered during warmboot. 1039 */ 1040 static int 1041 fxp_shutdown(device_t dev) 1042 { 1043 1044 /* 1045 * Make sure that DMA is disabled prior to reboot. Not doing 1046 * do could allow DMA to corrupt kernel memory during the 1047 * reboot before the driver initializes. 1048 */ 1049 return (fxp_suspend(dev)); 1050 } 1051 1052 /* 1053 * Device suspend routine. Stop the interface and save some PCI 1054 * settings in case the BIOS doesn't restore them properly on 1055 * resume. 1056 */ 1057 static int 1058 fxp_suspend(device_t dev) 1059 { 1060 struct fxp_softc *sc = device_get_softc(dev); 1061 struct ifnet *ifp; 1062 int pmc; 1063 uint16_t pmstat; 1064 1065 FXP_LOCK(sc); 1066 1067 ifp = sc->ifp; 1068 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1069 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1070 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1071 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1072 /* Request PME. */ 1073 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1074 sc->flags |= FXP_FLAG_WOL; 1075 /* Reconfigure hardware to accept magic frames. */ 1076 fxp_init_body(sc); 1077 } 1078 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1079 } 1080 fxp_stop(sc); 1081 1082 sc->suspended = 1; 1083 1084 FXP_UNLOCK(sc); 1085 return (0); 1086 } 1087 1088 /* 1089 * Device resume routine. re-enable busmastering, and restart the interface if 1090 * appropriate. 1091 */ 1092 static int 1093 fxp_resume(device_t dev) 1094 { 1095 struct fxp_softc *sc = device_get_softc(dev); 1096 struct ifnet *ifp = sc->ifp; 1097 int pmc; 1098 uint16_t pmstat; 1099 1100 FXP_LOCK(sc); 1101 1102 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1103 sc->flags &= ~FXP_FLAG_WOL; 1104 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1105 /* Disable PME and clear PME status. */ 1106 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1107 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1108 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1109 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1110 CSR_READ_1(sc, FXP_CSR_PMDR)); 1111 } 1112 1113 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1114 DELAY(10); 1115 1116 /* reinitialize interface if necessary */ 1117 if (ifp->if_flags & IFF_UP) 1118 fxp_init_body(sc); 1119 1120 sc->suspended = 0; 1121 1122 FXP_UNLOCK(sc); 1123 return (0); 1124 } 1125 1126 static void 1127 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1128 { 1129 uint16_t reg; 1130 int x; 1131 1132 /* 1133 * Shift in data. 1134 */ 1135 for (x = 1 << (length - 1); x; x >>= 1) { 1136 if (data & x) 1137 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1138 else 1139 reg = FXP_EEPROM_EECS; 1140 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1141 DELAY(1); 1142 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1143 DELAY(1); 1144 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1145 DELAY(1); 1146 } 1147 } 1148 1149 /* 1150 * Read from the serial EEPROM. Basically, you manually shift in 1151 * the read opcode (one bit at a time) and then shift in the address, 1152 * and then you shift out the data (all of this one bit at a time). 1153 * The word size is 16 bits, so you have to provide the address for 1154 * every 16 bits of data. 1155 */ 1156 static uint16_t 1157 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1158 { 1159 uint16_t reg, data; 1160 int x; 1161 1162 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1163 /* 1164 * Shift in read opcode. 1165 */ 1166 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1167 /* 1168 * Shift in address. 1169 */ 1170 data = 0; 1171 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1172 if (offset & x) 1173 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1174 else 1175 reg = FXP_EEPROM_EECS; 1176 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1177 DELAY(1); 1178 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1179 DELAY(1); 1180 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1181 DELAY(1); 1182 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1183 data++; 1184 if (autosize && reg == 0) { 1185 sc->eeprom_size = data; 1186 break; 1187 } 1188 } 1189 /* 1190 * Shift out data. 1191 */ 1192 data = 0; 1193 reg = FXP_EEPROM_EECS; 1194 for (x = 1 << 15; x; x >>= 1) { 1195 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1196 DELAY(1); 1197 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1198 data |= x; 1199 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1200 DELAY(1); 1201 } 1202 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1203 DELAY(1); 1204 1205 return (data); 1206 } 1207 1208 static void 1209 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1210 { 1211 int i; 1212 1213 /* 1214 * Erase/write enable. 1215 */ 1216 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1217 fxp_eeprom_shiftin(sc, 0x4, 3); 1218 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1219 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1220 DELAY(1); 1221 /* 1222 * Shift in write opcode, address, data. 1223 */ 1224 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1225 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1226 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1227 fxp_eeprom_shiftin(sc, data, 16); 1228 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1229 DELAY(1); 1230 /* 1231 * Wait for EEPROM to finish up. 1232 */ 1233 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1234 DELAY(1); 1235 for (i = 0; i < 1000; i++) { 1236 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1237 break; 1238 DELAY(50); 1239 } 1240 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1241 DELAY(1); 1242 /* 1243 * Erase/write disable. 1244 */ 1245 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1246 fxp_eeprom_shiftin(sc, 0x4, 3); 1247 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1248 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1249 DELAY(1); 1250 } 1251 1252 /* 1253 * From NetBSD: 1254 * 1255 * Figure out EEPROM size. 1256 * 1257 * 559's can have either 64-word or 256-word EEPROMs, the 558 1258 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1259 * talks about the existance of 16 to 256 word EEPROMs. 1260 * 1261 * The only known sizes are 64 and 256, where the 256 version is used 1262 * by CardBus cards to store CIS information. 1263 * 1264 * The address is shifted in msb-to-lsb, and after the last 1265 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1266 * after which follows the actual data. We try to detect this zero, by 1267 * probing the data-out bit in the EEPROM control register just after 1268 * having shifted in a bit. If the bit is zero, we assume we've 1269 * shifted enough address bits. The data-out should be tri-state, 1270 * before this, which should translate to a logical one. 1271 */ 1272 static void 1273 fxp_autosize_eeprom(struct fxp_softc *sc) 1274 { 1275 1276 /* guess maximum size of 256 words */ 1277 sc->eeprom_size = 8; 1278 1279 /* autosize */ 1280 (void) fxp_eeprom_getword(sc, 0, 1); 1281 } 1282 1283 static void 1284 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1285 { 1286 int i; 1287 1288 for (i = 0; i < words; i++) 1289 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1290 } 1291 1292 static void 1293 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1294 { 1295 int i; 1296 1297 for (i = 0; i < words; i++) 1298 fxp_eeprom_putword(sc, offset + i, data[i]); 1299 } 1300 1301 /* 1302 * Grab the softc lock and call the real fxp_start_body() routine 1303 */ 1304 static void 1305 fxp_start(struct ifnet *ifp) 1306 { 1307 struct fxp_softc *sc = ifp->if_softc; 1308 1309 FXP_LOCK(sc); 1310 fxp_start_body(ifp); 1311 FXP_UNLOCK(sc); 1312 } 1313 1314 /* 1315 * Start packet transmission on the interface. 1316 * This routine must be called with the softc lock held, and is an 1317 * internal entry point only. 1318 */ 1319 static void 1320 fxp_start_body(struct ifnet *ifp) 1321 { 1322 struct fxp_softc *sc = ifp->if_softc; 1323 struct mbuf *mb_head; 1324 int txqueued; 1325 1326 FXP_LOCK_ASSERT(sc, MA_OWNED); 1327 1328 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1329 IFF_DRV_RUNNING) 1330 return; 1331 1332 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1333 fxp_txeof(sc); 1334 /* 1335 * We're finished if there is nothing more to add to the list or if 1336 * we're all filled up with buffers to transmit. 1337 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1338 * a NOP command when needed. 1339 */ 1340 txqueued = 0; 1341 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1342 sc->tx_queued < FXP_NTXCB - 1) { 1343 1344 /* 1345 * Grab a packet to transmit. 1346 */ 1347 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1348 if (mb_head == NULL) 1349 break; 1350 1351 if (fxp_encap(sc, &mb_head)) { 1352 if (mb_head == NULL) 1353 break; 1354 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1355 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1356 } 1357 txqueued++; 1358 /* 1359 * Pass packet to bpf if there is a listener. 1360 */ 1361 BPF_MTAP(ifp, mb_head); 1362 } 1363 1364 /* 1365 * We're finished. If we added to the list, issue a RESUME to get DMA 1366 * going again if suspended. 1367 */ 1368 if (txqueued > 0) { 1369 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1371 fxp_scb_wait(sc); 1372 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1373 /* 1374 * Set a 5 second timer just in case we don't hear 1375 * from the card again. 1376 */ 1377 sc->watchdog_timer = 5; 1378 } 1379 } 1380 1381 static int 1382 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1383 { 1384 struct ifnet *ifp; 1385 struct mbuf *m; 1386 struct fxp_tx *txp; 1387 struct fxp_cb_tx *cbp; 1388 struct tcphdr *tcp; 1389 bus_dma_segment_t segs[FXP_NTXSEG]; 1390 int error, i, nseg, tcp_payload; 1391 1392 FXP_LOCK_ASSERT(sc, MA_OWNED); 1393 ifp = sc->ifp; 1394 1395 tcp_payload = 0; 1396 tcp = NULL; 1397 /* 1398 * Get pointer to next available tx desc. 1399 */ 1400 txp = sc->fxp_desc.tx_last->tx_next; 1401 1402 /* 1403 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1404 * Ethernet Controller Family Open Source Software 1405 * Developer Manual says: 1406 * Using software parsing is only allowed with legal 1407 * TCP/IP or UDP/IP packets. 1408 * ... 1409 * For all other datagrams, hardware parsing must 1410 * be used. 1411 * Software parsing appears to truncate ICMP and 1412 * fragmented UDP packets that contain one to three 1413 * bytes in the second (and final) mbuf of the packet. 1414 */ 1415 if (sc->flags & FXP_FLAG_EXT_RFA) 1416 txp->tx_cb->ipcb_ip_activation_high = 1417 FXP_IPCB_HARDWAREPARSING_ENABLE; 1418 1419 m = *m_head; 1420 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1421 /* 1422 * 82550/82551 requires ethernet/IP/TCP headers must be 1423 * contained in the first active transmit buffer. 1424 */ 1425 struct ether_header *eh; 1426 struct ip *ip; 1427 uint32_t ip_off, poff; 1428 1429 if (M_WRITABLE(*m_head) == 0) { 1430 /* Get a writable copy. */ 1431 m = m_dup(*m_head, M_DONTWAIT); 1432 m_freem(*m_head); 1433 if (m == NULL) { 1434 *m_head = NULL; 1435 return (ENOBUFS); 1436 } 1437 *m_head = m; 1438 } 1439 ip_off = sizeof(struct ether_header); 1440 m = m_pullup(*m_head, ip_off); 1441 if (m == NULL) { 1442 *m_head = NULL; 1443 return (ENOBUFS); 1444 } 1445 eh = mtod(m, struct ether_header *); 1446 /* Check the existence of VLAN tag. */ 1447 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1448 ip_off = sizeof(struct ether_vlan_header); 1449 m = m_pullup(m, ip_off); 1450 if (m == NULL) { 1451 *m_head = NULL; 1452 return (ENOBUFS); 1453 } 1454 } 1455 m = m_pullup(m, ip_off + sizeof(struct ip)); 1456 if (m == NULL) { 1457 *m_head = NULL; 1458 return (ENOBUFS); 1459 } 1460 ip = (struct ip *)(mtod(m, char *) + ip_off); 1461 poff = ip_off + (ip->ip_hl << 2); 1462 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1463 if (m == NULL) { 1464 *m_head = NULL; 1465 return (ENOBUFS); 1466 } 1467 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1468 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 1469 if (m == NULL) { 1470 *m_head = NULL; 1471 return (ENOBUFS); 1472 } 1473 1474 /* 1475 * Since 82550/82551 doesn't modify IP length and pseudo 1476 * checksum in the first frame driver should compute it. 1477 */ 1478 ip->ip_sum = 0; 1479 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1480 (tcp->th_off << 2)); 1481 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1482 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1483 m->m_pkthdr.tso_segsz)); 1484 /* Compute total TCP payload. */ 1485 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1486 tcp_payload -= tcp->th_off << 2; 1487 *m_head = m; 1488 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1489 /* 1490 * Deal with TCP/IP checksum offload. Note that 1491 * in order for TCP checksum offload to work, 1492 * the pseudo header checksum must have already 1493 * been computed and stored in the checksum field 1494 * in the TCP header. The stack should have 1495 * already done this for us. 1496 */ 1497 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1498 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1499 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1500 1501 #ifdef FXP_IP_CSUM_WAR 1502 /* 1503 * XXX The 82550 chip appears to have trouble 1504 * dealing with IP header checksums in very small 1505 * datagrams, namely fragments from 1 to 3 bytes 1506 * in size. For example, say you want to transmit 1507 * a UDP packet of 1473 bytes. The packet will be 1508 * fragmented over two IP datagrams, the latter 1509 * containing only one byte of data. The 82550 will 1510 * botch the header checksum on the 1-byte fragment. 1511 * As long as the datagram contains 4 or more bytes 1512 * of data, you're ok. 1513 * 1514 * The following code attempts to work around this 1515 * problem: if the datagram is less than 38 bytes 1516 * in size (14 bytes ether header, 20 bytes IP header, 1517 * plus 4 bytes of data), we punt and compute the IP 1518 * header checksum by hand. This workaround doesn't 1519 * work very well, however, since it can be fooled 1520 * by things like VLAN tags and IP options that make 1521 * the header sizes/offsets vary. 1522 */ 1523 1524 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1525 if (m->m_pkthdr.len < 38) { 1526 struct ip *ip; 1527 m->m_data += ETHER_HDR_LEN; 1528 ip = mtod(m, struct ip *); 1529 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1530 m->m_data -= ETHER_HDR_LEN; 1531 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1532 } else { 1533 txp->tx_cb->ipcb_ip_activation_high = 1534 FXP_IPCB_HARDWAREPARSING_ENABLE; 1535 txp->tx_cb->ipcb_ip_schedule |= 1536 FXP_IPCB_IP_CHECKSUM_ENABLE; 1537 } 1538 } 1539 #endif 1540 } 1541 1542 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, 1543 segs, &nseg, 0); 1544 if (error == EFBIG) { 1545 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1546 if (m == NULL) { 1547 m_freem(*m_head); 1548 *m_head = NULL; 1549 return (ENOMEM); 1550 } 1551 *m_head = m; 1552 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, 1553 *m_head, segs, &nseg, 0); 1554 if (error != 0) { 1555 m_freem(*m_head); 1556 *m_head = NULL; 1557 return (ENOMEM); 1558 } 1559 } else if (error != 0) 1560 return (error); 1561 if (nseg == 0) { 1562 m_freem(*m_head); 1563 *m_head = NULL; 1564 return (EIO); 1565 } 1566 1567 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1568 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1569 1570 cbp = txp->tx_cb; 1571 for (i = 0; i < nseg; i++) { 1572 /* 1573 * If this is an 82550/82551, then we're using extended 1574 * TxCBs _and_ we're using checksum offload. This means 1575 * that the TxCB is really an IPCB. One major difference 1576 * between the two is that with plain extended TxCBs, 1577 * the bottom half of the TxCB contains two entries from 1578 * the TBD array, whereas IPCBs contain just one entry: 1579 * one entry (8 bytes) has been sacrificed for the TCP/IP 1580 * checksum offload control bits. So to make things work 1581 * right, we have to start filling in the TBD array 1582 * starting from a different place depending on whether 1583 * the chip is an 82550/82551 or not. 1584 */ 1585 if (sc->flags & FXP_FLAG_EXT_RFA) { 1586 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1587 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1588 } else { 1589 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1590 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1591 } 1592 } 1593 if (sc->flags & FXP_FLAG_EXT_RFA) { 1594 /* Configure dynamic TBD for 82550/82551. */ 1595 cbp->tbd_number = 0xFF; 1596 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1597 } else 1598 cbp->tbd_number = nseg; 1599 /* Configure TSO. */ 1600 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1601 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1602 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1603 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1604 FXP_IPCB_IP_CHECKSUM_ENABLE | 1605 FXP_IPCB_TCP_PACKET | 1606 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1607 } 1608 /* Configure VLAN hardware tag insertion. */ 1609 if ((m->m_flags & M_VLANTAG) != 0) { 1610 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1611 txp->tx_cb->ipcb_ip_activation_high |= 1612 FXP_IPCB_INSERTVLAN_ENABLE; 1613 } 1614 1615 txp->tx_mbuf = m; 1616 txp->tx_cb->cb_status = 0; 1617 txp->tx_cb->byte_count = 0; 1618 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1619 txp->tx_cb->cb_command = 1620 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1621 FXP_CB_COMMAND_S); 1622 else 1623 txp->tx_cb->cb_command = 1624 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1625 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1626 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1627 txp->tx_cb->tx_threshold = tx_threshold; 1628 1629 /* 1630 * Advance the end of list forward. 1631 */ 1632 1633 #ifdef __alpha__ 1634 /* 1635 * On platforms which can't access memory in 16-bit 1636 * granularities, we must prevent the card from DMA'ing 1637 * up the status while we update the command field. 1638 * This could cause us to overwrite the completion status. 1639 * XXX This is probably bogus and we're _not_ looking 1640 * for atomicity here. 1641 */ 1642 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1643 htole16(FXP_CB_COMMAND_S)); 1644 #else 1645 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1646 #endif /*__alpha__*/ 1647 sc->fxp_desc.tx_last = txp; 1648 1649 /* 1650 * Advance the beginning of the list forward if there are 1651 * no other packets queued (when nothing is queued, tx_first 1652 * sits on the last TxCB that was sent out). 1653 */ 1654 if (sc->tx_queued == 0) 1655 sc->fxp_desc.tx_first = txp; 1656 1657 sc->tx_queued++; 1658 1659 return (0); 1660 } 1661 1662 #ifdef DEVICE_POLLING 1663 static poll_handler_t fxp_poll; 1664 1665 static int 1666 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1667 { 1668 struct fxp_softc *sc = ifp->if_softc; 1669 uint8_t statack; 1670 int rx_npkts = 0; 1671 1672 FXP_LOCK(sc); 1673 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1674 FXP_UNLOCK(sc); 1675 return (rx_npkts); 1676 } 1677 1678 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1679 FXP_SCB_STATACK_FR; 1680 if (cmd == POLL_AND_CHECK_STATUS) { 1681 uint8_t tmp; 1682 1683 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1684 if (tmp == 0xff || tmp == 0) { 1685 FXP_UNLOCK(sc); 1686 return (rx_npkts); /* nothing to do */ 1687 } 1688 tmp &= ~statack; 1689 /* ack what we can */ 1690 if (tmp != 0) 1691 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1692 statack |= tmp; 1693 } 1694 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1695 FXP_UNLOCK(sc); 1696 return (rx_npkts); 1697 } 1698 #endif /* DEVICE_POLLING */ 1699 1700 /* 1701 * Process interface interrupts. 1702 */ 1703 static void 1704 fxp_intr(void *xsc) 1705 { 1706 struct fxp_softc *sc = xsc; 1707 struct ifnet *ifp = sc->ifp; 1708 uint8_t statack; 1709 1710 FXP_LOCK(sc); 1711 if (sc->suspended) { 1712 FXP_UNLOCK(sc); 1713 return; 1714 } 1715 1716 #ifdef DEVICE_POLLING 1717 if (ifp->if_capenable & IFCAP_POLLING) { 1718 FXP_UNLOCK(sc); 1719 return; 1720 } 1721 #endif 1722 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1723 /* 1724 * It should not be possible to have all bits set; the 1725 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1726 * all bits are set, this may indicate that the card has 1727 * been physically ejected, so ignore it. 1728 */ 1729 if (statack == 0xff) { 1730 FXP_UNLOCK(sc); 1731 return; 1732 } 1733 1734 /* 1735 * First ACK all the interrupts in this pass. 1736 */ 1737 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1738 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1739 fxp_intr_body(sc, ifp, statack, -1); 1740 } 1741 FXP_UNLOCK(sc); 1742 } 1743 1744 static void 1745 fxp_txeof(struct fxp_softc *sc) 1746 { 1747 struct ifnet *ifp; 1748 struct fxp_tx *txp; 1749 1750 ifp = sc->ifp; 1751 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1752 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1753 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1754 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1755 txp = txp->tx_next) { 1756 if (txp->tx_mbuf != NULL) { 1757 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, 1758 BUS_DMASYNC_POSTWRITE); 1759 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map); 1760 m_freem(txp->tx_mbuf); 1761 txp->tx_mbuf = NULL; 1762 /* clear this to reset csum offload bits */ 1763 txp->tx_cb->tbd[0].tb_addr = 0; 1764 } 1765 sc->tx_queued--; 1766 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1767 } 1768 sc->fxp_desc.tx_first = txp; 1769 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 1770 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1771 if (sc->tx_queued == 0) 1772 sc->watchdog_timer = 0; 1773 } 1774 1775 static void 1776 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1777 uint16_t status, int pos) 1778 { 1779 struct ether_header *eh; 1780 struct ip *ip; 1781 struct udphdr *uh; 1782 int32_t hlen, len, pktlen, temp32; 1783 uint16_t csum, *opts; 1784 1785 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1786 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1787 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1788 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1789 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1790 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1791 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1792 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1793 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1794 CSUM_PSEUDO_HDR; 1795 m->m_pkthdr.csum_data = 0xffff; 1796 } 1797 } 1798 return; 1799 } 1800 1801 pktlen = m->m_pkthdr.len; 1802 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1803 return; 1804 eh = mtod(m, struct ether_header *); 1805 if (eh->ether_type != htons(ETHERTYPE_IP)) 1806 return; 1807 ip = (struct ip *)(eh + 1); 1808 if (ip->ip_v != IPVERSION) 1809 return; 1810 1811 hlen = ip->ip_hl << 2; 1812 pktlen -= sizeof(struct ether_header); 1813 if (hlen < sizeof(struct ip)) 1814 return; 1815 if (ntohs(ip->ip_len) < hlen) 1816 return; 1817 if (ntohs(ip->ip_len) != pktlen) 1818 return; 1819 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1820 return; /* can't handle fragmented packet */ 1821 1822 switch (ip->ip_p) { 1823 case IPPROTO_TCP: 1824 if (pktlen < (hlen + sizeof(struct tcphdr))) 1825 return; 1826 break; 1827 case IPPROTO_UDP: 1828 if (pktlen < (hlen + sizeof(struct udphdr))) 1829 return; 1830 uh = (struct udphdr *)((caddr_t)ip + hlen); 1831 if (uh->uh_sum == 0) 1832 return; /* no checksum */ 1833 break; 1834 default: 1835 return; 1836 } 1837 /* Extract computed checksum. */ 1838 csum = be16dec(mtod(m, char *) + pos); 1839 /* checksum fixup for IP options */ 1840 len = hlen - sizeof(struct ip); 1841 if (len > 0) { 1842 opts = (uint16_t *)(ip + 1); 1843 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1844 temp32 = csum - *opts; 1845 temp32 = (temp32 >> 16) + (temp32 & 65535); 1846 csum = temp32 & 65535; 1847 } 1848 } 1849 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1850 m->m_pkthdr.csum_data = csum; 1851 } 1852 1853 static int 1854 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1855 int count) 1856 { 1857 struct mbuf *m; 1858 struct fxp_rx *rxp; 1859 struct fxp_rfa *rfa; 1860 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1861 int rx_npkts; 1862 uint16_t status; 1863 1864 rx_npkts = 0; 1865 FXP_LOCK_ASSERT(sc, MA_OWNED); 1866 1867 if (rnr) 1868 sc->rnr++; 1869 #ifdef DEVICE_POLLING 1870 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1871 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1872 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1873 rnr = 1; 1874 } 1875 #endif 1876 1877 /* 1878 * Free any finished transmit mbuf chains. 1879 * 1880 * Handle the CNA event likt a CXTNO event. It used to 1881 * be that this event (control unit not ready) was not 1882 * encountered, but it is now with the SMPng modifications. 1883 * The exact sequence of events that occur when the interface 1884 * is brought up are different now, and if this event 1885 * goes unhandled, the configuration/rxfilter setup sequence 1886 * can stall for several seconds. The result is that no 1887 * packets go out onto the wire for about 5 to 10 seconds 1888 * after the interface is ifconfig'ed for the first time. 1889 */ 1890 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1891 fxp_txeof(sc); 1892 1893 /* 1894 * Try to start more packets transmitting. 1895 */ 1896 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1897 fxp_start_body(ifp); 1898 1899 /* 1900 * Just return if nothing happened on the receive side. 1901 */ 1902 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1903 return (rx_npkts); 1904 1905 /* 1906 * Process receiver interrupts. If a no-resource (RNR) 1907 * condition exists, get whatever packets we can and 1908 * re-start the receiver. 1909 * 1910 * When using polling, we do not process the list to completion, 1911 * so when we get an RNR interrupt we must defer the restart 1912 * until we hit the last buffer with the C bit set. 1913 * If we run out of cycles and rfa_headm has the C bit set, 1914 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1915 * that the info will be used in the subsequent polling cycle. 1916 */ 1917 for (;;) { 1918 rxp = sc->fxp_desc.rx_head; 1919 m = rxp->rx_mbuf; 1920 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1921 RFA_ALIGNMENT_FUDGE); 1922 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 1923 BUS_DMASYNC_POSTREAD); 1924 1925 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1926 if (count >= 0 && count-- == 0) { 1927 if (rnr) { 1928 /* Defer RNR processing until the next time. */ 1929 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1930 rnr = 0; 1931 } 1932 break; 1933 } 1934 #endif /* DEVICE_POLLING */ 1935 1936 status = le16toh(rfa->rfa_status); 1937 if ((status & FXP_RFA_STATUS_C) == 0) 1938 break; 1939 1940 /* 1941 * Advance head forward. 1942 */ 1943 sc->fxp_desc.rx_head = rxp->rx_next; 1944 1945 /* 1946 * Add a new buffer to the receive chain. 1947 * If this fails, the old buffer is recycled 1948 * instead. 1949 */ 1950 if (fxp_new_rfabuf(sc, rxp) == 0) { 1951 int total_len; 1952 1953 /* 1954 * Fetch packet length (the top 2 bits of 1955 * actual_size are flags set by the controller 1956 * upon completion), and drop the packet in case 1957 * of bogus length or CRC errors. 1958 */ 1959 total_len = le16toh(rfa->actual_size) & 0x3fff; 1960 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1961 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1962 /* Adjust for appended checksum bytes. */ 1963 total_len -= 2; 1964 } 1965 if (total_len < sizeof(struct ether_header) || 1966 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1967 sc->rfa_size || status & FXP_RFA_STATUS_CRC) { 1968 m_freem(m); 1969 continue; 1970 } 1971 1972 m->m_pkthdr.len = m->m_len = total_len; 1973 m->m_pkthdr.rcvif = ifp; 1974 1975 /* Do IP checksum checking. */ 1976 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1977 fxp_rxcsum(sc, ifp, m, status, total_len); 1978 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1979 (status & FXP_RFA_STATUS_VLAN) != 0) { 1980 m->m_pkthdr.ether_vtag = 1981 ntohs(rfa->rfax_vlan_id); 1982 m->m_flags |= M_VLANTAG; 1983 } 1984 /* 1985 * Drop locks before calling if_input() since it 1986 * may re-enter fxp_start() in the netisr case. 1987 * This would result in a lock reversal. Better 1988 * performance might be obtained by chaining all 1989 * packets received, dropping the lock, and then 1990 * calling if_input() on each one. 1991 */ 1992 FXP_UNLOCK(sc); 1993 (*ifp->if_input)(ifp, m); 1994 FXP_LOCK(sc); 1995 rx_npkts++; 1996 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1997 return (rx_npkts); 1998 } else { 1999 /* Reuse RFA and loaded DMA map. */ 2000 ifp->if_iqdrops++; 2001 fxp_discard_rfabuf(sc, rxp); 2002 } 2003 fxp_add_rfabuf(sc, rxp); 2004 } 2005 if (rnr) { 2006 fxp_scb_wait(sc); 2007 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2008 sc->fxp_desc.rx_head->rx_addr); 2009 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2010 } 2011 return (rx_npkts); 2012 } 2013 2014 /* 2015 * Update packet in/out/collision statistics. The i82557 doesn't 2016 * allow you to access these counters without doing a fairly 2017 * expensive DMA to get _all_ of the statistics it maintains, so 2018 * we do this operation here only once per second. The statistics 2019 * counters in the kernel are updated from the previous dump-stats 2020 * DMA and then a new dump-stats DMA is started. The on-chip 2021 * counters are zeroed when the DMA completes. If we can't start 2022 * the DMA immediately, we don't wait - we just prepare to read 2023 * them again next time. 2024 */ 2025 static void 2026 fxp_tick(void *xsc) 2027 { 2028 struct fxp_softc *sc = xsc; 2029 struct ifnet *ifp = sc->ifp; 2030 struct fxp_stats *sp = sc->fxp_stats; 2031 2032 FXP_LOCK_ASSERT(sc, MA_OWNED); 2033 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 2034 ifp->if_opackets += le32toh(sp->tx_good); 2035 ifp->if_collisions += le32toh(sp->tx_total_collisions); 2036 if (sp->rx_good) { 2037 ifp->if_ipackets += le32toh(sp->rx_good); 2038 sc->rx_idle_secs = 0; 2039 } else if (sc->flags & FXP_FLAG_RXBUG) { 2040 /* 2041 * Receiver's been idle for another second. 2042 */ 2043 sc->rx_idle_secs++; 2044 } 2045 ifp->if_ierrors += 2046 le32toh(sp->rx_crc_errors) + 2047 le32toh(sp->rx_alignment_errors) + 2048 le32toh(sp->rx_rnr_errors) + 2049 le32toh(sp->rx_overrun_errors); 2050 /* 2051 * If any transmit underruns occured, bump up the transmit 2052 * threshold by another 512 bytes (64 * 8). 2053 */ 2054 if (sp->tx_underruns) { 2055 ifp->if_oerrors += le32toh(sp->tx_underruns); 2056 if (tx_threshold < 192) 2057 tx_threshold += 64; 2058 } 2059 2060 /* 2061 * Release any xmit buffers that have completed DMA. This isn't 2062 * strictly necessary to do here, but it's advantagous for mbufs 2063 * with external storage to be released in a timely manner rather 2064 * than being defered for a potentially long time. This limits 2065 * the delay to a maximum of one second. 2066 */ 2067 fxp_txeof(sc); 2068 2069 /* 2070 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2071 * then assume the receiver has locked up and attempt to clear 2072 * the condition by reprogramming the multicast filter. This is 2073 * a work-around for a bug in the 82557 where the receiver locks 2074 * up if it gets certain types of garbage in the syncronization 2075 * bits prior to the packet header. This bug is supposed to only 2076 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2077 * mode as well (perhaps due to a 10/100 speed transition). 2078 */ 2079 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2080 sc->rx_idle_secs = 0; 2081 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2082 fxp_init_body(sc); 2083 return; 2084 } 2085 /* 2086 * If there is no pending command, start another stats 2087 * dump. Otherwise punt for now. 2088 */ 2089 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2090 /* 2091 * Start another stats dump. 2092 */ 2093 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2094 BUS_DMASYNC_PREREAD); 2095 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2096 } else { 2097 /* 2098 * A previous command is still waiting to be accepted. 2099 * Just zero our copy of the stats and wait for the 2100 * next timer event to update them. 2101 */ 2102 sp->tx_good = 0; 2103 sp->tx_underruns = 0; 2104 sp->tx_total_collisions = 0; 2105 2106 sp->rx_good = 0; 2107 sp->rx_crc_errors = 0; 2108 sp->rx_alignment_errors = 0; 2109 sp->rx_rnr_errors = 0; 2110 sp->rx_overrun_errors = 0; 2111 } 2112 if (sc->miibus != NULL) 2113 mii_tick(device_get_softc(sc->miibus)); 2114 2115 /* 2116 * Check that chip hasn't hung. 2117 */ 2118 fxp_watchdog(sc); 2119 2120 /* 2121 * Schedule another timeout one second from now. 2122 */ 2123 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2124 } 2125 2126 /* 2127 * Stop the interface. Cancels the statistics updater and resets 2128 * the interface. 2129 */ 2130 static void 2131 fxp_stop(struct fxp_softc *sc) 2132 { 2133 struct ifnet *ifp = sc->ifp; 2134 struct fxp_tx *txp; 2135 int i; 2136 2137 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2138 sc->watchdog_timer = 0; 2139 2140 /* 2141 * Cancel stats updater. 2142 */ 2143 callout_stop(&sc->stat_ch); 2144 2145 /* 2146 * Preserve PCI configuration, configure, IA/multicast 2147 * setup and put RU and CU into idle state. 2148 */ 2149 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2150 DELAY(50); 2151 /* Disable interrupts. */ 2152 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2153 2154 /* 2155 * Release any xmit buffers. 2156 */ 2157 txp = sc->fxp_desc.tx_list; 2158 if (txp != NULL) { 2159 for (i = 0; i < FXP_NTXCB; i++) { 2160 if (txp[i].tx_mbuf != NULL) { 2161 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map, 2162 BUS_DMASYNC_POSTWRITE); 2163 bus_dmamap_unload(sc->fxp_txmtag, 2164 txp[i].tx_map); 2165 m_freem(txp[i].tx_mbuf); 2166 txp[i].tx_mbuf = NULL; 2167 /* clear this to reset csum offload bits */ 2168 txp[i].tx_cb->tbd[0].tb_addr = 0; 2169 } 2170 } 2171 } 2172 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2173 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2174 sc->tx_queued = 0; 2175 } 2176 2177 /* 2178 * Watchdog/transmission transmit timeout handler. Called when a 2179 * transmission is started on the interface, but no interrupt is 2180 * received before the timeout. This usually indicates that the 2181 * card has wedged for some reason. 2182 */ 2183 static void 2184 fxp_watchdog(struct fxp_softc *sc) 2185 { 2186 2187 FXP_LOCK_ASSERT(sc, MA_OWNED); 2188 2189 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2190 return; 2191 2192 device_printf(sc->dev, "device timeout\n"); 2193 sc->ifp->if_oerrors++; 2194 2195 fxp_init_body(sc); 2196 } 2197 2198 /* 2199 * Acquire locks and then call the real initialization function. This 2200 * is necessary because ether_ioctl() calls if_init() and this would 2201 * result in mutex recursion if the mutex was held. 2202 */ 2203 static void 2204 fxp_init(void *xsc) 2205 { 2206 struct fxp_softc *sc = xsc; 2207 2208 FXP_LOCK(sc); 2209 fxp_init_body(sc); 2210 FXP_UNLOCK(sc); 2211 } 2212 2213 /* 2214 * Perform device initialization. This routine must be called with the 2215 * softc lock held. 2216 */ 2217 static void 2218 fxp_init_body(struct fxp_softc *sc) 2219 { 2220 struct ifnet *ifp = sc->ifp; 2221 struct fxp_cb_config *cbp; 2222 struct fxp_cb_ias *cb_ias; 2223 struct fxp_cb_tx *tcbp; 2224 struct fxp_tx *txp; 2225 int i, prm; 2226 2227 FXP_LOCK_ASSERT(sc, MA_OWNED); 2228 /* 2229 * Cancel any pending I/O 2230 */ 2231 fxp_stop(sc); 2232 2233 /* 2234 * Issue software reset, which also unloads the microcode. 2235 */ 2236 sc->flags &= ~FXP_FLAG_UCODE; 2237 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2238 DELAY(50); 2239 2240 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2241 2242 /* 2243 * Initialize base of CBL and RFA memory. Loading with zero 2244 * sets it up for regular linear addressing. 2245 */ 2246 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2247 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2248 2249 fxp_scb_wait(sc); 2250 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2251 2252 /* 2253 * Initialize base of dump-stats buffer. 2254 */ 2255 fxp_scb_wait(sc); 2256 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2257 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2258 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2259 2260 /* 2261 * Attempt to load microcode if requested. 2262 * For ICH based controllers do not load microcode. 2263 */ 2264 if (sc->ident->ich == 0) { 2265 if (ifp->if_flags & IFF_LINK0 && 2266 (sc->flags & FXP_FLAG_UCODE) == 0) 2267 fxp_load_ucode(sc); 2268 } 2269 2270 /* 2271 * Set IFF_ALLMULTI status. It's needed in configure action 2272 * command. 2273 */ 2274 fxp_mc_addrs(sc); 2275 2276 /* 2277 * We temporarily use memory that contains the TxCB list to 2278 * construct the config CB. The TxCB list memory is rebuilt 2279 * later. 2280 */ 2281 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2282 2283 /* 2284 * This bcopy is kind of disgusting, but there are a bunch of must be 2285 * zero and must be one bits in this structure and this is the easiest 2286 * way to initialize them all to proper values. 2287 */ 2288 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2289 2290 cbp->cb_status = 0; 2291 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2292 FXP_CB_COMMAND_EL); 2293 cbp->link_addr = 0xffffffff; /* (no) next command */ 2294 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2295 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2296 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2297 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2298 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2299 cbp->type_enable = 0; /* actually reserved */ 2300 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2301 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2302 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2303 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2304 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2305 cbp->late_scb = 0; /* (don't) defer SCB update */ 2306 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2307 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2308 cbp->ci_int = 1; /* interrupt on CU idle */ 2309 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2310 cbp->ext_stats_dis = 1; /* disable extended counters */ 2311 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2312 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2313 cbp->disc_short_rx = !prm; /* discard short packets */ 2314 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2315 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2316 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2317 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2318 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2319 cbp->csma_dis = 0; /* (don't) disable link */ 2320 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2321 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2322 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2323 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2324 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2325 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2326 cbp->nsai = 1; /* (don't) disable source addr insert */ 2327 cbp->preamble_length = 2; /* (7 byte) preamble */ 2328 cbp->loopback = 0; /* (don't) loopback */ 2329 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2330 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2331 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2332 cbp->promiscuous = prm; /* promiscuous mode */ 2333 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2334 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2335 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2336 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2337 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2338 2339 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2340 cbp->padding = 1; /* (do) pad short tx packets */ 2341 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2342 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2343 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2344 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2345 cbp->force_fdx = 0; /* (don't) force full duplex */ 2346 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2347 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2348 cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 2349 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2350 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2351 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2352 2353 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2354 /* 2355 * The 82557 has no hardware flow control, the values 2356 * below are the defaults for the chip. 2357 */ 2358 cbp->fc_delay_lsb = 0; 2359 cbp->fc_delay_msb = 0x40; 2360 cbp->pri_fc_thresh = 3; 2361 cbp->tx_fc_dis = 0; 2362 cbp->rx_fc_restop = 0; 2363 cbp->rx_fc_restart = 0; 2364 cbp->fc_filter = 0; 2365 cbp->pri_fc_loc = 1; 2366 } else { 2367 cbp->fc_delay_lsb = 0x1f; 2368 cbp->fc_delay_msb = 0x01; 2369 cbp->pri_fc_thresh = 3; 2370 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2371 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2372 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2373 cbp->fc_filter = !prm; /* drop FC frames to host */ 2374 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2375 } 2376 2377 /* 2378 * Start the config command/DMA. 2379 */ 2380 fxp_scb_wait(sc); 2381 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2383 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2384 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2385 /* ...and wait for it to complete. */ 2386 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2387 2388 /* 2389 * Now initialize the station address. Temporarily use the TxCB 2390 * memory area like we did above for the config CB. 2391 */ 2392 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2393 cb_ias->cb_status = 0; 2394 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2395 cb_ias->link_addr = 0xffffffff; 2396 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2397 2398 /* 2399 * Start the IAS (Individual Address Setup) command/DMA. 2400 */ 2401 fxp_scb_wait(sc); 2402 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2403 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2404 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2405 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2406 /* ...and wait for it to complete. */ 2407 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2408 2409 /* 2410 * Initialize the multicast address list. 2411 */ 2412 fxp_mc_setup(sc); 2413 2414 /* 2415 * Initialize transmit control block (TxCB) list. 2416 */ 2417 txp = sc->fxp_desc.tx_list; 2418 tcbp = sc->fxp_desc.cbl_list; 2419 bzero(tcbp, FXP_TXCB_SZ); 2420 for (i = 0; i < FXP_NTXCB; i++) { 2421 txp[i].tx_mbuf = NULL; 2422 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2423 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2424 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2425 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2426 if (sc->flags & FXP_FLAG_EXT_TXCB) 2427 tcbp[i].tbd_array_addr = 2428 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2429 else 2430 tcbp[i].tbd_array_addr = 2431 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2432 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2433 } 2434 /* 2435 * Set the suspend flag on the first TxCB and start the control 2436 * unit. It will execute the NOP and then suspend. 2437 */ 2438 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2439 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2440 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2441 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2442 sc->tx_queued = 1; 2443 2444 fxp_scb_wait(sc); 2445 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2446 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2447 2448 /* 2449 * Initialize receiver buffer area - RFA. 2450 */ 2451 fxp_scb_wait(sc); 2452 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2453 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2454 2455 /* 2456 * Set current media. 2457 */ 2458 if (sc->miibus != NULL) 2459 mii_mediachg(device_get_softc(sc->miibus)); 2460 2461 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2462 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2463 2464 /* 2465 * Enable interrupts. 2466 */ 2467 #ifdef DEVICE_POLLING 2468 /* 2469 * ... but only do that if we are not polling. And because (presumably) 2470 * the default is interrupts on, we need to disable them explicitly! 2471 */ 2472 if (ifp->if_capenable & IFCAP_POLLING ) 2473 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2474 else 2475 #endif /* DEVICE_POLLING */ 2476 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2477 2478 /* 2479 * Start stats updater. 2480 */ 2481 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2482 } 2483 2484 static int 2485 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2486 { 2487 2488 return (0); 2489 } 2490 2491 static void 2492 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2493 { 2494 2495 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2496 } 2497 2498 /* 2499 * Change media according to request. 2500 */ 2501 static int 2502 fxp_ifmedia_upd(struct ifnet *ifp) 2503 { 2504 struct fxp_softc *sc = ifp->if_softc; 2505 struct mii_data *mii; 2506 2507 mii = device_get_softc(sc->miibus); 2508 FXP_LOCK(sc); 2509 if (mii->mii_instance) { 2510 struct mii_softc *miisc; 2511 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2512 mii_phy_reset(miisc); 2513 } 2514 mii_mediachg(mii); 2515 FXP_UNLOCK(sc); 2516 return (0); 2517 } 2518 2519 /* 2520 * Notify the world which media we're using. 2521 */ 2522 static void 2523 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2524 { 2525 struct fxp_softc *sc = ifp->if_softc; 2526 struct mii_data *mii; 2527 2528 mii = device_get_softc(sc->miibus); 2529 FXP_LOCK(sc); 2530 mii_pollstat(mii); 2531 ifmr->ifm_active = mii->mii_media_active; 2532 ifmr->ifm_status = mii->mii_media_status; 2533 2534 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2535 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2536 sc->cu_resume_bug = 1; 2537 else 2538 sc->cu_resume_bug = 0; 2539 FXP_UNLOCK(sc); 2540 } 2541 2542 /* 2543 * Add a buffer to the end of the RFA buffer list. 2544 * Return 0 if successful, 1 for failure. A failure results in 2545 * reusing the RFA buffer. 2546 * The RFA struct is stuck at the beginning of mbuf cluster and the 2547 * data pointer is fixed up to point just past it. 2548 */ 2549 static int 2550 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2551 { 2552 struct mbuf *m; 2553 struct fxp_rfa *rfa; 2554 bus_dmamap_t tmp_map; 2555 int error; 2556 2557 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2558 if (m == NULL) 2559 return (ENOBUFS); 2560 2561 /* 2562 * Move the data pointer up so that the incoming data packet 2563 * will be 32-bit aligned. 2564 */ 2565 m->m_data += RFA_ALIGNMENT_FUDGE; 2566 2567 /* 2568 * Get a pointer to the base of the mbuf cluster and move 2569 * data start past it. 2570 */ 2571 rfa = mtod(m, struct fxp_rfa *); 2572 m->m_data += sc->rfa_size; 2573 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2574 2575 rfa->rfa_status = 0; 2576 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2577 rfa->actual_size = 0; 2578 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2579 sc->rfa_size; 2580 2581 /* 2582 * Initialize the rest of the RFA. Note that since the RFA 2583 * is misaligned, we cannot store values directly. We're thus 2584 * using the le32enc() function which handles endianness and 2585 * is also alignment-safe. 2586 */ 2587 le32enc(&rfa->link_addr, 0xffffffff); 2588 le32enc(&rfa->rbd_addr, 0xffffffff); 2589 2590 /* Map the RFA into DMA memory. */ 2591 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa, 2592 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2593 &rxp->rx_addr, 0); 2594 if (error) { 2595 m_freem(m); 2596 return (error); 2597 } 2598 2599 if (rxp->rx_mbuf != NULL) 2600 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map); 2601 tmp_map = sc->spare_map; 2602 sc->spare_map = rxp->rx_map; 2603 rxp->rx_map = tmp_map; 2604 rxp->rx_mbuf = m; 2605 2606 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2607 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2608 return (0); 2609 } 2610 2611 static void 2612 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2613 { 2614 struct fxp_rfa *p_rfa; 2615 struct fxp_rx *p_rx; 2616 2617 /* 2618 * If there are other buffers already on the list, attach this 2619 * one to the end by fixing up the tail to point to this one. 2620 */ 2621 if (sc->fxp_desc.rx_head != NULL) { 2622 p_rx = sc->fxp_desc.rx_tail; 2623 p_rfa = (struct fxp_rfa *) 2624 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2625 p_rx->rx_next = rxp; 2626 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2627 p_rfa->rfa_control = 0; 2628 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map, 2629 BUS_DMASYNC_PREWRITE); 2630 } else { 2631 rxp->rx_next = NULL; 2632 sc->fxp_desc.rx_head = rxp; 2633 } 2634 sc->fxp_desc.rx_tail = rxp; 2635 } 2636 2637 static void 2638 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2639 { 2640 struct mbuf *m; 2641 struct fxp_rfa *rfa; 2642 2643 m = rxp->rx_mbuf; 2644 m->m_data = m->m_ext.ext_buf; 2645 /* 2646 * Move the data pointer up so that the incoming data packet 2647 * will be 32-bit aligned. 2648 */ 2649 m->m_data += RFA_ALIGNMENT_FUDGE; 2650 2651 /* 2652 * Get a pointer to the base of the mbuf cluster and move 2653 * data start past it. 2654 */ 2655 rfa = mtod(m, struct fxp_rfa *); 2656 m->m_data += sc->rfa_size; 2657 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2658 2659 rfa->rfa_status = 0; 2660 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2661 rfa->actual_size = 0; 2662 2663 /* 2664 * Initialize the rest of the RFA. Note that since the RFA 2665 * is misaligned, we cannot store values directly. We're thus 2666 * using the le32enc() function which handles endianness and 2667 * is also alignment-safe. 2668 */ 2669 le32enc(&rfa->link_addr, 0xffffffff); 2670 le32enc(&rfa->rbd_addr, 0xffffffff); 2671 2672 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map, 2673 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2674 } 2675 2676 static int 2677 fxp_miibus_readreg(device_t dev, int phy, int reg) 2678 { 2679 struct fxp_softc *sc = device_get_softc(dev); 2680 int count = 10000; 2681 int value; 2682 2683 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2684 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2685 2686 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2687 && count--) 2688 DELAY(10); 2689 2690 if (count <= 0) 2691 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2692 2693 return (value & 0xffff); 2694 } 2695 2696 static int 2697 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2698 { 2699 struct fxp_softc *sc = device_get_softc(dev); 2700 int count = 10000; 2701 2702 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2703 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2704 (value & 0xffff)); 2705 2706 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2707 count--) 2708 DELAY(10); 2709 2710 if (count <= 0) 2711 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2712 return (0); 2713 } 2714 2715 static int 2716 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2717 { 2718 struct fxp_softc *sc = ifp->if_softc; 2719 struct ifreq *ifr = (struct ifreq *)data; 2720 struct mii_data *mii; 2721 int flag, mask, error = 0, reinit; 2722 2723 switch (command) { 2724 case SIOCSIFFLAGS: 2725 FXP_LOCK(sc); 2726 /* 2727 * If interface is marked up and not running, then start it. 2728 * If it is marked down and running, stop it. 2729 * XXX If it's up then re-initialize it. This is so flags 2730 * such as IFF_PROMISC are handled. 2731 */ 2732 if (ifp->if_flags & IFF_UP) { 2733 if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) && 2734 ((ifp->if_flags ^ sc->if_flags) & 2735 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) 2736 fxp_init_body(sc); 2737 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2738 fxp_init_body(sc); 2739 } else { 2740 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2741 fxp_stop(sc); 2742 } 2743 sc->if_flags = ifp->if_flags; 2744 FXP_UNLOCK(sc); 2745 break; 2746 2747 case SIOCADDMULTI: 2748 case SIOCDELMULTI: 2749 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2750 fxp_init(sc); 2751 break; 2752 2753 case SIOCSIFMEDIA: 2754 case SIOCGIFMEDIA: 2755 if (sc->miibus != NULL) { 2756 mii = device_get_softc(sc->miibus); 2757 error = ifmedia_ioctl(ifp, ifr, 2758 &mii->mii_media, command); 2759 } else { 2760 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2761 } 2762 break; 2763 2764 case SIOCSIFCAP: 2765 reinit = 0; 2766 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2767 #ifdef DEVICE_POLLING 2768 if (mask & IFCAP_POLLING) { 2769 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2770 error = ether_poll_register(fxp_poll, ifp); 2771 if (error) 2772 return(error); 2773 FXP_LOCK(sc); 2774 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2775 FXP_SCB_INTR_DISABLE); 2776 ifp->if_capenable |= IFCAP_POLLING; 2777 FXP_UNLOCK(sc); 2778 } else { 2779 error = ether_poll_deregister(ifp); 2780 /* Enable interrupts in any case */ 2781 FXP_LOCK(sc); 2782 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2783 ifp->if_capenable &= ~IFCAP_POLLING; 2784 FXP_UNLOCK(sc); 2785 } 2786 } 2787 #endif 2788 FXP_LOCK(sc); 2789 if ((mask & IFCAP_TXCSUM) != 0 && 2790 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2791 ifp->if_capenable ^= IFCAP_TXCSUM; 2792 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2793 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2794 else 2795 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2796 } 2797 if ((mask & IFCAP_RXCSUM) != 0 && 2798 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2799 ifp->if_capenable ^= IFCAP_RXCSUM; 2800 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2801 reinit++; 2802 } 2803 if ((mask & IFCAP_TSO4) != 0 && 2804 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2805 ifp->if_capenable ^= IFCAP_TSO4; 2806 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2807 ifp->if_hwassist |= CSUM_TSO; 2808 else 2809 ifp->if_hwassist &= ~CSUM_TSO; 2810 } 2811 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2812 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2813 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2814 if ((mask & IFCAP_VLAN_MTU) != 0 && 2815 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2816 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2817 if (sc->revision != FXP_REV_82557) 2818 flag = FXP_FLAG_LONG_PKT_EN; 2819 else /* a hack to get long frames on the old chip */ 2820 flag = FXP_FLAG_SAVE_BAD; 2821 sc->flags ^= flag; 2822 if (ifp->if_flags & IFF_UP) 2823 reinit++; 2824 } 2825 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2826 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2827 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2828 reinit++; 2829 } 2830 if (reinit > 0 && ifp->if_flags & IFF_UP) 2831 fxp_init_body(sc); 2832 FXP_UNLOCK(sc); 2833 VLAN_CAPABILITIES(ifp); 2834 break; 2835 2836 default: 2837 error = ether_ioctl(ifp, command, data); 2838 } 2839 return (error); 2840 } 2841 2842 /* 2843 * Fill in the multicast address list and return number of entries. 2844 */ 2845 static int 2846 fxp_mc_addrs(struct fxp_softc *sc) 2847 { 2848 struct fxp_cb_mcs *mcsp = sc->mcsp; 2849 struct ifnet *ifp = sc->ifp; 2850 struct ifmultiaddr *ifma; 2851 int nmcasts; 2852 2853 nmcasts = 0; 2854 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2855 if_maddr_rlock(ifp); 2856 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2857 if (ifma->ifma_addr->sa_family != AF_LINK) 2858 continue; 2859 if (nmcasts >= MAXMCADDR) { 2860 ifp->if_flags |= IFF_ALLMULTI; 2861 nmcasts = 0; 2862 break; 2863 } 2864 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2865 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2866 nmcasts++; 2867 } 2868 if_maddr_runlock(ifp); 2869 } 2870 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2871 return (nmcasts); 2872 } 2873 2874 /* 2875 * Program the multicast filter. 2876 * 2877 * We have an artificial restriction that the multicast setup command 2878 * must be the first command in the chain, so we take steps to ensure 2879 * this. By requiring this, it allows us to keep up the performance of 2880 * the pre-initialized command ring (esp. link pointers) by not actually 2881 * inserting the mcsetup command in the ring - i.e. its link pointer 2882 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2883 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2884 * lead into the regular TxCB ring when it completes. 2885 */ 2886 static void 2887 fxp_mc_setup(struct fxp_softc *sc) 2888 { 2889 struct fxp_cb_mcs *mcsp; 2890 int count; 2891 2892 FXP_LOCK_ASSERT(sc, MA_OWNED); 2893 2894 mcsp = sc->mcsp; 2895 mcsp->cb_status = 0; 2896 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2897 mcsp->link_addr = 0xffffffff; 2898 fxp_mc_addrs(sc); 2899 2900 /* 2901 * Wait until command unit is idle. This should never be the 2902 * case when nothing is queued, but make sure anyway. 2903 */ 2904 count = 100; 2905 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) != 2906 FXP_SCB_CUS_IDLE && --count) 2907 DELAY(10); 2908 if (count == 0) { 2909 device_printf(sc->dev, "command queue timeout\n"); 2910 return; 2911 } 2912 2913 /* 2914 * Start the multicast setup command. 2915 */ 2916 fxp_scb_wait(sc); 2917 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2918 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2919 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2920 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2921 /* ...and wait for it to complete. */ 2922 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2923 } 2924 2925 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2926 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2927 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2928 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2929 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2930 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2931 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2932 2933 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2934 2935 struct ucode { 2936 uint32_t revision; 2937 uint32_t *ucode; 2938 int length; 2939 u_short int_delay_offset; 2940 u_short bundle_max_offset; 2941 } ucode_table[] = { 2942 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2943 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2944 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2945 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2946 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2947 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2948 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2949 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2950 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2951 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2952 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2953 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2954 { 0, NULL, 0, 0, 0 } 2955 }; 2956 2957 static void 2958 fxp_load_ucode(struct fxp_softc *sc) 2959 { 2960 struct ucode *uc; 2961 struct fxp_cb_ucode *cbp; 2962 int i; 2963 2964 for (uc = ucode_table; uc->ucode != NULL; uc++) 2965 if (sc->revision == uc->revision) 2966 break; 2967 if (uc->ucode == NULL) 2968 return; 2969 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2970 cbp->cb_status = 0; 2971 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2972 cbp->link_addr = 0xffffffff; /* (no) next command */ 2973 for (i = 0; i < uc->length; i++) 2974 cbp->ucode[i] = htole32(uc->ucode[i]); 2975 if (uc->int_delay_offset) 2976 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2977 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2978 if (uc->bundle_max_offset) 2979 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2980 htole16(sc->tunable_bundle_max); 2981 /* 2982 * Download the ucode to the chip. 2983 */ 2984 fxp_scb_wait(sc); 2985 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, 2986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2987 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2988 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2989 /* ...and wait for it to complete. */ 2990 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2991 device_printf(sc->dev, 2992 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2993 sc->tunable_int_delay, 2994 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2995 sc->flags |= FXP_FLAG_UCODE; 2996 } 2997 2998 static int 2999 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3000 { 3001 int error, value; 3002 3003 value = *(int *)arg1; 3004 error = sysctl_handle_int(oidp, &value, 0, req); 3005 if (error || !req->newptr) 3006 return (error); 3007 if (value < low || value > high) 3008 return (EINVAL); 3009 *(int *)arg1 = value; 3010 return (0); 3011 } 3012 3013 /* 3014 * Interrupt delay is expressed in microseconds, a multiplier is used 3015 * to convert this to the appropriate clock ticks before using. 3016 */ 3017 static int 3018 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3019 { 3020 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3021 } 3022 3023 static int 3024 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3025 { 3026 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3027 } 3028