1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #ifdef HAVE_KERNEL_OPTION_HEADERS 38 #include "opt_device_polling.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/lock.h> 48 #include <sys/module.h> 49 #include <sys/mutex.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 #include <netinet/udp.h> 69 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 #include <machine/resource.h> 73 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/fxp/if_fxpreg.h> 81 #include <dev/fxp/if_fxpvar.h> 82 #include <dev/fxp/rcvbundl.h> 83 84 MODULE_DEPEND(fxp, pci, 1, 1, 1); 85 MODULE_DEPEND(fxp, ether, 1, 1, 1); 86 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 87 #include "miibus_if.h" 88 89 /* 90 * NOTE! On the Alpha, we have an alignment constraint. The 91 * card DMAs the packet immediately following the RFA. However, 92 * the first thing in the packet is a 14-byte Ethernet header. 93 * This means that the packet is misaligned. To compensate, 94 * we actually offset the RFA 2 bytes into the cluster. This 95 * alignes the packet after the Ethernet header at a 32-bit 96 * boundary. HOWEVER! This means that the RFA is misaligned! 97 */ 98 #define RFA_ALIGNMENT_FUDGE 2 99 100 /* 101 * Set initial transmit threshold at 64 (512 bytes). This is 102 * increased by 64 (512 bytes) at a time, to maximum of 192 103 * (1536 bytes), if an underrun occurs. 104 */ 105 static int tx_threshold = 64; 106 107 /* 108 * The configuration byte map has several undefined fields which 109 * must be one or must be zero. Set up a template for these bits 110 * only, (assuming a 82557 chip) leaving the actual configuration 111 * to fxp_init. 112 * 113 * See struct fxp_cb_config for the bit definitions. 114 */ 115 static u_char fxp_cb_config_template[] = { 116 0x0, 0x0, /* cb_status */ 117 0x0, 0x0, /* cb_command */ 118 0x0, 0x0, 0x0, 0x0, /* link_addr */ 119 0x0, /* 0 */ 120 0x0, /* 1 */ 121 0x0, /* 2 */ 122 0x0, /* 3 */ 123 0x0, /* 4 */ 124 0x0, /* 5 */ 125 0x32, /* 6 */ 126 0x0, /* 7 */ 127 0x0, /* 8 */ 128 0x0, /* 9 */ 129 0x6, /* 10 */ 130 0x0, /* 11 */ 131 0x0, /* 12 */ 132 0x0, /* 13 */ 133 0xf2, /* 14 */ 134 0x48, /* 15 */ 135 0x0, /* 16 */ 136 0x40, /* 17 */ 137 0xf0, /* 18 */ 138 0x0, /* 19 */ 139 0x3f, /* 20 */ 140 0x5 /* 21 */ 141 }; 142 143 struct fxp_ident { 144 uint16_t devid; 145 int16_t revid; /* -1 matches anything */ 146 char *name; 147 }; 148 149 /* 150 * Claim various Intel PCI device identifiers for this driver. The 151 * sub-vendor and sub-device field are extensively used to identify 152 * particular variants, but we don't currently differentiate between 153 * them. 154 */ 155 static struct fxp_ident fxp_ident_table[] = { 156 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 157 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 158 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 160 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 162 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 165 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 166 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 167 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 169 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 170 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 171 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 172 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 173 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 175 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 176 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 177 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 178 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 179 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 180 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 181 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 182 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 183 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 184 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 185 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 186 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 187 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 188 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 189 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 190 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 191 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 192 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 193 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 194 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 195 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 196 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 197 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 198 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 199 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 200 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 201 { 0, -1, NULL }, 202 }; 203 204 #ifdef FXP_IP_CSUM_WAR 205 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 206 #else 207 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 208 #endif 209 210 static int fxp_probe(device_t dev); 211 static int fxp_attach(device_t dev); 212 static int fxp_detach(device_t dev); 213 static int fxp_shutdown(device_t dev); 214 static int fxp_suspend(device_t dev); 215 static int fxp_resume(device_t dev); 216 217 static void fxp_intr(void *xsc); 218 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, 219 struct mbuf *m, uint16_t status, int pos); 220 static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 221 uint8_t statack, int count); 222 static void fxp_init(void *xsc); 223 static void fxp_init_body(struct fxp_softc *sc); 224 static void fxp_tick(void *xsc); 225 static void fxp_start(struct ifnet *ifp); 226 static void fxp_start_body(struct ifnet *ifp); 227 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head); 228 static void fxp_txeof(struct fxp_softc *sc); 229 static void fxp_stop(struct fxp_softc *sc); 230 static void fxp_release(struct fxp_softc *sc); 231 static int fxp_ioctl(struct ifnet *ifp, u_long command, 232 caddr_t data); 233 static void fxp_watchdog(struct fxp_softc *sc); 234 static void fxp_add_rfabuf(struct fxp_softc *sc, 235 struct fxp_rx *rxp); 236 static void fxp_discard_rfabuf(struct fxp_softc *sc, 237 struct fxp_rx *rxp); 238 static int fxp_new_rfabuf(struct fxp_softc *sc, 239 struct fxp_rx *rxp); 240 static int fxp_mc_addrs(struct fxp_softc *sc); 241 static void fxp_mc_setup(struct fxp_softc *sc); 242 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 243 int autosize); 244 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 245 uint16_t data); 246 static void fxp_autosize_eeprom(struct fxp_softc *sc); 247 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 248 int offset, int words); 249 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 250 int offset, int words); 251 static int fxp_ifmedia_upd(struct ifnet *ifp); 252 static void fxp_ifmedia_sts(struct ifnet *ifp, 253 struct ifmediareq *ifmr); 254 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 255 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 256 struct ifmediareq *ifmr); 257 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 258 static int fxp_miibus_writereg(device_t dev, int phy, int reg, 259 int value); 260 static void fxp_load_ucode(struct fxp_softc *sc); 261 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 262 int low, int high); 263 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 264 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 265 static void fxp_scb_wait(struct fxp_softc *sc); 266 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 267 static void fxp_dma_wait(struct fxp_softc *sc, 268 volatile uint16_t *status, bus_dma_tag_t dmat, 269 bus_dmamap_t map); 270 271 static device_method_t fxp_methods[] = { 272 /* Device interface */ 273 DEVMETHOD(device_probe, fxp_probe), 274 DEVMETHOD(device_attach, fxp_attach), 275 DEVMETHOD(device_detach, fxp_detach), 276 DEVMETHOD(device_shutdown, fxp_shutdown), 277 DEVMETHOD(device_suspend, fxp_suspend), 278 DEVMETHOD(device_resume, fxp_resume), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 282 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 283 284 { 0, 0 } 285 }; 286 287 static driver_t fxp_driver = { 288 "fxp", 289 fxp_methods, 290 sizeof(struct fxp_softc), 291 }; 292 293 static devclass_t fxp_devclass; 294 295 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 296 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 297 298 static struct resource_spec fxp_res_spec_mem[] = { 299 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 300 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 301 { -1, 0 } 302 }; 303 304 static struct resource_spec fxp_res_spec_io[] = { 305 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 306 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 307 { -1, 0 } 308 }; 309 310 /* 311 * Wait for the previous command to be accepted (but not necessarily 312 * completed). 313 */ 314 static void 315 fxp_scb_wait(struct fxp_softc *sc) 316 { 317 union { 318 uint16_t w; 319 uint8_t b[2]; 320 } flowctl; 321 int i = 10000; 322 323 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 324 DELAY(2); 325 if (i == 0) { 326 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 327 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 328 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 329 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 330 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 331 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 332 } 333 } 334 335 static void 336 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 337 { 338 339 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 340 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 341 fxp_scb_wait(sc); 342 } 343 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 344 } 345 346 static void 347 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 348 bus_dma_tag_t dmat, bus_dmamap_t map) 349 { 350 int i = 10000; 351 352 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 353 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 354 DELAY(2); 355 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 356 } 357 if (i == 0) 358 device_printf(sc->dev, "DMA timeout\n"); 359 } 360 361 /* 362 * Return identification string if this device is ours. 363 */ 364 static int 365 fxp_probe(device_t dev) 366 { 367 uint16_t devid; 368 uint8_t revid; 369 struct fxp_ident *ident; 370 371 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 372 devid = pci_get_device(dev); 373 revid = pci_get_revid(dev); 374 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 375 if (ident->devid == devid && 376 (ident->revid == revid || ident->revid == -1)) { 377 device_set_desc(dev, ident->name); 378 return (BUS_PROBE_DEFAULT); 379 } 380 } 381 } 382 return (ENXIO); 383 } 384 385 static void 386 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 387 { 388 uint32_t *addr; 389 390 if (error) 391 return; 392 393 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 394 addr = arg; 395 *addr = segs->ds_addr; 396 } 397 398 static int 399 fxp_attach(device_t dev) 400 { 401 struct fxp_softc *sc; 402 struct fxp_cb_tx *tcbp; 403 struct fxp_tx *txp; 404 struct fxp_rx *rxp; 405 struct ifnet *ifp; 406 uint32_t val; 407 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 408 u_char eaddr[ETHER_ADDR_LEN]; 409 int i, pmc, prefer_iomap; 410 int error; 411 412 error = 0; 413 sc = device_get_softc(dev); 414 sc->dev = dev; 415 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 416 MTX_DEF); 417 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 418 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 419 fxp_serial_ifmedia_sts); 420 421 ifp = sc->ifp = if_alloc(IFT_ETHER); 422 if (ifp == NULL) { 423 device_printf(dev, "can not if_alloc()\n"); 424 error = ENOSPC; 425 goto fail; 426 } 427 428 /* 429 * Enable bus mastering. 430 */ 431 pci_enable_busmaster(dev); 432 val = pci_read_config(dev, PCIR_COMMAND, 2); 433 434 /* 435 * Figure out which we should try first - memory mapping or i/o mapping? 436 * We default to memory mapping. Then we accept an override from the 437 * command line. Then we check to see which one is enabled. 438 */ 439 prefer_iomap = 0; 440 resource_int_value(device_get_name(dev), device_get_unit(dev), 441 "prefer_iomap", &prefer_iomap); 442 if (prefer_iomap) 443 sc->fxp_spec = fxp_res_spec_io; 444 else 445 sc->fxp_spec = fxp_res_spec_mem; 446 447 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 448 if (error) { 449 if (sc->fxp_spec == fxp_res_spec_mem) 450 sc->fxp_spec = fxp_res_spec_io; 451 else 452 sc->fxp_spec = fxp_res_spec_mem; 453 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 454 } 455 if (error) { 456 device_printf(dev, "could not allocate resources\n"); 457 error = ENXIO; 458 goto fail; 459 } 460 461 if (bootverbose) { 462 device_printf(dev, "using %s space register mapping\n", 463 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 464 } 465 466 /* 467 * Reset to a stable state. 468 */ 469 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 470 DELAY(10); 471 472 /* 473 * Find out how large of an SEEPROM we have. 474 */ 475 fxp_autosize_eeprom(sc); 476 477 /* 478 * Find out the chip revision; lump all 82557 revs together. 479 */ 480 fxp_read_eeprom(sc, &data, 5, 1); 481 if ((data >> 8) == 1) 482 sc->revision = FXP_REV_82557; 483 else 484 sc->revision = pci_get_revid(dev); 485 486 /* 487 * Check availability of WOL. 82559ER does not support WOL. 488 */ 489 if (sc->revision >= FXP_REV_82558_A4 && 490 sc->revision != FXP_REV_82559S_A) { 491 fxp_read_eeprom(sc, &data, 10, 1); 492 if ((data & 0x20) != 0 && 493 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) 494 sc->flags |= FXP_FLAG_WOLCAP; 495 } 496 497 /* 498 * Determine whether we must use the 503 serial interface. 499 */ 500 fxp_read_eeprom(sc, &data, 6, 1); 501 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 502 && (data & FXP_PHY_SERIAL_ONLY)) 503 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 504 505 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 506 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 507 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 508 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 509 "FXP driver receive interrupt microcode bundling delay"); 510 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 511 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 512 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 513 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 514 "FXP driver receive interrupt microcode bundle size limit"); 515 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 516 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 517 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 518 "FXP RNR events"); 519 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 520 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 521 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 522 "FXP flow control disabled"); 523 524 /* 525 * Pull in device tunables. 526 */ 527 sc->tunable_int_delay = TUNABLE_INT_DELAY; 528 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 529 sc->tunable_noflow = 1; 530 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 531 "int_delay", &sc->tunable_int_delay); 532 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 533 "bundle_max", &sc->tunable_bundle_max); 534 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 535 "noflow", &sc->tunable_noflow); 536 sc->rnr = 0; 537 538 /* 539 * Enable workarounds for certain chip revision deficiencies. 540 * 541 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 542 * some systems based a normal 82559 design, have a defect where 543 * the chip can cause a PCI protocol violation if it receives 544 * a CU_RESUME command when it is entering the IDLE state. The 545 * workaround is to disable Dynamic Standby Mode, so the chip never 546 * deasserts CLKRUN#, and always remains in an active state. 547 * 548 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 549 */ 550 i = pci_get_device(dev); 551 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 552 sc->revision >= FXP_REV_82559_A0) { 553 fxp_read_eeprom(sc, &data, 10, 1); 554 if (data & 0x02) { /* STB enable */ 555 uint16_t cksum; 556 int i; 557 558 device_printf(dev, 559 "Disabling dynamic standby mode in EEPROM\n"); 560 data &= ~0x02; 561 fxp_write_eeprom(sc, &data, 10, 1); 562 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 563 cksum = 0; 564 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 565 fxp_read_eeprom(sc, &data, i, 1); 566 cksum += data; 567 } 568 i = (1 << sc->eeprom_size) - 1; 569 cksum = 0xBABA - cksum; 570 fxp_read_eeprom(sc, &data, i, 1); 571 fxp_write_eeprom(sc, &cksum, i, 1); 572 device_printf(dev, 573 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 574 i, data, cksum); 575 #if 1 576 /* 577 * If the user elects to continue, try the software 578 * workaround, as it is better than nothing. 579 */ 580 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 581 #endif 582 } 583 } 584 585 /* 586 * If we are not a 82557 chip, we can enable extended features. 587 */ 588 if (sc->revision != FXP_REV_82557) { 589 /* 590 * If MWI is enabled in the PCI configuration, and there 591 * is a valid cacheline size (8 or 16 dwords), then tell 592 * the board to turn on MWI. 593 */ 594 if (val & PCIM_CMD_MWRICEN && 595 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 596 sc->flags |= FXP_FLAG_MWI_ENABLE; 597 598 /* turn on the extended TxCB feature */ 599 sc->flags |= FXP_FLAG_EXT_TXCB; 600 601 /* enable reception of long frames for VLAN */ 602 sc->flags |= FXP_FLAG_LONG_PKT_EN; 603 } else { 604 /* a hack to get long VLAN frames on a 82557 */ 605 sc->flags |= FXP_FLAG_SAVE_BAD; 606 } 607 608 /* For 82559 or later chips, Rx checksum offload is supported. */ 609 if (sc->revision >= FXP_REV_82559_A0) 610 sc->flags |= FXP_FLAG_82559_RXCSUM; 611 /* 612 * Enable use of extended RFDs and TCBs for 82550 613 * and later chips. Note: we need extended TXCB support 614 * too, but that's already enabled by the code above. 615 * Be careful to do this only on the right devices. 616 */ 617 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 618 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 619 || sc->revision == FXP_REV_82551_10) { 620 sc->rfa_size = sizeof (struct fxp_rfa); 621 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 622 sc->flags |= FXP_FLAG_EXT_RFA; 623 /* Use extended RFA instead of 82559 checksum mode. */ 624 sc->flags &= ~FXP_FLAG_82559_RXCSUM; 625 } else { 626 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 627 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 628 } 629 630 /* 631 * Allocate DMA tags and DMA safe memory. 632 */ 633 sc->maxtxseg = FXP_NTXSEG; 634 sc->maxsegsize = MCLBYTES; 635 if (sc->flags & FXP_FLAG_EXT_RFA) { 636 sc->maxtxseg--; 637 sc->maxsegsize = FXP_TSO_SEGSIZE; 638 } 639 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 640 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 641 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header), 642 sc->maxtxseg, sc->maxsegsize, 0, 643 busdma_lock_mutex, &Giant, &sc->fxp_mtag); 644 if (error) { 645 device_printf(dev, "could not allocate dma tag\n"); 646 goto fail; 647 } 648 649 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 650 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 651 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, 652 busdma_lock_mutex, &Giant, &sc->fxp_stag); 653 if (error) { 654 device_printf(dev, "could not allocate dma tag\n"); 655 goto fail; 656 } 657 658 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 659 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 660 if (error) 661 goto fail; 662 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 663 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 664 if (error) { 665 device_printf(dev, "could not map the stats buffer\n"); 666 goto fail; 667 } 668 669 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 670 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 671 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, 672 busdma_lock_mutex, &Giant, &sc->cbl_tag); 673 if (error) { 674 device_printf(dev, "could not allocate dma tag\n"); 675 goto fail; 676 } 677 678 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 679 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 680 if (error) 681 goto fail; 682 683 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 684 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 685 &sc->fxp_desc.cbl_addr, 0); 686 if (error) { 687 device_printf(dev, "could not map DMA memory\n"); 688 goto fail; 689 } 690 691 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 692 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 693 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, 694 busdma_lock_mutex, &Giant, &sc->mcs_tag); 695 if (error) { 696 device_printf(dev, "could not allocate dma tag\n"); 697 goto fail; 698 } 699 700 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 701 BUS_DMA_NOWAIT, &sc->mcs_map); 702 if (error) 703 goto fail; 704 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 705 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 706 if (error) { 707 device_printf(dev, "can't map the multicast setup command\n"); 708 goto fail; 709 } 710 711 /* 712 * Pre-allocate the TX DMA maps and setup the pointers to 713 * the TX command blocks. 714 */ 715 txp = sc->fxp_desc.tx_list; 716 tcbp = sc->fxp_desc.cbl_list; 717 for (i = 0; i < FXP_NTXCB; i++) { 718 txp[i].tx_cb = tcbp + i; 719 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 720 if (error) { 721 device_printf(dev, "can't create DMA map for TX\n"); 722 goto fail; 723 } 724 } 725 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 726 if (error) { 727 device_printf(dev, "can't create spare DMA map\n"); 728 goto fail; 729 } 730 731 /* 732 * Pre-allocate our receive buffers. 733 */ 734 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 735 for (i = 0; i < FXP_NRFABUFS; i++) { 736 rxp = &sc->fxp_desc.rx_list[i]; 737 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 738 if (error) { 739 device_printf(dev, "can't create DMA map for RX\n"); 740 goto fail; 741 } 742 if (fxp_new_rfabuf(sc, rxp) != 0) { 743 error = ENOMEM; 744 goto fail; 745 } 746 fxp_add_rfabuf(sc, rxp); 747 } 748 749 /* 750 * Read MAC address. 751 */ 752 fxp_read_eeprom(sc, myea, 0, 3); 753 eaddr[0] = myea[0] & 0xff; 754 eaddr[1] = myea[0] >> 8; 755 eaddr[2] = myea[1] & 0xff; 756 eaddr[3] = myea[1] >> 8; 757 eaddr[4] = myea[2] & 0xff; 758 eaddr[5] = myea[2] >> 8; 759 if (bootverbose) { 760 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 761 pci_get_vendor(dev), pci_get_device(dev), 762 pci_get_subvendor(dev), pci_get_subdevice(dev), 763 pci_get_revid(dev)); 764 fxp_read_eeprom(sc, &data, 10, 1); 765 device_printf(dev, "Dynamic Standby mode is %s\n", 766 data & 0x02 ? "enabled" : "disabled"); 767 } 768 769 /* 770 * If this is only a 10Mbps device, then there is no MII, and 771 * the PHY will use a serial interface instead. 772 * 773 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 774 * doesn't have a programming interface of any sort. The 775 * media is sensed automatically based on how the link partner 776 * is configured. This is, in essence, manual configuration. 777 */ 778 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 779 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 780 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 781 } else { 782 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 783 fxp_ifmedia_sts)) { 784 device_printf(dev, "MII without any PHY!\n"); 785 error = ENXIO; 786 goto fail; 787 } 788 } 789 790 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 791 ifp->if_init = fxp_init; 792 ifp->if_softc = sc; 793 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 794 ifp->if_ioctl = fxp_ioctl; 795 ifp->if_start = fxp_start; 796 797 ifp->if_capabilities = ifp->if_capenable = 0; 798 799 /* Enable checksum offload/TSO for 82550 or better chips */ 800 if (sc->flags & FXP_FLAG_EXT_RFA) { 801 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO; 802 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 803 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4; 804 } 805 806 if (sc->flags & FXP_FLAG_82559_RXCSUM) { 807 ifp->if_capabilities |= IFCAP_RXCSUM; 808 ifp->if_capenable |= IFCAP_RXCSUM; 809 } 810 811 if (sc->flags & FXP_FLAG_WOLCAP) { 812 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 813 ifp->if_capenable |= IFCAP_WOL_MAGIC; 814 } 815 816 #ifdef DEVICE_POLLING 817 /* Inform the world we support polling. */ 818 ifp->if_capabilities |= IFCAP_POLLING; 819 #endif 820 821 /* 822 * Attach the interface. 823 */ 824 ether_ifattach(ifp, eaddr); 825 826 /* 827 * Tell the upper layer(s) we support long frames. 828 * Must appear after the call to ether_ifattach() because 829 * ether_ifattach() sets ifi_hdrlen to the default value. 830 */ 831 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 832 ifp->if_capabilities |= IFCAP_VLAN_MTU; 833 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 834 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) { 835 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | 836 IFCAP_VLAN_HWCSUM; 837 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | 838 IFCAP_VLAN_HWCSUM; 839 } 840 841 /* 842 * Let the system queue as many packets as we have available 843 * TX descriptors. 844 */ 845 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 846 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 847 IFQ_SET_READY(&ifp->if_snd); 848 849 /* 850 * Hook our interrupt after all initialization is complete. 851 */ 852 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 853 NULL, fxp_intr, sc, &sc->ih); 854 if (error) { 855 device_printf(dev, "could not setup irq\n"); 856 ether_ifdetach(sc->ifp); 857 goto fail; 858 } 859 860 /* 861 * Configure hardware to reject magic frames otherwise 862 * system will hang on recipt of magic frames. 863 */ 864 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) { 865 FXP_LOCK(sc); 866 /* Clear wakeup events. */ 867 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); 868 fxp_init_body(sc); 869 fxp_stop(sc); 870 FXP_UNLOCK(sc); 871 } 872 873 fail: 874 if (error) 875 fxp_release(sc); 876 return (error); 877 } 878 879 /* 880 * Release all resources. The softc lock should not be held and the 881 * interrupt should already be torn down. 882 */ 883 static void 884 fxp_release(struct fxp_softc *sc) 885 { 886 struct fxp_rx *rxp; 887 struct fxp_tx *txp; 888 int i; 889 890 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 891 KASSERT(sc->ih == NULL, 892 ("fxp_release() called with intr handle still active")); 893 if (sc->miibus) 894 device_delete_child(sc->dev, sc->miibus); 895 bus_generic_detach(sc->dev); 896 ifmedia_removeall(&sc->sc_media); 897 if (sc->fxp_desc.cbl_list) { 898 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 899 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 900 sc->cbl_map); 901 } 902 if (sc->fxp_stats) { 903 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 904 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 905 } 906 if (sc->mcsp) { 907 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 908 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 909 } 910 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 911 if (sc->fxp_mtag) { 912 for (i = 0; i < FXP_NRFABUFS; i++) { 913 rxp = &sc->fxp_desc.rx_list[i]; 914 if (rxp->rx_mbuf != NULL) { 915 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 916 BUS_DMASYNC_POSTREAD); 917 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 918 m_freem(rxp->rx_mbuf); 919 } 920 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 921 } 922 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 923 for (i = 0; i < FXP_NTXCB; i++) { 924 txp = &sc->fxp_desc.tx_list[i]; 925 if (txp->tx_mbuf != NULL) { 926 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 927 BUS_DMASYNC_POSTWRITE); 928 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 929 m_freem(txp->tx_mbuf); 930 } 931 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 932 } 933 bus_dma_tag_destroy(sc->fxp_mtag); 934 } 935 if (sc->fxp_stag) 936 bus_dma_tag_destroy(sc->fxp_stag); 937 if (sc->cbl_tag) 938 bus_dma_tag_destroy(sc->cbl_tag); 939 if (sc->mcs_tag) 940 bus_dma_tag_destroy(sc->mcs_tag); 941 if (sc->ifp) 942 if_free(sc->ifp); 943 944 mtx_destroy(&sc->sc_mtx); 945 } 946 947 /* 948 * Detach interface. 949 */ 950 static int 951 fxp_detach(device_t dev) 952 { 953 struct fxp_softc *sc = device_get_softc(dev); 954 955 #ifdef DEVICE_POLLING 956 if (sc->ifp->if_capenable & IFCAP_POLLING) 957 ether_poll_deregister(sc->ifp); 958 #endif 959 960 FXP_LOCK(sc); 961 sc->suspended = 1; /* Do same thing as we do for suspend */ 962 /* 963 * Stop DMA and drop transmit queue, but disable interrupts first. 964 */ 965 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 966 fxp_stop(sc); 967 FXP_UNLOCK(sc); 968 callout_drain(&sc->stat_ch); 969 970 /* 971 * Close down routes etc. 972 */ 973 ether_ifdetach(sc->ifp); 974 975 /* 976 * Unhook interrupt before dropping lock. This is to prevent 977 * races with fxp_intr(). 978 */ 979 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 980 sc->ih = NULL; 981 982 /* Release our allocated resources. */ 983 fxp_release(sc); 984 return (0); 985 } 986 987 /* 988 * Device shutdown routine. Called at system shutdown after sync. The 989 * main purpose of this routine is to shut off receiver DMA so that 990 * kernel memory doesn't get clobbered during warmboot. 991 */ 992 static int 993 fxp_shutdown(device_t dev) 994 { 995 996 /* 997 * Make sure that DMA is disabled prior to reboot. Not doing 998 * do could allow DMA to corrupt kernel memory during the 999 * reboot before the driver initializes. 1000 */ 1001 return (fxp_suspend(dev)); 1002 } 1003 1004 /* 1005 * Device suspend routine. Stop the interface and save some PCI 1006 * settings in case the BIOS doesn't restore them properly on 1007 * resume. 1008 */ 1009 static int 1010 fxp_suspend(device_t dev) 1011 { 1012 struct fxp_softc *sc = device_get_softc(dev); 1013 struct ifnet *ifp; 1014 int pmc; 1015 uint16_t pmstat; 1016 1017 FXP_LOCK(sc); 1018 1019 ifp = sc->ifp; 1020 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1021 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1022 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1023 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1024 /* Request PME. */ 1025 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1026 sc->flags |= FXP_FLAG_WOL; 1027 /* Reconfigure hardware to accept magic frames. */ 1028 fxp_init_body(sc); 1029 } 1030 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1031 } 1032 fxp_stop(sc); 1033 1034 sc->suspended = 1; 1035 1036 FXP_UNLOCK(sc); 1037 return (0); 1038 } 1039 1040 /* 1041 * Device resume routine. re-enable busmastering, and restart the interface if 1042 * appropriate. 1043 */ 1044 static int 1045 fxp_resume(device_t dev) 1046 { 1047 struct fxp_softc *sc = device_get_softc(dev); 1048 struct ifnet *ifp = sc->ifp; 1049 int pmc; 1050 uint16_t pmstat; 1051 1052 FXP_LOCK(sc); 1053 1054 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { 1055 sc->flags &= ~FXP_FLAG_WOL; 1056 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1057 /* Disable PME and clear PME status. */ 1058 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1059 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1060 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) 1061 CSR_WRITE_1(sc, FXP_CSR_PMDR, 1062 CSR_READ_1(sc, FXP_CSR_PMDR)); 1063 } 1064 1065 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1066 DELAY(10); 1067 1068 /* reinitialize interface if necessary */ 1069 if (ifp->if_flags & IFF_UP) 1070 fxp_init_body(sc); 1071 1072 sc->suspended = 0; 1073 1074 FXP_UNLOCK(sc); 1075 return (0); 1076 } 1077 1078 static void 1079 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1080 { 1081 uint16_t reg; 1082 int x; 1083 1084 /* 1085 * Shift in data. 1086 */ 1087 for (x = 1 << (length - 1); x; x >>= 1) { 1088 if (data & x) 1089 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1090 else 1091 reg = FXP_EEPROM_EECS; 1092 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1093 DELAY(1); 1094 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1095 DELAY(1); 1096 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1097 DELAY(1); 1098 } 1099 } 1100 1101 /* 1102 * Read from the serial EEPROM. Basically, you manually shift in 1103 * the read opcode (one bit at a time) and then shift in the address, 1104 * and then you shift out the data (all of this one bit at a time). 1105 * The word size is 16 bits, so you have to provide the address for 1106 * every 16 bits of data. 1107 */ 1108 static uint16_t 1109 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1110 { 1111 uint16_t reg, data; 1112 int x; 1113 1114 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1115 /* 1116 * Shift in read opcode. 1117 */ 1118 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1119 /* 1120 * Shift in address. 1121 */ 1122 data = 0; 1123 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1124 if (offset & x) 1125 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1126 else 1127 reg = FXP_EEPROM_EECS; 1128 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1129 DELAY(1); 1130 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1131 DELAY(1); 1132 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1133 DELAY(1); 1134 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1135 data++; 1136 if (autosize && reg == 0) { 1137 sc->eeprom_size = data; 1138 break; 1139 } 1140 } 1141 /* 1142 * Shift out data. 1143 */ 1144 data = 0; 1145 reg = FXP_EEPROM_EECS; 1146 for (x = 1 << 15; x; x >>= 1) { 1147 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1148 DELAY(1); 1149 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1150 data |= x; 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1152 DELAY(1); 1153 } 1154 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1155 DELAY(1); 1156 1157 return (data); 1158 } 1159 1160 static void 1161 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1162 { 1163 int i; 1164 1165 /* 1166 * Erase/write enable. 1167 */ 1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1169 fxp_eeprom_shiftin(sc, 0x4, 3); 1170 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1171 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1172 DELAY(1); 1173 /* 1174 * Shift in write opcode, address, data. 1175 */ 1176 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1177 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1178 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1179 fxp_eeprom_shiftin(sc, data, 16); 1180 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1181 DELAY(1); 1182 /* 1183 * Wait for EEPROM to finish up. 1184 */ 1185 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1186 DELAY(1); 1187 for (i = 0; i < 1000; i++) { 1188 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1189 break; 1190 DELAY(50); 1191 } 1192 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1193 DELAY(1); 1194 /* 1195 * Erase/write disable. 1196 */ 1197 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1198 fxp_eeprom_shiftin(sc, 0x4, 3); 1199 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1200 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1201 DELAY(1); 1202 } 1203 1204 /* 1205 * From NetBSD: 1206 * 1207 * Figure out EEPROM size. 1208 * 1209 * 559's can have either 64-word or 256-word EEPROMs, the 558 1210 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1211 * talks about the existance of 16 to 256 word EEPROMs. 1212 * 1213 * The only known sizes are 64 and 256, where the 256 version is used 1214 * by CardBus cards to store CIS information. 1215 * 1216 * The address is shifted in msb-to-lsb, and after the last 1217 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1218 * after which follows the actual data. We try to detect this zero, by 1219 * probing the data-out bit in the EEPROM control register just after 1220 * having shifted in a bit. If the bit is zero, we assume we've 1221 * shifted enough address bits. The data-out should be tri-state, 1222 * before this, which should translate to a logical one. 1223 */ 1224 static void 1225 fxp_autosize_eeprom(struct fxp_softc *sc) 1226 { 1227 1228 /* guess maximum size of 256 words */ 1229 sc->eeprom_size = 8; 1230 1231 /* autosize */ 1232 (void) fxp_eeprom_getword(sc, 0, 1); 1233 } 1234 1235 static void 1236 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1237 { 1238 int i; 1239 1240 for (i = 0; i < words; i++) 1241 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1242 } 1243 1244 static void 1245 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1246 { 1247 int i; 1248 1249 for (i = 0; i < words; i++) 1250 fxp_eeprom_putword(sc, offset + i, data[i]); 1251 } 1252 1253 /* 1254 * Grab the softc lock and call the real fxp_start_body() routine 1255 */ 1256 static void 1257 fxp_start(struct ifnet *ifp) 1258 { 1259 struct fxp_softc *sc = ifp->if_softc; 1260 1261 FXP_LOCK(sc); 1262 fxp_start_body(ifp); 1263 FXP_UNLOCK(sc); 1264 } 1265 1266 /* 1267 * Start packet transmission on the interface. 1268 * This routine must be called with the softc lock held, and is an 1269 * internal entry point only. 1270 */ 1271 static void 1272 fxp_start_body(struct ifnet *ifp) 1273 { 1274 struct fxp_softc *sc = ifp->if_softc; 1275 struct mbuf *mb_head; 1276 int txqueued; 1277 1278 FXP_LOCK_ASSERT(sc, MA_OWNED); 1279 1280 /* 1281 * See if we need to suspend xmit until the multicast filter 1282 * has been reprogrammed (which can only be done at the head 1283 * of the command chain). 1284 */ 1285 if (sc->need_mcsetup) 1286 return; 1287 1288 if (sc->tx_queued > FXP_NTXCB_HIWAT) 1289 fxp_txeof(sc); 1290 /* 1291 * We're finished if there is nothing more to add to the list or if 1292 * we're all filled up with buffers to transmit. 1293 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1294 * a NOP command when needed. 1295 */ 1296 txqueued = 0; 1297 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1298 sc->tx_queued < FXP_NTXCB - 1) { 1299 1300 /* 1301 * Grab a packet to transmit. 1302 */ 1303 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1304 if (mb_head == NULL) 1305 break; 1306 1307 if (fxp_encap(sc, &mb_head)) { 1308 if (mb_head == NULL) 1309 break; 1310 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 1311 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1312 } 1313 txqueued++; 1314 /* 1315 * Pass packet to bpf if there is a listener. 1316 */ 1317 BPF_MTAP(ifp, mb_head); 1318 } 1319 1320 /* 1321 * We're finished. If we added to the list, issue a RESUME to get DMA 1322 * going again if suspended. 1323 */ 1324 if (txqueued > 0) { 1325 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1326 fxp_scb_wait(sc); 1327 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1328 /* 1329 * Set a 5 second timer just in case we don't hear 1330 * from the card again. 1331 */ 1332 sc->watchdog_timer = 5; 1333 } 1334 } 1335 1336 static int 1337 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) 1338 { 1339 struct ifnet *ifp; 1340 struct mbuf *m; 1341 struct fxp_tx *txp; 1342 struct fxp_cb_tx *cbp; 1343 struct tcphdr *tcp; 1344 bus_dma_segment_t segs[FXP_NTXSEG]; 1345 int error, i, nseg, tcp_payload; 1346 1347 FXP_LOCK_ASSERT(sc, MA_OWNED); 1348 ifp = sc->ifp; 1349 1350 tcp_payload = 0; 1351 tcp = NULL; 1352 /* 1353 * Get pointer to next available tx desc. 1354 */ 1355 txp = sc->fxp_desc.tx_last->tx_next; 1356 1357 /* 1358 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1359 * Ethernet Controller Family Open Source Software 1360 * Developer Manual says: 1361 * Using software parsing is only allowed with legal 1362 * TCP/IP or UDP/IP packets. 1363 * ... 1364 * For all other datagrams, hardware parsing must 1365 * be used. 1366 * Software parsing appears to truncate ICMP and 1367 * fragmented UDP packets that contain one to three 1368 * bytes in the second (and final) mbuf of the packet. 1369 */ 1370 if (sc->flags & FXP_FLAG_EXT_RFA) 1371 txp->tx_cb->ipcb_ip_activation_high = 1372 FXP_IPCB_HARDWAREPARSING_ENABLE; 1373 1374 m = *m_head; 1375 /* 1376 * Deal with TCP/IP checksum offload. Note that 1377 * in order for TCP checksum offload to work, 1378 * the pseudo header checksum must have already 1379 * been computed and stored in the checksum field 1380 * in the TCP header. The stack should have 1381 * already done this for us. 1382 */ 1383 if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) { 1384 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1385 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1386 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; 1387 1388 #ifdef FXP_IP_CSUM_WAR 1389 /* 1390 * XXX The 82550 chip appears to have trouble 1391 * dealing with IP header checksums in very small 1392 * datagrams, namely fragments from 1 to 3 bytes 1393 * in size. For example, say you want to transmit 1394 * a UDP packet of 1473 bytes. The packet will be 1395 * fragmented over two IP datagrams, the latter 1396 * containing only one byte of data. The 82550 will 1397 * botch the header checksum on the 1-byte fragment. 1398 * As long as the datagram contains 4 or more bytes 1399 * of data, you're ok. 1400 * 1401 * The following code attempts to work around this 1402 * problem: if the datagram is less than 38 bytes 1403 * in size (14 bytes ether header, 20 bytes IP header, 1404 * plus 4 bytes of data), we punt and compute the IP 1405 * header checksum by hand. This workaround doesn't 1406 * work very well, however, since it can be fooled 1407 * by things like VLAN tags and IP options that make 1408 * the header sizes/offsets vary. 1409 */ 1410 1411 if (m->m_pkthdr.csum_flags & CSUM_IP) { 1412 if (m->m_pkthdr.len < 38) { 1413 struct ip *ip; 1414 m->m_data += ETHER_HDR_LEN; 1415 ip = mtod(m, struct ip *); 1416 ip->ip_sum = in_cksum(m, ip->ip_hl << 2); 1417 m->m_data -= ETHER_HDR_LEN; 1418 m->m_pkthdr.csum_flags &= ~CSUM_IP; 1419 } else { 1420 txp->tx_cb->ipcb_ip_activation_high = 1421 FXP_IPCB_HARDWAREPARSING_ENABLE; 1422 txp->tx_cb->ipcb_ip_schedule |= 1423 FXP_IPCB_IP_CHECKSUM_ENABLE; 1424 } 1425 } 1426 #endif 1427 } 1428 1429 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1430 /* 1431 * 82550/82551 requires ethernet/IP/TCP headers must be 1432 * contained in the first active transmit buffer. 1433 */ 1434 struct ether_header *eh; 1435 struct ip *ip; 1436 uint32_t ip_off, poff; 1437 1438 if (M_WRITABLE(*m_head) == 0) { 1439 /* Get a writable copy. */ 1440 m = m_dup(*m_head, M_DONTWAIT); 1441 m_freem(*m_head); 1442 if (m == NULL) { 1443 *m_head = NULL; 1444 return (ENOBUFS); 1445 } 1446 *m_head = m; 1447 } 1448 ip_off = sizeof(struct ether_header); 1449 m = m_pullup(*m_head, ip_off); 1450 if (m == NULL) { 1451 *m_head = NULL; 1452 return (ENOBUFS); 1453 } 1454 eh = mtod(m, struct ether_header *); 1455 /* Check the existence of VLAN tag. */ 1456 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1457 ip_off = sizeof(struct ether_vlan_header); 1458 m = m_pullup(m, ip_off); 1459 if (m == NULL) { 1460 *m_head = NULL; 1461 return (ENOBUFS); 1462 } 1463 } 1464 m = m_pullup(m, ip_off + sizeof(struct ip)); 1465 if (m == NULL) { 1466 *m_head = NULL; 1467 return (ENOBUFS); 1468 } 1469 ip = (struct ip *)(mtod(m, char *) + ip_off); 1470 poff = ip_off + (ip->ip_hl << 2); 1471 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1472 if (m == NULL) { 1473 *m_head = NULL; 1474 return (ENOBUFS); 1475 } 1476 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1477 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 1478 if (m == NULL) { 1479 *m_head = NULL; 1480 return (ENOBUFS); 1481 } 1482 1483 /* 1484 * Since 82550/82551 doesn't modify IP length and pseudo 1485 * checksum in the first frame driver should compute it. 1486 */ 1487 ip->ip_sum = 0; 1488 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) + 1489 (tcp->th_off << 2)); 1490 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1491 htons(IPPROTO_TCP + (tcp->th_off << 2) + 1492 m->m_pkthdr.tso_segsz)); 1493 /* Compute total TCP payload. */ 1494 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2); 1495 tcp_payload -= tcp->th_off << 2; 1496 *m_head = m; 1497 } 1498 1499 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, *m_head, 1500 segs, &nseg, 0); 1501 if (error == EFBIG) { 1502 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); 1503 if (m == NULL) { 1504 m_freem(*m_head); 1505 *m_head = NULL; 1506 return (ENOMEM); 1507 } 1508 *m_head = m; 1509 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1510 *m_head, segs, &nseg, 0); 1511 if (error != 0) { 1512 m_freem(*m_head); 1513 *m_head = NULL; 1514 return (ENOMEM); 1515 } 1516 } else if (error != 0) 1517 return (error); 1518 if (nseg == 0) { 1519 m_freem(*m_head); 1520 *m_head = NULL; 1521 return (EIO); 1522 } 1523 1524 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1525 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1526 1527 cbp = txp->tx_cb; 1528 for (i = 0; i < nseg; i++) { 1529 /* 1530 * If this is an 82550/82551, then we're using extended 1531 * TxCBs _and_ we're using checksum offload. This means 1532 * that the TxCB is really an IPCB. One major difference 1533 * between the two is that with plain extended TxCBs, 1534 * the bottom half of the TxCB contains two entries from 1535 * the TBD array, whereas IPCBs contain just one entry: 1536 * one entry (8 bytes) has been sacrificed for the TCP/IP 1537 * checksum offload control bits. So to make things work 1538 * right, we have to start filling in the TBD array 1539 * starting from a different place depending on whether 1540 * the chip is an 82550/82551 or not. 1541 */ 1542 if (sc->flags & FXP_FLAG_EXT_RFA) { 1543 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1544 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1545 } else { 1546 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1547 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1548 } 1549 } 1550 if (sc->flags & FXP_FLAG_EXT_RFA) { 1551 /* Configure dynamic TBD for 82550/82551. */ 1552 cbp->tbd_number = 0xFF; 1553 cbp->tbd[nseg].tb_size |= htole32(0x8000); 1554 } else 1555 cbp->tbd_number = nseg; 1556 /* Configure TSO. */ 1557 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1558 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16); 1559 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16); 1560 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE | 1561 FXP_IPCB_IP_CHECKSUM_ENABLE | 1562 FXP_IPCB_TCP_PACKET | 1563 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1564 } 1565 /* Configure VLAN hardware tag insertion. */ 1566 if ((m->m_flags & M_VLANTAG) != 0) { 1567 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag); 1568 txp->tx_cb->ipcb_ip_activation_high |= 1569 FXP_IPCB_INSERTVLAN_ENABLE; 1570 } 1571 1572 txp->tx_mbuf = m; 1573 txp->tx_cb->cb_status = 0; 1574 txp->tx_cb->byte_count = 0; 1575 if (sc->tx_queued != FXP_CXINT_THRESH - 1) 1576 txp->tx_cb->cb_command = 1577 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1578 FXP_CB_COMMAND_S); 1579 else 1580 txp->tx_cb->cb_command = 1581 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1582 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1583 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) 1584 txp->tx_cb->tx_threshold = tx_threshold; 1585 1586 /* 1587 * Advance the end of list forward. 1588 */ 1589 1590 #ifdef __alpha__ 1591 /* 1592 * On platforms which can't access memory in 16-bit 1593 * granularities, we must prevent the card from DMA'ing 1594 * up the status while we update the command field. 1595 * This could cause us to overwrite the completion status. 1596 * XXX This is probably bogus and we're _not_ looking 1597 * for atomicity here. 1598 */ 1599 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1600 htole16(FXP_CB_COMMAND_S)); 1601 #else 1602 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1603 #endif /*__alpha__*/ 1604 sc->fxp_desc.tx_last = txp; 1605 1606 /* 1607 * Advance the beginning of the list forward if there are 1608 * no other packets queued (when nothing is queued, tx_first 1609 * sits on the last TxCB that was sent out). 1610 */ 1611 if (sc->tx_queued == 0) 1612 sc->fxp_desc.tx_first = txp; 1613 1614 sc->tx_queued++; 1615 1616 return (0); 1617 } 1618 1619 #ifdef DEVICE_POLLING 1620 static poll_handler_t fxp_poll; 1621 1622 static int 1623 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1624 { 1625 struct fxp_softc *sc = ifp->if_softc; 1626 uint8_t statack; 1627 int rx_npkts = 0; 1628 1629 FXP_LOCK(sc); 1630 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1631 FXP_UNLOCK(sc); 1632 return (rx_npkts); 1633 } 1634 1635 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1636 FXP_SCB_STATACK_FR; 1637 if (cmd == POLL_AND_CHECK_STATUS) { 1638 uint8_t tmp; 1639 1640 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1641 if (tmp == 0xff || tmp == 0) { 1642 FXP_UNLOCK(sc); 1643 return (rx_npkts); /* nothing to do */ 1644 } 1645 tmp &= ~statack; 1646 /* ack what we can */ 1647 if (tmp != 0) 1648 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1649 statack |= tmp; 1650 } 1651 rx_npkts = fxp_intr_body(sc, ifp, statack, count); 1652 FXP_UNLOCK(sc); 1653 return (rx_npkts); 1654 } 1655 #endif /* DEVICE_POLLING */ 1656 1657 /* 1658 * Process interface interrupts. 1659 */ 1660 static void 1661 fxp_intr(void *xsc) 1662 { 1663 struct fxp_softc *sc = xsc; 1664 struct ifnet *ifp = sc->ifp; 1665 uint8_t statack; 1666 1667 FXP_LOCK(sc); 1668 if (sc->suspended) { 1669 FXP_UNLOCK(sc); 1670 return; 1671 } 1672 1673 #ifdef DEVICE_POLLING 1674 if (ifp->if_capenable & IFCAP_POLLING) { 1675 FXP_UNLOCK(sc); 1676 return; 1677 } 1678 #endif 1679 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1680 /* 1681 * It should not be possible to have all bits set; the 1682 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1683 * all bits are set, this may indicate that the card has 1684 * been physically ejected, so ignore it. 1685 */ 1686 if (statack == 0xff) { 1687 FXP_UNLOCK(sc); 1688 return; 1689 } 1690 1691 /* 1692 * First ACK all the interrupts in this pass. 1693 */ 1694 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1695 fxp_intr_body(sc, ifp, statack, -1); 1696 } 1697 FXP_UNLOCK(sc); 1698 } 1699 1700 static void 1701 fxp_txeof(struct fxp_softc *sc) 1702 { 1703 struct ifnet *ifp; 1704 struct fxp_tx *txp; 1705 1706 ifp = sc->ifp; 1707 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1708 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1709 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1710 txp = txp->tx_next) { 1711 if (txp->tx_mbuf != NULL) { 1712 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1713 BUS_DMASYNC_POSTWRITE); 1714 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1715 m_freem(txp->tx_mbuf); 1716 txp->tx_mbuf = NULL; 1717 /* clear this to reset csum offload bits */ 1718 txp->tx_cb->tbd[0].tb_addr = 0; 1719 } 1720 sc->tx_queued--; 1721 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1722 } 1723 sc->fxp_desc.tx_first = txp; 1724 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1725 if (sc->tx_queued == 0) { 1726 sc->watchdog_timer = 0; 1727 if (sc->need_mcsetup) 1728 fxp_mc_setup(sc); 1729 } 1730 } 1731 1732 static void 1733 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m, 1734 uint16_t status, int pos) 1735 { 1736 struct ether_header *eh; 1737 struct ip *ip; 1738 struct udphdr *uh; 1739 int32_t hlen, len, pktlen, temp32; 1740 uint16_t csum, *opts; 1741 1742 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) { 1743 if ((status & FXP_RFA_STATUS_PARSE) != 0) { 1744 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1745 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1746 if (status & FXP_RFDX_CS_IP_CSUM_VALID) 1747 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1748 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1749 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1750 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1751 CSUM_PSEUDO_HDR; 1752 m->m_pkthdr.csum_data = 0xffff; 1753 } 1754 } 1755 return; 1756 } 1757 1758 pktlen = m->m_pkthdr.len; 1759 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 1760 return; 1761 eh = mtod(m, struct ether_header *); 1762 if (eh->ether_type != htons(ETHERTYPE_IP)) 1763 return; 1764 ip = (struct ip *)(eh + 1); 1765 if (ip->ip_v != IPVERSION) 1766 return; 1767 1768 hlen = ip->ip_hl << 2; 1769 pktlen -= sizeof(struct ether_header); 1770 if (hlen < sizeof(struct ip)) 1771 return; 1772 if (ntohs(ip->ip_len) < hlen) 1773 return; 1774 if (ntohs(ip->ip_len) != pktlen) 1775 return; 1776 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1777 return; /* can't handle fragmented packet */ 1778 1779 switch (ip->ip_p) { 1780 case IPPROTO_TCP: 1781 if (pktlen < (hlen + sizeof(struct tcphdr))) 1782 return; 1783 break; 1784 case IPPROTO_UDP: 1785 if (pktlen < (hlen + sizeof(struct udphdr))) 1786 return; 1787 uh = (struct udphdr *)((caddr_t)ip + hlen); 1788 if (uh->uh_sum == 0) 1789 return; /* no checksum */ 1790 break; 1791 default: 1792 return; 1793 } 1794 /* Extract computed checksum. */ 1795 csum = be16dec(mtod(m, char *) + pos); 1796 /* checksum fixup for IP options */ 1797 len = hlen - sizeof(struct ip); 1798 if (len > 0) { 1799 opts = (uint16_t *)(ip + 1); 1800 for (; len > 0; len -= sizeof(uint16_t), opts++) { 1801 temp32 = csum - *opts; 1802 temp32 = (temp32 >> 16) + (temp32 & 65535); 1803 csum = temp32 & 65535; 1804 } 1805 } 1806 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1807 m->m_pkthdr.csum_data = csum; 1808 } 1809 1810 static int 1811 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1812 int count) 1813 { 1814 struct mbuf *m; 1815 struct fxp_rx *rxp; 1816 struct fxp_rfa *rfa; 1817 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1818 int rx_npkts; 1819 uint16_t status; 1820 1821 rx_npkts = 0; 1822 FXP_LOCK_ASSERT(sc, MA_OWNED); 1823 1824 if (rnr) 1825 sc->rnr++; 1826 #ifdef DEVICE_POLLING 1827 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1828 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1829 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1830 rnr = 1; 1831 } 1832 #endif 1833 1834 /* 1835 * Free any finished transmit mbuf chains. 1836 * 1837 * Handle the CNA event likt a CXTNO event. It used to 1838 * be that this event (control unit not ready) was not 1839 * encountered, but it is now with the SMPng modifications. 1840 * The exact sequence of events that occur when the interface 1841 * is brought up are different now, and if this event 1842 * goes unhandled, the configuration/rxfilter setup sequence 1843 * can stall for several seconds. The result is that no 1844 * packets go out onto the wire for about 5 to 10 seconds 1845 * after the interface is ifconfig'ed for the first time. 1846 */ 1847 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) 1848 fxp_txeof(sc); 1849 1850 /* 1851 * Try to start more packets transmitting. 1852 */ 1853 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1854 fxp_start_body(ifp); 1855 1856 /* 1857 * Just return if nothing happened on the receive side. 1858 */ 1859 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1860 return (rx_npkts); 1861 1862 /* 1863 * Process receiver interrupts. If a no-resource (RNR) 1864 * condition exists, get whatever packets we can and 1865 * re-start the receiver. 1866 * 1867 * When using polling, we do not process the list to completion, 1868 * so when we get an RNR interrupt we must defer the restart 1869 * until we hit the last buffer with the C bit set. 1870 * If we run out of cycles and rfa_headm has the C bit set, 1871 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1872 * that the info will be used in the subsequent polling cycle. 1873 */ 1874 for (;;) { 1875 rxp = sc->fxp_desc.rx_head; 1876 m = rxp->rx_mbuf; 1877 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1878 RFA_ALIGNMENT_FUDGE); 1879 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1880 BUS_DMASYNC_POSTREAD); 1881 1882 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1883 if (count >= 0 && count-- == 0) { 1884 if (rnr) { 1885 /* Defer RNR processing until the next time. */ 1886 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1887 rnr = 0; 1888 } 1889 break; 1890 } 1891 #endif /* DEVICE_POLLING */ 1892 1893 status = le16toh(rfa->rfa_status); 1894 if ((status & FXP_RFA_STATUS_C) == 0) 1895 break; 1896 1897 /* 1898 * Advance head forward. 1899 */ 1900 sc->fxp_desc.rx_head = rxp->rx_next; 1901 1902 /* 1903 * Add a new buffer to the receive chain. 1904 * If this fails, the old buffer is recycled 1905 * instead. 1906 */ 1907 if (fxp_new_rfabuf(sc, rxp) == 0) { 1908 int total_len; 1909 1910 /* 1911 * Fetch packet length (the top 2 bits of 1912 * actual_size are flags set by the controller 1913 * upon completion), and drop the packet in case 1914 * of bogus length or CRC errors. 1915 */ 1916 total_len = le16toh(rfa->actual_size) & 0x3fff; 1917 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 1918 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1919 /* Adjust for appended checksum bytes. */ 1920 total_len -= 2; 1921 } 1922 if (total_len < sizeof(struct ether_header) || 1923 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1924 sc->rfa_size || status & FXP_RFA_STATUS_CRC) { 1925 m_freem(m); 1926 continue; 1927 } 1928 1929 m->m_pkthdr.len = m->m_len = total_len; 1930 m->m_pkthdr.rcvif = ifp; 1931 1932 /* Do IP checksum checking. */ 1933 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1934 fxp_rxcsum(sc, ifp, m, status, total_len); 1935 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1936 (status & FXP_RFA_STATUS_VLAN) != 0) { 1937 m->m_pkthdr.ether_vtag = 1938 ntohs(rfa->rfax_vlan_id); 1939 m->m_flags |= M_VLANTAG; 1940 } 1941 /* 1942 * Drop locks before calling if_input() since it 1943 * may re-enter fxp_start() in the netisr case. 1944 * This would result in a lock reversal. Better 1945 * performance might be obtained by chaining all 1946 * packets received, dropping the lock, and then 1947 * calling if_input() on each one. 1948 */ 1949 FXP_UNLOCK(sc); 1950 (*ifp->if_input)(ifp, m); 1951 FXP_LOCK(sc); 1952 rx_npkts++; 1953 } else { 1954 /* Reuse RFA and loaded DMA map. */ 1955 ifp->if_iqdrops++; 1956 fxp_discard_rfabuf(sc, rxp); 1957 } 1958 fxp_add_rfabuf(sc, rxp); 1959 } 1960 if (rnr) { 1961 fxp_scb_wait(sc); 1962 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1963 sc->fxp_desc.rx_head->rx_addr); 1964 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1965 } 1966 return (rx_npkts); 1967 } 1968 1969 /* 1970 * Update packet in/out/collision statistics. The i82557 doesn't 1971 * allow you to access these counters without doing a fairly 1972 * expensive DMA to get _all_ of the statistics it maintains, so 1973 * we do this operation here only once per second. The statistics 1974 * counters in the kernel are updated from the previous dump-stats 1975 * DMA and then a new dump-stats DMA is started. The on-chip 1976 * counters are zeroed when the DMA completes. If we can't start 1977 * the DMA immediately, we don't wait - we just prepare to read 1978 * them again next time. 1979 */ 1980 static void 1981 fxp_tick(void *xsc) 1982 { 1983 struct fxp_softc *sc = xsc; 1984 struct ifnet *ifp = sc->ifp; 1985 struct fxp_stats *sp = sc->fxp_stats; 1986 1987 FXP_LOCK_ASSERT(sc, MA_OWNED); 1988 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1989 ifp->if_opackets += le32toh(sp->tx_good); 1990 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1991 if (sp->rx_good) { 1992 ifp->if_ipackets += le32toh(sp->rx_good); 1993 sc->rx_idle_secs = 0; 1994 } else { 1995 /* 1996 * Receiver's been idle for another second. 1997 */ 1998 sc->rx_idle_secs++; 1999 } 2000 ifp->if_ierrors += 2001 le32toh(sp->rx_crc_errors) + 2002 le32toh(sp->rx_alignment_errors) + 2003 le32toh(sp->rx_rnr_errors) + 2004 le32toh(sp->rx_overrun_errors); 2005 /* 2006 * If any transmit underruns occured, bump up the transmit 2007 * threshold by another 512 bytes (64 * 8). 2008 */ 2009 if (sp->tx_underruns) { 2010 ifp->if_oerrors += le32toh(sp->tx_underruns); 2011 if (tx_threshold < 192) 2012 tx_threshold += 64; 2013 } 2014 2015 /* 2016 * Release any xmit buffers that have completed DMA. This isn't 2017 * strictly necessary to do here, but it's advantagous for mbufs 2018 * with external storage to be released in a timely manner rather 2019 * than being defered for a potentially long time. This limits 2020 * the delay to a maximum of one second. 2021 */ 2022 fxp_txeof(sc); 2023 2024 /* 2025 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 2026 * then assume the receiver has locked up and attempt to clear 2027 * the condition by reprogramming the multicast filter. This is 2028 * a work-around for a bug in the 82557 where the receiver locks 2029 * up if it gets certain types of garbage in the syncronization 2030 * bits prior to the packet header. This bug is supposed to only 2031 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 2032 * mode as well (perhaps due to a 10/100 speed transition). 2033 */ 2034 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 2035 sc->rx_idle_secs = 0; 2036 fxp_mc_setup(sc); 2037 } 2038 /* 2039 * If there is no pending command, start another stats 2040 * dump. Otherwise punt for now. 2041 */ 2042 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 2043 /* 2044 * Start another stats dump. 2045 */ 2046 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 2047 BUS_DMASYNC_PREREAD); 2048 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 2049 } else { 2050 /* 2051 * A previous command is still waiting to be accepted. 2052 * Just zero our copy of the stats and wait for the 2053 * next timer event to update them. 2054 */ 2055 sp->tx_good = 0; 2056 sp->tx_underruns = 0; 2057 sp->tx_total_collisions = 0; 2058 2059 sp->rx_good = 0; 2060 sp->rx_crc_errors = 0; 2061 sp->rx_alignment_errors = 0; 2062 sp->rx_rnr_errors = 0; 2063 sp->rx_overrun_errors = 0; 2064 } 2065 if (sc->miibus != NULL) 2066 mii_tick(device_get_softc(sc->miibus)); 2067 2068 /* 2069 * Check that chip hasn't hung. 2070 */ 2071 fxp_watchdog(sc); 2072 2073 /* 2074 * Schedule another timeout one second from now. 2075 */ 2076 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2077 } 2078 2079 /* 2080 * Stop the interface. Cancels the statistics updater and resets 2081 * the interface. 2082 */ 2083 static void 2084 fxp_stop(struct fxp_softc *sc) 2085 { 2086 struct ifnet *ifp = sc->ifp; 2087 struct fxp_tx *txp; 2088 int i; 2089 2090 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2091 sc->watchdog_timer = 0; 2092 2093 /* 2094 * Cancel stats updater. 2095 */ 2096 callout_stop(&sc->stat_ch); 2097 2098 /* 2099 * Preserve PCI configuration, configure, IA/multicast 2100 * setup and put RU and CU into idle state. 2101 */ 2102 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 2103 DELAY(50); 2104 /* Disable interrupts. */ 2105 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2106 2107 /* 2108 * Release any xmit buffers. 2109 */ 2110 txp = sc->fxp_desc.tx_list; 2111 if (txp != NULL) { 2112 for (i = 0; i < FXP_NTXCB; i++) { 2113 if (txp[i].tx_mbuf != NULL) { 2114 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 2115 BUS_DMASYNC_POSTWRITE); 2116 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 2117 m_freem(txp[i].tx_mbuf); 2118 txp[i].tx_mbuf = NULL; 2119 /* clear this to reset csum offload bits */ 2120 txp[i].tx_cb->tbd[0].tb_addr = 0; 2121 } 2122 } 2123 } 2124 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2125 sc->tx_queued = 0; 2126 } 2127 2128 /* 2129 * Watchdog/transmission transmit timeout handler. Called when a 2130 * transmission is started on the interface, but no interrupt is 2131 * received before the timeout. This usually indicates that the 2132 * card has wedged for some reason. 2133 */ 2134 static void 2135 fxp_watchdog(struct fxp_softc *sc) 2136 { 2137 2138 FXP_LOCK_ASSERT(sc, MA_OWNED); 2139 2140 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 2141 return; 2142 2143 device_printf(sc->dev, "device timeout\n"); 2144 sc->ifp->if_oerrors++; 2145 2146 fxp_init_body(sc); 2147 } 2148 2149 /* 2150 * Acquire locks and then call the real initialization function. This 2151 * is necessary because ether_ioctl() calls if_init() and this would 2152 * result in mutex recursion if the mutex was held. 2153 */ 2154 static void 2155 fxp_init(void *xsc) 2156 { 2157 struct fxp_softc *sc = xsc; 2158 2159 FXP_LOCK(sc); 2160 fxp_init_body(sc); 2161 FXP_UNLOCK(sc); 2162 } 2163 2164 /* 2165 * Perform device initialization. This routine must be called with the 2166 * softc lock held. 2167 */ 2168 static void 2169 fxp_init_body(struct fxp_softc *sc) 2170 { 2171 struct ifnet *ifp = sc->ifp; 2172 struct fxp_cb_config *cbp; 2173 struct fxp_cb_ias *cb_ias; 2174 struct fxp_cb_tx *tcbp; 2175 struct fxp_tx *txp; 2176 struct fxp_cb_mcs *mcsp; 2177 int i, prm; 2178 2179 FXP_LOCK_ASSERT(sc, MA_OWNED); 2180 /* 2181 * Cancel any pending I/O 2182 */ 2183 fxp_stop(sc); 2184 2185 /* 2186 * Issue software reset, which also unloads the microcode. 2187 */ 2188 sc->flags &= ~FXP_FLAG_UCODE; 2189 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 2190 DELAY(50); 2191 2192 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 2193 2194 /* 2195 * Initialize base of CBL and RFA memory. Loading with zero 2196 * sets it up for regular linear addressing. 2197 */ 2198 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 2199 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 2200 2201 fxp_scb_wait(sc); 2202 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2203 2204 /* 2205 * Initialize base of dump-stats buffer. 2206 */ 2207 fxp_scb_wait(sc); 2208 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2209 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2210 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2211 2212 /* 2213 * Attempt to load microcode if requested. 2214 */ 2215 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2216 fxp_load_ucode(sc); 2217 2218 /* 2219 * Initialize the multicast address list. 2220 */ 2221 if (fxp_mc_addrs(sc)) { 2222 mcsp = sc->mcsp; 2223 mcsp->cb_status = 0; 2224 mcsp->cb_command = 2225 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2226 mcsp->link_addr = 0xffffffff; 2227 /* 2228 * Start the multicast setup command. 2229 */ 2230 fxp_scb_wait(sc); 2231 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2232 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2233 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2234 /* ...and wait for it to complete. */ 2235 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2236 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2237 BUS_DMASYNC_POSTWRITE); 2238 } 2239 2240 /* 2241 * We temporarily use memory that contains the TxCB list to 2242 * construct the config CB. The TxCB list memory is rebuilt 2243 * later. 2244 */ 2245 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2246 2247 /* 2248 * This bcopy is kind of disgusting, but there are a bunch of must be 2249 * zero and must be one bits in this structure and this is the easiest 2250 * way to initialize them all to proper values. 2251 */ 2252 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2253 2254 cbp->cb_status = 0; 2255 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2256 FXP_CB_COMMAND_EL); 2257 cbp->link_addr = 0xffffffff; /* (no) next command */ 2258 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2259 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2260 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2261 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2262 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2263 cbp->type_enable = 0; /* actually reserved */ 2264 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2265 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2266 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2267 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2268 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2269 cbp->late_scb = 0; /* (don't) defer SCB update */ 2270 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2271 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2272 cbp->ci_int = 1; /* interrupt on CU idle */ 2273 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2274 cbp->ext_stats_dis = 1; /* disable extended counters */ 2275 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2276 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2277 cbp->disc_short_rx = !prm; /* discard short packets */ 2278 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2279 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2280 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2281 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2282 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2283 cbp->csma_dis = 0; /* (don't) disable link */ 2284 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 && 2285 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0; 2286 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2287 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2288 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2289 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2290 cbp->nsai = 1; /* (don't) disable source addr insert */ 2291 cbp->preamble_length = 2; /* (7 byte) preamble */ 2292 cbp->loopback = 0; /* (don't) loopback */ 2293 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2294 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2295 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2296 cbp->promiscuous = prm; /* promiscuous mode */ 2297 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2298 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2299 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2300 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2301 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2302 2303 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2304 cbp->padding = 1; /* (do) pad short tx packets */ 2305 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2306 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2307 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2308 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1; 2309 cbp->force_fdx = 0; /* (don't) force full duplex */ 2310 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2311 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2312 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2313 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2314 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 && 2315 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0; 2316 2317 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2318 /* 2319 * The 82557 has no hardware flow control, the values 2320 * below are the defaults for the chip. 2321 */ 2322 cbp->fc_delay_lsb = 0; 2323 cbp->fc_delay_msb = 0x40; 2324 cbp->pri_fc_thresh = 3; 2325 cbp->tx_fc_dis = 0; 2326 cbp->rx_fc_restop = 0; 2327 cbp->rx_fc_restart = 0; 2328 cbp->fc_filter = 0; 2329 cbp->pri_fc_loc = 1; 2330 } else { 2331 cbp->fc_delay_lsb = 0x1f; 2332 cbp->fc_delay_msb = 0x01; 2333 cbp->pri_fc_thresh = 3; 2334 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2335 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2336 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2337 cbp->fc_filter = !prm; /* drop FC frames to host */ 2338 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2339 } 2340 2341 /* 2342 * Start the config command/DMA. 2343 */ 2344 fxp_scb_wait(sc); 2345 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2346 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2347 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2348 /* ...and wait for it to complete. */ 2349 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2350 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2351 2352 /* 2353 * Now initialize the station address. Temporarily use the TxCB 2354 * memory area like we did above for the config CB. 2355 */ 2356 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2357 cb_ias->cb_status = 0; 2358 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2359 cb_ias->link_addr = 0xffffffff; 2360 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN); 2361 2362 /* 2363 * Start the IAS (Individual Address Setup) command/DMA. 2364 */ 2365 fxp_scb_wait(sc); 2366 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2367 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2368 /* ...and wait for it to complete. */ 2369 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2370 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2371 2372 /* 2373 * Initialize transmit control block (TxCB) list. 2374 */ 2375 txp = sc->fxp_desc.tx_list; 2376 tcbp = sc->fxp_desc.cbl_list; 2377 bzero(tcbp, FXP_TXCB_SZ); 2378 for (i = 0; i < FXP_NTXCB; i++) { 2379 txp[i].tx_mbuf = NULL; 2380 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2381 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2382 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2383 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2384 if (sc->flags & FXP_FLAG_EXT_TXCB) 2385 tcbp[i].tbd_array_addr = 2386 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2387 else 2388 tcbp[i].tbd_array_addr = 2389 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2390 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2391 } 2392 /* 2393 * Set the suspend flag on the first TxCB and start the control 2394 * unit. It will execute the NOP and then suspend. 2395 */ 2396 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2397 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2398 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2399 sc->tx_queued = 1; 2400 2401 fxp_scb_wait(sc); 2402 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2403 2404 /* 2405 * Initialize receiver buffer area - RFA. 2406 */ 2407 fxp_scb_wait(sc); 2408 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2409 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2410 2411 /* 2412 * Set current media. 2413 */ 2414 if (sc->miibus != NULL) 2415 mii_mediachg(device_get_softc(sc->miibus)); 2416 2417 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2418 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2419 2420 /* 2421 * Enable interrupts. 2422 */ 2423 #ifdef DEVICE_POLLING 2424 /* 2425 * ... but only do that if we are not polling. And because (presumably) 2426 * the default is interrupts on, we need to disable them explicitly! 2427 */ 2428 if (ifp->if_capenable & IFCAP_POLLING ) 2429 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2430 else 2431 #endif /* DEVICE_POLLING */ 2432 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2433 2434 /* 2435 * Start stats updater. 2436 */ 2437 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2438 } 2439 2440 static int 2441 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2442 { 2443 2444 return (0); 2445 } 2446 2447 static void 2448 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2449 { 2450 2451 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2452 } 2453 2454 /* 2455 * Change media according to request. 2456 */ 2457 static int 2458 fxp_ifmedia_upd(struct ifnet *ifp) 2459 { 2460 struct fxp_softc *sc = ifp->if_softc; 2461 struct mii_data *mii; 2462 2463 mii = device_get_softc(sc->miibus); 2464 FXP_LOCK(sc); 2465 if (mii->mii_instance) { 2466 struct mii_softc *miisc; 2467 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2468 mii_phy_reset(miisc); 2469 } 2470 mii_mediachg(mii); 2471 FXP_UNLOCK(sc); 2472 return (0); 2473 } 2474 2475 /* 2476 * Notify the world which media we're using. 2477 */ 2478 static void 2479 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2480 { 2481 struct fxp_softc *sc = ifp->if_softc; 2482 struct mii_data *mii; 2483 2484 mii = device_get_softc(sc->miibus); 2485 FXP_LOCK(sc); 2486 mii_pollstat(mii); 2487 ifmr->ifm_active = mii->mii_media_active; 2488 ifmr->ifm_status = mii->mii_media_status; 2489 2490 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T && 2491 sc->flags & FXP_FLAG_CU_RESUME_BUG) 2492 sc->cu_resume_bug = 1; 2493 else 2494 sc->cu_resume_bug = 0; 2495 FXP_UNLOCK(sc); 2496 } 2497 2498 /* 2499 * Add a buffer to the end of the RFA buffer list. 2500 * Return 0 if successful, 1 for failure. A failure results in 2501 * reusing the RFA buffer. 2502 * The RFA struct is stuck at the beginning of mbuf cluster and the 2503 * data pointer is fixed up to point just past it. 2504 */ 2505 static int 2506 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2507 { 2508 struct mbuf *m; 2509 struct fxp_rfa *rfa; 2510 bus_dmamap_t tmp_map; 2511 int error; 2512 2513 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2514 if (m == NULL) 2515 return (ENOBUFS); 2516 2517 /* 2518 * Move the data pointer up so that the incoming data packet 2519 * will be 32-bit aligned. 2520 */ 2521 m->m_data += RFA_ALIGNMENT_FUDGE; 2522 2523 /* 2524 * Get a pointer to the base of the mbuf cluster and move 2525 * data start past it. 2526 */ 2527 rfa = mtod(m, struct fxp_rfa *); 2528 m->m_data += sc->rfa_size; 2529 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2530 2531 rfa->rfa_status = 0; 2532 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2533 rfa->actual_size = 0; 2534 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE - 2535 sc->rfa_size; 2536 2537 /* 2538 * Initialize the rest of the RFA. Note that since the RFA 2539 * is misaligned, we cannot store values directly. We're thus 2540 * using the le32enc() function which handles endianness and 2541 * is also alignment-safe. 2542 */ 2543 le32enc(&rfa->link_addr, 0xffffffff); 2544 le32enc(&rfa->rbd_addr, 0xffffffff); 2545 2546 /* Map the RFA into DMA memory. */ 2547 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2548 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2549 &rxp->rx_addr, 0); 2550 if (error) { 2551 m_freem(m); 2552 return (error); 2553 } 2554 2555 if (rxp->rx_mbuf != NULL) 2556 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2557 tmp_map = sc->spare_map; 2558 sc->spare_map = rxp->rx_map; 2559 rxp->rx_map = tmp_map; 2560 rxp->rx_mbuf = m; 2561 2562 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2563 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2564 return (0); 2565 } 2566 2567 static void 2568 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2569 { 2570 struct fxp_rfa *p_rfa; 2571 struct fxp_rx *p_rx; 2572 2573 /* 2574 * If there are other buffers already on the list, attach this 2575 * one to the end by fixing up the tail to point to this one. 2576 */ 2577 if (sc->fxp_desc.rx_head != NULL) { 2578 p_rx = sc->fxp_desc.rx_tail; 2579 p_rfa = (struct fxp_rfa *) 2580 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2581 p_rx->rx_next = rxp; 2582 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2583 p_rfa->rfa_control = 0; 2584 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2585 BUS_DMASYNC_PREWRITE); 2586 } else { 2587 rxp->rx_next = NULL; 2588 sc->fxp_desc.rx_head = rxp; 2589 } 2590 sc->fxp_desc.rx_tail = rxp; 2591 } 2592 2593 static void 2594 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2595 { 2596 struct mbuf *m; 2597 struct fxp_rfa *rfa; 2598 2599 m = rxp->rx_mbuf; 2600 m->m_data = m->m_ext.ext_buf; 2601 /* 2602 * Move the data pointer up so that the incoming data packet 2603 * will be 32-bit aligned. 2604 */ 2605 m->m_data += RFA_ALIGNMENT_FUDGE; 2606 2607 /* 2608 * Get a pointer to the base of the mbuf cluster and move 2609 * data start past it. 2610 */ 2611 rfa = mtod(m, struct fxp_rfa *); 2612 m->m_data += sc->rfa_size; 2613 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2614 2615 rfa->rfa_status = 0; 2616 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2617 rfa->actual_size = 0; 2618 2619 /* 2620 * Initialize the rest of the RFA. Note that since the RFA 2621 * is misaligned, we cannot store values directly. We're thus 2622 * using the le32enc() function which handles endianness and 2623 * is also alignment-safe. 2624 */ 2625 le32enc(&rfa->link_addr, 0xffffffff); 2626 le32enc(&rfa->rbd_addr, 0xffffffff); 2627 2628 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2629 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2630 } 2631 2632 static int 2633 fxp_miibus_readreg(device_t dev, int phy, int reg) 2634 { 2635 struct fxp_softc *sc = device_get_softc(dev); 2636 int count = 10000; 2637 int value; 2638 2639 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2640 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2641 2642 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2643 && count--) 2644 DELAY(10); 2645 2646 if (count <= 0) 2647 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2648 2649 return (value & 0xffff); 2650 } 2651 2652 static int 2653 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2654 { 2655 struct fxp_softc *sc = device_get_softc(dev); 2656 int count = 10000; 2657 2658 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2659 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2660 (value & 0xffff)); 2661 2662 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2663 count--) 2664 DELAY(10); 2665 2666 if (count <= 0) 2667 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2668 return (0); 2669 } 2670 2671 static int 2672 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2673 { 2674 struct fxp_softc *sc = ifp->if_softc; 2675 struct ifreq *ifr = (struct ifreq *)data; 2676 struct mii_data *mii; 2677 int flag, mask, error = 0, reinit; 2678 2679 switch (command) { 2680 case SIOCSIFFLAGS: 2681 FXP_LOCK(sc); 2682 if (ifp->if_flags & IFF_ALLMULTI) 2683 sc->flags |= FXP_FLAG_ALL_MCAST; 2684 else 2685 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2686 2687 /* 2688 * If interface is marked up and not running, then start it. 2689 * If it is marked down and running, stop it. 2690 * XXX If it's up then re-initialize it. This is so flags 2691 * such as IFF_PROMISC are handled. 2692 */ 2693 if (ifp->if_flags & IFF_UP) { 2694 fxp_init_body(sc); 2695 } else { 2696 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2697 fxp_stop(sc); 2698 } 2699 FXP_UNLOCK(sc); 2700 break; 2701 2702 case SIOCADDMULTI: 2703 case SIOCDELMULTI: 2704 FXP_LOCK(sc); 2705 if (ifp->if_flags & IFF_ALLMULTI) 2706 sc->flags |= FXP_FLAG_ALL_MCAST; 2707 else 2708 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2709 /* 2710 * Multicast list has changed; set the hardware filter 2711 * accordingly. 2712 */ 2713 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2714 fxp_mc_setup(sc); 2715 /* 2716 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2717 * again rather than else {}. 2718 */ 2719 if (sc->flags & FXP_FLAG_ALL_MCAST) 2720 fxp_init_body(sc); 2721 FXP_UNLOCK(sc); 2722 error = 0; 2723 break; 2724 2725 case SIOCSIFMEDIA: 2726 case SIOCGIFMEDIA: 2727 if (sc->miibus != NULL) { 2728 mii = device_get_softc(sc->miibus); 2729 error = ifmedia_ioctl(ifp, ifr, 2730 &mii->mii_media, command); 2731 } else { 2732 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2733 } 2734 break; 2735 2736 case SIOCSIFCAP: 2737 reinit = 0; 2738 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2739 #ifdef DEVICE_POLLING 2740 if (mask & IFCAP_POLLING) { 2741 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2742 error = ether_poll_register(fxp_poll, ifp); 2743 if (error) 2744 return(error); 2745 FXP_LOCK(sc); 2746 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 2747 FXP_SCB_INTR_DISABLE); 2748 ifp->if_capenable |= IFCAP_POLLING; 2749 FXP_UNLOCK(sc); 2750 } else { 2751 error = ether_poll_deregister(ifp); 2752 /* Enable interrupts in any case */ 2753 FXP_LOCK(sc); 2754 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2755 ifp->if_capenable &= ~IFCAP_POLLING; 2756 FXP_UNLOCK(sc); 2757 } 2758 } 2759 #endif 2760 FXP_LOCK(sc); 2761 if ((mask & IFCAP_TXCSUM) != 0 && 2762 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2763 ifp->if_capenable ^= IFCAP_TXCSUM; 2764 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2765 ifp->if_hwassist |= FXP_CSUM_FEATURES; 2766 else 2767 ifp->if_hwassist &= ~FXP_CSUM_FEATURES; 2768 } 2769 if ((mask & IFCAP_RXCSUM) != 0 && 2770 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 2771 ifp->if_capenable ^= IFCAP_RXCSUM; 2772 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0) 2773 reinit++; 2774 } 2775 if ((mask & IFCAP_TSO4) != 0 && 2776 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2777 ifp->if_capenable ^= IFCAP_TSO4; 2778 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2779 ifp->if_hwassist |= CSUM_TSO; 2780 else 2781 ifp->if_hwassist &= ~CSUM_TSO; 2782 } 2783 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2784 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2785 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2786 if ((mask & IFCAP_VLAN_MTU) != 0 && 2787 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) { 2788 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2789 if (sc->revision != FXP_REV_82557) 2790 flag = FXP_FLAG_LONG_PKT_EN; 2791 else /* a hack to get long frames on the old chip */ 2792 flag = FXP_FLAG_SAVE_BAD; 2793 sc->flags ^= flag; 2794 if (ifp->if_flags & IFF_UP) 2795 reinit++; 2796 } 2797 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2798 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2799 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2800 reinit++; 2801 } 2802 if (reinit > 0 && ifp->if_flags & IFF_UP) 2803 fxp_init_body(sc); 2804 FXP_UNLOCK(sc); 2805 VLAN_CAPABILITIES(ifp); 2806 break; 2807 2808 default: 2809 error = ether_ioctl(ifp, command, data); 2810 } 2811 return (error); 2812 } 2813 2814 /* 2815 * Fill in the multicast address list and return number of entries. 2816 */ 2817 static int 2818 fxp_mc_addrs(struct fxp_softc *sc) 2819 { 2820 struct fxp_cb_mcs *mcsp = sc->mcsp; 2821 struct ifnet *ifp = sc->ifp; 2822 struct ifmultiaddr *ifma; 2823 int nmcasts; 2824 2825 nmcasts = 0; 2826 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2827 IF_ADDR_LOCK(ifp); 2828 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2829 if (ifma->ifma_addr->sa_family != AF_LINK) 2830 continue; 2831 if (nmcasts >= MAXMCADDR) { 2832 sc->flags |= FXP_FLAG_ALL_MCAST; 2833 nmcasts = 0; 2834 break; 2835 } 2836 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2837 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2838 nmcasts++; 2839 } 2840 IF_ADDR_UNLOCK(ifp); 2841 } 2842 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2843 return (nmcasts); 2844 } 2845 2846 /* 2847 * Program the multicast filter. 2848 * 2849 * We have an artificial restriction that the multicast setup command 2850 * must be the first command in the chain, so we take steps to ensure 2851 * this. By requiring this, it allows us to keep up the performance of 2852 * the pre-initialized command ring (esp. link pointers) by not actually 2853 * inserting the mcsetup command in the ring - i.e. its link pointer 2854 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2855 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2856 * lead into the regular TxCB ring when it completes. 2857 * 2858 * This function must be called at splimp. 2859 */ 2860 static void 2861 fxp_mc_setup(struct fxp_softc *sc) 2862 { 2863 struct fxp_cb_mcs *mcsp = sc->mcsp; 2864 struct fxp_tx *txp; 2865 int count; 2866 2867 FXP_LOCK_ASSERT(sc, MA_OWNED); 2868 /* 2869 * If there are queued commands, we must wait until they are all 2870 * completed. If we are already waiting, then add a NOP command 2871 * with interrupt option so that we're notified when all commands 2872 * have been completed - fxp_start() ensures that no additional 2873 * TX commands will be added when need_mcsetup is true. 2874 */ 2875 if (sc->tx_queued) { 2876 /* 2877 * need_mcsetup will be true if we are already waiting for the 2878 * NOP command to be completed (see below). In this case, bail. 2879 */ 2880 if (sc->need_mcsetup) 2881 return; 2882 sc->need_mcsetup = 1; 2883 2884 /* 2885 * Add a NOP command with interrupt so that we are notified 2886 * when all TX commands have been processed. 2887 */ 2888 txp = sc->fxp_desc.tx_last->tx_next; 2889 txp->tx_mbuf = NULL; 2890 txp->tx_cb->cb_status = 0; 2891 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2892 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2893 /* 2894 * Advance the end of list forward. 2895 */ 2896 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2897 htole16(~FXP_CB_COMMAND_S); 2898 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2899 sc->fxp_desc.tx_last = txp; 2900 sc->tx_queued++; 2901 /* 2902 * Issue a resume in case the CU has just suspended. 2903 */ 2904 fxp_scb_wait(sc); 2905 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2906 /* 2907 * Set a 5 second timer just in case we don't hear from the 2908 * card again. 2909 */ 2910 sc->watchdog_timer = 5; 2911 2912 return; 2913 } 2914 sc->need_mcsetup = 0; 2915 2916 /* 2917 * Initialize multicast setup descriptor. 2918 */ 2919 mcsp->cb_status = 0; 2920 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2921 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2922 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2923 txp = &sc->fxp_desc.mcs_tx; 2924 txp->tx_mbuf = NULL; 2925 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2926 txp->tx_next = sc->fxp_desc.tx_list; 2927 (void) fxp_mc_addrs(sc); 2928 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2929 sc->tx_queued = 1; 2930 2931 /* 2932 * Wait until command unit is not active. This should never 2933 * be the case when nothing is queued, but make sure anyway. 2934 */ 2935 count = 100; 2936 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2937 FXP_SCB_CUS_ACTIVE && --count) 2938 DELAY(10); 2939 if (count == 0) { 2940 device_printf(sc->dev, "command queue timeout\n"); 2941 return; 2942 } 2943 2944 /* 2945 * Start the multicast setup command. 2946 */ 2947 fxp_scb_wait(sc); 2948 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2949 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2950 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2951 2952 sc->watchdog_timer = 2; 2953 return; 2954 } 2955 2956 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2957 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2958 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2959 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2960 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2961 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2962 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2963 2964 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2965 2966 struct ucode { 2967 uint32_t revision; 2968 uint32_t *ucode; 2969 int length; 2970 u_short int_delay_offset; 2971 u_short bundle_max_offset; 2972 } ucode_table[] = { 2973 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2974 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2975 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2976 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2977 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2978 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2979 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2980 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2981 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2982 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2983 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2984 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2985 { 0, NULL, 0, 0, 0 } 2986 }; 2987 2988 static void 2989 fxp_load_ucode(struct fxp_softc *sc) 2990 { 2991 struct ucode *uc; 2992 struct fxp_cb_ucode *cbp; 2993 int i; 2994 2995 for (uc = ucode_table; uc->ucode != NULL; uc++) 2996 if (sc->revision == uc->revision) 2997 break; 2998 if (uc->ucode == NULL) 2999 return; 3000 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 3001 cbp->cb_status = 0; 3002 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 3003 cbp->link_addr = 0xffffffff; /* (no) next command */ 3004 for (i = 0; i < uc->length; i++) 3005 cbp->ucode[i] = htole32(uc->ucode[i]); 3006 if (uc->int_delay_offset) 3007 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 3008 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 3009 if (uc->bundle_max_offset) 3010 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 3011 htole16(sc->tunable_bundle_max); 3012 /* 3013 * Download the ucode to the chip. 3014 */ 3015 fxp_scb_wait(sc); 3016 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 3017 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 3018 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 3019 /* ...and wait for it to complete. */ 3020 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 3021 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 3022 device_printf(sc->dev, 3023 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 3024 sc->tunable_int_delay, 3025 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 3026 sc->flags |= FXP_FLAG_UCODE; 3027 } 3028 3029 static int 3030 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3031 { 3032 int error, value; 3033 3034 value = *(int *)arg1; 3035 error = sysctl_handle_int(oidp, &value, 0, req); 3036 if (error || !req->newptr) 3037 return (error); 3038 if (value < low || value > high) 3039 return (EINVAL); 3040 *(int *)arg1 = value; 3041 return (0); 3042 } 3043 3044 /* 3045 * Interrupt delay is expressed in microseconds, a multiplier is used 3046 * to convert this to the appropriate clock ticks before using. 3047 */ 3048 static int 3049 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 3050 { 3051 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 3052 } 3053 3054 static int 3055 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 3056 { 3057 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 3058 } 3059