1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 #include <sys/sockio.h> 53 #include <sys/bus.h> 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <net/ethernet.h> 59 #include <net/if_arp.h> 60 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #ifdef FXP_IP_CSUM_WAR 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <machine/in_cksum.h> 71 #endif 72 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 #include <dev/fxp/rcvbundl.h> 82 83 MODULE_DEPEND(fxp, pci, 1, 1, 1); 84 MODULE_DEPEND(fxp, ether, 1, 1, 1); 85 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86 #include "miibus_if.h" 87 88 /* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97 #define RFA_ALIGNMENT_FUDGE 2 98 99 /* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104 static int tx_threshold = 64; 105 106 /* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114 static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140 }; 141 142 struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146 }; 147 148 /* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154 static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0, -1, NULL }, 194 }; 195 196 #ifdef FXP_IP_CSUM_WAR 197 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 198 #else 199 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 200 #endif 201 202 static int fxp_probe(device_t dev); 203 static int fxp_attach(device_t dev); 204 static int fxp_detach(device_t dev); 205 static int fxp_shutdown(device_t dev); 206 static int fxp_suspend(device_t dev); 207 static int fxp_resume(device_t dev); 208 209 static void fxp_intr(void *xsc); 210 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 211 uint8_t statack, int count); 212 static void fxp_init(void *xsc); 213 static void fxp_init_body(struct fxp_softc *sc); 214 static void fxp_tick(void *xsc); 215 static void fxp_start(struct ifnet *ifp); 216 static void fxp_start_body(struct ifnet *ifp); 217 static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 218 static void fxp_stop(struct fxp_softc *sc); 219 static void fxp_release(struct fxp_softc *sc); 220 static int fxp_ioctl(struct ifnet *ifp, u_long command, 221 caddr_t data); 222 static void fxp_watchdog(struct ifnet *ifp); 223 static int fxp_add_rfabuf(struct fxp_softc *sc, 224 struct fxp_rx *rxp); 225 static int fxp_mc_addrs(struct fxp_softc *sc); 226 static void fxp_mc_setup(struct fxp_softc *sc); 227 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 228 int autosize); 229 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 230 uint16_t data); 231 static void fxp_autosize_eeprom(struct fxp_softc *sc); 232 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 235 int offset, int words); 236 static int fxp_ifmedia_upd(struct ifnet *ifp); 237 static void fxp_ifmedia_sts(struct ifnet *ifp, 238 struct ifmediareq *ifmr); 239 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 240 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 241 struct ifmediareq *ifmr); 242 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 243 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 244 int value); 245 static void fxp_load_ucode(struct fxp_softc *sc); 246 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 247 int low, int high); 248 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 249 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 250 static void fxp_scb_wait(struct fxp_softc *sc); 251 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252 static void fxp_dma_wait(struct fxp_softc *sc, 253 volatile uint16_t *status, bus_dma_tag_t dmat, 254 bus_dmamap_t map); 255 256 static device_method_t fxp_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, fxp_probe), 259 DEVMETHOD(device_attach, fxp_attach), 260 DEVMETHOD(device_detach, fxp_detach), 261 DEVMETHOD(device_shutdown, fxp_shutdown), 262 DEVMETHOD(device_suspend, fxp_suspend), 263 DEVMETHOD(device_resume, fxp_resume), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 267 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 268 269 { 0, 0 } 270 }; 271 272 static driver_t fxp_driver = { 273 "fxp", 274 fxp_methods, 275 sizeof(struct fxp_softc), 276 }; 277 278 static devclass_t fxp_devclass; 279 280 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284 /* 285 * Wait for the previous command to be accepted (but not necessarily 286 * completed). 287 */ 288 static void 289 fxp_scb_wait(struct fxp_softc *sc) 290 { 291 int i = 10000; 292 293 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 294 DELAY(2); 295 if (i == 0) 296 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 297 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 298 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 299 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 300 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 301 } 302 303 static void 304 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 305 { 306 307 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 309 fxp_scb_wait(sc); 310 } 311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 312 } 313 314 static void 315 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 316 bus_dma_tag_t dmat, bus_dmamap_t map) 317 { 318 int i = 10000; 319 320 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 321 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 322 DELAY(2); 323 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 324 } 325 if (i == 0) 326 device_printf(sc->dev, "DMA timeout\n"); 327 } 328 329 /* 330 * Return identification string if this device is ours. 331 */ 332 static int 333 fxp_probe(device_t dev) 334 { 335 uint16_t devid; 336 uint8_t revid; 337 struct fxp_ident *ident; 338 339 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 340 devid = pci_get_device(dev); 341 revid = pci_get_revid(dev); 342 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 343 if (ident->devid == devid && 344 (ident->revid == revid || ident->revid == -1)) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 } 349 } 350 return (ENXIO); 351 } 352 353 static void 354 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 355 { 356 uint32_t *addr; 357 358 if (error) 359 return; 360 361 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 362 addr = arg; 363 *addr = segs->ds_addr; 364 } 365 366 static int 367 fxp_attach(device_t dev) 368 { 369 struct fxp_softc *sc; 370 struct fxp_cb_tx *tcbp; 371 struct fxp_tx *txp; 372 struct fxp_rx *rxp; 373 struct ifnet *ifp; 374 uint32_t val; 375 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 376 u_char eaddr[ETHER_ADDR_LEN]; 377 int i, rid, m1, m2, prefer_iomap; 378 int error, s; 379 380 error = 0; 381 sc = device_get_softc(dev); 382 sc->dev = dev; 383 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 384 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 385 MTX_DEF); 386 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 387 fxp_serial_ifmedia_sts); 388 389 s = splimp(); 390 391 ifp = sc->ifp = if_alloc(IFT_ETHER); 392 if (ifp == NULL) { 393 device_printf(dev, "can not if_alloc()\n"); 394 error = ENOSPC; 395 goto fail; 396 } 397 398 /* 399 * Enable bus mastering. 400 */ 401 pci_enable_busmaster(dev); 402 val = pci_read_config(dev, PCIR_COMMAND, 2); 403 404 /* 405 * Figure out which we should try first - memory mapping or i/o mapping? 406 * We default to memory mapping. Then we accept an override from the 407 * command line. Then we check to see which one is enabled. 408 */ 409 m1 = PCIM_CMD_MEMEN; 410 m2 = PCIM_CMD_PORTEN; 411 prefer_iomap = 0; 412 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 413 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 414 m1 = PCIM_CMD_PORTEN; 415 m2 = PCIM_CMD_MEMEN; 416 } 417 418 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 419 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 420 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 421 if (sc->mem == NULL) { 422 sc->rtp = 423 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 424 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 425 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 426 RF_ACTIVE); 427 } 428 429 if (!sc->mem) { 430 error = ENXIO; 431 goto fail; 432 } 433 if (bootverbose) { 434 device_printf(dev, "using %s space register mapping\n", 435 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 436 } 437 438 sc->sc_st = rman_get_bustag(sc->mem); 439 sc->sc_sh = rman_get_bushandle(sc->mem); 440 441 /* 442 * Allocate our interrupt. 443 */ 444 rid = 0; 445 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 446 RF_SHAREABLE | RF_ACTIVE); 447 if (sc->irq == NULL) { 448 device_printf(dev, "could not map interrupt\n"); 449 error = ENXIO; 450 goto fail; 451 } 452 453 /* 454 * Reset to a stable state. 455 */ 456 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 457 DELAY(10); 458 459 /* 460 * Find out how large of an SEEPROM we have. 461 */ 462 fxp_autosize_eeprom(sc); 463 464 /* 465 * Find out the chip revision; lump all 82557 revs together. 466 */ 467 fxp_read_eeprom(sc, &data, 5, 1); 468 if ((data >> 8) == 1) 469 sc->revision = FXP_REV_82557; 470 else 471 sc->revision = pci_get_revid(dev); 472 473 /* 474 * Determine whether we must use the 503 serial interface. 475 */ 476 fxp_read_eeprom(sc, &data, 6, 1); 477 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 478 && (data & FXP_PHY_SERIAL_ONLY)) 479 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 480 481 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 482 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 483 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 484 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 485 "FXP driver receive interrupt microcode bundling delay"); 486 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 487 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 488 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 489 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 490 "FXP driver receive interrupt microcode bundle size limit"); 491 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 492 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 493 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 494 "FXP RNR events"); 495 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 496 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 497 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 498 "FXP flow control disabled"); 499 500 /* 501 * Pull in device tunables. 502 */ 503 sc->tunable_int_delay = TUNABLE_INT_DELAY; 504 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 505 sc->tunable_noflow = 1; 506 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "int_delay", &sc->tunable_int_delay); 508 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 509 "bundle_max", &sc->tunable_bundle_max); 510 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 511 "noflow", &sc->tunable_noflow); 512 sc->rnr = 0; 513 514 /* 515 * Enable workarounds for certain chip revision deficiencies. 516 * 517 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 518 * some systems based a normal 82559 design, have a defect where 519 * the chip can cause a PCI protocol violation if it receives 520 * a CU_RESUME command when it is entering the IDLE state. The 521 * workaround is to disable Dynamic Standby Mode, so the chip never 522 * deasserts CLKRUN#, and always remains in an active state. 523 * 524 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 525 */ 526 i = pci_get_device(dev); 527 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 528 sc->revision >= FXP_REV_82559_A0) { 529 fxp_read_eeprom(sc, &data, 10, 1); 530 if (data & 0x02) { /* STB enable */ 531 uint16_t cksum; 532 int i; 533 534 device_printf(dev, 535 "Disabling dynamic standby mode in EEPROM\n"); 536 data &= ~0x02; 537 fxp_write_eeprom(sc, &data, 10, 1); 538 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 539 cksum = 0; 540 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 541 fxp_read_eeprom(sc, &data, i, 1); 542 cksum += data; 543 } 544 i = (1 << sc->eeprom_size) - 1; 545 cksum = 0xBABA - cksum; 546 fxp_read_eeprom(sc, &data, i, 1); 547 fxp_write_eeprom(sc, &cksum, i, 1); 548 device_printf(dev, 549 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 550 i, data, cksum); 551 #if 1 552 /* 553 * If the user elects to continue, try the software 554 * workaround, as it is better than nothing. 555 */ 556 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 557 #endif 558 } 559 } 560 561 /* 562 * If we are not a 82557 chip, we can enable extended features. 563 */ 564 if (sc->revision != FXP_REV_82557) { 565 /* 566 * If MWI is enabled in the PCI configuration, and there 567 * is a valid cacheline size (8 or 16 dwords), then tell 568 * the board to turn on MWI. 569 */ 570 if (val & PCIM_CMD_MWRICEN && 571 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 572 sc->flags |= FXP_FLAG_MWI_ENABLE; 573 574 /* turn on the extended TxCB feature */ 575 sc->flags |= FXP_FLAG_EXT_TXCB; 576 577 /* enable reception of long frames for VLAN */ 578 sc->flags |= FXP_FLAG_LONG_PKT_EN; 579 } else { 580 /* a hack to get long VLAN frames on a 82557 */ 581 sc->flags |= FXP_FLAG_SAVE_BAD; 582 } 583 584 /* 585 * Enable use of extended RFDs and TCBs for 82550 586 * and later chips. Note: we need extended TXCB support 587 * too, but that's already enabled by the code above. 588 * Be careful to do this only on the right devices. 589 */ 590 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 591 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 592 || sc->revision == FXP_REV_82551_10) { 593 sc->rfa_size = sizeof (struct fxp_rfa); 594 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 595 sc->flags |= FXP_FLAG_EXT_RFA; 596 } else { 597 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 598 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 599 } 600 601 /* 602 * Allocate DMA tags and DMA safe memory. 603 */ 604 sc->maxtxseg = FXP_NTXSEG; 605 if (sc->flags & FXP_FLAG_EXT_RFA) 606 sc->maxtxseg--; 607 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 608 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 609 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 610 &sc->fxp_mtag); 611 if (error) { 612 device_printf(dev, "could not allocate dma tag\n"); 613 goto fail; 614 } 615 616 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 617 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 618 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 619 &sc->fxp_stag); 620 if (error) { 621 device_printf(dev, "could not allocate dma tag\n"); 622 goto fail; 623 } 624 625 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 626 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 627 if (error) 628 goto fail; 629 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 630 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 631 if (error) { 632 device_printf(dev, "could not map the stats buffer\n"); 633 goto fail; 634 } 635 636 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 637 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 638 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 639 if (error) { 640 device_printf(dev, "could not allocate dma tag\n"); 641 goto fail; 642 } 643 644 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 645 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 646 if (error) 647 goto fail; 648 649 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 650 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 651 &sc->fxp_desc.cbl_addr, 0); 652 if (error) { 653 device_printf(dev, "could not map DMA memory\n"); 654 goto fail; 655 } 656 657 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 658 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 659 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 660 &sc->mcs_tag); 661 if (error) { 662 device_printf(dev, "could not allocate dma tag\n"); 663 goto fail; 664 } 665 666 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 667 BUS_DMA_NOWAIT, &sc->mcs_map); 668 if (error) 669 goto fail; 670 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 671 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 672 if (error) { 673 device_printf(dev, "can't map the multicast setup command\n"); 674 goto fail; 675 } 676 677 /* 678 * Pre-allocate the TX DMA maps and setup the pointers to 679 * the TX command blocks. 680 */ 681 txp = sc->fxp_desc.tx_list; 682 tcbp = sc->fxp_desc.cbl_list; 683 for (i = 0; i < FXP_NTXCB; i++) { 684 txp[i].tx_cb = tcbp + i; 685 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 686 if (error) { 687 device_printf(dev, "can't create DMA map for TX\n"); 688 goto fail; 689 } 690 } 691 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 692 if (error) { 693 device_printf(dev, "can't create spare DMA map\n"); 694 goto fail; 695 } 696 697 /* 698 * Pre-allocate our receive buffers. 699 */ 700 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 701 for (i = 0; i < FXP_NRFABUFS; i++) { 702 rxp = &sc->fxp_desc.rx_list[i]; 703 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 704 if (error) { 705 device_printf(dev, "can't create DMA map for RX\n"); 706 goto fail; 707 } 708 if (fxp_add_rfabuf(sc, rxp) != 0) { 709 error = ENOMEM; 710 goto fail; 711 } 712 } 713 714 /* 715 * Read MAC address. 716 */ 717 fxp_read_eeprom(sc, myea, 0, 3); 718 eaddr[0] = myea[0] & 0xff; 719 eaddr[1] = myea[0] >> 8; 720 eaddr[2] = myea[1] & 0xff; 721 eaddr[3] = myea[1] >> 8; 722 eaddr[4] = myea[2] & 0xff; 723 eaddr[5] = myea[2] >> 8; 724 if (bootverbose) { 725 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 726 pci_get_vendor(dev), pci_get_device(dev), 727 pci_get_subvendor(dev), pci_get_subdevice(dev), 728 pci_get_revid(dev)); 729 fxp_read_eeprom(sc, &data, 10, 1); 730 device_printf(dev, "Dynamic Standby mode is %s\n", 731 data & 0x02 ? "enabled" : "disabled"); 732 } 733 734 /* 735 * If this is only a 10Mbps device, then there is no MII, and 736 * the PHY will use a serial interface instead. 737 * 738 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 739 * doesn't have a programming interface of any sort. The 740 * media is sensed automatically based on how the link partner 741 * is configured. This is, in essence, manual configuration. 742 */ 743 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 744 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 745 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 746 } else { 747 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 748 fxp_ifmedia_sts)) { 749 device_printf(dev, "MII without any PHY!\n"); 750 error = ENXIO; 751 goto fail; 752 } 753 } 754 755 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 756 ifp->if_baudrate = 100000000; 757 ifp->if_init = fxp_init; 758 ifp->if_softc = sc; 759 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 760 ifp->if_ioctl = fxp_ioctl; 761 ifp->if_start = fxp_start; 762 ifp->if_watchdog = fxp_watchdog; 763 764 ifp->if_capabilities = ifp->if_capenable = 0; 765 766 /* Enable checksum offload for 82550 or better chips */ 767 if (sc->flags & FXP_FLAG_EXT_RFA) { 768 ifp->if_hwassist = FXP_CSUM_FEATURES; 769 ifp->if_capabilities |= IFCAP_HWCSUM; 770 ifp->if_capenable |= IFCAP_HWCSUM; 771 } 772 773 #ifdef DEVICE_POLLING 774 /* Inform the world we support polling. */ 775 ifp->if_capabilities |= IFCAP_POLLING; 776 ifp->if_capenable |= IFCAP_POLLING; 777 #endif 778 779 /* 780 * Attach the interface. 781 */ 782 ether_ifattach(ifp, eaddr); 783 784 /* 785 * Tell the upper layer(s) we support long frames. 786 * Must appear after the call to ether_ifattach() because 787 * ether_ifattach() sets ifi_hdrlen to the default value. 788 */ 789 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 790 ifp->if_capabilities |= IFCAP_VLAN_MTU; 791 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 792 793 /* 794 * Let the system queue as many packets as we have available 795 * TX descriptors. 796 */ 797 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 798 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 799 IFQ_SET_READY(&ifp->if_snd); 800 801 /* 802 * Hook our interrupt after all initialization is complete. 803 */ 804 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 805 fxp_intr, sc, &sc->ih); 806 if (error) { 807 device_printf(dev, "could not setup irq\n"); 808 ether_ifdetach(sc->ifp); 809 goto fail; 810 } 811 812 fail: 813 splx(s); 814 if (error) 815 fxp_release(sc); 816 return (error); 817 } 818 819 /* 820 * Release all resources. The softc lock should not be held and the 821 * interrupt should already be torn down. 822 */ 823 static void 824 fxp_release(struct fxp_softc *sc) 825 { 826 struct fxp_rx *rxp; 827 struct fxp_tx *txp; 828 int i; 829 830 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 831 KASSERT(sc->ih == NULL, 832 ("fxp_release() called with intr handle still active")); 833 if (sc->miibus) 834 device_delete_child(sc->dev, sc->miibus); 835 bus_generic_detach(sc->dev); 836 ifmedia_removeall(&sc->sc_media); 837 if (sc->fxp_desc.cbl_list) { 838 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 839 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 840 sc->cbl_map); 841 } 842 if (sc->fxp_stats) { 843 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 844 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 845 } 846 if (sc->mcsp) { 847 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 848 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 849 } 850 if (sc->irq) 851 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 852 if (sc->mem) 853 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 854 if (sc->fxp_mtag) { 855 for (i = 0; i < FXP_NRFABUFS; i++) { 856 rxp = &sc->fxp_desc.rx_list[i]; 857 if (rxp->rx_mbuf != NULL) { 858 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 859 BUS_DMASYNC_POSTREAD); 860 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 861 m_freem(rxp->rx_mbuf); 862 } 863 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 864 } 865 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 866 for (i = 0; i < FXP_NTXCB; i++) { 867 txp = &sc->fxp_desc.tx_list[i]; 868 if (txp->tx_mbuf != NULL) { 869 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 870 BUS_DMASYNC_POSTWRITE); 871 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 872 m_freem(txp->tx_mbuf); 873 } 874 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 875 } 876 bus_dma_tag_destroy(sc->fxp_mtag); 877 } 878 if (sc->fxp_stag) 879 bus_dma_tag_destroy(sc->fxp_stag); 880 if (sc->cbl_tag) 881 bus_dma_tag_destroy(sc->cbl_tag); 882 if (sc->mcs_tag) 883 bus_dma_tag_destroy(sc->mcs_tag); 884 if (sc->ifp) 885 if_free(sc->ifp); 886 887 mtx_destroy(&sc->sc_mtx); 888 } 889 890 /* 891 * Detach interface. 892 */ 893 static int 894 fxp_detach(device_t dev) 895 { 896 struct fxp_softc *sc = device_get_softc(dev); 897 int s; 898 899 FXP_LOCK(sc); 900 s = splimp(); 901 902 sc->suspended = 1; /* Do same thing as we do for suspend */ 903 /* 904 * Close down routes etc. 905 */ 906 ether_ifdetach(sc->ifp); 907 908 /* 909 * Stop DMA and drop transmit queue, but disable interrupts first. 910 */ 911 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 912 fxp_stop(sc); 913 FXP_UNLOCK(sc); 914 915 /* 916 * Unhook interrupt before dropping lock. This is to prevent 917 * races with fxp_intr(). 918 */ 919 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 920 sc->ih = NULL; 921 922 splx(s); 923 924 /* Release our allocated resources. */ 925 fxp_release(sc); 926 return (0); 927 } 928 929 /* 930 * Device shutdown routine. Called at system shutdown after sync. The 931 * main purpose of this routine is to shut off receiver DMA so that 932 * kernel memory doesn't get clobbered during warmboot. 933 */ 934 static int 935 fxp_shutdown(device_t dev) 936 { 937 /* 938 * Make sure that DMA is disabled prior to reboot. Not doing 939 * do could allow DMA to corrupt kernel memory during the 940 * reboot before the driver initializes. 941 */ 942 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 943 return (0); 944 } 945 946 /* 947 * Device suspend routine. Stop the interface and save some PCI 948 * settings in case the BIOS doesn't restore them properly on 949 * resume. 950 */ 951 static int 952 fxp_suspend(device_t dev) 953 { 954 struct fxp_softc *sc = device_get_softc(dev); 955 int s; 956 957 FXP_LOCK(sc); 958 s = splimp(); 959 960 fxp_stop(sc); 961 962 sc->suspended = 1; 963 964 FXP_UNLOCK(sc); 965 splx(s); 966 return (0); 967 } 968 969 /* 970 * Device resume routine. re-enable busmastering, and restart the interface if 971 * appropriate. 972 */ 973 static int 974 fxp_resume(device_t dev) 975 { 976 struct fxp_softc *sc = device_get_softc(dev); 977 struct ifnet *ifp = sc->ifp; 978 uint16_t pci_command; 979 int s; 980 981 FXP_LOCK(sc); 982 s = splimp(); 983 984 /* reenable busmastering */ 985 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 986 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 987 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 988 989 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 990 DELAY(10); 991 992 /* reinitialize interface if necessary */ 993 if (ifp->if_flags & IFF_UP) 994 fxp_init_body(sc); 995 996 sc->suspended = 0; 997 998 FXP_UNLOCK(sc); 999 splx(s); 1000 return (0); 1001 } 1002 1003 static void 1004 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1005 { 1006 uint16_t reg; 1007 int x; 1008 1009 /* 1010 * Shift in data. 1011 */ 1012 for (x = 1 << (length - 1); x; x >>= 1) { 1013 if (data & x) 1014 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1015 else 1016 reg = FXP_EEPROM_EECS; 1017 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1018 DELAY(1); 1019 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1020 DELAY(1); 1021 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1022 DELAY(1); 1023 } 1024 } 1025 1026 /* 1027 * Read from the serial EEPROM. Basically, you manually shift in 1028 * the read opcode (one bit at a time) and then shift in the address, 1029 * and then you shift out the data (all of this one bit at a time). 1030 * The word size is 16 bits, so you have to provide the address for 1031 * every 16 bits of data. 1032 */ 1033 static uint16_t 1034 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1035 { 1036 uint16_t reg, data; 1037 int x; 1038 1039 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1040 /* 1041 * Shift in read opcode. 1042 */ 1043 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1044 /* 1045 * Shift in address. 1046 */ 1047 data = 0; 1048 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1049 if (offset & x) 1050 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1051 else 1052 reg = FXP_EEPROM_EECS; 1053 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1054 DELAY(1); 1055 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1056 DELAY(1); 1057 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1058 DELAY(1); 1059 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1060 data++; 1061 if (autosize && reg == 0) { 1062 sc->eeprom_size = data; 1063 break; 1064 } 1065 } 1066 /* 1067 * Shift out data. 1068 */ 1069 data = 0; 1070 reg = FXP_EEPROM_EECS; 1071 for (x = 1 << 15; x; x >>= 1) { 1072 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1073 DELAY(1); 1074 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1075 data |= x; 1076 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1077 DELAY(1); 1078 } 1079 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1080 DELAY(1); 1081 1082 return (data); 1083 } 1084 1085 static void 1086 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1087 { 1088 int i; 1089 1090 /* 1091 * Erase/write enable. 1092 */ 1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1094 fxp_eeprom_shiftin(sc, 0x4, 3); 1095 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1096 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1097 DELAY(1); 1098 /* 1099 * Shift in write opcode, address, data. 1100 */ 1101 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1102 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1103 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1104 fxp_eeprom_shiftin(sc, data, 16); 1105 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1106 DELAY(1); 1107 /* 1108 * Wait for EEPROM to finish up. 1109 */ 1110 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1111 DELAY(1); 1112 for (i = 0; i < 1000; i++) { 1113 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1114 break; 1115 DELAY(50); 1116 } 1117 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1118 DELAY(1); 1119 /* 1120 * Erase/write disable. 1121 */ 1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1123 fxp_eeprom_shiftin(sc, 0x4, 3); 1124 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1125 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1126 DELAY(1); 1127 } 1128 1129 /* 1130 * From NetBSD: 1131 * 1132 * Figure out EEPROM size. 1133 * 1134 * 559's can have either 64-word or 256-word EEPROMs, the 558 1135 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1136 * talks about the existance of 16 to 256 word EEPROMs. 1137 * 1138 * The only known sizes are 64 and 256, where the 256 version is used 1139 * by CardBus cards to store CIS information. 1140 * 1141 * The address is shifted in msb-to-lsb, and after the last 1142 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1143 * after which follows the actual data. We try to detect this zero, by 1144 * probing the data-out bit in the EEPROM control register just after 1145 * having shifted in a bit. If the bit is zero, we assume we've 1146 * shifted enough address bits. The data-out should be tri-state, 1147 * before this, which should translate to a logical one. 1148 */ 1149 static void 1150 fxp_autosize_eeprom(struct fxp_softc *sc) 1151 { 1152 1153 /* guess maximum size of 256 words */ 1154 sc->eeprom_size = 8; 1155 1156 /* autosize */ 1157 (void) fxp_eeprom_getword(sc, 0, 1); 1158 } 1159 1160 static void 1161 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1162 { 1163 int i; 1164 1165 for (i = 0; i < words; i++) 1166 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1167 } 1168 1169 static void 1170 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1171 { 1172 int i; 1173 1174 for (i = 0; i < words; i++) 1175 fxp_eeprom_putword(sc, offset + i, data[i]); 1176 } 1177 1178 /* 1179 * Grab the softc lock and call the real fxp_start_body() routine 1180 */ 1181 static void 1182 fxp_start(struct ifnet *ifp) 1183 { 1184 struct fxp_softc *sc = ifp->if_softc; 1185 1186 FXP_LOCK(sc); 1187 fxp_start_body(ifp); 1188 FXP_UNLOCK(sc); 1189 } 1190 1191 /* 1192 * Start packet transmission on the interface. 1193 * This routine must be called with the softc lock held, and is an 1194 * internal entry point only. 1195 */ 1196 static void 1197 fxp_start_body(struct ifnet *ifp) 1198 { 1199 struct fxp_softc *sc = ifp->if_softc; 1200 struct mbuf *mb_head; 1201 int error, txqueued; 1202 1203 FXP_LOCK_ASSERT(sc, MA_OWNED); 1204 1205 /* 1206 * See if we need to suspend xmit until the multicast filter 1207 * has been reprogrammed (which can only be done at the head 1208 * of the command chain). 1209 */ 1210 if (sc->need_mcsetup) 1211 return; 1212 1213 /* 1214 * We're finished if there is nothing more to add to the list or if 1215 * we're all filled up with buffers to transmit. 1216 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1217 * a NOP command when needed. 1218 */ 1219 txqueued = 0; 1220 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1221 sc->tx_queued < FXP_NTXCB - 1) { 1222 1223 /* 1224 * Grab a packet to transmit. 1225 */ 1226 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1227 if (mb_head == NULL) 1228 break; 1229 1230 error = fxp_encap(sc, mb_head); 1231 if (error) 1232 break; 1233 txqueued = 1; 1234 } 1235 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1236 1237 /* 1238 * We're finished. If we added to the list, issue a RESUME to get DMA 1239 * going again if suspended. 1240 */ 1241 if (txqueued) { 1242 fxp_scb_wait(sc); 1243 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1244 } 1245 } 1246 1247 static int 1248 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1249 { 1250 struct ifnet *ifp; 1251 struct mbuf *m; 1252 struct fxp_tx *txp; 1253 struct fxp_cb_tx *cbp; 1254 bus_dma_segment_t segs[FXP_NTXSEG]; 1255 int chainlen, error, i, nseg; 1256 1257 FXP_LOCK_ASSERT(sc, MA_OWNED); 1258 ifp = sc->ifp; 1259 1260 /* 1261 * Get pointer to next available tx desc. 1262 */ 1263 txp = sc->fxp_desc.tx_last->tx_next; 1264 1265 /* 1266 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1267 * Ethernet Controller Family Open Source Software 1268 * Developer Manual says: 1269 * Using software parsing is only allowed with legal 1270 * TCP/IP or UDP/IP packets. 1271 * ... 1272 * For all other datagrams, hardware parsing must 1273 * be used. 1274 * Software parsing appears to truncate ICMP and 1275 * fragmented UDP packets that contain one to three 1276 * bytes in the second (and final) mbuf of the packet. 1277 */ 1278 if (sc->flags & FXP_FLAG_EXT_RFA) 1279 txp->tx_cb->ipcb_ip_activation_high = 1280 FXP_IPCB_HARDWAREPARSING_ENABLE; 1281 1282 /* 1283 * Deal with TCP/IP checksum offload. Note that 1284 * in order for TCP checksum offload to work, 1285 * the pseudo header checksum must have already 1286 * been computed and stored in the checksum field 1287 * in the TCP header. The stack should have 1288 * already done this for us. 1289 */ 1290 if (m_head->m_pkthdr.csum_flags) { 1291 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1292 txp->tx_cb->ipcb_ip_schedule = 1293 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1294 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1295 txp->tx_cb->ipcb_ip_schedule |= 1296 FXP_IPCB_TCP_PACKET; 1297 } 1298 1299 #ifdef FXP_IP_CSUM_WAR 1300 /* 1301 * XXX The 82550 chip appears to have trouble 1302 * dealing with IP header checksums in very small 1303 * datagrams, namely fragments from 1 to 3 bytes 1304 * in size. For example, say you want to transmit 1305 * a UDP packet of 1473 bytes. The packet will be 1306 * fragmented over two IP datagrams, the latter 1307 * containing only one byte of data. The 82550 will 1308 * botch the header checksum on the 1-byte fragment. 1309 * As long as the datagram contains 4 or more bytes 1310 * of data, you're ok. 1311 * 1312 * The following code attempts to work around this 1313 * problem: if the datagram is less than 38 bytes 1314 * in size (14 bytes ether header, 20 bytes IP header, 1315 * plus 4 bytes of data), we punt and compute the IP 1316 * header checksum by hand. This workaround doesn't 1317 * work very well, however, since it can be fooled 1318 * by things like VLAN tags and IP options that make 1319 * the header sizes/offsets vary. 1320 */ 1321 1322 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1323 if (m_head->m_pkthdr.len < 38) { 1324 struct ip *ip; 1325 m_head->m_data += ETHER_HDR_LEN; 1326 ip = mtod(mb_head, struct ip *); 1327 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1328 m_head->m_data -= ETHER_HDR_LEN; 1329 } else { 1330 txp->tx_cb->ipcb_ip_activation_high = 1331 FXP_IPCB_HARDWAREPARSING_ENABLE; 1332 txp->tx_cb->ipcb_ip_schedule |= 1333 FXP_IPCB_IP_CHECKSUM_ENABLE; 1334 } 1335 } 1336 #endif 1337 } 1338 1339 chainlen = 0; 1340 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1341 chainlen++; 1342 if (chainlen > sc->maxtxseg) { 1343 struct mbuf *mn; 1344 1345 /* 1346 * We ran out of segments. We have to recopy this 1347 * mbuf chain first. Bail out if we can't get the 1348 * new buffers. 1349 */ 1350 mn = m_defrag(m_head, M_DONTWAIT); 1351 if (mn == NULL) { 1352 m_freem(m_head); 1353 return (-1); 1354 } else { 1355 m_head = mn; 1356 } 1357 } 1358 1359 /* 1360 * Go through each of the mbufs in the chain and initialize 1361 * the transmit buffer descriptors with the physical address 1362 * and size of the mbuf. 1363 */ 1364 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1365 m_head, segs, &nseg, 0); 1366 if (error) { 1367 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1368 m_freem(m_head); 1369 return (-1); 1370 } 1371 1372 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1373 1374 cbp = txp->tx_cb; 1375 for (i = 0; i < nseg; i++) { 1376 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1377 /* 1378 * If this is an 82550/82551, then we're using extended 1379 * TxCBs _and_ we're using checksum offload. This means 1380 * that the TxCB is really an IPCB. One major difference 1381 * between the two is that with plain extended TxCBs, 1382 * the bottom half of the TxCB contains two entries from 1383 * the TBD array, whereas IPCBs contain just one entry: 1384 * one entry (8 bytes) has been sacrificed for the TCP/IP 1385 * checksum offload control bits. So to make things work 1386 * right, we have to start filling in the TBD array 1387 * starting from a different place depending on whether 1388 * the chip is an 82550/82551 or not. 1389 */ 1390 if (sc->flags & FXP_FLAG_EXT_RFA) { 1391 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1392 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1393 } else { 1394 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1395 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1396 } 1397 } 1398 cbp->tbd_number = nseg; 1399 1400 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1401 txp->tx_mbuf = m_head; 1402 txp->tx_cb->cb_status = 0; 1403 txp->tx_cb->byte_count = 0; 1404 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1405 txp->tx_cb->cb_command = 1406 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1407 FXP_CB_COMMAND_S); 1408 } else { 1409 txp->tx_cb->cb_command = 1410 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1411 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1412 /* 1413 * Set a 5 second timer just in case we don't hear 1414 * from the card again. 1415 */ 1416 ifp->if_timer = 5; 1417 } 1418 txp->tx_cb->tx_threshold = tx_threshold; 1419 1420 /* 1421 * Advance the end of list forward. 1422 */ 1423 1424 #ifdef __alpha__ 1425 /* 1426 * On platforms which can't access memory in 16-bit 1427 * granularities, we must prevent the card from DMA'ing 1428 * up the status while we update the command field. 1429 * This could cause us to overwrite the completion status. 1430 * XXX This is probably bogus and we're _not_ looking 1431 * for atomicity here. 1432 */ 1433 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1434 htole16(FXP_CB_COMMAND_S)); 1435 #else 1436 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1437 #endif /*__alpha__*/ 1438 sc->fxp_desc.tx_last = txp; 1439 1440 /* 1441 * Advance the beginning of the list forward if there are 1442 * no other packets queued (when nothing is queued, tx_first 1443 * sits on the last TxCB that was sent out). 1444 */ 1445 if (sc->tx_queued == 0) 1446 sc->fxp_desc.tx_first = txp; 1447 1448 sc->tx_queued++; 1449 1450 /* 1451 * Pass packet to bpf if there is a listener. 1452 */ 1453 BPF_MTAP(ifp, m_head); 1454 return (0); 1455 } 1456 1457 #ifdef DEVICE_POLLING 1458 static poll_handler_t fxp_poll; 1459 1460 static void 1461 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1462 { 1463 struct fxp_softc *sc = ifp->if_softc; 1464 uint8_t statack; 1465 1466 FXP_LOCK(sc); 1467 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1468 ether_poll_deregister(ifp); 1469 cmd = POLL_DEREGISTER; 1470 } 1471 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1472 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1473 FXP_UNLOCK(sc); 1474 return; 1475 } 1476 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1477 FXP_SCB_STATACK_FR; 1478 if (cmd == POLL_AND_CHECK_STATUS) { 1479 uint8_t tmp; 1480 1481 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1482 if (tmp == 0xff || tmp == 0) { 1483 FXP_UNLOCK(sc); 1484 return; /* nothing to do */ 1485 } 1486 tmp &= ~statack; 1487 /* ack what we can */ 1488 if (tmp != 0) 1489 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1490 statack |= tmp; 1491 } 1492 fxp_intr_body(sc, ifp, statack, count); 1493 FXP_UNLOCK(sc); 1494 } 1495 #endif /* DEVICE_POLLING */ 1496 1497 /* 1498 * Process interface interrupts. 1499 */ 1500 static void 1501 fxp_intr(void *xsc) 1502 { 1503 struct fxp_softc *sc = xsc; 1504 struct ifnet *ifp = sc->ifp; 1505 uint8_t statack; 1506 1507 FXP_LOCK(sc); 1508 if (sc->suspended) { 1509 FXP_UNLOCK(sc); 1510 return; 1511 } 1512 1513 #ifdef DEVICE_POLLING 1514 if (ifp->if_flags & IFF_POLLING) { 1515 FXP_UNLOCK(sc); 1516 return; 1517 } 1518 if ((ifp->if_capenable & IFCAP_POLLING) && 1519 ether_poll_register(fxp_poll, ifp)) { 1520 /* disable interrupts */ 1521 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1522 FXP_UNLOCK(sc); 1523 fxp_poll(ifp, 0, 1); 1524 return; 1525 } 1526 #endif 1527 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1528 /* 1529 * It should not be possible to have all bits set; the 1530 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1531 * all bits are set, this may indicate that the card has 1532 * been physically ejected, so ignore it. 1533 */ 1534 if (statack == 0xff) { 1535 FXP_UNLOCK(sc); 1536 return; 1537 } 1538 1539 /* 1540 * First ACK all the interrupts in this pass. 1541 */ 1542 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1543 fxp_intr_body(sc, ifp, statack, -1); 1544 } 1545 FXP_UNLOCK(sc); 1546 } 1547 1548 static void 1549 fxp_txeof(struct fxp_softc *sc) 1550 { 1551 struct fxp_tx *txp; 1552 1553 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1554 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1555 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1556 txp = txp->tx_next) { 1557 if (txp->tx_mbuf != NULL) { 1558 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1559 BUS_DMASYNC_POSTWRITE); 1560 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1561 m_freem(txp->tx_mbuf); 1562 txp->tx_mbuf = NULL; 1563 /* clear this to reset csum offload bits */ 1564 txp->tx_cb->tbd[0].tb_addr = 0; 1565 } 1566 sc->tx_queued--; 1567 } 1568 sc->fxp_desc.tx_first = txp; 1569 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1570 } 1571 1572 static void 1573 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1574 int count) 1575 { 1576 struct mbuf *m; 1577 struct fxp_rx *rxp; 1578 struct fxp_rfa *rfa; 1579 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1580 int fxp_rc = 0; 1581 1582 FXP_LOCK_ASSERT(sc, MA_OWNED); 1583 if (rnr) 1584 sc->rnr++; 1585 #ifdef DEVICE_POLLING 1586 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1587 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1588 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1589 rnr = 1; 1590 } 1591 #endif 1592 1593 /* 1594 * Free any finished transmit mbuf chains. 1595 * 1596 * Handle the CNA event likt a CXTNO event. It used to 1597 * be that this event (control unit not ready) was not 1598 * encountered, but it is now with the SMPng modifications. 1599 * The exact sequence of events that occur when the interface 1600 * is brought up are different now, and if this event 1601 * goes unhandled, the configuration/rxfilter setup sequence 1602 * can stall for several seconds. The result is that no 1603 * packets go out onto the wire for about 5 to 10 seconds 1604 * after the interface is ifconfig'ed for the first time. 1605 */ 1606 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1607 fxp_txeof(sc); 1608 1609 ifp->if_timer = 0; 1610 if (sc->tx_queued == 0) { 1611 if (sc->need_mcsetup) 1612 fxp_mc_setup(sc); 1613 } 1614 /* 1615 * Try to start more packets transmitting. 1616 */ 1617 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1618 fxp_start_body(ifp); 1619 } 1620 1621 /* 1622 * Just return if nothing happened on the receive side. 1623 */ 1624 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1625 return; 1626 1627 /* 1628 * Process receiver interrupts. If a no-resource (RNR) 1629 * condition exists, get whatever packets we can and 1630 * re-start the receiver. 1631 * 1632 * When using polling, we do not process the list to completion, 1633 * so when we get an RNR interrupt we must defer the restart 1634 * until we hit the last buffer with the C bit set. 1635 * If we run out of cycles and rfa_headm has the C bit set, 1636 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1637 * that the info will be used in the subsequent polling cycle. 1638 */ 1639 for (;;) { 1640 rxp = sc->fxp_desc.rx_head; 1641 m = rxp->rx_mbuf; 1642 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1643 RFA_ALIGNMENT_FUDGE); 1644 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1645 BUS_DMASYNC_POSTREAD); 1646 1647 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1648 if (count >= 0 && count-- == 0) { 1649 if (rnr) { 1650 /* Defer RNR processing until the next time. */ 1651 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1652 rnr = 0; 1653 } 1654 break; 1655 } 1656 #endif /* DEVICE_POLLING */ 1657 1658 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1659 break; 1660 1661 /* 1662 * Advance head forward. 1663 */ 1664 sc->fxp_desc.rx_head = rxp->rx_next; 1665 1666 /* 1667 * Add a new buffer to the receive chain. 1668 * If this fails, the old buffer is recycled 1669 * instead. 1670 */ 1671 fxp_rc = fxp_add_rfabuf(sc, rxp); 1672 if (fxp_rc == 0) { 1673 int total_len; 1674 1675 /* 1676 * Fetch packet length (the top 2 bits of 1677 * actual_size are flags set by the controller 1678 * upon completion), and drop the packet in case 1679 * of bogus length or CRC errors. 1680 */ 1681 total_len = le16toh(rfa->actual_size) & 0x3fff; 1682 if (total_len < sizeof(struct ether_header) || 1683 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1684 sc->rfa_size || 1685 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1686 m_freem(m); 1687 continue; 1688 } 1689 1690 /* Do IP checksum checking. */ 1691 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1692 if (rfa->rfax_csum_sts & 1693 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1694 m->m_pkthdr.csum_flags |= 1695 CSUM_IP_CHECKED; 1696 if (rfa->rfax_csum_sts & 1697 FXP_RFDX_CS_IP_CSUM_VALID) 1698 m->m_pkthdr.csum_flags |= 1699 CSUM_IP_VALID; 1700 if ((rfa->rfax_csum_sts & 1701 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1702 (rfa->rfax_csum_sts & 1703 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1704 m->m_pkthdr.csum_flags |= 1705 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1706 m->m_pkthdr.csum_data = 0xffff; 1707 } 1708 } 1709 1710 m->m_pkthdr.len = m->m_len = total_len; 1711 m->m_pkthdr.rcvif = ifp; 1712 1713 /* 1714 * Drop locks before calling if_input() since it 1715 * may re-enter fxp_start() in the netisr case. 1716 * This would result in a lock reversal. Better 1717 * performance might be obtained by chaining all 1718 * packets received, dropping the lock, and then 1719 * calling if_input() on each one. 1720 */ 1721 FXP_UNLOCK(sc); 1722 (*ifp->if_input)(ifp, m); 1723 FXP_LOCK(sc); 1724 } else if (fxp_rc == ENOBUFS) { 1725 rnr = 0; 1726 break; 1727 } 1728 } 1729 if (rnr) { 1730 fxp_scb_wait(sc); 1731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1732 sc->fxp_desc.rx_head->rx_addr); 1733 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1734 } 1735 } 1736 1737 /* 1738 * Update packet in/out/collision statistics. The i82557 doesn't 1739 * allow you to access these counters without doing a fairly 1740 * expensive DMA to get _all_ of the statistics it maintains, so 1741 * we do this operation here only once per second. The statistics 1742 * counters in the kernel are updated from the previous dump-stats 1743 * DMA and then a new dump-stats DMA is started. The on-chip 1744 * counters are zeroed when the DMA completes. If we can't start 1745 * the DMA immediately, we don't wait - we just prepare to read 1746 * them again next time. 1747 */ 1748 static void 1749 fxp_tick(void *xsc) 1750 { 1751 struct fxp_softc *sc = xsc; 1752 struct ifnet *ifp = sc->ifp; 1753 struct fxp_stats *sp = sc->fxp_stats; 1754 int s; 1755 1756 FXP_LOCK(sc); 1757 s = splimp(); 1758 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1759 ifp->if_opackets += le32toh(sp->tx_good); 1760 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1761 if (sp->rx_good) { 1762 ifp->if_ipackets += le32toh(sp->rx_good); 1763 sc->rx_idle_secs = 0; 1764 } else { 1765 /* 1766 * Receiver's been idle for another second. 1767 */ 1768 sc->rx_idle_secs++; 1769 } 1770 ifp->if_ierrors += 1771 le32toh(sp->rx_crc_errors) + 1772 le32toh(sp->rx_alignment_errors) + 1773 le32toh(sp->rx_rnr_errors) + 1774 le32toh(sp->rx_overrun_errors); 1775 /* 1776 * If any transmit underruns occured, bump up the transmit 1777 * threshold by another 512 bytes (64 * 8). 1778 */ 1779 if (sp->tx_underruns) { 1780 ifp->if_oerrors += le32toh(sp->tx_underruns); 1781 if (tx_threshold < 192) 1782 tx_threshold += 64; 1783 } 1784 1785 /* 1786 * Release any xmit buffers that have completed DMA. This isn't 1787 * strictly necessary to do here, but it's advantagous for mbufs 1788 * with external storage to be released in a timely manner rather 1789 * than being defered for a potentially long time. This limits 1790 * the delay to a maximum of one second. 1791 */ 1792 fxp_txeof(sc); 1793 1794 /* 1795 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1796 * then assume the receiver has locked up and attempt to clear 1797 * the condition by reprogramming the multicast filter. This is 1798 * a work-around for a bug in the 82557 where the receiver locks 1799 * up if it gets certain types of garbage in the syncronization 1800 * bits prior to the packet header. This bug is supposed to only 1801 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1802 * mode as well (perhaps due to a 10/100 speed transition). 1803 */ 1804 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1805 sc->rx_idle_secs = 0; 1806 fxp_mc_setup(sc); 1807 } 1808 /* 1809 * If there is no pending command, start another stats 1810 * dump. Otherwise punt for now. 1811 */ 1812 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1813 /* 1814 * Start another stats dump. 1815 */ 1816 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1817 BUS_DMASYNC_PREREAD); 1818 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1819 } else { 1820 /* 1821 * A previous command is still waiting to be accepted. 1822 * Just zero our copy of the stats and wait for the 1823 * next timer event to update them. 1824 */ 1825 sp->tx_good = 0; 1826 sp->tx_underruns = 0; 1827 sp->tx_total_collisions = 0; 1828 1829 sp->rx_good = 0; 1830 sp->rx_crc_errors = 0; 1831 sp->rx_alignment_errors = 0; 1832 sp->rx_rnr_errors = 0; 1833 sp->rx_overrun_errors = 0; 1834 } 1835 if (sc->miibus != NULL) 1836 mii_tick(device_get_softc(sc->miibus)); 1837 1838 /* 1839 * Schedule another timeout one second from now. 1840 */ 1841 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1842 FXP_UNLOCK(sc); 1843 splx(s); 1844 } 1845 1846 /* 1847 * Stop the interface. Cancels the statistics updater and resets 1848 * the interface. 1849 */ 1850 static void 1851 fxp_stop(struct fxp_softc *sc) 1852 { 1853 struct ifnet *ifp = sc->ifp; 1854 struct fxp_tx *txp; 1855 int i; 1856 1857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1858 ifp->if_timer = 0; 1859 1860 #ifdef DEVICE_POLLING 1861 ether_poll_deregister(ifp); 1862 #endif 1863 /* 1864 * Cancel stats updater. 1865 */ 1866 callout_stop(&sc->stat_ch); 1867 1868 /* 1869 * Issue software reset, which also unloads the microcode. 1870 */ 1871 sc->flags &= ~FXP_FLAG_UCODE; 1872 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1873 DELAY(50); 1874 1875 /* 1876 * Release any xmit buffers. 1877 */ 1878 txp = sc->fxp_desc.tx_list; 1879 if (txp != NULL) { 1880 for (i = 0; i < FXP_NTXCB; i++) { 1881 if (txp[i].tx_mbuf != NULL) { 1882 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1883 BUS_DMASYNC_POSTWRITE); 1884 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1885 m_freem(txp[i].tx_mbuf); 1886 txp[i].tx_mbuf = NULL; 1887 /* clear this to reset csum offload bits */ 1888 txp[i].tx_cb->tbd[0].tb_addr = 0; 1889 } 1890 } 1891 } 1892 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1893 sc->tx_queued = 0; 1894 } 1895 1896 /* 1897 * Watchdog/transmission transmit timeout handler. Called when a 1898 * transmission is started on the interface, but no interrupt is 1899 * received before the timeout. This usually indicates that the 1900 * card has wedged for some reason. 1901 */ 1902 static void 1903 fxp_watchdog(struct ifnet *ifp) 1904 { 1905 struct fxp_softc *sc = ifp->if_softc; 1906 1907 FXP_LOCK(sc); 1908 device_printf(sc->dev, "device timeout\n"); 1909 ifp->if_oerrors++; 1910 1911 fxp_init_body(sc); 1912 FXP_UNLOCK(sc); 1913 } 1914 1915 /* 1916 * Acquire locks and then call the real initialization function. This 1917 * is necessary because ether_ioctl() calls if_init() and this would 1918 * result in mutex recursion if the mutex was held. 1919 */ 1920 static void 1921 fxp_init(void *xsc) 1922 { 1923 struct fxp_softc *sc = xsc; 1924 1925 FXP_LOCK(sc); 1926 fxp_init_body(sc); 1927 FXP_UNLOCK(sc); 1928 } 1929 1930 /* 1931 * Perform device initialization. This routine must be called with the 1932 * softc lock held. 1933 */ 1934 static void 1935 fxp_init_body(struct fxp_softc *sc) 1936 { 1937 struct ifnet *ifp = sc->ifp; 1938 struct fxp_cb_config *cbp; 1939 struct fxp_cb_ias *cb_ias; 1940 struct fxp_cb_tx *tcbp; 1941 struct fxp_tx *txp; 1942 struct fxp_cb_mcs *mcsp; 1943 int i, prm, s; 1944 1945 FXP_LOCK_ASSERT(sc, MA_OWNED); 1946 s = splimp(); 1947 /* 1948 * Cancel any pending I/O 1949 */ 1950 fxp_stop(sc); 1951 1952 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1953 1954 /* 1955 * Initialize base of CBL and RFA memory. Loading with zero 1956 * sets it up for regular linear addressing. 1957 */ 1958 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1959 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1960 1961 fxp_scb_wait(sc); 1962 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1963 1964 /* 1965 * Initialize base of dump-stats buffer. 1966 */ 1967 fxp_scb_wait(sc); 1968 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1969 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1970 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1971 1972 /* 1973 * Attempt to load microcode if requested. 1974 */ 1975 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1976 fxp_load_ucode(sc); 1977 1978 /* 1979 * Initialize the multicast address list. 1980 */ 1981 if (fxp_mc_addrs(sc)) { 1982 mcsp = sc->mcsp; 1983 mcsp->cb_status = 0; 1984 mcsp->cb_command = 1985 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1986 mcsp->link_addr = 0xffffffff; 1987 /* 1988 * Start the multicast setup command. 1989 */ 1990 fxp_scb_wait(sc); 1991 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1992 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1993 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1994 /* ...and wait for it to complete. */ 1995 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1996 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1997 BUS_DMASYNC_POSTWRITE); 1998 } 1999 2000 /* 2001 * We temporarily use memory that contains the TxCB list to 2002 * construct the config CB. The TxCB list memory is rebuilt 2003 * later. 2004 */ 2005 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2006 2007 /* 2008 * This bcopy is kind of disgusting, but there are a bunch of must be 2009 * zero and must be one bits in this structure and this is the easiest 2010 * way to initialize them all to proper values. 2011 */ 2012 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2013 2014 cbp->cb_status = 0; 2015 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2016 FXP_CB_COMMAND_EL); 2017 cbp->link_addr = 0xffffffff; /* (no) next command */ 2018 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2019 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2020 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2021 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2022 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2023 cbp->type_enable = 0; /* actually reserved */ 2024 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2025 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2026 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2027 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2028 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2029 cbp->late_scb = 0; /* (don't) defer SCB update */ 2030 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2031 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2032 cbp->ci_int = 1; /* interrupt on CU idle */ 2033 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2034 cbp->ext_stats_dis = 1; /* disable extended counters */ 2035 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2036 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2037 cbp->disc_short_rx = !prm; /* discard short packets */ 2038 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2039 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2040 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2041 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2042 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2043 cbp->csma_dis = 0; /* (don't) disable link */ 2044 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2045 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2046 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2047 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2048 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2049 cbp->nsai = 1; /* (don't) disable source addr insert */ 2050 cbp->preamble_length = 2; /* (7 byte) preamble */ 2051 cbp->loopback = 0; /* (don't) loopback */ 2052 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2053 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2054 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2055 cbp->promiscuous = prm; /* promiscuous mode */ 2056 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2057 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2058 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2059 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2060 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2061 2062 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2063 cbp->padding = 1; /* (do) pad short tx packets */ 2064 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2065 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2066 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2067 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2068 /* must set wake_en in PMCSR also */ 2069 cbp->force_fdx = 0; /* (don't) force full duplex */ 2070 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2071 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2072 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2073 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2074 2075 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2076 /* 2077 * The 82557 has no hardware flow control, the values 2078 * below are the defaults for the chip. 2079 */ 2080 cbp->fc_delay_lsb = 0; 2081 cbp->fc_delay_msb = 0x40; 2082 cbp->pri_fc_thresh = 3; 2083 cbp->tx_fc_dis = 0; 2084 cbp->rx_fc_restop = 0; 2085 cbp->rx_fc_restart = 0; 2086 cbp->fc_filter = 0; 2087 cbp->pri_fc_loc = 1; 2088 } else { 2089 cbp->fc_delay_lsb = 0x1f; 2090 cbp->fc_delay_msb = 0x01; 2091 cbp->pri_fc_thresh = 3; 2092 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2093 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2094 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2095 cbp->fc_filter = !prm; /* drop FC frames to host */ 2096 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2097 } 2098 2099 /* 2100 * Start the config command/DMA. 2101 */ 2102 fxp_scb_wait(sc); 2103 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2104 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2105 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2106 /* ...and wait for it to complete. */ 2107 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2108 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2109 2110 /* 2111 * Now initialize the station address. Temporarily use the TxCB 2112 * memory area like we did above for the config CB. 2113 */ 2114 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2115 cb_ias->cb_status = 0; 2116 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2117 cb_ias->link_addr = 0xffffffff; 2118 bcopy(IFP2ENADDR(sc->ifp), cb_ias->macaddr, 2119 sizeof(IFP2ENADDR(sc->ifp))); 2120 2121 /* 2122 * Start the IAS (Individual Address Setup) command/DMA. 2123 */ 2124 fxp_scb_wait(sc); 2125 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2127 /* ...and wait for it to complete. */ 2128 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2129 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2130 2131 /* 2132 * Initialize transmit control block (TxCB) list. 2133 */ 2134 txp = sc->fxp_desc.tx_list; 2135 tcbp = sc->fxp_desc.cbl_list; 2136 bzero(tcbp, FXP_TXCB_SZ); 2137 for (i = 0; i < FXP_NTXCB; i++) { 2138 txp[i].tx_mbuf = NULL; 2139 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2140 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2141 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2142 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2143 if (sc->flags & FXP_FLAG_EXT_TXCB) 2144 tcbp[i].tbd_array_addr = 2145 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2146 else 2147 tcbp[i].tbd_array_addr = 2148 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2149 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2150 } 2151 /* 2152 * Set the suspend flag on the first TxCB and start the control 2153 * unit. It will execute the NOP and then suspend. 2154 */ 2155 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2156 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2157 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2158 sc->tx_queued = 1; 2159 2160 fxp_scb_wait(sc); 2161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2162 2163 /* 2164 * Initialize receiver buffer area - RFA. 2165 */ 2166 fxp_scb_wait(sc); 2167 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2168 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2169 2170 /* 2171 * Set current media. 2172 */ 2173 if (sc->miibus != NULL) 2174 mii_mediachg(device_get_softc(sc->miibus)); 2175 2176 ifp->if_flags |= IFF_RUNNING; 2177 ifp->if_flags &= ~IFF_OACTIVE; 2178 2179 /* 2180 * Enable interrupts. 2181 */ 2182 #ifdef DEVICE_POLLING 2183 /* 2184 * ... but only do that if we are not polling. And because (presumably) 2185 * the default is interrupts on, we need to disable them explicitly! 2186 */ 2187 if ( ifp->if_flags & IFF_POLLING ) 2188 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2189 else 2190 #endif /* DEVICE_POLLING */ 2191 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2192 2193 /* 2194 * Start stats updater. 2195 */ 2196 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2197 splx(s); 2198 } 2199 2200 static int 2201 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2202 { 2203 2204 return (0); 2205 } 2206 2207 static void 2208 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2209 { 2210 2211 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2212 } 2213 2214 /* 2215 * Change media according to request. 2216 */ 2217 static int 2218 fxp_ifmedia_upd(struct ifnet *ifp) 2219 { 2220 struct fxp_softc *sc = ifp->if_softc; 2221 struct mii_data *mii; 2222 2223 mii = device_get_softc(sc->miibus); 2224 mii_mediachg(mii); 2225 return (0); 2226 } 2227 2228 /* 2229 * Notify the world which media we're using. 2230 */ 2231 static void 2232 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2233 { 2234 struct fxp_softc *sc = ifp->if_softc; 2235 struct mii_data *mii; 2236 2237 mii = device_get_softc(sc->miibus); 2238 mii_pollstat(mii); 2239 ifmr->ifm_active = mii->mii_media_active; 2240 ifmr->ifm_status = mii->mii_media_status; 2241 2242 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2243 sc->cu_resume_bug = 1; 2244 else 2245 sc->cu_resume_bug = 0; 2246 } 2247 2248 /* 2249 * Add a buffer to the end of the RFA buffer list. 2250 * Return 0 if successful, 1 for failure. A failure results in 2251 * adding the 'oldm' (if non-NULL) on to the end of the list - 2252 * tossing out its old contents and recycling it. 2253 * The RFA struct is stuck at the beginning of mbuf cluster and the 2254 * data pointer is fixed up to point just past it. 2255 */ 2256 static int 2257 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2258 { 2259 struct mbuf *m; 2260 struct fxp_rfa *rfa, *p_rfa; 2261 struct fxp_rx *p_rx; 2262 bus_dmamap_t tmp_map; 2263 int error; 2264 2265 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2266 if (m == NULL) 2267 return (ENOBUFS); 2268 2269 /* 2270 * Move the data pointer up so that the incoming data packet 2271 * will be 32-bit aligned. 2272 */ 2273 m->m_data += RFA_ALIGNMENT_FUDGE; 2274 2275 /* 2276 * Get a pointer to the base of the mbuf cluster and move 2277 * data start past it. 2278 */ 2279 rfa = mtod(m, struct fxp_rfa *); 2280 m->m_data += sc->rfa_size; 2281 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2282 2283 rfa->rfa_status = 0; 2284 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2285 rfa->actual_size = 0; 2286 2287 /* 2288 * Initialize the rest of the RFA. Note that since the RFA 2289 * is misaligned, we cannot store values directly. We're thus 2290 * using the le32enc() function which handles endianness and 2291 * is also alignment-safe. 2292 */ 2293 le32enc(&rfa->link_addr, 0xffffffff); 2294 le32enc(&rfa->rbd_addr, 0xffffffff); 2295 2296 /* Map the RFA into DMA memory. */ 2297 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2298 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2299 &rxp->rx_addr, 0); 2300 if (error) { 2301 m_freem(m); 2302 return (error); 2303 } 2304 2305 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2306 tmp_map = sc->spare_map; 2307 sc->spare_map = rxp->rx_map; 2308 rxp->rx_map = tmp_map; 2309 rxp->rx_mbuf = m; 2310 2311 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2312 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2313 2314 /* 2315 * If there are other buffers already on the list, attach this 2316 * one to the end by fixing up the tail to point to this one. 2317 */ 2318 if (sc->fxp_desc.rx_head != NULL) { 2319 p_rx = sc->fxp_desc.rx_tail; 2320 p_rfa = (struct fxp_rfa *) 2321 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2322 p_rx->rx_next = rxp; 2323 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2324 p_rfa->rfa_control = 0; 2325 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2326 BUS_DMASYNC_PREWRITE); 2327 } else { 2328 rxp->rx_next = NULL; 2329 sc->fxp_desc.rx_head = rxp; 2330 } 2331 sc->fxp_desc.rx_tail = rxp; 2332 return (0); 2333 } 2334 2335 static volatile int 2336 fxp_miibus_readreg(device_t dev, int phy, int reg) 2337 { 2338 struct fxp_softc *sc = device_get_softc(dev); 2339 int count = 10000; 2340 int value; 2341 2342 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2343 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2344 2345 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2346 && count--) 2347 DELAY(10); 2348 2349 if (count <= 0) 2350 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2351 2352 return (value & 0xffff); 2353 } 2354 2355 static void 2356 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2357 { 2358 struct fxp_softc *sc = device_get_softc(dev); 2359 int count = 10000; 2360 2361 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2362 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2363 (value & 0xffff)); 2364 2365 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2366 count--) 2367 DELAY(10); 2368 2369 if (count <= 0) 2370 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2371 } 2372 2373 static int 2374 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2375 { 2376 struct fxp_softc *sc = ifp->if_softc; 2377 struct ifreq *ifr = (struct ifreq *)data; 2378 struct mii_data *mii; 2379 int flag, mask, s, error = 0; 2380 2381 /* 2382 * Detaching causes us to call ioctl with the mutex owned. Preclude 2383 * that by saying we're busy if the lock is already held. 2384 */ 2385 if (FXP_LOCKED(sc)) 2386 return (EBUSY); 2387 2388 FXP_LOCK(sc); 2389 s = splimp(); 2390 2391 switch (command) { 2392 case SIOCSIFFLAGS: 2393 if (ifp->if_flags & IFF_ALLMULTI) 2394 sc->flags |= FXP_FLAG_ALL_MCAST; 2395 else 2396 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2397 2398 /* 2399 * If interface is marked up and not running, then start it. 2400 * If it is marked down and running, stop it. 2401 * XXX If it's up then re-initialize it. This is so flags 2402 * such as IFF_PROMISC are handled. 2403 */ 2404 if (ifp->if_flags & IFF_UP) { 2405 fxp_init_body(sc); 2406 } else { 2407 if (ifp->if_flags & IFF_RUNNING) 2408 fxp_stop(sc); 2409 } 2410 break; 2411 2412 case SIOCADDMULTI: 2413 case SIOCDELMULTI: 2414 if (ifp->if_flags & IFF_ALLMULTI) 2415 sc->flags |= FXP_FLAG_ALL_MCAST; 2416 else 2417 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2418 /* 2419 * Multicast list has changed; set the hardware filter 2420 * accordingly. 2421 */ 2422 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2423 fxp_mc_setup(sc); 2424 /* 2425 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2426 * again rather than else {}. 2427 */ 2428 if (sc->flags & FXP_FLAG_ALL_MCAST) 2429 fxp_init_body(sc); 2430 error = 0; 2431 break; 2432 2433 case SIOCSIFMEDIA: 2434 case SIOCGIFMEDIA: 2435 if (sc->miibus != NULL) { 2436 mii = device_get_softc(sc->miibus); 2437 error = ifmedia_ioctl(ifp, ifr, 2438 &mii->mii_media, command); 2439 } else { 2440 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2441 } 2442 break; 2443 2444 case SIOCSIFCAP: 2445 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2446 if (mask & IFCAP_POLLING) 2447 ifp->if_capenable ^= IFCAP_POLLING; 2448 if (mask & IFCAP_VLAN_MTU) { 2449 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2450 if (sc->revision != FXP_REV_82557) 2451 flag = FXP_FLAG_LONG_PKT_EN; 2452 else /* a hack to get long frames on the old chip */ 2453 flag = FXP_FLAG_SAVE_BAD; 2454 sc->flags ^= flag; 2455 if (ifp->if_flags & IFF_UP) 2456 fxp_init_body(sc); 2457 } 2458 break; 2459 2460 default: 2461 /* 2462 * ether_ioctl() will eventually call fxp_start() which 2463 * will result in mutex recursion so drop it first. 2464 */ 2465 FXP_UNLOCK(sc); 2466 error = ether_ioctl(ifp, command, data); 2467 } 2468 if (FXP_LOCKED(sc)) 2469 FXP_UNLOCK(sc); 2470 splx(s); 2471 return (error); 2472 } 2473 2474 /* 2475 * Fill in the multicast address list and return number of entries. 2476 */ 2477 static int 2478 fxp_mc_addrs(struct fxp_softc *sc) 2479 { 2480 struct fxp_cb_mcs *mcsp = sc->mcsp; 2481 struct ifnet *ifp = sc->ifp; 2482 struct ifmultiaddr *ifma; 2483 int nmcasts; 2484 2485 nmcasts = 0; 2486 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2487 #if __FreeBSD_version < 500000 2488 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2489 #else 2490 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2491 #endif 2492 if (ifma->ifma_addr->sa_family != AF_LINK) 2493 continue; 2494 if (nmcasts >= MAXMCADDR) { 2495 sc->flags |= FXP_FLAG_ALL_MCAST; 2496 nmcasts = 0; 2497 break; 2498 } 2499 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2500 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2501 nmcasts++; 2502 } 2503 } 2504 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2505 return (nmcasts); 2506 } 2507 2508 /* 2509 * Program the multicast filter. 2510 * 2511 * We have an artificial restriction that the multicast setup command 2512 * must be the first command in the chain, so we take steps to ensure 2513 * this. By requiring this, it allows us to keep up the performance of 2514 * the pre-initialized command ring (esp. link pointers) by not actually 2515 * inserting the mcsetup command in the ring - i.e. its link pointer 2516 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2517 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2518 * lead into the regular TxCB ring when it completes. 2519 * 2520 * This function must be called at splimp. 2521 */ 2522 static void 2523 fxp_mc_setup(struct fxp_softc *sc) 2524 { 2525 struct fxp_cb_mcs *mcsp = sc->mcsp; 2526 struct ifnet *ifp = sc->ifp; 2527 struct fxp_tx *txp; 2528 int count; 2529 2530 FXP_LOCK_ASSERT(sc, MA_OWNED); 2531 /* 2532 * If there are queued commands, we must wait until they are all 2533 * completed. If we are already waiting, then add a NOP command 2534 * with interrupt option so that we're notified when all commands 2535 * have been completed - fxp_start() ensures that no additional 2536 * TX commands will be added when need_mcsetup is true. 2537 */ 2538 if (sc->tx_queued) { 2539 /* 2540 * need_mcsetup will be true if we are already waiting for the 2541 * NOP command to be completed (see below). In this case, bail. 2542 */ 2543 if (sc->need_mcsetup) 2544 return; 2545 sc->need_mcsetup = 1; 2546 2547 /* 2548 * Add a NOP command with interrupt so that we are notified 2549 * when all TX commands have been processed. 2550 */ 2551 txp = sc->fxp_desc.tx_last->tx_next; 2552 txp->tx_mbuf = NULL; 2553 txp->tx_cb->cb_status = 0; 2554 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2555 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2556 /* 2557 * Advance the end of list forward. 2558 */ 2559 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2560 htole16(~FXP_CB_COMMAND_S); 2561 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2562 sc->fxp_desc.tx_last = txp; 2563 sc->tx_queued++; 2564 /* 2565 * Issue a resume in case the CU has just suspended. 2566 */ 2567 fxp_scb_wait(sc); 2568 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2569 /* 2570 * Set a 5 second timer just in case we don't hear from the 2571 * card again. 2572 */ 2573 ifp->if_timer = 5; 2574 2575 return; 2576 } 2577 sc->need_mcsetup = 0; 2578 2579 /* 2580 * Initialize multicast setup descriptor. 2581 */ 2582 mcsp->cb_status = 0; 2583 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2584 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2585 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2586 txp = &sc->fxp_desc.mcs_tx; 2587 txp->tx_mbuf = NULL; 2588 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2589 txp->tx_next = sc->fxp_desc.tx_list; 2590 (void) fxp_mc_addrs(sc); 2591 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2592 sc->tx_queued = 1; 2593 2594 /* 2595 * Wait until command unit is not active. This should never 2596 * be the case when nothing is queued, but make sure anyway. 2597 */ 2598 count = 100; 2599 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2600 FXP_SCB_CUS_ACTIVE && --count) 2601 DELAY(10); 2602 if (count == 0) { 2603 device_printf(sc->dev, "command queue timeout\n"); 2604 return; 2605 } 2606 2607 /* 2608 * Start the multicast setup command. 2609 */ 2610 fxp_scb_wait(sc); 2611 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2612 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2613 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2614 2615 ifp->if_timer = 2; 2616 return; 2617 } 2618 2619 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2620 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2621 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2622 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2623 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2624 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2625 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2626 2627 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2628 2629 struct ucode { 2630 uint32_t revision; 2631 uint32_t *ucode; 2632 int length; 2633 u_short int_delay_offset; 2634 u_short bundle_max_offset; 2635 } ucode_table[] = { 2636 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2637 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2638 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2639 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2640 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2641 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2642 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2643 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2644 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2645 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2646 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2647 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2648 { 0, NULL, 0, 0, 0 } 2649 }; 2650 2651 static void 2652 fxp_load_ucode(struct fxp_softc *sc) 2653 { 2654 struct ucode *uc; 2655 struct fxp_cb_ucode *cbp; 2656 int i; 2657 2658 for (uc = ucode_table; uc->ucode != NULL; uc++) 2659 if (sc->revision == uc->revision) 2660 break; 2661 if (uc->ucode == NULL) 2662 return; 2663 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2664 cbp->cb_status = 0; 2665 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2666 cbp->link_addr = 0xffffffff; /* (no) next command */ 2667 for (i = 0; i < uc->length; i++) 2668 cbp->ucode[i] = htole32(uc->ucode[i]); 2669 if (uc->int_delay_offset) 2670 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2671 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2672 if (uc->bundle_max_offset) 2673 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2674 htole16(sc->tunable_bundle_max); 2675 /* 2676 * Download the ucode to the chip. 2677 */ 2678 fxp_scb_wait(sc); 2679 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2680 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2681 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2682 /* ...and wait for it to complete. */ 2683 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2684 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2685 device_printf(sc->dev, 2686 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2687 sc->tunable_int_delay, 2688 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2689 sc->flags |= FXP_FLAG_UCODE; 2690 } 2691 2692 static int 2693 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2694 { 2695 int error, value; 2696 2697 value = *(int *)arg1; 2698 error = sysctl_handle_int(oidp, &value, 0, req); 2699 if (error || !req->newptr) 2700 return (error); 2701 if (value < low || value > high) 2702 return (EINVAL); 2703 *(int *)arg1 = value; 2704 return (0); 2705 } 2706 2707 /* 2708 * Interrupt delay is expressed in microseconds, a multiplier is used 2709 * to convert this to the appropriate clock ticks before using. 2710 */ 2711 static int 2712 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2713 { 2714 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2715 } 2716 2717 static int 2718 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2719 { 2720 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2721 } 2722