1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 #include <sys/sockio.h> 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 57 #include <net/ethernet.h> 58 #include <net/if_arp.h> 59 60 #include <machine/clock.h> /* for DELAY */ 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #ifdef FXP_IP_CSUM_WAR 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <machine/in_cksum.h> 70 #endif 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/fxp/if_fxpreg.h> 79 #include <dev/fxp/if_fxpvar.h> 80 #include <dev/fxp/rcvbundl.h> 81 82 MODULE_DEPEND(fxp, pci, 1, 1, 1); 83 MODULE_DEPEND(fxp, ether, 1, 1, 1); 84 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 85 #include "miibus_if.h" 86 87 /* 88 * NOTE! On the Alpha, we have an alignment constraint. The 89 * card DMAs the packet immediately following the RFA. However, 90 * the first thing in the packet is a 14-byte Ethernet header. 91 * This means that the packet is misaligned. To compensate, 92 * we actually offset the RFA 2 bytes into the cluster. This 93 * alignes the packet after the Ethernet header at a 32-bit 94 * boundary. HOWEVER! This means that the RFA is misaligned! 95 */ 96 #define RFA_ALIGNMENT_FUDGE 2 97 98 /* 99 * Set initial transmit threshold at 64 (512 bytes). This is 100 * increased by 64 (512 bytes) at a time, to maximum of 192 101 * (1536 bytes), if an underrun occurs. 102 */ 103 static int tx_threshold = 64; 104 105 /* 106 * The configuration byte map has several undefined fields which 107 * must be one or must be zero. Set up a template for these bits 108 * only, (assuming a 82557 chip) leaving the actual configuration 109 * to fxp_init. 110 * 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x0, 0x0, /* cb_command */ 116 0x0, 0x0, 0x0, 0x0, /* link_addr */ 117 0x0, /* 0 */ 118 0x0, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x0, /* 5 */ 123 0x32, /* 6 */ 124 0x0, /* 7 */ 125 0x0, /* 8 */ 126 0x0, /* 9 */ 127 0x6, /* 10 */ 128 0x0, /* 11 */ 129 0x0, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf0, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 struct fxp_ident { 142 u_int16_t devid; 143 int16_t revid; /* -1 matches anything */ 144 char *name; 145 }; 146 147 /* 148 * Claim various Intel PCI device identifiers for this driver. The 149 * sub-vendor and sub-device field are extensively used to identify 150 * particular variants, but we don't currently differentiate between 151 * them. 152 */ 153 static struct fxp_ident fxp_ident_table[] = { 154 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 155 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 156 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 157 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 159 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 161 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 164 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 166 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 167 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 168 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 169 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 170 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 171 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 172 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 173 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 174 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 177 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 179 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 182 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 183 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 186 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 188 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 189 { 0, -1, NULL }, 190 }; 191 192 #ifdef FXP_IP_CSUM_WAR 193 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 194 #else 195 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 196 #endif 197 198 static int fxp_probe(device_t dev); 199 static int fxp_attach(device_t dev); 200 static int fxp_detach(device_t dev); 201 static int fxp_shutdown(device_t dev); 202 static int fxp_suspend(device_t dev); 203 static int fxp_resume(device_t dev); 204 205 static void fxp_intr(void *xsc); 206 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 207 u_int8_t statack, int count); 208 static void fxp_init(void *xsc); 209 static void fxp_init_body(struct fxp_softc *sc); 210 static void fxp_tick(void *xsc); 211 #ifndef BURN_BRIDGES 212 static void fxp_powerstate_d0(device_t dev); 213 #endif 214 static void fxp_start(struct ifnet *ifp); 215 static void fxp_start_body(struct ifnet *ifp); 216 static void fxp_stop(struct fxp_softc *sc); 217 static void fxp_release(struct fxp_softc *sc); 218 static int fxp_ioctl(struct ifnet *ifp, u_long command, 219 caddr_t data); 220 static void fxp_watchdog(struct ifnet *ifp); 221 static int fxp_add_rfabuf(struct fxp_softc *sc, 222 struct fxp_rx *rxp); 223 static int fxp_mc_addrs(struct fxp_softc *sc); 224 static void fxp_mc_setup(struct fxp_softc *sc); 225 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 226 int autosize); 227 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 228 u_int16_t data); 229 static void fxp_autosize_eeprom(struct fxp_softc *sc); 230 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 231 int offset, int words); 232 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 233 int offset, int words); 234 static int fxp_ifmedia_upd(struct ifnet *ifp); 235 static void fxp_ifmedia_sts(struct ifnet *ifp, 236 struct ifmediareq *ifmr); 237 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 238 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 241 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 242 int value); 243 static void fxp_load_ucode(struct fxp_softc *sc); 244 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 245 int low, int high); 246 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 247 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 248 static void fxp_scb_wait(struct fxp_softc *sc); 249 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 250 static void fxp_dma_wait(struct fxp_softc *sc, 251 volatile u_int16_t *status, bus_dma_tag_t dmat, 252 bus_dmamap_t map); 253 254 static device_method_t fxp_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, fxp_probe), 257 DEVMETHOD(device_attach, fxp_attach), 258 DEVMETHOD(device_detach, fxp_detach), 259 DEVMETHOD(device_shutdown, fxp_shutdown), 260 DEVMETHOD(device_suspend, fxp_suspend), 261 DEVMETHOD(device_resume, fxp_resume), 262 263 /* MII interface */ 264 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 265 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 266 267 { 0, 0 } 268 }; 269 270 static driver_t fxp_driver = { 271 "fxp", 272 fxp_methods, 273 sizeof(struct fxp_softc), 274 }; 275 276 static devclass_t fxp_devclass; 277 278 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 279 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 280 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 281 282 static int fxp_rnr; 283 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 284 285 static int fxp_noflow; 286 SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); 287 TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); 288 289 /* 290 * Wait for the previous command to be accepted (but not necessarily 291 * completed). 292 */ 293 static void 294 fxp_scb_wait(struct fxp_softc *sc) 295 { 296 int i = 10000; 297 298 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 299 DELAY(2); 300 if (i == 0) 301 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 302 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 303 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 304 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 305 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 306 } 307 308 static void 309 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 310 { 311 312 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 313 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 314 fxp_scb_wait(sc); 315 } 316 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 317 } 318 319 static void 320 fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, 321 bus_dma_tag_t dmat, bus_dmamap_t map) 322 { 323 int i = 10000; 324 325 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 326 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 327 DELAY(2); 328 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 329 } 330 if (i == 0) 331 device_printf(sc->dev, "DMA timeout\n"); 332 } 333 334 /* 335 * Return identification string if this device is ours. 336 */ 337 static int 338 fxp_probe(device_t dev) 339 { 340 u_int16_t devid; 341 u_int8_t revid; 342 struct fxp_ident *ident; 343 344 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 345 devid = pci_get_device(dev); 346 revid = pci_get_revid(dev); 347 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 348 if (ident->devid == devid && 349 (ident->revid == revid || ident->revid == -1)) { 350 device_set_desc(dev, ident->name); 351 return (0); 352 } 353 } 354 } 355 return (ENXIO); 356 } 357 358 #ifndef BURN_BRIDGES 359 static void 360 fxp_powerstate_d0(device_t dev) 361 { 362 #if __FreeBSD_version >= 430002 363 u_int32_t iobase, membase, irq; 364 365 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 366 /* Save important PCI config data. */ 367 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 368 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 369 irq = pci_read_config(dev, PCIR_INTLINE, 4); 370 371 /* Reset the power state. */ 372 device_printf(dev, "chip is in D%d power mode " 373 "-- setting to D0\n", pci_get_powerstate(dev)); 374 375 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 376 377 /* Restore PCI config data. */ 378 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 379 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 380 pci_write_config(dev, PCIR_INTLINE, irq, 4); 381 } 382 #endif 383 } 384 #endif 385 386 static void 387 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 388 { 389 u_int32_t *addr; 390 391 if (error) 392 return; 393 394 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 395 addr = arg; 396 *addr = segs->ds_addr; 397 } 398 399 static int 400 fxp_attach(device_t dev) 401 { 402 int error = 0; 403 struct fxp_softc *sc = device_get_softc(dev); 404 struct ifnet *ifp; 405 struct fxp_rx *rxp; 406 u_int32_t val; 407 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 408 int i, rid, m1, m2, prefer_iomap, maxtxseg; 409 int s, ipcbxmit_disable; 410 411 sc->dev = dev; 412 callout_init(&sc->stat_ch, CALLOUT_MPSAFE); 413 sysctl_ctx_init(&sc->sysctl_ctx); 414 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 415 MTX_DEF); 416 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 417 fxp_serial_ifmedia_sts); 418 419 s = splimp(); 420 421 /* 422 * Enable bus mastering. 423 */ 424 pci_enable_busmaster(dev); 425 val = pci_read_config(dev, PCIR_COMMAND, 2); 426 #ifndef BURN_BRIDGES 427 fxp_powerstate_d0(dev); 428 #endif 429 /* 430 * Figure out which we should try first - memory mapping or i/o mapping? 431 * We default to memory mapping. Then we accept an override from the 432 * command line. Then we check to see which one is enabled. 433 */ 434 m1 = PCIM_CMD_MEMEN; 435 m2 = PCIM_CMD_PORTEN; 436 prefer_iomap = 0; 437 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 438 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 439 m1 = PCIM_CMD_PORTEN; 440 m2 = PCIM_CMD_MEMEN; 441 } 442 443 sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 444 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 445 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, RF_ACTIVE); 446 if (sc->mem == NULL) { 447 sc->rtp = 448 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 449 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 450 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 451 RF_ACTIVE); 452 } 453 454 if (!sc->mem) { 455 error = ENXIO; 456 goto fail; 457 } 458 if (bootverbose) { 459 device_printf(dev, "using %s space register mapping\n", 460 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 461 } 462 463 sc->sc_st = rman_get_bustag(sc->mem); 464 sc->sc_sh = rman_get_bushandle(sc->mem); 465 466 /* 467 * Allocate our interrupt. 468 */ 469 rid = 0; 470 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 471 RF_SHAREABLE | RF_ACTIVE); 472 if (sc->irq == NULL) { 473 device_printf(dev, "could not map interrupt\n"); 474 error = ENXIO; 475 goto fail; 476 } 477 478 /* 479 * Reset to a stable state. 480 */ 481 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 482 DELAY(10); 483 484 /* 485 * Find out how large of an SEEPROM we have. 486 */ 487 fxp_autosize_eeprom(sc); 488 489 /* 490 * Determine whether we must use the 503 serial interface. 491 */ 492 fxp_read_eeprom(sc, &data, 6, 1); 493 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 494 (data & FXP_PHY_SERIAL_ONLY)) 495 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 496 497 /* 498 * Create the sysctl tree 499 */ 500 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 501 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 502 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 503 if (sc->sysctl_tree == NULL) { 504 error = ENXIO; 505 goto fail; 506 } 507 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 508 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 509 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 510 "FXP driver receive interrupt microcode bundling delay"); 511 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 512 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 513 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 514 "FXP driver receive interrupt microcode bundle size limit"); 515 516 /* 517 * Pull in device tunables. 518 */ 519 sc->tunable_int_delay = TUNABLE_INT_DELAY; 520 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 521 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 522 "int_delay", &sc->tunable_int_delay); 523 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 524 "bundle_max", &sc->tunable_bundle_max); 525 526 /* 527 * Find out the chip revision; lump all 82557 revs together. 528 */ 529 fxp_read_eeprom(sc, &data, 5, 1); 530 if ((data >> 8) == 1) 531 sc->revision = FXP_REV_82557; 532 else 533 sc->revision = pci_get_revid(dev); 534 535 /* 536 * Enable workarounds for certain chip revision deficiencies. 537 * 538 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 539 * some systems based a normal 82559 design, have a defect where 540 * the chip can cause a PCI protocol violation if it receives 541 * a CU_RESUME command when it is entering the IDLE state. The 542 * workaround is to disable Dynamic Standby Mode, so the chip never 543 * deasserts CLKRUN#, and always remains in an active state. 544 * 545 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 546 */ 547 i = pci_get_device(dev); 548 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 549 sc->revision >= FXP_REV_82559_A0) { 550 fxp_read_eeprom(sc, &data, 10, 1); 551 if (data & 0x02) { /* STB enable */ 552 u_int16_t cksum; 553 int i; 554 555 device_printf(dev, 556 "Disabling dynamic standby mode in EEPROM\n"); 557 data &= ~0x02; 558 fxp_write_eeprom(sc, &data, 10, 1); 559 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 560 cksum = 0; 561 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 562 fxp_read_eeprom(sc, &data, i, 1); 563 cksum += data; 564 } 565 i = (1 << sc->eeprom_size) - 1; 566 cksum = 0xBABA - cksum; 567 fxp_read_eeprom(sc, &data, i, 1); 568 fxp_write_eeprom(sc, &cksum, i, 1); 569 device_printf(dev, 570 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 571 i, data, cksum); 572 #if 1 573 /* 574 * If the user elects to continue, try the software 575 * workaround, as it is better than nothing. 576 */ 577 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 578 #endif 579 } 580 } 581 582 /* 583 * If we are not a 82557 chip, we can enable extended features. 584 */ 585 if (sc->revision != FXP_REV_82557) { 586 /* 587 * If MWI is enabled in the PCI configuration, and there 588 * is a valid cacheline size (8 or 16 dwords), then tell 589 * the board to turn on MWI. 590 */ 591 if (val & PCIM_CMD_MWRICEN && 592 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 593 sc->flags |= FXP_FLAG_MWI_ENABLE; 594 595 /* turn on the extended TxCB feature */ 596 sc->flags |= FXP_FLAG_EXT_TXCB; 597 598 /* enable reception of long frames for VLAN */ 599 sc->flags |= FXP_FLAG_LONG_PKT_EN; 600 } 601 602 /* 603 * Enable use of extended RFDs and TCBs for 82550 604 * and later chips. Note: we need extended TXCB support 605 * too, but that's already enabled by the code above. 606 * Be careful to do this only on the right devices. 607 * 608 * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" 609 * truncate packets that end with an mbuf containing 1 to 3 bytes 610 * when used with this feature enabled in the previous version of the 611 * driver. This problem appears to be fixed now that the driver 612 * always sets the hardware parse bit in the IPCB structure, which 613 * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open 614 * Source Software Developer Manual" says is necessary in the 615 * cases where packet truncation was observed. 616 * 617 * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" 618 * allows this feature to be disabled at boot time. 619 * 620 * If fxp is not compiled into the kernel, this feature may also 621 * be disabled at run time: 622 * # kldunload fxp 623 * # kenv hint.fxp.0.ipcbxmit_disable=1 624 * # kldload fxp 625 */ 626 627 if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", 628 &ipcbxmit_disable) != 0) 629 ipcbxmit_disable = 0; 630 if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || 631 sc->revision == FXP_REV_82550_C)) { 632 sc->rfa_size = sizeof (struct fxp_rfa); 633 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 634 sc->flags |= FXP_FLAG_EXT_RFA; 635 } else { 636 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 637 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 638 } 639 640 /* 641 * Allocate DMA tags and DMA safe memory. 642 */ 643 maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; 644 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 645 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, 646 maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); 647 if (error) { 648 device_printf(dev, "could not allocate dma tag\n"); 649 goto fail; 650 } 651 652 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 653 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 654 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 655 &sc->fxp_stag); 656 if (error) { 657 device_printf(dev, "could not allocate dma tag\n"); 658 goto fail; 659 } 660 661 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 662 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 663 if (error) 664 goto fail; 665 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 666 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 667 if (error) { 668 device_printf(dev, "could not map the stats buffer\n"); 669 goto fail; 670 } 671 672 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 673 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 674 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 675 if (error) { 676 device_printf(dev, "could not allocate dma tag\n"); 677 goto fail; 678 } 679 680 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 681 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 682 if (error) 683 goto fail; 684 685 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 686 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 687 &sc->fxp_desc.cbl_addr, 0); 688 if (error) { 689 device_printf(dev, "could not map DMA memory\n"); 690 goto fail; 691 } 692 693 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 694 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 695 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 696 &sc->mcs_tag); 697 if (error) { 698 device_printf(dev, "could not allocate dma tag\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 703 BUS_DMA_NOWAIT, &sc->mcs_map); 704 if (error) 705 goto fail; 706 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 707 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 708 if (error) { 709 device_printf(dev, "can't map the multicast setup command\n"); 710 goto fail; 711 } 712 713 /* 714 * Pre-allocate the TX DMA maps. 715 */ 716 for (i = 0; i < FXP_NTXCB; i++) { 717 error = bus_dmamap_create(sc->fxp_mtag, 0, 718 &sc->fxp_desc.tx_list[i].tx_map); 719 if (error) { 720 device_printf(dev, "can't create DMA map for TX\n"); 721 goto fail; 722 } 723 } 724 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 725 if (error) { 726 device_printf(dev, "can't create spare DMA map\n"); 727 goto fail; 728 } 729 730 /* 731 * Pre-allocate our receive buffers. 732 */ 733 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 734 for (i = 0; i < FXP_NRFABUFS; i++) { 735 rxp = &sc->fxp_desc.rx_list[i]; 736 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 737 if (error) { 738 device_printf(dev, "can't create DMA map for RX\n"); 739 goto fail; 740 } 741 if (fxp_add_rfabuf(sc, rxp) != 0) { 742 error = ENOMEM; 743 goto fail; 744 } 745 } 746 747 /* 748 * Read MAC address. 749 */ 750 fxp_read_eeprom(sc, myea, 0, 3); 751 sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; 752 sc->arpcom.ac_enaddr[1] = myea[0] >> 8; 753 sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; 754 sc->arpcom.ac_enaddr[3] = myea[1] >> 8; 755 sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; 756 sc->arpcom.ac_enaddr[5] = myea[2] >> 8; 757 if (bootverbose) { 758 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 759 pci_get_vendor(dev), pci_get_device(dev), 760 pci_get_subvendor(dev), pci_get_subdevice(dev), 761 pci_get_revid(dev)); 762 fxp_read_eeprom(sc, &data, 10, 1); 763 device_printf(dev, "Dynamic Standby mode is %s\n", 764 data & 0x02 ? "enabled" : "disabled"); 765 } 766 767 /* 768 * If this is only a 10Mbps device, then there is no MII, and 769 * the PHY will use a serial interface instead. 770 * 771 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 772 * doesn't have a programming interface of any sort. The 773 * media is sensed automatically based on how the link partner 774 * is configured. This is, in essence, manual configuration. 775 */ 776 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 777 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 778 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 779 } else { 780 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 781 fxp_ifmedia_sts)) { 782 device_printf(dev, "MII without any PHY!\n"); 783 error = ENXIO; 784 goto fail; 785 } 786 } 787 788 ifp = &sc->arpcom.ac_if; 789 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 790 ifp->if_output = ether_output; 791 ifp->if_baudrate = 100000000; 792 ifp->if_init = fxp_init; 793 ifp->if_softc = sc; 794 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 795 ifp->if_ioctl = fxp_ioctl; 796 ifp->if_start = fxp_start; 797 ifp->if_watchdog = fxp_watchdog; 798 799 /* Enable checksum offload for 82550 or better chips */ 800 if (sc->flags & FXP_FLAG_EXT_RFA) { 801 ifp->if_hwassist = FXP_CSUM_FEATURES; 802 ifp->if_capabilities = IFCAP_HWCSUM; 803 ifp->if_capenable = ifp->if_capabilities; 804 } 805 806 /* 807 * Attach the interface. 808 */ 809 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 810 811 /* 812 * Tell the upper layer(s) we support long frames. 813 */ 814 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 815 ifp->if_capabilities |= IFCAP_VLAN_MTU; 816 817 /* 818 * Let the system queue as many packets as we have available 819 * TX descriptors. 820 */ 821 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 822 823 /* 824 * Hook our interrupt after all initialization is complete. 825 * XXX This driver has been tested with the INTR_MPSAFFE flag set 826 * however, ifp and its functions are not fully locked so MPSAFE 827 * should not be used unless you can handle potential data loss. 828 */ 829 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 830 fxp_intr, sc, &sc->ih); 831 if (error) { 832 device_printf(dev, "could not setup irq\n"); 833 ether_ifdetach(&sc->arpcom.ac_if); 834 goto fail; 835 } 836 837 fail: 838 splx(s); 839 if (error) 840 fxp_release(sc); 841 return (error); 842 } 843 844 /* 845 * Release all resources. The softc lock should not be held and the 846 * interrupt should already be torn down. 847 */ 848 static void 849 fxp_release(struct fxp_softc *sc) 850 { 851 struct fxp_rx *rxp; 852 struct fxp_tx *txp; 853 int i; 854 855 mtx_assert(&sc->sc_mtx, MA_NOTOWNED); 856 if (sc->ih) 857 panic("fxp_release() called with intr handle still active"); 858 if (sc->miibus) 859 device_delete_child(sc->dev, sc->miibus); 860 bus_generic_detach(sc->dev); 861 ifmedia_removeall(&sc->sc_media); 862 if (sc->fxp_desc.cbl_list) { 863 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 864 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 865 sc->cbl_map); 866 } 867 if (sc->fxp_stats) { 868 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 869 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 870 } 871 if (sc->mcsp) { 872 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 873 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 874 } 875 if (sc->irq) 876 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 877 if (sc->mem) 878 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 879 if (sc->fxp_mtag) { 880 for (i = 0; i < FXP_NRFABUFS; i++) { 881 rxp = &sc->fxp_desc.rx_list[i]; 882 if (rxp->rx_mbuf != NULL) { 883 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 884 BUS_DMASYNC_POSTREAD); 885 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 886 m_freem(rxp->rx_mbuf); 887 } 888 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 889 } 890 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 891 bus_dma_tag_destroy(sc->fxp_mtag); 892 } 893 if (sc->fxp_stag) { 894 for (i = 0; i < FXP_NTXCB; i++) { 895 txp = &sc->fxp_desc.tx_list[i]; 896 if (txp->tx_mbuf != NULL) { 897 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 898 BUS_DMASYNC_POSTWRITE); 899 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 900 m_freem(txp->tx_mbuf); 901 } 902 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 903 } 904 bus_dma_tag_destroy(sc->fxp_stag); 905 } 906 if (sc->cbl_tag) 907 bus_dma_tag_destroy(sc->cbl_tag); 908 if (sc->mcs_tag) 909 bus_dma_tag_destroy(sc->mcs_tag); 910 911 sysctl_ctx_free(&sc->sysctl_ctx); 912 913 mtx_destroy(&sc->sc_mtx); 914 } 915 916 /* 917 * Detach interface. 918 */ 919 static int 920 fxp_detach(device_t dev) 921 { 922 struct fxp_softc *sc = device_get_softc(dev); 923 int s; 924 925 FXP_LOCK(sc); 926 s = splimp(); 927 928 sc->suspended = 1; /* Do same thing as we do for suspend */ 929 /* 930 * Close down routes etc. 931 */ 932 ether_ifdetach(&sc->arpcom.ac_if); 933 934 /* 935 * Stop DMA and drop transmit queue, but disable interrupts first. 936 */ 937 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 938 fxp_stop(sc); 939 FXP_UNLOCK(sc); 940 941 /* 942 * Unhook interrupt before dropping lock. This is to prevent 943 * races with fxp_intr(). 944 */ 945 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 946 sc->ih = NULL; 947 948 splx(s); 949 950 /* Release our allocated resources. */ 951 fxp_release(sc); 952 return (0); 953 } 954 955 /* 956 * Device shutdown routine. Called at system shutdown after sync. The 957 * main purpose of this routine is to shut off receiver DMA so that 958 * kernel memory doesn't get clobbered during warmboot. 959 */ 960 static int 961 fxp_shutdown(device_t dev) 962 { 963 /* 964 * Make sure that DMA is disabled prior to reboot. Not doing 965 * do could allow DMA to corrupt kernel memory during the 966 * reboot before the driver initializes. 967 */ 968 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 969 return (0); 970 } 971 972 /* 973 * Device suspend routine. Stop the interface and save some PCI 974 * settings in case the BIOS doesn't restore them properly on 975 * resume. 976 */ 977 static int 978 fxp_suspend(device_t dev) 979 { 980 struct fxp_softc *sc = device_get_softc(dev); 981 int i, s; 982 983 FXP_LOCK(sc); 984 s = splimp(); 985 986 fxp_stop(sc); 987 988 for (i = 0; i < 5; i++) 989 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 990 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 991 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 992 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 993 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 994 995 sc->suspended = 1; 996 997 FXP_UNLOCK(sc); 998 splx(s); 999 return (0); 1000 } 1001 1002 /* 1003 * Device resume routine. Restore some PCI settings in case the BIOS 1004 * doesn't, re-enable busmastering, and restart the interface if 1005 * appropriate. 1006 */ 1007 static int 1008 fxp_resume(device_t dev) 1009 { 1010 struct fxp_softc *sc = device_get_softc(dev); 1011 struct ifnet *ifp = &sc->sc_if; 1012 u_int16_t pci_command; 1013 int i, s; 1014 1015 FXP_LOCK(sc); 1016 s = splimp(); 1017 #ifndef BURN_BRIDGES 1018 fxp_powerstate_d0(dev); 1019 #endif 1020 /* better way to do this? */ 1021 for (i = 0; i < 5; i++) 1022 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1023 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1024 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1025 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1026 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1027 1028 /* reenable busmastering */ 1029 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 1030 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1031 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 1032 1033 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1034 DELAY(10); 1035 1036 /* reinitialize interface if necessary */ 1037 if (ifp->if_flags & IFF_UP) 1038 fxp_init_body(sc); 1039 1040 sc->suspended = 0; 1041 1042 FXP_UNLOCK(sc); 1043 splx(s); 1044 return (0); 1045 } 1046 1047 static void 1048 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 1049 { 1050 u_int16_t reg; 1051 int x; 1052 1053 /* 1054 * Shift in data. 1055 */ 1056 for (x = 1 << (length - 1); x; x >>= 1) { 1057 if (data & x) 1058 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1059 else 1060 reg = FXP_EEPROM_EECS; 1061 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1062 DELAY(1); 1063 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1064 DELAY(1); 1065 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1066 DELAY(1); 1067 } 1068 } 1069 1070 /* 1071 * Read from the serial EEPROM. Basically, you manually shift in 1072 * the read opcode (one bit at a time) and then shift in the address, 1073 * and then you shift out the data (all of this one bit at a time). 1074 * The word size is 16 bits, so you have to provide the address for 1075 * every 16 bits of data. 1076 */ 1077 static u_int16_t 1078 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1079 { 1080 u_int16_t reg, data; 1081 int x; 1082 1083 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1084 /* 1085 * Shift in read opcode. 1086 */ 1087 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1088 /* 1089 * Shift in address. 1090 */ 1091 data = 0; 1092 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1093 if (offset & x) 1094 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1095 else 1096 reg = FXP_EEPROM_EECS; 1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1098 DELAY(1); 1099 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1100 DELAY(1); 1101 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1102 DELAY(1); 1103 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1104 data++; 1105 if (autosize && reg == 0) { 1106 sc->eeprom_size = data; 1107 break; 1108 } 1109 } 1110 /* 1111 * Shift out data. 1112 */ 1113 data = 0; 1114 reg = FXP_EEPROM_EECS; 1115 for (x = 1 << 15; x; x >>= 1) { 1116 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1117 DELAY(1); 1118 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1119 data |= x; 1120 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1121 DELAY(1); 1122 } 1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1124 DELAY(1); 1125 1126 return (data); 1127 } 1128 1129 static void 1130 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 1131 { 1132 int i; 1133 1134 /* 1135 * Erase/write enable. 1136 */ 1137 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1138 fxp_eeprom_shiftin(sc, 0x4, 3); 1139 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1140 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1141 DELAY(1); 1142 /* 1143 * Shift in write opcode, address, data. 1144 */ 1145 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1146 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1147 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1148 fxp_eeprom_shiftin(sc, data, 16); 1149 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1150 DELAY(1); 1151 /* 1152 * Wait for EEPROM to finish up. 1153 */ 1154 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1155 DELAY(1); 1156 for (i = 0; i < 1000; i++) { 1157 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1158 break; 1159 DELAY(50); 1160 } 1161 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1162 DELAY(1); 1163 /* 1164 * Erase/write disable. 1165 */ 1166 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1167 fxp_eeprom_shiftin(sc, 0x4, 3); 1168 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1170 DELAY(1); 1171 } 1172 1173 /* 1174 * From NetBSD: 1175 * 1176 * Figure out EEPROM size. 1177 * 1178 * 559's can have either 64-word or 256-word EEPROMs, the 558 1179 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1180 * talks about the existance of 16 to 256 word EEPROMs. 1181 * 1182 * The only known sizes are 64 and 256, where the 256 version is used 1183 * by CardBus cards to store CIS information. 1184 * 1185 * The address is shifted in msb-to-lsb, and after the last 1186 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1187 * after which follows the actual data. We try to detect this zero, by 1188 * probing the data-out bit in the EEPROM control register just after 1189 * having shifted in a bit. If the bit is zero, we assume we've 1190 * shifted enough address bits. The data-out should be tri-state, 1191 * before this, which should translate to a logical one. 1192 */ 1193 static void 1194 fxp_autosize_eeprom(struct fxp_softc *sc) 1195 { 1196 1197 /* guess maximum size of 256 words */ 1198 sc->eeprom_size = 8; 1199 1200 /* autosize */ 1201 (void) fxp_eeprom_getword(sc, 0, 1); 1202 } 1203 1204 static void 1205 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1206 { 1207 int i; 1208 1209 for (i = 0; i < words; i++) 1210 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1211 } 1212 1213 static void 1214 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1215 { 1216 int i; 1217 1218 for (i = 0; i < words; i++) 1219 fxp_eeprom_putword(sc, offset + i, data[i]); 1220 } 1221 1222 static void 1223 fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 1224 bus_size_t mapsize, int error) 1225 { 1226 struct fxp_softc *sc; 1227 struct fxp_cb_tx *txp; 1228 int i; 1229 1230 if (error) 1231 return; 1232 1233 KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); 1234 1235 sc = arg; 1236 txp = sc->fxp_desc.tx_last->tx_next->tx_cb; 1237 for (i = 0; i < nseg; i++) { 1238 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1239 /* 1240 * If this is an 82550/82551, then we're using extended 1241 * TxCBs _and_ we're using checksum offload. This means 1242 * that the TxCB is really an IPCB. One major difference 1243 * between the two is that with plain extended TxCBs, 1244 * the bottom half of the TxCB contains two entries from 1245 * the TBD array, whereas IPCBs contain just one entry: 1246 * one entry (8 bytes) has been sacrificed for the TCP/IP 1247 * checksum offload control bits. So to make things work 1248 * right, we have to start filling in the TBD array 1249 * starting from a different place depending on whether 1250 * the chip is an 82550/82551 or not. 1251 */ 1252 if (sc->flags & FXP_FLAG_EXT_RFA) { 1253 txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1254 txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1255 } else { 1256 txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1257 txp->tbd[i].tb_size = htole32(segs[i].ds_len); 1258 } 1259 } 1260 txp->tbd_number = nseg; 1261 } 1262 1263 /* 1264 * Grab the softc lock and call the real fxp_start_body() routine 1265 */ 1266 static void 1267 fxp_start(struct ifnet *ifp) 1268 { 1269 struct fxp_softc *sc = ifp->if_softc; 1270 1271 FXP_LOCK(sc); 1272 fxp_start_body(ifp); 1273 FXP_UNLOCK(sc); 1274 } 1275 1276 /* 1277 * Start packet transmission on the interface. 1278 * This routine must be called with the softc lock held, and is an 1279 * internal entry point only. 1280 */ 1281 static void 1282 fxp_start_body(struct ifnet *ifp) 1283 { 1284 struct fxp_softc *sc = ifp->if_softc; 1285 struct fxp_tx *txp; 1286 struct mbuf *mb_head; 1287 int error; 1288 1289 mtx_assert(&sc->sc_mtx, MA_OWNED); 1290 /* 1291 * See if we need to suspend xmit until the multicast filter 1292 * has been reprogrammed (which can only be done at the head 1293 * of the command chain). 1294 */ 1295 if (sc->need_mcsetup) { 1296 return; 1297 } 1298 1299 txp = NULL; 1300 1301 /* 1302 * We're finished if there is nothing more to add to the list or if 1303 * we're all filled up with buffers to transmit. 1304 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1305 * a NOP command when needed. 1306 */ 1307 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1308 1309 /* 1310 * Grab a packet to transmit. 1311 */ 1312 IF_DEQUEUE(&ifp->if_snd, mb_head); 1313 1314 /* 1315 * Get pointer to next available tx desc. 1316 */ 1317 txp = sc->fxp_desc.tx_last->tx_next; 1318 1319 /* 1320 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1321 * Ethernet Controller Family Open Source Software 1322 * Developer Manual says: 1323 * Using software parsing is only allowed with legal 1324 * TCP/IP or UDP/IP packets. 1325 * ... 1326 * For all other datagrams, hardware parsing must 1327 * be used. 1328 * Software parsing appears to truncate ICMP and 1329 * fragmented UDP packets that contain one to three 1330 * bytes in the second (and final) mbuf of the packet. 1331 */ 1332 if (sc->flags & FXP_FLAG_EXT_RFA) 1333 txp->tx_cb->ipcb_ip_activation_high = 1334 FXP_IPCB_HARDWAREPARSING_ENABLE; 1335 1336 /* 1337 * Deal with TCP/IP checksum offload. Note that 1338 * in order for TCP checksum offload to work, 1339 * the pseudo header checksum must have already 1340 * been computed and stored in the checksum field 1341 * in the TCP header. The stack should have 1342 * already done this for us. 1343 */ 1344 1345 if (mb_head->m_pkthdr.csum_flags) { 1346 if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1347 txp->tx_cb->ipcb_ip_schedule = 1348 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1349 if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) 1350 txp->tx_cb->ipcb_ip_schedule |= 1351 FXP_IPCB_TCP_PACKET; 1352 } 1353 #ifdef FXP_IP_CSUM_WAR 1354 /* 1355 * XXX The 82550 chip appears to have trouble 1356 * dealing with IP header checksums in very small 1357 * datagrams, namely fragments from 1 to 3 bytes 1358 * in size. For example, say you want to transmit 1359 * a UDP packet of 1473 bytes. The packet will be 1360 * fragmented over two IP datagrams, the latter 1361 * containing only one byte of data. The 82550 will 1362 * botch the header checksum on the 1-byte fragment. 1363 * As long as the datagram contains 4 or more bytes 1364 * of data, you're ok. 1365 * 1366 * The following code attempts to work around this 1367 * problem: if the datagram is less than 38 bytes 1368 * in size (14 bytes ether header, 20 bytes IP header, 1369 * plus 4 bytes of data), we punt and compute the IP 1370 * header checksum by hand. This workaround doesn't 1371 * work very well, however, since it can be fooled 1372 * by things like VLAN tags and IP options that make 1373 * the header sizes/offsets vary. 1374 */ 1375 1376 if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { 1377 if (mb_head->m_pkthdr.len < 38) { 1378 struct ip *ip; 1379 mb_head->m_data += ETHER_HDR_LEN; 1380 ip = mtod(mb_head, struct ip *); 1381 ip->ip_sum = in_cksum(mb_head, 1382 ip->ip_hl << 2); 1383 mb_head->m_data -= ETHER_HDR_LEN; 1384 } else { 1385 txp->tx_cb->ipcb_ip_activation_high = 1386 FXP_IPCB_HARDWAREPARSING_ENABLE; 1387 txp->tx_cb->ipcb_ip_schedule |= 1388 FXP_IPCB_IP_CHECKSUM_ENABLE; 1389 } 1390 } 1391 #endif 1392 } 1393 1394 /* 1395 * Go through each of the mbufs in the chain and initialize 1396 * the transmit buffer descriptors with the physical address 1397 * and size of the mbuf. 1398 */ 1399 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1400 mb_head, fxp_dma_map_txbuf, sc, 0); 1401 1402 if (error && error != EFBIG) { 1403 device_printf(sc->dev, "can't map mbuf (error %d)\n", 1404 error); 1405 m_freem(mb_head); 1406 break; 1407 } 1408 1409 if (error) { 1410 struct mbuf *mn; 1411 1412 /* 1413 * We ran out of segments. We have to recopy this 1414 * mbuf chain first. Bail out if we can't get the 1415 * new buffers. 1416 */ 1417 mn = m_defrag(mb_head, M_DONTWAIT); 1418 if (mn == NULL) { 1419 m_freem(mb_head); 1420 break; 1421 } else { 1422 mb_head = mn; 1423 } 1424 error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, 1425 mb_head, fxp_dma_map_txbuf, sc, 0); 1426 if (error) { 1427 device_printf(sc->dev, 1428 "can't map mbuf (error %d)\n", error); 1429 m_freem(mb_head); 1430 break; 1431 } 1432 } 1433 1434 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1435 BUS_DMASYNC_PREWRITE); 1436 1437 txp->tx_mbuf = mb_head; 1438 txp->tx_cb->cb_status = 0; 1439 txp->tx_cb->byte_count = 0; 1440 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1441 txp->tx_cb->cb_command = 1442 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1443 FXP_CB_COMMAND_S); 1444 } else { 1445 txp->tx_cb->cb_command = 1446 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1447 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1448 /* 1449 * Set a 5 second timer just in case we don't hear 1450 * from the card again. 1451 */ 1452 ifp->if_timer = 5; 1453 } 1454 txp->tx_cb->tx_threshold = tx_threshold; 1455 1456 /* 1457 * Advance the end of list forward. 1458 */ 1459 1460 #ifdef __alpha__ 1461 /* 1462 * On platforms which can't access memory in 16-bit 1463 * granularities, we must prevent the card from DMA'ing 1464 * up the status while we update the command field. 1465 * This could cause us to overwrite the completion status. 1466 * XXX This is probably bogus and we're _not_ looking 1467 * for atomicity here. 1468 */ 1469 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1470 htole16(FXP_CB_COMMAND_S)); 1471 #else 1472 sc->fxp_desc.tx_last->tx_cb->cb_command &= 1473 htole16(~FXP_CB_COMMAND_S); 1474 #endif /*__alpha__*/ 1475 sc->fxp_desc.tx_last = txp; 1476 1477 /* 1478 * Advance the beginning of the list forward if there are 1479 * no other packets queued (when nothing is queued, tx_first 1480 * sits on the last TxCB that was sent out). 1481 */ 1482 if (sc->tx_queued == 0) 1483 sc->fxp_desc.tx_first = txp; 1484 1485 sc->tx_queued++; 1486 1487 /* 1488 * Pass packet to bpf if there is a listener. 1489 */ 1490 BPF_MTAP(ifp, mb_head); 1491 } 1492 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1493 1494 /* 1495 * We're finished. If we added to the list, issue a RESUME to get DMA 1496 * going again if suspended. 1497 */ 1498 if (txp != NULL) { 1499 fxp_scb_wait(sc); 1500 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1501 } 1502 } 1503 1504 #ifdef DEVICE_POLLING 1505 static poll_handler_t fxp_poll; 1506 1507 static void 1508 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1509 { 1510 struct fxp_softc *sc = ifp->if_softc; 1511 u_int8_t statack; 1512 1513 FXP_LOCK(sc); 1514 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1515 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1516 FXP_UNLOCK(sc); 1517 return; 1518 } 1519 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1520 FXP_SCB_STATACK_FR; 1521 if (cmd == POLL_AND_CHECK_STATUS) { 1522 u_int8_t tmp; 1523 1524 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1525 if (tmp == 0xff || tmp == 0) { 1526 FXP_UNLOCK(sc); 1527 return; /* nothing to do */ 1528 } 1529 tmp &= ~statack; 1530 /* ack what we can */ 1531 if (tmp != 0) 1532 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1533 statack |= tmp; 1534 } 1535 fxp_intr_body(sc, ifp, statack, count); 1536 FXP_UNLOCK(sc); 1537 } 1538 #endif /* DEVICE_POLLING */ 1539 1540 /* 1541 * Process interface interrupts. 1542 */ 1543 static void 1544 fxp_intr(void *xsc) 1545 { 1546 struct fxp_softc *sc = xsc; 1547 struct ifnet *ifp = &sc->sc_if; 1548 u_int8_t statack; 1549 1550 FXP_LOCK(sc); 1551 if (sc->suspended) { 1552 FXP_UNLOCK(sc); 1553 return; 1554 } 1555 1556 #ifdef DEVICE_POLLING 1557 if (ifp->if_flags & IFF_POLLING) { 1558 FXP_UNLOCK(sc); 1559 return; 1560 } 1561 if (ether_poll_register(fxp_poll, ifp)) { 1562 /* disable interrupts */ 1563 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1564 FXP_UNLOCK(sc); 1565 fxp_poll(ifp, 0, 1); 1566 return; 1567 } 1568 #endif 1569 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1570 /* 1571 * It should not be possible to have all bits set; the 1572 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1573 * all bits are set, this may indicate that the card has 1574 * been physically ejected, so ignore it. 1575 */ 1576 if (statack == 0xff) { 1577 FXP_UNLOCK(sc); 1578 return; 1579 } 1580 1581 /* 1582 * First ACK all the interrupts in this pass. 1583 */ 1584 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1585 fxp_intr_body(sc, ifp, statack, -1); 1586 } 1587 FXP_UNLOCK(sc); 1588 } 1589 1590 static void 1591 fxp_txeof(struct fxp_softc *sc) 1592 { 1593 struct fxp_tx *txp; 1594 1595 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1596 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1597 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1598 txp = txp->tx_next) { 1599 if (txp->tx_mbuf != NULL) { 1600 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1601 BUS_DMASYNC_POSTWRITE); 1602 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1603 m_freem(txp->tx_mbuf); 1604 txp->tx_mbuf = NULL; 1605 /* clear this to reset csum offload bits */ 1606 txp->tx_cb->tbd[0].tb_addr = 0; 1607 } 1608 sc->tx_queued--; 1609 } 1610 sc->fxp_desc.tx_first = txp; 1611 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1612 } 1613 1614 static void 1615 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, 1616 int count) 1617 { 1618 struct mbuf *m; 1619 struct fxp_rx *rxp; 1620 struct fxp_rfa *rfa; 1621 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1622 1623 mtx_assert(&sc->sc_mtx, MA_OWNED); 1624 if (rnr) 1625 fxp_rnr++; 1626 #ifdef DEVICE_POLLING 1627 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1628 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1629 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1630 rnr = 1; 1631 } 1632 #endif 1633 1634 /* 1635 * Free any finished transmit mbuf chains. 1636 * 1637 * Handle the CNA event likt a CXTNO event. It used to 1638 * be that this event (control unit not ready) was not 1639 * encountered, but it is now with the SMPng modifications. 1640 * The exact sequence of events that occur when the interface 1641 * is brought up are different now, and if this event 1642 * goes unhandled, the configuration/rxfilter setup sequence 1643 * can stall for several seconds. The result is that no 1644 * packets go out onto the wire for about 5 to 10 seconds 1645 * after the interface is ifconfig'ed for the first time. 1646 */ 1647 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1648 fxp_txeof(sc); 1649 1650 ifp->if_timer = 0; 1651 if (sc->tx_queued == 0) { 1652 if (sc->need_mcsetup) 1653 fxp_mc_setup(sc); 1654 } 1655 /* 1656 * Try to start more packets transmitting. 1657 */ 1658 if (ifp->if_snd.ifq_head != NULL) 1659 fxp_start_body(ifp); 1660 } 1661 1662 /* 1663 * Just return if nothing happened on the receive side. 1664 */ 1665 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1666 return; 1667 1668 /* 1669 * Process receiver interrupts. If a no-resource (RNR) 1670 * condition exists, get whatever packets we can and 1671 * re-start the receiver. 1672 * 1673 * When using polling, we do not process the list to completion, 1674 * so when we get an RNR interrupt we must defer the restart 1675 * until we hit the last buffer with the C bit set. 1676 * If we run out of cycles and rfa_headm has the C bit set, 1677 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1678 * that the info will be used in the subsequent polling cycle. 1679 */ 1680 for (;;) { 1681 rxp = sc->fxp_desc.rx_head; 1682 m = rxp->rx_mbuf; 1683 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1684 RFA_ALIGNMENT_FUDGE); 1685 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1686 BUS_DMASYNC_POSTREAD); 1687 1688 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1689 if (count >= 0 && count-- == 0) { 1690 if (rnr) { 1691 /* Defer RNR processing until the next time. */ 1692 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1693 rnr = 0; 1694 } 1695 break; 1696 } 1697 #endif /* DEVICE_POLLING */ 1698 1699 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1700 break; 1701 1702 /* 1703 * Advance head forward. 1704 */ 1705 sc->fxp_desc.rx_head = rxp->rx_next; 1706 1707 /* 1708 * Add a new buffer to the receive chain. 1709 * If this fails, the old buffer is recycled 1710 * instead. 1711 */ 1712 if (fxp_add_rfabuf(sc, rxp) == 0) { 1713 int total_len; 1714 1715 /* 1716 * Fetch packet length (the top 2 bits of 1717 * actual_size are flags set by the controller 1718 * upon completion), and drop the packet in case 1719 * of bogus length or CRC errors. 1720 */ 1721 total_len = le16toh(rfa->actual_size) & 0x3fff; 1722 if (total_len < sizeof(struct ether_header) || 1723 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1724 sc->rfa_size || 1725 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1726 m_freem(m); 1727 continue; 1728 } 1729 1730 /* Do IP checksum checking. */ 1731 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1732 if (rfa->rfax_csum_sts & 1733 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1734 m->m_pkthdr.csum_flags |= 1735 CSUM_IP_CHECKED; 1736 if (rfa->rfax_csum_sts & 1737 FXP_RFDX_CS_IP_CSUM_VALID) 1738 m->m_pkthdr.csum_flags |= 1739 CSUM_IP_VALID; 1740 if ((rfa->rfax_csum_sts & 1741 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1742 (rfa->rfax_csum_sts & 1743 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1744 m->m_pkthdr.csum_flags |= 1745 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1746 m->m_pkthdr.csum_data = 0xffff; 1747 } 1748 } 1749 1750 m->m_pkthdr.len = m->m_len = total_len; 1751 m->m_pkthdr.rcvif = ifp; 1752 1753 /* 1754 * Drop locks before calling if_input() since it 1755 * may re-enter fxp_start() in the netisr case. 1756 * This would result in a lock reversal. Better 1757 * performance might be obtained by chaining all 1758 * packets received, dropping the lock, and then 1759 * calling if_input() on each one. 1760 */ 1761 FXP_UNLOCK(sc); 1762 (*ifp->if_input)(ifp, m); 1763 FXP_LOCK(sc); 1764 } 1765 } 1766 if (rnr) { 1767 fxp_scb_wait(sc); 1768 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1769 sc->fxp_desc.rx_head->rx_addr); 1770 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1771 } 1772 } 1773 1774 /* 1775 * Update packet in/out/collision statistics. The i82557 doesn't 1776 * allow you to access these counters without doing a fairly 1777 * expensive DMA to get _all_ of the statistics it maintains, so 1778 * we do this operation here only once per second. The statistics 1779 * counters in the kernel are updated from the previous dump-stats 1780 * DMA and then a new dump-stats DMA is started. The on-chip 1781 * counters are zeroed when the DMA completes. If we can't start 1782 * the DMA immediately, we don't wait - we just prepare to read 1783 * them again next time. 1784 */ 1785 static void 1786 fxp_tick(void *xsc) 1787 { 1788 struct fxp_softc *sc = xsc; 1789 struct ifnet *ifp = &sc->sc_if; 1790 struct fxp_stats *sp = sc->fxp_stats; 1791 int s; 1792 1793 FXP_LOCK(sc); 1794 s = splimp(); 1795 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1796 ifp->if_opackets += le32toh(sp->tx_good); 1797 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1798 if (sp->rx_good) { 1799 ifp->if_ipackets += le32toh(sp->rx_good); 1800 sc->rx_idle_secs = 0; 1801 } else { 1802 /* 1803 * Receiver's been idle for another second. 1804 */ 1805 sc->rx_idle_secs++; 1806 } 1807 ifp->if_ierrors += 1808 le32toh(sp->rx_crc_errors) + 1809 le32toh(sp->rx_alignment_errors) + 1810 le32toh(sp->rx_rnr_errors) + 1811 le32toh(sp->rx_overrun_errors); 1812 /* 1813 * If any transmit underruns occured, bump up the transmit 1814 * threshold by another 512 bytes (64 * 8). 1815 */ 1816 if (sp->tx_underruns) { 1817 ifp->if_oerrors += le32toh(sp->tx_underruns); 1818 if (tx_threshold < 192) 1819 tx_threshold += 64; 1820 } 1821 1822 /* 1823 * Release any xmit buffers that have completed DMA. This isn't 1824 * strictly necessary to do here, but it's advantagous for mbufs 1825 * with external storage to be released in a timely manner rather 1826 * than being defered for a potentially long time. This limits 1827 * the delay to a maximum of one second. 1828 */ 1829 fxp_txeof(sc); 1830 1831 /* 1832 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1833 * then assume the receiver has locked up and attempt to clear 1834 * the condition by reprogramming the multicast filter. This is 1835 * a work-around for a bug in the 82557 where the receiver locks 1836 * up if it gets certain types of garbage in the syncronization 1837 * bits prior to the packet header. This bug is supposed to only 1838 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1839 * mode as well (perhaps due to a 10/100 speed transition). 1840 */ 1841 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1842 sc->rx_idle_secs = 0; 1843 fxp_mc_setup(sc); 1844 } 1845 /* 1846 * If there is no pending command, start another stats 1847 * dump. Otherwise punt for now. 1848 */ 1849 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1850 /* 1851 * Start another stats dump. 1852 */ 1853 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1854 BUS_DMASYNC_PREREAD); 1855 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1856 } else { 1857 /* 1858 * A previous command is still waiting to be accepted. 1859 * Just zero our copy of the stats and wait for the 1860 * next timer event to update them. 1861 */ 1862 sp->tx_good = 0; 1863 sp->tx_underruns = 0; 1864 sp->tx_total_collisions = 0; 1865 1866 sp->rx_good = 0; 1867 sp->rx_crc_errors = 0; 1868 sp->rx_alignment_errors = 0; 1869 sp->rx_rnr_errors = 0; 1870 sp->rx_overrun_errors = 0; 1871 } 1872 if (sc->miibus != NULL) 1873 mii_tick(device_get_softc(sc->miibus)); 1874 1875 /* 1876 * Schedule another timeout one second from now. 1877 */ 1878 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1879 FXP_UNLOCK(sc); 1880 splx(s); 1881 } 1882 1883 /* 1884 * Stop the interface. Cancels the statistics updater and resets 1885 * the interface. 1886 */ 1887 static void 1888 fxp_stop(struct fxp_softc *sc) 1889 { 1890 struct ifnet *ifp = &sc->sc_if; 1891 struct fxp_tx *txp; 1892 int i; 1893 1894 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1895 ifp->if_timer = 0; 1896 1897 #ifdef DEVICE_POLLING 1898 ether_poll_deregister(ifp); 1899 #endif 1900 /* 1901 * Cancel stats updater. 1902 */ 1903 callout_stop(&sc->stat_ch); 1904 1905 /* 1906 * Issue software reset, which also unloads the microcode. 1907 */ 1908 sc->flags &= ~FXP_FLAG_UCODE; 1909 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1910 DELAY(50); 1911 1912 /* 1913 * Release any xmit buffers. 1914 */ 1915 txp = sc->fxp_desc.tx_list; 1916 if (txp != NULL) { 1917 for (i = 0; i < FXP_NTXCB; i++) { 1918 if (txp[i].tx_mbuf != NULL) { 1919 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1920 BUS_DMASYNC_POSTWRITE); 1921 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1922 m_freem(txp[i].tx_mbuf); 1923 txp[i].tx_mbuf = NULL; 1924 /* clear this to reset csum offload bits */ 1925 txp[i].tx_cb->tbd[0].tb_addr = 0; 1926 } 1927 } 1928 } 1929 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1930 sc->tx_queued = 0; 1931 } 1932 1933 /* 1934 * Watchdog/transmission transmit timeout handler. Called when a 1935 * transmission is started on the interface, but no interrupt is 1936 * received before the timeout. This usually indicates that the 1937 * card has wedged for some reason. 1938 */ 1939 static void 1940 fxp_watchdog(struct ifnet *ifp) 1941 { 1942 struct fxp_softc *sc = ifp->if_softc; 1943 1944 FXP_LOCK(sc); 1945 device_printf(sc->dev, "device timeout\n"); 1946 ifp->if_oerrors++; 1947 1948 fxp_init_body(sc); 1949 FXP_UNLOCK(sc); 1950 } 1951 1952 /* 1953 * Acquire locks and then call the real initialization function. This 1954 * is necessary because ether_ioctl() calls if_init() and this would 1955 * result in mutex recursion if the mutex was held. 1956 */ 1957 static void 1958 fxp_init(void *xsc) 1959 { 1960 struct fxp_softc *sc = xsc; 1961 1962 FXP_LOCK(sc); 1963 fxp_init_body(sc); 1964 FXP_UNLOCK(sc); 1965 } 1966 1967 /* 1968 * Perform device initialization. This routine must be called with the 1969 * softc lock held. 1970 */ 1971 static void 1972 fxp_init_body(struct fxp_softc *sc) 1973 { 1974 struct ifnet *ifp = &sc->sc_if; 1975 struct fxp_cb_config *cbp; 1976 struct fxp_cb_ias *cb_ias; 1977 struct fxp_cb_tx *tcbp; 1978 struct fxp_tx *txp; 1979 struct fxp_cb_mcs *mcsp; 1980 int i, prm, s; 1981 1982 mtx_assert(&sc->sc_mtx, MA_OWNED); 1983 s = splimp(); 1984 /* 1985 * Cancel any pending I/O 1986 */ 1987 fxp_stop(sc); 1988 1989 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1990 1991 /* 1992 * Initialize base of CBL and RFA memory. Loading with zero 1993 * sets it up for regular linear addressing. 1994 */ 1995 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1996 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1997 1998 fxp_scb_wait(sc); 1999 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 2000 2001 /* 2002 * Initialize base of dump-stats buffer. 2003 */ 2004 fxp_scb_wait(sc); 2005 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 2006 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 2007 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 2008 2009 /* 2010 * Attempt to load microcode if requested. 2011 */ 2012 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 2013 fxp_load_ucode(sc); 2014 2015 /* 2016 * Initialize the multicast address list. 2017 */ 2018 if (fxp_mc_addrs(sc)) { 2019 mcsp = sc->mcsp; 2020 mcsp->cb_status = 0; 2021 mcsp->cb_command = 2022 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2023 mcsp->link_addr = 0xffffffff; 2024 /* 2025 * Start the multicast setup command. 2026 */ 2027 fxp_scb_wait(sc); 2028 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2029 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2030 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2031 /* ...and wait for it to complete. */ 2032 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 2033 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 2034 BUS_DMASYNC_POSTWRITE); 2035 } 2036 2037 /* 2038 * We temporarily use memory that contains the TxCB list to 2039 * construct the config CB. The TxCB list memory is rebuilt 2040 * later. 2041 */ 2042 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 2043 2044 /* 2045 * This bcopy is kind of disgusting, but there are a bunch of must be 2046 * zero and must be one bits in this structure and this is the easiest 2047 * way to initialize them all to proper values. 2048 */ 2049 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 2050 2051 cbp->cb_status = 0; 2052 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 2053 FXP_CB_COMMAND_EL); 2054 cbp->link_addr = 0xffffffff; /* (no) next command */ 2055 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 2056 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 2057 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2058 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2059 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2060 cbp->type_enable = 0; /* actually reserved */ 2061 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2062 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2063 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2064 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2065 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2066 cbp->late_scb = 0; /* (don't) defer SCB update */ 2067 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2068 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2069 cbp->ci_int = 1; /* interrupt on CU idle */ 2070 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2071 cbp->ext_stats_dis = 1; /* disable extended counters */ 2072 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2073 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 2074 cbp->disc_short_rx = !prm; /* discard short packets */ 2075 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2076 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2077 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2078 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2079 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2080 cbp->csma_dis = 0; /* (don't) disable link */ 2081 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2082 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2083 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2084 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2085 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2086 cbp->nsai = 1; /* (don't) disable source addr insert */ 2087 cbp->preamble_length = 2; /* (7 byte) preamble */ 2088 cbp->loopback = 0; /* (don't) loopback */ 2089 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2090 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2091 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2092 cbp->promiscuous = prm; /* promiscuous mode */ 2093 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2094 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2095 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2096 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2097 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2098 2099 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2100 cbp->padding = 1; /* (do) pad short tx packets */ 2101 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2102 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2103 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2104 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2105 /* must set wake_en in PMCSR also */ 2106 cbp->force_fdx = 0; /* (don't) force full duplex */ 2107 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2108 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2109 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2110 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2111 2112 if (fxp_noflow || sc->revision == FXP_REV_82557) { 2113 /* 2114 * The 82557 has no hardware flow control, the values 2115 * below are the defaults for the chip. 2116 */ 2117 cbp->fc_delay_lsb = 0; 2118 cbp->fc_delay_msb = 0x40; 2119 cbp->pri_fc_thresh = 3; 2120 cbp->tx_fc_dis = 0; 2121 cbp->rx_fc_restop = 0; 2122 cbp->rx_fc_restart = 0; 2123 cbp->fc_filter = 0; 2124 cbp->pri_fc_loc = 1; 2125 } else { 2126 cbp->fc_delay_lsb = 0x1f; 2127 cbp->fc_delay_msb = 0x01; 2128 cbp->pri_fc_thresh = 3; 2129 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2130 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2131 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2132 cbp->fc_filter = !prm; /* drop FC frames to host */ 2133 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2134 } 2135 2136 /* 2137 * Start the config command/DMA. 2138 */ 2139 fxp_scb_wait(sc); 2140 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2141 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2142 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2143 /* ...and wait for it to complete. */ 2144 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2145 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2146 2147 /* 2148 * Now initialize the station address. Temporarily use the TxCB 2149 * memory area like we did above for the config CB. 2150 */ 2151 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2152 cb_ias->cb_status = 0; 2153 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2154 cb_ias->link_addr = 0xffffffff; 2155 bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, 2156 sizeof(sc->arpcom.ac_enaddr)); 2157 2158 /* 2159 * Start the IAS (Individual Address Setup) command/DMA. 2160 */ 2161 fxp_scb_wait(sc); 2162 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2163 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2164 /* ...and wait for it to complete. */ 2165 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2166 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2167 2168 /* 2169 * Initialize transmit control block (TxCB) list. 2170 */ 2171 txp = sc->fxp_desc.tx_list; 2172 tcbp = sc->fxp_desc.cbl_list; 2173 bzero(tcbp, FXP_TXCB_SZ); 2174 for (i = 0; i < FXP_NTXCB; i++) { 2175 txp[i].tx_cb = tcbp + i; 2176 txp[i].tx_mbuf = NULL; 2177 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2178 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2179 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2180 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2181 if (sc->flags & FXP_FLAG_EXT_TXCB) 2182 tcbp[i].tbd_array_addr = 2183 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2184 else 2185 tcbp[i].tbd_array_addr = 2186 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2187 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2188 } 2189 /* 2190 * Set the suspend flag on the first TxCB and start the control 2191 * unit. It will execute the NOP and then suspend. 2192 */ 2193 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2194 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2195 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2196 sc->tx_queued = 1; 2197 2198 fxp_scb_wait(sc); 2199 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2200 2201 /* 2202 * Initialize receiver buffer area - RFA. 2203 */ 2204 fxp_scb_wait(sc); 2205 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2206 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2207 2208 /* 2209 * Set current media. 2210 */ 2211 if (sc->miibus != NULL) 2212 mii_mediachg(device_get_softc(sc->miibus)); 2213 2214 ifp->if_flags |= IFF_RUNNING; 2215 ifp->if_flags &= ~IFF_OACTIVE; 2216 2217 /* 2218 * Enable interrupts. 2219 */ 2220 #ifdef DEVICE_POLLING 2221 /* 2222 * ... but only do that if we are not polling. And because (presumably) 2223 * the default is interrupts on, we need to disable them explicitly! 2224 */ 2225 if ( ifp->if_flags & IFF_POLLING ) 2226 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2227 else 2228 #endif /* DEVICE_POLLING */ 2229 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2230 2231 /* 2232 * Start stats updater. 2233 */ 2234 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2235 splx(s); 2236 } 2237 2238 static int 2239 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2240 { 2241 2242 return (0); 2243 } 2244 2245 static void 2246 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2247 { 2248 2249 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2250 } 2251 2252 /* 2253 * Change media according to request. 2254 */ 2255 static int 2256 fxp_ifmedia_upd(struct ifnet *ifp) 2257 { 2258 struct fxp_softc *sc = ifp->if_softc; 2259 struct mii_data *mii; 2260 2261 mii = device_get_softc(sc->miibus); 2262 mii_mediachg(mii); 2263 return (0); 2264 } 2265 2266 /* 2267 * Notify the world which media we're using. 2268 */ 2269 static void 2270 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2271 { 2272 struct fxp_softc *sc = ifp->if_softc; 2273 struct mii_data *mii; 2274 2275 mii = device_get_softc(sc->miibus); 2276 mii_pollstat(mii); 2277 ifmr->ifm_active = mii->mii_media_active; 2278 ifmr->ifm_status = mii->mii_media_status; 2279 2280 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2281 sc->cu_resume_bug = 1; 2282 else 2283 sc->cu_resume_bug = 0; 2284 } 2285 2286 /* 2287 * Add a buffer to the end of the RFA buffer list. 2288 * Return 0 if successful, 1 for failure. A failure results in 2289 * adding the 'oldm' (if non-NULL) on to the end of the list - 2290 * tossing out its old contents and recycling it. 2291 * The RFA struct is stuck at the beginning of mbuf cluster and the 2292 * data pointer is fixed up to point just past it. 2293 */ 2294 static int 2295 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2296 { 2297 struct mbuf *m; 2298 struct fxp_rfa *rfa, *p_rfa; 2299 struct fxp_rx *p_rx; 2300 bus_dmamap_t tmp_map; 2301 int error; 2302 2303 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2304 if (m == NULL) 2305 return (ENOBUFS); 2306 2307 /* 2308 * Move the data pointer up so that the incoming data packet 2309 * will be 32-bit aligned. 2310 */ 2311 m->m_data += RFA_ALIGNMENT_FUDGE; 2312 2313 /* 2314 * Get a pointer to the base of the mbuf cluster and move 2315 * data start past it. 2316 */ 2317 rfa = mtod(m, struct fxp_rfa *); 2318 m->m_data += sc->rfa_size; 2319 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2320 2321 rfa->rfa_status = 0; 2322 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2323 rfa->actual_size = 0; 2324 2325 /* 2326 * Initialize the rest of the RFA. Note that since the RFA 2327 * is misaligned, we cannot store values directly. We're thus 2328 * using the le32enc() function which handles endianness and 2329 * is also alignment-safe. 2330 */ 2331 le32enc(&rfa->link_addr, 0xffffffff); 2332 le32enc(&rfa->rbd_addr, 0xffffffff); 2333 2334 /* Map the RFA into DMA memory. */ 2335 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2336 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2337 &rxp->rx_addr, 0); 2338 if (error) { 2339 m_freem(m); 2340 return (error); 2341 } 2342 2343 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2344 tmp_map = sc->spare_map; 2345 sc->spare_map = rxp->rx_map; 2346 rxp->rx_map = tmp_map; 2347 rxp->rx_mbuf = m; 2348 2349 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2350 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2351 2352 /* 2353 * If there are other buffers already on the list, attach this 2354 * one to the end by fixing up the tail to point to this one. 2355 */ 2356 if (sc->fxp_desc.rx_head != NULL) { 2357 p_rx = sc->fxp_desc.rx_tail; 2358 p_rfa = (struct fxp_rfa *) 2359 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2360 p_rx->rx_next = rxp; 2361 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2362 p_rfa->rfa_control = 0; 2363 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2364 BUS_DMASYNC_PREWRITE); 2365 } else { 2366 rxp->rx_next = NULL; 2367 sc->fxp_desc.rx_head = rxp; 2368 } 2369 sc->fxp_desc.rx_tail = rxp; 2370 return (0); 2371 } 2372 2373 static volatile int 2374 fxp_miibus_readreg(device_t dev, int phy, int reg) 2375 { 2376 struct fxp_softc *sc = device_get_softc(dev); 2377 int count = 10000; 2378 int value; 2379 2380 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2381 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2382 2383 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2384 && count--) 2385 DELAY(10); 2386 2387 if (count <= 0) 2388 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2389 2390 return (value & 0xffff); 2391 } 2392 2393 static void 2394 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2395 { 2396 struct fxp_softc *sc = device_get_softc(dev); 2397 int count = 10000; 2398 2399 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2400 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2401 (value & 0xffff)); 2402 2403 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2404 count--) 2405 DELAY(10); 2406 2407 if (count <= 0) 2408 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2409 } 2410 2411 static int 2412 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2413 { 2414 struct fxp_softc *sc = ifp->if_softc; 2415 struct ifreq *ifr = (struct ifreq *)data; 2416 struct mii_data *mii; 2417 int s, error = 0; 2418 2419 /* 2420 * Detaching causes us to call ioctl with the mutex owned. Preclude 2421 * that by saying we're busy if the lock is already held. 2422 */ 2423 if (mtx_owned(&sc->sc_mtx)) 2424 return (EBUSY); 2425 2426 FXP_LOCK(sc); 2427 s = splimp(); 2428 2429 switch (command) { 2430 case SIOCSIFFLAGS: 2431 if (ifp->if_flags & IFF_ALLMULTI) 2432 sc->flags |= FXP_FLAG_ALL_MCAST; 2433 else 2434 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2435 2436 /* 2437 * If interface is marked up and not running, then start it. 2438 * If it is marked down and running, stop it. 2439 * XXX If it's up then re-initialize it. This is so flags 2440 * such as IFF_PROMISC are handled. 2441 */ 2442 if (ifp->if_flags & IFF_UP) { 2443 fxp_init_body(sc); 2444 } else { 2445 if (ifp->if_flags & IFF_RUNNING) 2446 fxp_stop(sc); 2447 } 2448 break; 2449 2450 case SIOCADDMULTI: 2451 case SIOCDELMULTI: 2452 if (ifp->if_flags & IFF_ALLMULTI) 2453 sc->flags |= FXP_FLAG_ALL_MCAST; 2454 else 2455 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2456 /* 2457 * Multicast list has changed; set the hardware filter 2458 * accordingly. 2459 */ 2460 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2461 fxp_mc_setup(sc); 2462 /* 2463 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2464 * again rather than else {}. 2465 */ 2466 if (sc->flags & FXP_FLAG_ALL_MCAST) 2467 fxp_init_body(sc); 2468 error = 0; 2469 break; 2470 2471 case SIOCSIFMEDIA: 2472 case SIOCGIFMEDIA: 2473 if (sc->miibus != NULL) { 2474 mii = device_get_softc(sc->miibus); 2475 error = ifmedia_ioctl(ifp, ifr, 2476 &mii->mii_media, command); 2477 } else { 2478 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2479 } 2480 break; 2481 2482 default: 2483 /* 2484 * ether_ioctl() will eventually call fxp_start() which 2485 * will result in mutex recursion so drop it first. 2486 */ 2487 FXP_UNLOCK(sc); 2488 error = ether_ioctl(ifp, command, data); 2489 } 2490 if (mtx_owned(&sc->sc_mtx)) 2491 FXP_UNLOCK(sc); 2492 splx(s); 2493 return (error); 2494 } 2495 2496 /* 2497 * Fill in the multicast address list and return number of entries. 2498 */ 2499 static int 2500 fxp_mc_addrs(struct fxp_softc *sc) 2501 { 2502 struct fxp_cb_mcs *mcsp = sc->mcsp; 2503 struct ifnet *ifp = &sc->sc_if; 2504 struct ifmultiaddr *ifma; 2505 int nmcasts; 2506 2507 nmcasts = 0; 2508 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2509 #if __FreeBSD_version < 500000 2510 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2511 #else 2512 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2513 #endif 2514 if (ifma->ifma_addr->sa_family != AF_LINK) 2515 continue; 2516 if (nmcasts >= MAXMCADDR) { 2517 sc->flags |= FXP_FLAG_ALL_MCAST; 2518 nmcasts = 0; 2519 break; 2520 } 2521 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2522 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2523 nmcasts++; 2524 } 2525 } 2526 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2527 return (nmcasts); 2528 } 2529 2530 /* 2531 * Program the multicast filter. 2532 * 2533 * We have an artificial restriction that the multicast setup command 2534 * must be the first command in the chain, so we take steps to ensure 2535 * this. By requiring this, it allows us to keep up the performance of 2536 * the pre-initialized command ring (esp. link pointers) by not actually 2537 * inserting the mcsetup command in the ring - i.e. its link pointer 2538 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2539 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2540 * lead into the regular TxCB ring when it completes. 2541 * 2542 * This function must be called at splimp. 2543 */ 2544 static void 2545 fxp_mc_setup(struct fxp_softc *sc) 2546 { 2547 struct fxp_cb_mcs *mcsp = sc->mcsp; 2548 struct ifnet *ifp = &sc->sc_if; 2549 struct fxp_tx *txp; 2550 int count; 2551 2552 /* 2553 * If there are queued commands, we must wait until they are all 2554 * completed. If we are already waiting, then add a NOP command 2555 * with interrupt option so that we're notified when all commands 2556 * have been completed - fxp_start() ensures that no additional 2557 * TX commands will be added when need_mcsetup is true. 2558 */ 2559 if (sc->tx_queued) { 2560 /* 2561 * need_mcsetup will be true if we are already waiting for the 2562 * NOP command to be completed (see below). In this case, bail. 2563 */ 2564 if (sc->need_mcsetup) 2565 return; 2566 sc->need_mcsetup = 1; 2567 2568 /* 2569 * Add a NOP command with interrupt so that we are notified 2570 * when all TX commands have been processed. 2571 */ 2572 txp = sc->fxp_desc.tx_last->tx_next; 2573 txp->tx_mbuf = NULL; 2574 txp->tx_cb->cb_status = 0; 2575 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2576 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2577 /* 2578 * Advance the end of list forward. 2579 */ 2580 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2581 htole16(~FXP_CB_COMMAND_S); 2582 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2583 sc->fxp_desc.tx_last = txp; 2584 sc->tx_queued++; 2585 /* 2586 * Issue a resume in case the CU has just suspended. 2587 */ 2588 fxp_scb_wait(sc); 2589 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2590 /* 2591 * Set a 5 second timer just in case we don't hear from the 2592 * card again. 2593 */ 2594 ifp->if_timer = 5; 2595 2596 return; 2597 } 2598 sc->need_mcsetup = 0; 2599 2600 /* 2601 * Initialize multicast setup descriptor. 2602 */ 2603 mcsp->cb_status = 0; 2604 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2605 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2606 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2607 txp = &sc->fxp_desc.mcs_tx; 2608 txp->tx_mbuf = NULL; 2609 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2610 txp->tx_next = sc->fxp_desc.tx_list; 2611 (void) fxp_mc_addrs(sc); 2612 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2613 sc->tx_queued = 1; 2614 2615 /* 2616 * Wait until command unit is not active. This should never 2617 * be the case when nothing is queued, but make sure anyway. 2618 */ 2619 count = 100; 2620 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2621 FXP_SCB_CUS_ACTIVE && --count) 2622 DELAY(10); 2623 if (count == 0) { 2624 device_printf(sc->dev, "command queue timeout\n"); 2625 return; 2626 } 2627 2628 /* 2629 * Start the multicast setup command. 2630 */ 2631 fxp_scb_wait(sc); 2632 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2633 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2634 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2635 2636 ifp->if_timer = 2; 2637 return; 2638 } 2639 2640 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2641 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2642 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2643 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2644 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2645 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2646 2647 #define UCODE(x) x, sizeof(x) 2648 2649 struct ucode { 2650 u_int32_t revision; 2651 u_int32_t *ucode; 2652 int length; 2653 u_short int_delay_offset; 2654 u_short bundle_max_offset; 2655 } ucode_table[] = { 2656 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2657 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2658 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2659 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2660 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2661 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2662 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2663 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2664 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2665 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2666 { 0, NULL, 0, 0, 0 } 2667 }; 2668 2669 static void 2670 fxp_load_ucode(struct fxp_softc *sc) 2671 { 2672 struct ucode *uc; 2673 struct fxp_cb_ucode *cbp; 2674 2675 for (uc = ucode_table; uc->ucode != NULL; uc++) 2676 if (sc->revision == uc->revision) 2677 break; 2678 if (uc->ucode == NULL) 2679 return; 2680 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2681 cbp->cb_status = 0; 2682 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2683 cbp->link_addr = 0xffffffff; /* (no) next command */ 2684 memcpy(cbp->ucode, uc->ucode, uc->length); 2685 if (uc->int_delay_offset) 2686 *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = 2687 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2688 if (uc->bundle_max_offset) 2689 *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = 2690 htole16(sc->tunable_bundle_max); 2691 /* 2692 * Download the ucode to the chip. 2693 */ 2694 fxp_scb_wait(sc); 2695 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2696 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2697 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2698 /* ...and wait for it to complete. */ 2699 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2700 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2701 device_printf(sc->dev, 2702 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2703 sc->tunable_int_delay, 2704 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2705 sc->flags |= FXP_FLAG_UCODE; 2706 } 2707 2708 static int 2709 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2710 { 2711 int error, value; 2712 2713 value = *(int *)arg1; 2714 error = sysctl_handle_int(oidp, &value, 0, req); 2715 if (error || !req->newptr) 2716 return (error); 2717 if (value < low || value > high) 2718 return (EINVAL); 2719 *(int *)arg1 = value; 2720 return (0); 2721 } 2722 2723 /* 2724 * Interrupt delay is expressed in microseconds, a multiplier is used 2725 * to convert this to the appropriate clock ticks before using. 2726 */ 2727 static int 2728 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2729 { 2730 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2731 } 2732 2733 static int 2734 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2735 { 2736 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2737 } 2738