xref: /freebsd/sys/dev/fxp/if_fxp.c (revision cc3f4b99653c34ae64f8a1fddea370abefef680e)
1 /*-
2  * Copyright (c) 1995, David Greenman
3  * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice unmodified, this list of conditions, and the following
11  *    disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 /*
34  * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35  */
36 
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
39 #endif
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
46 #include <sys/mbuf.h>
47 #include <sys/lock.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
50 #include <sys/rman.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 
55 #include <net/bpf.h>
56 #include <net/ethernet.h>
57 #include <net/if.h>
58 #include <net/if_var.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_types.h>
63 #include <net/if_vlan_var.h>
64 
65 #include <netinet/in.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/ip.h>
68 #include <netinet/tcp.h>
69 #include <netinet/udp.h>
70 
71 #include <machine/bus.h>
72 #include <machine/in_cksum.h>
73 #include <machine/resource.h>
74 
75 #include <dev/pci/pcivar.h>
76 #include <dev/pci/pcireg.h>		/* for PCIM_CMD_xxx */
77 
78 #include <dev/mii/mii.h>
79 #include <dev/mii/miivar.h>
80 
81 #include <dev/fxp/if_fxpreg.h>
82 #include <dev/fxp/if_fxpvar.h>
83 #include <dev/fxp/rcvbundl.h>
84 
85 MODULE_DEPEND(fxp, pci, 1, 1, 1);
86 MODULE_DEPEND(fxp, ether, 1, 1, 1);
87 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
88 #include "miibus_if.h"
89 
90 /*
91  * NOTE!  On !x86 we typically have an alignment constraint.  The
92  * card DMAs the packet immediately following the RFA.  However,
93  * the first thing in the packet is a 14-byte Ethernet header.
94  * This means that the packet is misaligned.  To compensate,
95  * we actually offset the RFA 2 bytes into the cluster.  This
96  * alignes the packet after the Ethernet header at a 32-bit
97  * boundary.  HOWEVER!  This means that the RFA is misaligned!
98  */
99 #define	RFA_ALIGNMENT_FUDGE	2
100 
101 /*
102  * Set initial transmit threshold at 64 (512 bytes). This is
103  * increased by 64 (512 bytes) at a time, to maximum of 192
104  * (1536 bytes), if an underrun occurs.
105  */
106 static int tx_threshold = 64;
107 
108 /*
109  * The configuration byte map has several undefined fields which
110  * must be one or must be zero.  Set up a template for these bits.
111  * The actual configuration is performed in fxp_init_body.
112  *
113  * See struct fxp_cb_config for the bit definitions.
114  */
115 static const u_char fxp_cb_config_template[] = {
116 	0x0, 0x0,		/* cb_status */
117 	0x0, 0x0,		/* cb_command */
118 	0x0, 0x0, 0x0, 0x0,	/* link_addr */
119 	0x0,	/*  0 */
120 	0x0,	/*  1 */
121 	0x0,	/*  2 */
122 	0x0,	/*  3 */
123 	0x0,	/*  4 */
124 	0x0,	/*  5 */
125 	0x32,	/*  6 */
126 	0x0,	/*  7 */
127 	0x0,	/*  8 */
128 	0x0,	/*  9 */
129 	0x6,	/* 10 */
130 	0x0,	/* 11 */
131 	0x0,	/* 12 */
132 	0x0,	/* 13 */
133 	0xf2,	/* 14 */
134 	0x48,	/* 15 */
135 	0x0,	/* 16 */
136 	0x40,	/* 17 */
137 	0xf0,	/* 18 */
138 	0x0,	/* 19 */
139 	0x3f,	/* 20 */
140 	0x5,	/* 21 */
141 	0x0,	/* 22 */
142 	0x0,	/* 23 */
143 	0x0,	/* 24 */
144 	0x0,	/* 25 */
145 	0x0,	/* 26 */
146 	0x0,	/* 27 */
147 	0x0,	/* 28 */
148 	0x0,	/* 29 */
149 	0x0,	/* 30 */
150 	0x0	/* 31 */
151 };
152 
153 /*
154  * Claim various Intel PCI device identifiers for this driver.  The
155  * sub-vendor and sub-device field are extensively used to identify
156  * particular variants, but we don't currently differentiate between
157  * them.
158  */
159 static const struct fxp_ident fxp_ident_table[] = {
160     { 0x1029,	-1,	0, "Intel 82559 PCI/CardBus Pro/100" },
161     { 0x1030,	-1,	0, "Intel 82559 Pro/100 Ethernet" },
162     { 0x1031,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
163     { 0x1032,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
164     { 0x1033,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
165     { 0x1034,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
166     { 0x1035,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
167     { 0x1036,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168     { 0x1037,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
169     { 0x1038,	-1,	3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
170     { 0x1039,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
171     { 0x103A,	-1,	4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
172     { 0x103B,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
173     { 0x103C,	-1,	4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
174     { 0x103D,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
175     { 0x103E,	-1,	4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
176     { 0x1050,	-1,	5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
177     { 0x1051,	-1,	5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
178     { 0x1059,	-1,	0, "Intel 82551QM Pro/100 M Mobile Connection" },
179     { 0x1064,	-1,	6, "Intel 82562EZ (ICH6)" },
180     { 0x1065,	-1,	6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
181     { 0x1068,	-1,	6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
182     { 0x1069,	-1,	6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
183     { 0x1091,	-1,	7, "Intel 82562GX Pro/100 Ethernet" },
184     { 0x1092,	-1,	7, "Intel Pro/100 VE Network Connection" },
185     { 0x1093,	-1,	7, "Intel Pro/100 VM Network Connection" },
186     { 0x1094,	-1,	7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
187     { 0x1209,	-1,	0, "Intel 82559ER Embedded 10/100 Ethernet" },
188     { 0x1229,	0x01,	0, "Intel 82557 Pro/100 Ethernet" },
189     { 0x1229,	0x02,	0, "Intel 82557 Pro/100 Ethernet" },
190     { 0x1229,	0x03,	0, "Intel 82557 Pro/100 Ethernet" },
191     { 0x1229,	0x04,	0, "Intel 82558 Pro/100 Ethernet" },
192     { 0x1229,	0x05,	0, "Intel 82558 Pro/100 Ethernet" },
193     { 0x1229,	0x06,	0, "Intel 82559 Pro/100 Ethernet" },
194     { 0x1229,	0x07,	0, "Intel 82559 Pro/100 Ethernet" },
195     { 0x1229,	0x08,	0, "Intel 82559 Pro/100 Ethernet" },
196     { 0x1229,	0x09,	0, "Intel 82559ER Pro/100 Ethernet" },
197     { 0x1229,	0x0c,	0, "Intel 82550 Pro/100 Ethernet" },
198     { 0x1229,	0x0d,	0, "Intel 82550C Pro/100 Ethernet" },
199     { 0x1229,	0x0e,	0, "Intel 82550 Pro/100 Ethernet" },
200     { 0x1229,	0x0f,	0, "Intel 82551 Pro/100 Ethernet" },
201     { 0x1229,	0x10,	0, "Intel 82551 Pro/100 Ethernet" },
202     { 0x1229,	-1,	0, "Intel 82557/8/9 Pro/100 Ethernet" },
203     { 0x2449,	-1,	2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
204     { 0x27dc,	-1,	7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
205     { 0,	-1,	0, NULL },
206 };
207 
208 #ifdef FXP_IP_CSUM_WAR
209 #define FXP_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
210 #else
211 #define FXP_CSUM_FEATURES    (CSUM_TCP | CSUM_UDP)
212 #endif
213 
214 static int		fxp_probe(device_t dev);
215 static int		fxp_attach(device_t dev);
216 static int		fxp_detach(device_t dev);
217 static int		fxp_shutdown(device_t dev);
218 static int		fxp_suspend(device_t dev);
219 static int		fxp_resume(device_t dev);
220 
221 static const struct fxp_ident *fxp_find_ident(device_t dev);
222 static void		fxp_intr(void *xsc);
223 static void		fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp,
224 			    struct mbuf *m, uint16_t status, int pos);
225 static int		fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
226 			    uint8_t statack, int count);
227 static void 		fxp_init(void *xsc);
228 static void 		fxp_init_body(struct fxp_softc *sc, int);
229 static void 		fxp_tick(void *xsc);
230 static void 		fxp_start(struct ifnet *ifp);
231 static void 		fxp_start_body(struct ifnet *ifp);
232 static int		fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
233 static void		fxp_txeof(struct fxp_softc *sc);
234 static void		fxp_stop(struct fxp_softc *sc);
235 static void 		fxp_release(struct fxp_softc *sc);
236 static int		fxp_ioctl(struct ifnet *ifp, u_long command,
237 			    caddr_t data);
238 static void 		fxp_watchdog(struct fxp_softc *sc);
239 static void		fxp_add_rfabuf(struct fxp_softc *sc,
240 			    struct fxp_rx *rxp);
241 static void		fxp_discard_rfabuf(struct fxp_softc *sc,
242 			    struct fxp_rx *rxp);
243 static int		fxp_new_rfabuf(struct fxp_softc *sc,
244 			    struct fxp_rx *rxp);
245 static int		fxp_mc_addrs(struct fxp_softc *sc);
246 static void		fxp_mc_setup(struct fxp_softc *sc);
247 static uint16_t		fxp_eeprom_getword(struct fxp_softc *sc, int offset,
248 			    int autosize);
249 static void 		fxp_eeprom_putword(struct fxp_softc *sc, int offset,
250 			    uint16_t data);
251 static void		fxp_autosize_eeprom(struct fxp_softc *sc);
252 static void		fxp_load_eeprom(struct fxp_softc *sc);
253 static void		fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
254 			    int offset, int words);
255 static void		fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
256 			    int offset, int words);
257 static int		fxp_ifmedia_upd(struct ifnet *ifp);
258 static void		fxp_ifmedia_sts(struct ifnet *ifp,
259 			    struct ifmediareq *ifmr);
260 static int		fxp_serial_ifmedia_upd(struct ifnet *ifp);
261 static void		fxp_serial_ifmedia_sts(struct ifnet *ifp,
262 			    struct ifmediareq *ifmr);
263 static int		fxp_miibus_readreg(device_t dev, int phy, int reg);
264 static int		fxp_miibus_writereg(device_t dev, int phy, int reg,
265 			    int value);
266 static void		fxp_miibus_statchg(device_t dev);
267 static void		fxp_load_ucode(struct fxp_softc *sc);
268 static void		fxp_update_stats(struct fxp_softc *sc);
269 static void		fxp_sysctl_node(struct fxp_softc *sc);
270 static int		sysctl_int_range(SYSCTL_HANDLER_ARGS,
271 			    int low, int high);
272 static int		sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
273 static int		sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
274 static void 		fxp_scb_wait(struct fxp_softc *sc);
275 static void		fxp_scb_cmd(struct fxp_softc *sc, int cmd);
276 static void		fxp_dma_wait(struct fxp_softc *sc,
277 			    volatile uint16_t *status, bus_dma_tag_t dmat,
278 			    bus_dmamap_t map);
279 
280 static device_method_t fxp_methods[] = {
281 	/* Device interface */
282 	DEVMETHOD(device_probe,		fxp_probe),
283 	DEVMETHOD(device_attach,	fxp_attach),
284 	DEVMETHOD(device_detach,	fxp_detach),
285 	DEVMETHOD(device_shutdown,	fxp_shutdown),
286 	DEVMETHOD(device_suspend,	fxp_suspend),
287 	DEVMETHOD(device_resume,	fxp_resume),
288 
289 	/* MII interface */
290 	DEVMETHOD(miibus_readreg,	fxp_miibus_readreg),
291 	DEVMETHOD(miibus_writereg,	fxp_miibus_writereg),
292 	DEVMETHOD(miibus_statchg,	fxp_miibus_statchg),
293 
294 	DEVMETHOD_END
295 };
296 
297 static driver_t fxp_driver = {
298 	"fxp",
299 	fxp_methods,
300 	sizeof(struct fxp_softc),
301 };
302 
303 static devclass_t fxp_devclass;
304 
305 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL,
306     SI_ORDER_ANY);
307 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
308 
309 static struct resource_spec fxp_res_spec_mem[] = {
310 	{ SYS_RES_MEMORY,	FXP_PCI_MMBA,	RF_ACTIVE },
311 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
312 	{ -1, 0 }
313 };
314 
315 static struct resource_spec fxp_res_spec_io[] = {
316 	{ SYS_RES_IOPORT,	FXP_PCI_IOBA,	RF_ACTIVE },
317 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
318 	{ -1, 0 }
319 };
320 
321 /*
322  * Wait for the previous command to be accepted (but not necessarily
323  * completed).
324  */
325 static void
326 fxp_scb_wait(struct fxp_softc *sc)
327 {
328 	union {
329 		uint16_t w;
330 		uint8_t b[2];
331 	} flowctl;
332 	int i = 10000;
333 
334 	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
335 		DELAY(2);
336 	if (i == 0) {
337 		flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
338 		flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
339 		device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
340 		    CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
341 		    CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
342 		    CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
343 	}
344 }
345 
346 static void
347 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
348 {
349 
350 	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
351 		CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
352 		fxp_scb_wait(sc);
353 	}
354 	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
355 }
356 
357 static void
358 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
359     bus_dma_tag_t dmat, bus_dmamap_t map)
360 {
361 	int i;
362 
363 	for (i = 10000; i > 0; i--) {
364 		DELAY(2);
365 		bus_dmamap_sync(dmat, map,
366 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
367 		if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
368 			break;
369 	}
370 	if (i == 0)
371 		device_printf(sc->dev, "DMA timeout\n");
372 }
373 
374 static const struct fxp_ident *
375 fxp_find_ident(device_t dev)
376 {
377 	uint16_t devid;
378 	uint8_t revid;
379 	const struct fxp_ident *ident;
380 
381 	if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
382 		devid = pci_get_device(dev);
383 		revid = pci_get_revid(dev);
384 		for (ident = fxp_ident_table; ident->name != NULL; ident++) {
385 			if (ident->devid == devid &&
386 			    (ident->revid == revid || ident->revid == -1)) {
387 				return (ident);
388 			}
389 		}
390 	}
391 	return (NULL);
392 }
393 
394 /*
395  * Return identification string if this device is ours.
396  */
397 static int
398 fxp_probe(device_t dev)
399 {
400 	const struct fxp_ident *ident;
401 
402 	ident = fxp_find_ident(dev);
403 	if (ident != NULL) {
404 		device_set_desc(dev, ident->name);
405 		return (BUS_PROBE_DEFAULT);
406 	}
407 	return (ENXIO);
408 }
409 
410 static void
411 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
412 {
413 	uint32_t *addr;
414 
415 	if (error)
416 		return;
417 
418 	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
419 	addr = arg;
420 	*addr = segs->ds_addr;
421 }
422 
423 static int
424 fxp_attach(device_t dev)
425 {
426 	struct fxp_softc *sc;
427 	struct fxp_cb_tx *tcbp;
428 	struct fxp_tx *txp;
429 	struct fxp_rx *rxp;
430 	struct ifnet *ifp;
431 	uint32_t val;
432 	uint16_t data;
433 	u_char eaddr[ETHER_ADDR_LEN];
434 	int error, flags, i, pmc, prefer_iomap;
435 
436 	error = 0;
437 	sc = device_get_softc(dev);
438 	sc->dev = dev;
439 	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
440 	    MTX_DEF);
441 	callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
442 	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
443 	    fxp_serial_ifmedia_sts);
444 
445 	ifp = sc->ifp = if_alloc(IFT_ETHER);
446 	if (ifp == NULL) {
447 		device_printf(dev, "can not if_alloc()\n");
448 		error = ENOSPC;
449 		goto fail;
450 	}
451 
452 	/*
453 	 * Enable bus mastering.
454 	 */
455 	pci_enable_busmaster(dev);
456 
457 	/*
458 	 * Figure out which we should try first - memory mapping or i/o mapping?
459 	 * We default to memory mapping. Then we accept an override from the
460 	 * command line. Then we check to see which one is enabled.
461 	 */
462 	prefer_iomap = 0;
463 	resource_int_value(device_get_name(dev), device_get_unit(dev),
464 	    "prefer_iomap", &prefer_iomap);
465 	if (prefer_iomap)
466 		sc->fxp_spec = fxp_res_spec_io;
467 	else
468 		sc->fxp_spec = fxp_res_spec_mem;
469 
470 	error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
471 	if (error) {
472 		if (sc->fxp_spec == fxp_res_spec_mem)
473 			sc->fxp_spec = fxp_res_spec_io;
474 		else
475 			sc->fxp_spec = fxp_res_spec_mem;
476 		error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
477 	}
478 	if (error) {
479 		device_printf(dev, "could not allocate resources\n");
480 		error = ENXIO;
481 		goto fail;
482 	}
483 
484 	if (bootverbose) {
485 		device_printf(dev, "using %s space register mapping\n",
486 		   sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
487 	}
488 
489 	/*
490 	 * Put CU/RU idle state and prepare full reset.
491 	 */
492 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
493 	DELAY(10);
494 	/* Full reset and disable interrupts. */
495 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
496 	DELAY(10);
497 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
498 
499 	/*
500 	 * Find out how large of an SEEPROM we have.
501 	 */
502 	fxp_autosize_eeprom(sc);
503 	fxp_load_eeprom(sc);
504 
505 	/*
506 	 * Find out the chip revision; lump all 82557 revs together.
507 	 */
508 	sc->ident = fxp_find_ident(dev);
509 	if (sc->ident->ich > 0) {
510 		/* Assume ICH controllers are 82559. */
511 		sc->revision = FXP_REV_82559_A0;
512 	} else {
513 		data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
514 		if ((data >> 8) == 1)
515 			sc->revision = FXP_REV_82557;
516 		else
517 			sc->revision = pci_get_revid(dev);
518 	}
519 
520 	/*
521 	 * Check availability of WOL. 82559ER does not support WOL.
522 	 */
523 	if (sc->revision >= FXP_REV_82558_A4 &&
524 	    sc->revision != FXP_REV_82559S_A) {
525 		data = sc->eeprom[FXP_EEPROM_MAP_ID];
526 		if ((data & 0x20) != 0 &&
527 		    pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
528 			sc->flags |= FXP_FLAG_WOLCAP;
529 	}
530 
531 	if (sc->revision == FXP_REV_82550_C) {
532 		/*
533 		 * 82550C with server extension requires microcode to
534 		 * receive fragmented UDP datagrams.  However if the
535 		 * microcode is used for client-only featured 82550C
536 		 * it locks up controller.
537 		 */
538 		data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
539 		if ((data & 0x0400) == 0)
540 			sc->flags |= FXP_FLAG_NO_UCODE;
541 	}
542 
543 	/* Receiver lock-up workaround detection. */
544 	if (sc->revision < FXP_REV_82558_A4) {
545 		data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
546 		if ((data & 0x03) != 0x03) {
547 			sc->flags |= FXP_FLAG_RXBUG;
548 			device_printf(dev, "Enabling Rx lock-up workaround\n");
549 		}
550 	}
551 
552 	/*
553 	 * Determine whether we must use the 503 serial interface.
554 	 */
555 	data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
556 	if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
557 	    && (data & FXP_PHY_SERIAL_ONLY))
558 		sc->flags |= FXP_FLAG_SERIAL_MEDIA;
559 
560 	fxp_sysctl_node(sc);
561 	/*
562 	 * Enable workarounds for certain chip revision deficiencies.
563 	 *
564 	 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
565 	 * some systems based a normal 82559 design, have a defect where
566 	 * the chip can cause a PCI protocol violation if it receives
567 	 * a CU_RESUME command when it is entering the IDLE state.  The
568 	 * workaround is to disable Dynamic Standby Mode, so the chip never
569 	 * deasserts CLKRUN#, and always remains in an active state.
570 	 *
571 	 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
572 	 */
573 	if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
574 	    (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
575 		data = sc->eeprom[FXP_EEPROM_MAP_ID];
576 		if (data & 0x02) {			/* STB enable */
577 			uint16_t cksum;
578 			int i;
579 
580 			device_printf(dev,
581 			    "Disabling dynamic standby mode in EEPROM\n");
582 			data &= ~0x02;
583 			sc->eeprom[FXP_EEPROM_MAP_ID] = data;
584 			fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
585 			device_printf(dev, "New EEPROM ID: 0x%x\n", data);
586 			cksum = 0;
587 			for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
588 				cksum += sc->eeprom[i];
589 			i = (1 << sc->eeprom_size) - 1;
590 			cksum = 0xBABA - cksum;
591 			fxp_write_eeprom(sc, &cksum, i, 1);
592 			device_printf(dev,
593 			    "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
594 			    i, sc->eeprom[i], cksum);
595 			sc->eeprom[i] = cksum;
596 			/*
597 			 * If the user elects to continue, try the software
598 			 * workaround, as it is better than nothing.
599 			 */
600 			sc->flags |= FXP_FLAG_CU_RESUME_BUG;
601 		}
602 	}
603 
604 	/*
605 	 * If we are not a 82557 chip, we can enable extended features.
606 	 */
607 	if (sc->revision != FXP_REV_82557) {
608 		/*
609 		 * If MWI is enabled in the PCI configuration, and there
610 		 * is a valid cacheline size (8 or 16 dwords), then tell
611 		 * the board to turn on MWI.
612 		 */
613 		val = pci_read_config(dev, PCIR_COMMAND, 2);
614 		if (val & PCIM_CMD_MWRICEN &&
615 		    pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
616 			sc->flags |= FXP_FLAG_MWI_ENABLE;
617 
618 		/* turn on the extended TxCB feature */
619 		sc->flags |= FXP_FLAG_EXT_TXCB;
620 
621 		/* enable reception of long frames for VLAN */
622 		sc->flags |= FXP_FLAG_LONG_PKT_EN;
623 	} else {
624 		/* a hack to get long VLAN frames on a 82557 */
625 		sc->flags |= FXP_FLAG_SAVE_BAD;
626 	}
627 
628 	/* For 82559 or later chips, Rx checksum offload is supported. */
629 	if (sc->revision >= FXP_REV_82559_A0) {
630 		/* 82559ER does not support Rx checksum offloading. */
631 		if (sc->ident->devid != 0x1209)
632 			sc->flags |= FXP_FLAG_82559_RXCSUM;
633 	}
634 	/*
635 	 * Enable use of extended RFDs and TCBs for 82550
636 	 * and later chips. Note: we need extended TXCB support
637 	 * too, but that's already enabled by the code above.
638 	 * Be careful to do this only on the right devices.
639 	 */
640 	if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
641 	    sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
642 	    || sc->revision == FXP_REV_82551_10) {
643 		sc->rfa_size = sizeof (struct fxp_rfa);
644 		sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
645 		sc->flags |= FXP_FLAG_EXT_RFA;
646 		/* Use extended RFA instead of 82559 checksum mode. */
647 		sc->flags &= ~FXP_FLAG_82559_RXCSUM;
648 	} else {
649 		sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
650 		sc->tx_cmd = FXP_CB_COMMAND_XMIT;
651 	}
652 
653 	/*
654 	 * Allocate DMA tags and DMA safe memory.
655 	 */
656 	sc->maxtxseg = FXP_NTXSEG;
657 	sc->maxsegsize = MCLBYTES;
658 	if (sc->flags & FXP_FLAG_EXT_RFA) {
659 		sc->maxtxseg--;
660 		sc->maxsegsize = FXP_TSO_SEGSIZE;
661 	}
662 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
663 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
664 	    sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
665 	    sc->maxtxseg, sc->maxsegsize, 0,
666 	    busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
667 	if (error) {
668 		device_printf(dev, "could not create TX DMA tag\n");
669 		goto fail;
670 	}
671 
672 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
673 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
674 	    MCLBYTES, 1, MCLBYTES, 0,
675 	    busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
676 	if (error) {
677 		device_printf(dev, "could not create RX DMA tag\n");
678 		goto fail;
679 	}
680 
681 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
682 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
683 	    sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
684 	    busdma_lock_mutex, &Giant, &sc->fxp_stag);
685 	if (error) {
686 		device_printf(dev, "could not create stats DMA tag\n");
687 		goto fail;
688 	}
689 
690 	error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
691 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
692 	if (error) {
693 		device_printf(dev, "could not allocate stats DMA memory\n");
694 		goto fail;
695 	}
696 	error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
697 	    sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
698 	    BUS_DMA_NOWAIT);
699 	if (error) {
700 		device_printf(dev, "could not load the stats DMA buffer\n");
701 		goto fail;
702 	}
703 
704 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
705 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
706 	    FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
707 	    busdma_lock_mutex, &Giant, &sc->cbl_tag);
708 	if (error) {
709 		device_printf(dev, "could not create TxCB DMA tag\n");
710 		goto fail;
711 	}
712 
713 	error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
714 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
715 	if (error) {
716 		device_printf(dev, "could not allocate TxCB DMA memory\n");
717 		goto fail;
718 	}
719 
720 	error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
721 	    sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
722 	    &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
723 	if (error) {
724 		device_printf(dev, "could not load TxCB DMA buffer\n");
725 		goto fail;
726 	}
727 
728 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
729 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
730 	    sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
731 	    busdma_lock_mutex, &Giant, &sc->mcs_tag);
732 	if (error) {
733 		device_printf(dev,
734 		    "could not create multicast setup DMA tag\n");
735 		goto fail;
736 	}
737 
738 	error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
739 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
740 	if (error) {
741 		device_printf(dev,
742 		    "could not allocate multicast setup DMA memory\n");
743 		goto fail;
744 	}
745 	error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
746 	    sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
747 	    BUS_DMA_NOWAIT);
748 	if (error) {
749 		device_printf(dev,
750 		    "can't load the multicast setup DMA buffer\n");
751 		goto fail;
752 	}
753 
754 	/*
755 	 * Pre-allocate the TX DMA maps and setup the pointers to
756 	 * the TX command blocks.
757 	 */
758 	txp = sc->fxp_desc.tx_list;
759 	tcbp = sc->fxp_desc.cbl_list;
760 	for (i = 0; i < FXP_NTXCB; i++) {
761 		txp[i].tx_cb = tcbp + i;
762 		error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
763 		if (error) {
764 			device_printf(dev, "can't create DMA map for TX\n");
765 			goto fail;
766 		}
767 	}
768 	error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
769 	if (error) {
770 		device_printf(dev, "can't create spare DMA map\n");
771 		goto fail;
772 	}
773 
774 	/*
775 	 * Pre-allocate our receive buffers.
776 	 */
777 	sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
778 	for (i = 0; i < FXP_NRFABUFS; i++) {
779 		rxp = &sc->fxp_desc.rx_list[i];
780 		error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
781 		if (error) {
782 			device_printf(dev, "can't create DMA map for RX\n");
783 			goto fail;
784 		}
785 		if (fxp_new_rfabuf(sc, rxp) != 0) {
786 			error = ENOMEM;
787 			goto fail;
788 		}
789 		fxp_add_rfabuf(sc, rxp);
790 	}
791 
792 	/*
793 	 * Read MAC address.
794 	 */
795 	eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
796 	eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
797 	eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
798 	eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
799 	eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
800 	eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
801 	if (bootverbose) {
802 		device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
803 		    pci_get_vendor(dev), pci_get_device(dev),
804 		    pci_get_subvendor(dev), pci_get_subdevice(dev),
805 		    pci_get_revid(dev));
806 		device_printf(dev, "Dynamic Standby mode is %s\n",
807 		    sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
808 		    "disabled");
809 	}
810 
811 	/*
812 	 * If this is only a 10Mbps device, then there is no MII, and
813 	 * the PHY will use a serial interface instead.
814 	 *
815 	 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
816 	 * doesn't have a programming interface of any sort.  The
817 	 * media is sensed automatically based on how the link partner
818 	 * is configured.  This is, in essence, manual configuration.
819 	 */
820 	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
821 		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
822 		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
823 	} else {
824 		/*
825 		 * i82557 wedge when isolating all of their PHYs.
826 		 */
827 		flags = MIIF_NOISOLATE;
828 		if (sc->revision >= FXP_REV_82558_A4)
829 			flags |= MIIF_DOPAUSE;
830 		error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd,
831 		    fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
832 		    MII_OFFSET_ANY, flags);
833 		if (error != 0) {
834 			device_printf(dev, "attaching PHYs failed\n");
835 			goto fail;
836 		}
837 	}
838 
839 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
840 	ifp->if_init = fxp_init;
841 	ifp->if_softc = sc;
842 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
843 	ifp->if_ioctl = fxp_ioctl;
844 	ifp->if_start = fxp_start;
845 
846 	ifp->if_capabilities = ifp->if_capenable = 0;
847 
848 	/* Enable checksum offload/TSO for 82550 or better chips */
849 	if (sc->flags & FXP_FLAG_EXT_RFA) {
850 		ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO;
851 		ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
852 		ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4;
853 	}
854 
855 	if (sc->flags & FXP_FLAG_82559_RXCSUM) {
856 		ifp->if_capabilities |= IFCAP_RXCSUM;
857 		ifp->if_capenable |= IFCAP_RXCSUM;
858 	}
859 
860 	if (sc->flags & FXP_FLAG_WOLCAP) {
861 		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
862 		ifp->if_capenable |= IFCAP_WOL_MAGIC;
863 	}
864 
865 #ifdef DEVICE_POLLING
866 	/* Inform the world we support polling. */
867 	ifp->if_capabilities |= IFCAP_POLLING;
868 #endif
869 
870 	/*
871 	 * Attach the interface.
872 	 */
873 	ether_ifattach(ifp, eaddr);
874 
875 	/*
876 	 * Tell the upper layer(s) we support long frames.
877 	 * Must appear after the call to ether_ifattach() because
878 	 * ether_ifattach() sets ifi_hdrlen to the default value.
879 	 */
880 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
881 	ifp->if_capabilities |= IFCAP_VLAN_MTU;
882 	ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
883 	if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
884 		ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING |
885 		    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
886 		ifp->if_capenable |= IFCAP_VLAN_HWTAGGING |
887 		    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
888 	}
889 
890 	/*
891 	 * Let the system queue as many packets as we have available
892 	 * TX descriptors.
893 	 */
894 	IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
895 	ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
896 	IFQ_SET_READY(&ifp->if_snd);
897 
898 	/*
899 	 * Hook our interrupt after all initialization is complete.
900 	 */
901 	error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
902 			       NULL, fxp_intr, sc, &sc->ih);
903 	if (error) {
904 		device_printf(dev, "could not setup irq\n");
905 		ether_ifdetach(sc->ifp);
906 		goto fail;
907 	}
908 
909 	/*
910 	 * Configure hardware to reject magic frames otherwise
911 	 * system will hang on recipt of magic frames.
912 	 */
913 	if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
914 		FXP_LOCK(sc);
915 		/* Clear wakeup events. */
916 		CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
917 		fxp_init_body(sc, 0);
918 		fxp_stop(sc);
919 		FXP_UNLOCK(sc);
920 	}
921 
922 fail:
923 	if (error)
924 		fxp_release(sc);
925 	return (error);
926 }
927 
928 /*
929  * Release all resources.  The softc lock should not be held and the
930  * interrupt should already be torn down.
931  */
932 static void
933 fxp_release(struct fxp_softc *sc)
934 {
935 	struct fxp_rx *rxp;
936 	struct fxp_tx *txp;
937 	int i;
938 
939 	FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
940 	KASSERT(sc->ih == NULL,
941 	    ("fxp_release() called with intr handle still active"));
942 	if (sc->miibus)
943 		device_delete_child(sc->dev, sc->miibus);
944 	bus_generic_detach(sc->dev);
945 	ifmedia_removeall(&sc->sc_media);
946 	if (sc->fxp_desc.cbl_list) {
947 		bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
948 		bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
949 		    sc->cbl_map);
950 	}
951 	if (sc->fxp_stats) {
952 		bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
953 		bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
954 	}
955 	if (sc->mcsp) {
956 		bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
957 		bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
958 	}
959 	bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
960 	if (sc->fxp_rxmtag) {
961 		for (i = 0; i < FXP_NRFABUFS; i++) {
962 			rxp = &sc->fxp_desc.rx_list[i];
963 			if (rxp->rx_mbuf != NULL) {
964 				bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
965 				    BUS_DMASYNC_POSTREAD);
966 				bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
967 				m_freem(rxp->rx_mbuf);
968 			}
969 			bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
970 		}
971 		bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
972 		bus_dma_tag_destroy(sc->fxp_rxmtag);
973 	}
974 	if (sc->fxp_txmtag) {
975 		for (i = 0; i < FXP_NTXCB; i++) {
976 			txp = &sc->fxp_desc.tx_list[i];
977 			if (txp->tx_mbuf != NULL) {
978 				bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
979 				    BUS_DMASYNC_POSTWRITE);
980 				bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
981 				m_freem(txp->tx_mbuf);
982 			}
983 			bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
984 		}
985 		bus_dma_tag_destroy(sc->fxp_txmtag);
986 	}
987 	if (sc->fxp_stag)
988 		bus_dma_tag_destroy(sc->fxp_stag);
989 	if (sc->cbl_tag)
990 		bus_dma_tag_destroy(sc->cbl_tag);
991 	if (sc->mcs_tag)
992 		bus_dma_tag_destroy(sc->mcs_tag);
993 	if (sc->ifp)
994 		if_free(sc->ifp);
995 
996 	mtx_destroy(&sc->sc_mtx);
997 }
998 
999 /*
1000  * Detach interface.
1001  */
1002 static int
1003 fxp_detach(device_t dev)
1004 {
1005 	struct fxp_softc *sc = device_get_softc(dev);
1006 
1007 #ifdef DEVICE_POLLING
1008 	if (sc->ifp->if_capenable & IFCAP_POLLING)
1009 		ether_poll_deregister(sc->ifp);
1010 #endif
1011 
1012 	FXP_LOCK(sc);
1013 	/*
1014 	 * Stop DMA and drop transmit queue, but disable interrupts first.
1015 	 */
1016 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1017 	fxp_stop(sc);
1018 	FXP_UNLOCK(sc);
1019 	callout_drain(&sc->stat_ch);
1020 
1021 	/*
1022 	 * Close down routes etc.
1023 	 */
1024 	ether_ifdetach(sc->ifp);
1025 
1026 	/*
1027 	 * Unhook interrupt before dropping lock. This is to prevent
1028 	 * races with fxp_intr().
1029 	 */
1030 	bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1031 	sc->ih = NULL;
1032 
1033 	/* Release our allocated resources. */
1034 	fxp_release(sc);
1035 	return (0);
1036 }
1037 
1038 /*
1039  * Device shutdown routine. Called at system shutdown after sync. The
1040  * main purpose of this routine is to shut off receiver DMA so that
1041  * kernel memory doesn't get clobbered during warmboot.
1042  */
1043 static int
1044 fxp_shutdown(device_t dev)
1045 {
1046 
1047 	/*
1048 	 * Make sure that DMA is disabled prior to reboot. Not doing
1049 	 * do could allow DMA to corrupt kernel memory during the
1050 	 * reboot before the driver initializes.
1051 	 */
1052 	return (fxp_suspend(dev));
1053 }
1054 
1055 /*
1056  * Device suspend routine.  Stop the interface and save some PCI
1057  * settings in case the BIOS doesn't restore them properly on
1058  * resume.
1059  */
1060 static int
1061 fxp_suspend(device_t dev)
1062 {
1063 	struct fxp_softc *sc = device_get_softc(dev);
1064 	struct ifnet *ifp;
1065 	int pmc;
1066 	uint16_t pmstat;
1067 
1068 	FXP_LOCK(sc);
1069 
1070 	ifp = sc->ifp;
1071 	if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1072 		pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1073 		pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1074 		if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1075 			/* Request PME. */
1076 			pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1077 			sc->flags |= FXP_FLAG_WOL;
1078 			/* Reconfigure hardware to accept magic frames. */
1079 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1080 			fxp_init_body(sc, 0);
1081 		}
1082 		pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1083 	}
1084 	fxp_stop(sc);
1085 
1086 	sc->suspended = 1;
1087 
1088 	FXP_UNLOCK(sc);
1089 	return (0);
1090 }
1091 
1092 /*
1093  * Device resume routine. re-enable busmastering, and restart the interface if
1094  * appropriate.
1095  */
1096 static int
1097 fxp_resume(device_t dev)
1098 {
1099 	struct fxp_softc *sc = device_get_softc(dev);
1100 	struct ifnet *ifp = sc->ifp;
1101 	int pmc;
1102 	uint16_t pmstat;
1103 
1104 	FXP_LOCK(sc);
1105 
1106 	if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1107 		sc->flags &= ~FXP_FLAG_WOL;
1108 		pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1109 		/* Disable PME and clear PME status. */
1110 		pmstat &= ~PCIM_PSTAT_PMEENABLE;
1111 		pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1112 		if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1113 			CSR_WRITE_1(sc, FXP_CSR_PMDR,
1114 			    CSR_READ_1(sc, FXP_CSR_PMDR));
1115 	}
1116 
1117 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1118 	DELAY(10);
1119 
1120 	/* reinitialize interface if necessary */
1121 	if (ifp->if_flags & IFF_UP)
1122 		fxp_init_body(sc, 1);
1123 
1124 	sc->suspended = 0;
1125 
1126 	FXP_UNLOCK(sc);
1127 	return (0);
1128 }
1129 
1130 static void
1131 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1132 {
1133 	uint16_t reg;
1134 	int x;
1135 
1136 	/*
1137 	 * Shift in data.
1138 	 */
1139 	for (x = 1 << (length - 1); x; x >>= 1) {
1140 		if (data & x)
1141 			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1142 		else
1143 			reg = FXP_EEPROM_EECS;
1144 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1145 		DELAY(1);
1146 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1147 		DELAY(1);
1148 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1149 		DELAY(1);
1150 	}
1151 }
1152 
1153 /*
1154  * Read from the serial EEPROM. Basically, you manually shift in
1155  * the read opcode (one bit at a time) and then shift in the address,
1156  * and then you shift out the data (all of this one bit at a time).
1157  * The word size is 16 bits, so you have to provide the address for
1158  * every 16 bits of data.
1159  */
1160 static uint16_t
1161 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1162 {
1163 	uint16_t reg, data;
1164 	int x;
1165 
1166 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1167 	/*
1168 	 * Shift in read opcode.
1169 	 */
1170 	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1171 	/*
1172 	 * Shift in address.
1173 	 */
1174 	data = 0;
1175 	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1176 		if (offset & x)
1177 			reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1178 		else
1179 			reg = FXP_EEPROM_EECS;
1180 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1181 		DELAY(1);
1182 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1183 		DELAY(1);
1184 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1185 		DELAY(1);
1186 		reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1187 		data++;
1188 		if (autosize && reg == 0) {
1189 			sc->eeprom_size = data;
1190 			break;
1191 		}
1192 	}
1193 	/*
1194 	 * Shift out data.
1195 	 */
1196 	data = 0;
1197 	reg = FXP_EEPROM_EECS;
1198 	for (x = 1 << 15; x; x >>= 1) {
1199 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1200 		DELAY(1);
1201 		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1202 			data |= x;
1203 		CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1204 		DELAY(1);
1205 	}
1206 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1207 	DELAY(1);
1208 
1209 	return (data);
1210 }
1211 
1212 static void
1213 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1214 {
1215 	int i;
1216 
1217 	/*
1218 	 * Erase/write enable.
1219 	 */
1220 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1221 	fxp_eeprom_shiftin(sc, 0x4, 3);
1222 	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1223 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1224 	DELAY(1);
1225 	/*
1226 	 * Shift in write opcode, address, data.
1227 	 */
1228 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1229 	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1230 	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1231 	fxp_eeprom_shiftin(sc, data, 16);
1232 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1233 	DELAY(1);
1234 	/*
1235 	 * Wait for EEPROM to finish up.
1236 	 */
1237 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1238 	DELAY(1);
1239 	for (i = 0; i < 1000; i++) {
1240 		if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1241 			break;
1242 		DELAY(50);
1243 	}
1244 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1245 	DELAY(1);
1246 	/*
1247 	 * Erase/write disable.
1248 	 */
1249 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1250 	fxp_eeprom_shiftin(sc, 0x4, 3);
1251 	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1252 	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1253 	DELAY(1);
1254 }
1255 
1256 /*
1257  * From NetBSD:
1258  *
1259  * Figure out EEPROM size.
1260  *
1261  * 559's can have either 64-word or 256-word EEPROMs, the 558
1262  * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1263  * talks about the existance of 16 to 256 word EEPROMs.
1264  *
1265  * The only known sizes are 64 and 256, where the 256 version is used
1266  * by CardBus cards to store CIS information.
1267  *
1268  * The address is shifted in msb-to-lsb, and after the last
1269  * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1270  * after which follows the actual data. We try to detect this zero, by
1271  * probing the data-out bit in the EEPROM control register just after
1272  * having shifted in a bit. If the bit is zero, we assume we've
1273  * shifted enough address bits. The data-out should be tri-state,
1274  * before this, which should translate to a logical one.
1275  */
1276 static void
1277 fxp_autosize_eeprom(struct fxp_softc *sc)
1278 {
1279 
1280 	/* guess maximum size of 256 words */
1281 	sc->eeprom_size = 8;
1282 
1283 	/* autosize */
1284 	(void) fxp_eeprom_getword(sc, 0, 1);
1285 }
1286 
1287 static void
1288 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1289 {
1290 	int i;
1291 
1292 	for (i = 0; i < words; i++)
1293 		data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1294 }
1295 
1296 static void
1297 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1298 {
1299 	int i;
1300 
1301 	for (i = 0; i < words; i++)
1302 		fxp_eeprom_putword(sc, offset + i, data[i]);
1303 }
1304 
1305 static void
1306 fxp_load_eeprom(struct fxp_softc *sc)
1307 {
1308 	int i;
1309 	uint16_t cksum;
1310 
1311 	fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1312 	cksum = 0;
1313 	for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1314 		cksum += sc->eeprom[i];
1315 	cksum = 0xBABA - cksum;
1316 	if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1317 		device_printf(sc->dev,
1318 		    "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1319 		    cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1320 }
1321 
1322 /*
1323  * Grab the softc lock and call the real fxp_start_body() routine
1324  */
1325 static void
1326 fxp_start(struct ifnet *ifp)
1327 {
1328 	struct fxp_softc *sc = ifp->if_softc;
1329 
1330 	FXP_LOCK(sc);
1331 	fxp_start_body(ifp);
1332 	FXP_UNLOCK(sc);
1333 }
1334 
1335 /*
1336  * Start packet transmission on the interface.
1337  * This routine must be called with the softc lock held, and is an
1338  * internal entry point only.
1339  */
1340 static void
1341 fxp_start_body(struct ifnet *ifp)
1342 {
1343 	struct fxp_softc *sc = ifp->if_softc;
1344 	struct mbuf *mb_head;
1345 	int txqueued;
1346 
1347 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1348 
1349 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1350 	    IFF_DRV_RUNNING)
1351 		return;
1352 
1353 	if (sc->tx_queued > FXP_NTXCB_HIWAT)
1354 		fxp_txeof(sc);
1355 	/*
1356 	 * We're finished if there is nothing more to add to the list or if
1357 	 * we're all filled up with buffers to transmit.
1358 	 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1359 	 *       a NOP command when needed.
1360 	 */
1361 	txqueued = 0;
1362 	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1363 	    sc->tx_queued < FXP_NTXCB - 1) {
1364 
1365 		/*
1366 		 * Grab a packet to transmit.
1367 		 */
1368 		IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1369 		if (mb_head == NULL)
1370 			break;
1371 
1372 		if (fxp_encap(sc, &mb_head)) {
1373 			if (mb_head == NULL)
1374 				break;
1375 			IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1376 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1377 		}
1378 		txqueued++;
1379 		/*
1380 		 * Pass packet to bpf if there is a listener.
1381 		 */
1382 		BPF_MTAP(ifp, mb_head);
1383 	}
1384 
1385 	/*
1386 	 * We're finished. If we added to the list, issue a RESUME to get DMA
1387 	 * going again if suspended.
1388 	 */
1389 	if (txqueued > 0) {
1390 		bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1391 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1392 		fxp_scb_wait(sc);
1393 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1394 		/*
1395 		 * Set a 5 second timer just in case we don't hear
1396 		 * from the card again.
1397 		 */
1398 		sc->watchdog_timer = 5;
1399 	}
1400 }
1401 
1402 static int
1403 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1404 {
1405 	struct ifnet *ifp;
1406 	struct mbuf *m;
1407 	struct fxp_tx *txp;
1408 	struct fxp_cb_tx *cbp;
1409 	struct tcphdr *tcp;
1410 	bus_dma_segment_t segs[FXP_NTXSEG];
1411 	int error, i, nseg, tcp_payload;
1412 
1413 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1414 	ifp = sc->ifp;
1415 
1416 	tcp_payload = 0;
1417 	tcp = NULL;
1418 	/*
1419 	 * Get pointer to next available tx desc.
1420 	 */
1421 	txp = sc->fxp_desc.tx_last->tx_next;
1422 
1423 	/*
1424 	 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1425 	 * Ethernet Controller Family Open Source Software
1426 	 * Developer Manual says:
1427 	 *   Using software parsing is only allowed with legal
1428 	 *   TCP/IP or UDP/IP packets.
1429 	 *   ...
1430 	 *   For all other datagrams, hardware parsing must
1431 	 *   be used.
1432 	 * Software parsing appears to truncate ICMP and
1433 	 * fragmented UDP packets that contain one to three
1434 	 * bytes in the second (and final) mbuf of the packet.
1435 	 */
1436 	if (sc->flags & FXP_FLAG_EXT_RFA)
1437 		txp->tx_cb->ipcb_ip_activation_high =
1438 		    FXP_IPCB_HARDWAREPARSING_ENABLE;
1439 
1440 	m = *m_head;
1441 	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1442 		/*
1443 		 * 82550/82551 requires ethernet/IP/TCP headers must be
1444 		 * contained in the first active transmit buffer.
1445 		 */
1446 		struct ether_header *eh;
1447 		struct ip *ip;
1448 		uint32_t ip_off, poff;
1449 
1450 		if (M_WRITABLE(*m_head) == 0) {
1451 			/* Get a writable copy. */
1452 			m = m_dup(*m_head, M_NOWAIT);
1453 			m_freem(*m_head);
1454 			if (m == NULL) {
1455 				*m_head = NULL;
1456 				return (ENOBUFS);
1457 			}
1458 			*m_head = m;
1459 		}
1460 		ip_off = sizeof(struct ether_header);
1461 		m = m_pullup(*m_head, ip_off);
1462 		if (m == NULL) {
1463 			*m_head = NULL;
1464 			return (ENOBUFS);
1465 		}
1466 		eh = mtod(m, struct ether_header *);
1467 		/* Check the existence of VLAN tag. */
1468 		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1469 			ip_off = sizeof(struct ether_vlan_header);
1470 			m = m_pullup(m, ip_off);
1471 			if (m == NULL) {
1472 				*m_head = NULL;
1473 				return (ENOBUFS);
1474 			}
1475 		}
1476 		m = m_pullup(m, ip_off + sizeof(struct ip));
1477 		if (m == NULL) {
1478 			*m_head = NULL;
1479 			return (ENOBUFS);
1480 		}
1481 		ip = (struct ip *)(mtod(m, char *) + ip_off);
1482 		poff = ip_off + (ip->ip_hl << 2);
1483 		m = m_pullup(m, poff + sizeof(struct tcphdr));
1484 		if (m == NULL) {
1485 			*m_head = NULL;
1486 			return (ENOBUFS);
1487 		}
1488 		tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1489 		m = m_pullup(m, poff + (tcp->th_off << 2));
1490 		if (m == NULL) {
1491 			*m_head = NULL;
1492 			return (ENOBUFS);
1493 		}
1494 
1495 		/*
1496 		 * Since 82550/82551 doesn't modify IP length and pseudo
1497 		 * checksum in the first frame driver should compute it.
1498 		 */
1499 		ip = (struct ip *)(mtod(m, char *) + ip_off);
1500 		tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1501 		ip->ip_sum = 0;
1502 		ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1503 		    (tcp->th_off << 2));
1504 		tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1505 		    htons(IPPROTO_TCP + (tcp->th_off << 2) +
1506 		    m->m_pkthdr.tso_segsz));
1507 		/* Compute total TCP payload. */
1508 		tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1509 		tcp_payload -= tcp->th_off << 2;
1510 		*m_head = m;
1511 	} else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1512 		/*
1513 		 * Deal with TCP/IP checksum offload. Note that
1514 		 * in order for TCP checksum offload to work,
1515 		 * the pseudo header checksum must have already
1516 		 * been computed and stored in the checksum field
1517 		 * in the TCP header. The stack should have
1518 		 * already done this for us.
1519 		 */
1520 		txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1521 		if (m->m_pkthdr.csum_flags & CSUM_TCP)
1522 			txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1523 
1524 #ifdef FXP_IP_CSUM_WAR
1525 		/*
1526 		 * XXX The 82550 chip appears to have trouble
1527 		 * dealing with IP header checksums in very small
1528 		 * datagrams, namely fragments from 1 to 3 bytes
1529 		 * in size. For example, say you want to transmit
1530 		 * a UDP packet of 1473 bytes. The packet will be
1531 		 * fragmented over two IP datagrams, the latter
1532 		 * containing only one byte of data. The 82550 will
1533 		 * botch the header checksum on the 1-byte fragment.
1534 		 * As long as the datagram contains 4 or more bytes
1535 		 * of data, you're ok.
1536 		 *
1537                  * The following code attempts to work around this
1538 		 * problem: if the datagram is less than 38 bytes
1539 		 * in size (14 bytes ether header, 20 bytes IP header,
1540 		 * plus 4 bytes of data), we punt and compute the IP
1541 		 * header checksum by hand. This workaround doesn't
1542 		 * work very well, however, since it can be fooled
1543 		 * by things like VLAN tags and IP options that make
1544 		 * the header sizes/offsets vary.
1545 		 */
1546 
1547 		if (m->m_pkthdr.csum_flags & CSUM_IP) {
1548 			if (m->m_pkthdr.len < 38) {
1549 				struct ip *ip;
1550 				m->m_data += ETHER_HDR_LEN;
1551 				ip = mtod(m, struct ip *);
1552 				ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1553 				m->m_data -= ETHER_HDR_LEN;
1554 				m->m_pkthdr.csum_flags &= ~CSUM_IP;
1555 			} else {
1556 				txp->tx_cb->ipcb_ip_activation_high =
1557 				    FXP_IPCB_HARDWAREPARSING_ENABLE;
1558 				txp->tx_cb->ipcb_ip_schedule |=
1559 				    FXP_IPCB_IP_CHECKSUM_ENABLE;
1560 			}
1561 		}
1562 #endif
1563 	}
1564 
1565 	error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1566 	    segs, &nseg, 0);
1567 	if (error == EFBIG) {
1568 		m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1569 		if (m == NULL) {
1570 			m_freem(*m_head);
1571 			*m_head = NULL;
1572 			return (ENOMEM);
1573 		}
1574 		*m_head = m;
1575 		error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1576 		    *m_head, segs, &nseg, 0);
1577 		if (error != 0) {
1578 			m_freem(*m_head);
1579 			*m_head = NULL;
1580 			return (ENOMEM);
1581 		}
1582 	} else if (error != 0)
1583 		return (error);
1584 	if (nseg == 0) {
1585 		m_freem(*m_head);
1586 		*m_head = NULL;
1587 		return (EIO);
1588 	}
1589 
1590 	KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1591 	bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1592 
1593 	cbp = txp->tx_cb;
1594 	for (i = 0; i < nseg; i++) {
1595 		/*
1596 		 * If this is an 82550/82551, then we're using extended
1597 		 * TxCBs _and_ we're using checksum offload. This means
1598 		 * that the TxCB is really an IPCB. One major difference
1599 		 * between the two is that with plain extended TxCBs,
1600 		 * the bottom half of the TxCB contains two entries from
1601 		 * the TBD array, whereas IPCBs contain just one entry:
1602 		 * one entry (8 bytes) has been sacrificed for the TCP/IP
1603 		 * checksum offload control bits. So to make things work
1604 		 * right, we have to start filling in the TBD array
1605 		 * starting from a different place depending on whether
1606 		 * the chip is an 82550/82551 or not.
1607 		 */
1608 		if (sc->flags & FXP_FLAG_EXT_RFA) {
1609 			cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1610 			cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1611 		} else {
1612 			cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1613 			cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1614 		}
1615 	}
1616 	if (sc->flags & FXP_FLAG_EXT_RFA) {
1617 		/* Configure dynamic TBD for 82550/82551. */
1618 		cbp->tbd_number = 0xFF;
1619 		cbp->tbd[nseg].tb_size |= htole32(0x8000);
1620 	} else
1621 		cbp->tbd_number = nseg;
1622 	/* Configure TSO. */
1623 	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1624 		cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1625 		cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1626 		cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1627 		    FXP_IPCB_IP_CHECKSUM_ENABLE |
1628 		    FXP_IPCB_TCP_PACKET |
1629 		    FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1630 	}
1631 	/* Configure VLAN hardware tag insertion. */
1632 	if ((m->m_flags & M_VLANTAG) != 0) {
1633 		cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1634 		txp->tx_cb->ipcb_ip_activation_high |=
1635 		    FXP_IPCB_INSERTVLAN_ENABLE;
1636 	}
1637 
1638 	txp->tx_mbuf = m;
1639 	txp->tx_cb->cb_status = 0;
1640 	txp->tx_cb->byte_count = 0;
1641 	if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1642 		txp->tx_cb->cb_command =
1643 		    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1644 		    FXP_CB_COMMAND_S);
1645 	else
1646 		txp->tx_cb->cb_command =
1647 		    htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1648 		    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1649 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1650 		txp->tx_cb->tx_threshold = tx_threshold;
1651 
1652 	/*
1653 	 * Advance the end of list forward.
1654 	 */
1655 	sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1656 	sc->fxp_desc.tx_last = txp;
1657 
1658 	/*
1659 	 * Advance the beginning of the list forward if there are
1660 	 * no other packets queued (when nothing is queued, tx_first
1661 	 * sits on the last TxCB that was sent out).
1662 	 */
1663 	if (sc->tx_queued == 0)
1664 		sc->fxp_desc.tx_first = txp;
1665 
1666 	sc->tx_queued++;
1667 
1668 	return (0);
1669 }
1670 
1671 #ifdef DEVICE_POLLING
1672 static poll_handler_t fxp_poll;
1673 
1674 static int
1675 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1676 {
1677 	struct fxp_softc *sc = ifp->if_softc;
1678 	uint8_t statack;
1679 	int rx_npkts = 0;
1680 
1681 	FXP_LOCK(sc);
1682 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1683 		FXP_UNLOCK(sc);
1684 		return (rx_npkts);
1685 	}
1686 
1687 	statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1688 	    FXP_SCB_STATACK_FR;
1689 	if (cmd == POLL_AND_CHECK_STATUS) {
1690 		uint8_t tmp;
1691 
1692 		tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1693 		if (tmp == 0xff || tmp == 0) {
1694 			FXP_UNLOCK(sc);
1695 			return (rx_npkts); /* nothing to do */
1696 		}
1697 		tmp &= ~statack;
1698 		/* ack what we can */
1699 		if (tmp != 0)
1700 			CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1701 		statack |= tmp;
1702 	}
1703 	rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1704 	FXP_UNLOCK(sc);
1705 	return (rx_npkts);
1706 }
1707 #endif /* DEVICE_POLLING */
1708 
1709 /*
1710  * Process interface interrupts.
1711  */
1712 static void
1713 fxp_intr(void *xsc)
1714 {
1715 	struct fxp_softc *sc = xsc;
1716 	struct ifnet *ifp = sc->ifp;
1717 	uint8_t statack;
1718 
1719 	FXP_LOCK(sc);
1720 	if (sc->suspended) {
1721 		FXP_UNLOCK(sc);
1722 		return;
1723 	}
1724 
1725 #ifdef DEVICE_POLLING
1726 	if (ifp->if_capenable & IFCAP_POLLING) {
1727 		FXP_UNLOCK(sc);
1728 		return;
1729 	}
1730 #endif
1731 	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1732 		/*
1733 		 * It should not be possible to have all bits set; the
1734 		 * FXP_SCB_INTR_SWI bit always returns 0 on a read.  If
1735 		 * all bits are set, this may indicate that the card has
1736 		 * been physically ejected, so ignore it.
1737 		 */
1738 		if (statack == 0xff) {
1739 			FXP_UNLOCK(sc);
1740 			return;
1741 		}
1742 
1743 		/*
1744 		 * First ACK all the interrupts in this pass.
1745 		 */
1746 		CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1747 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1748 			fxp_intr_body(sc, ifp, statack, -1);
1749 	}
1750 	FXP_UNLOCK(sc);
1751 }
1752 
1753 static void
1754 fxp_txeof(struct fxp_softc *sc)
1755 {
1756 	struct ifnet *ifp;
1757 	struct fxp_tx *txp;
1758 
1759 	ifp = sc->ifp;
1760 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1761 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1762 	for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1763 	    (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1764 	    txp = txp->tx_next) {
1765 		if (txp->tx_mbuf != NULL) {
1766 			bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1767 			    BUS_DMASYNC_POSTWRITE);
1768 			bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1769 			m_freem(txp->tx_mbuf);
1770 			txp->tx_mbuf = NULL;
1771 			/* clear this to reset csum offload bits */
1772 			txp->tx_cb->tbd[0].tb_addr = 0;
1773 		}
1774 		sc->tx_queued--;
1775 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1776 	}
1777 	sc->fxp_desc.tx_first = txp;
1778 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1779 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1780 	if (sc->tx_queued == 0)
1781 		sc->watchdog_timer = 0;
1782 }
1783 
1784 static void
1785 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m,
1786     uint16_t status, int pos)
1787 {
1788 	struct ether_header *eh;
1789 	struct ip *ip;
1790 	struct udphdr *uh;
1791 	int32_t hlen, len, pktlen, temp32;
1792 	uint16_t csum, *opts;
1793 
1794 	if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1795 		if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1796 			if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1797 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1798 			if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1799 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1800 			if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1801 			    (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1802 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1803 				    CSUM_PSEUDO_HDR;
1804 				m->m_pkthdr.csum_data = 0xffff;
1805 			}
1806 		}
1807 		return;
1808 	}
1809 
1810 	pktlen = m->m_pkthdr.len;
1811 	if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1812 		return;
1813 	eh = mtod(m, struct ether_header *);
1814 	if (eh->ether_type != htons(ETHERTYPE_IP))
1815 		return;
1816 	ip = (struct ip *)(eh + 1);
1817 	if (ip->ip_v != IPVERSION)
1818 		return;
1819 
1820 	hlen = ip->ip_hl << 2;
1821 	pktlen -= sizeof(struct ether_header);
1822 	if (hlen < sizeof(struct ip))
1823 		return;
1824 	if (ntohs(ip->ip_len) < hlen)
1825 		return;
1826 	if (ntohs(ip->ip_len) != pktlen)
1827 		return;
1828 	if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1829 		return;	/* can't handle fragmented packet */
1830 
1831 	switch (ip->ip_p) {
1832 	case IPPROTO_TCP:
1833 		if (pktlen < (hlen + sizeof(struct tcphdr)))
1834 			return;
1835 		break;
1836 	case IPPROTO_UDP:
1837 		if (pktlen < (hlen + sizeof(struct udphdr)))
1838 			return;
1839 		uh = (struct udphdr *)((caddr_t)ip + hlen);
1840 		if (uh->uh_sum == 0)
1841 			return; /* no checksum */
1842 		break;
1843 	default:
1844 		return;
1845 	}
1846 	/* Extract computed checksum. */
1847 	csum = be16dec(mtod(m, char *) + pos);
1848 	/* checksum fixup for IP options */
1849 	len = hlen - sizeof(struct ip);
1850 	if (len > 0) {
1851 		opts = (uint16_t *)(ip + 1);
1852 		for (; len > 0; len -= sizeof(uint16_t), opts++) {
1853 			temp32 = csum - *opts;
1854 			temp32 = (temp32 >> 16) + (temp32 & 65535);
1855 			csum = temp32 & 65535;
1856 		}
1857 	}
1858 	m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1859 	m->m_pkthdr.csum_data = csum;
1860 }
1861 
1862 static int
1863 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1864     int count)
1865 {
1866 	struct mbuf *m;
1867 	struct fxp_rx *rxp;
1868 	struct fxp_rfa *rfa;
1869 	int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1870 	int rx_npkts;
1871 	uint16_t status;
1872 
1873 	rx_npkts = 0;
1874 	FXP_LOCK_ASSERT(sc, MA_OWNED);
1875 
1876 	if (rnr)
1877 		sc->rnr++;
1878 #ifdef DEVICE_POLLING
1879 	/* Pick up a deferred RNR condition if `count' ran out last time. */
1880 	if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1881 		sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1882 		rnr = 1;
1883 	}
1884 #endif
1885 
1886 	/*
1887 	 * Free any finished transmit mbuf chains.
1888 	 *
1889 	 * Handle the CNA event likt a CXTNO event. It used to
1890 	 * be that this event (control unit not ready) was not
1891 	 * encountered, but it is now with the SMPng modifications.
1892 	 * The exact sequence of events that occur when the interface
1893 	 * is brought up are different now, and if this event
1894 	 * goes unhandled, the configuration/rxfilter setup sequence
1895 	 * can stall for several seconds. The result is that no
1896 	 * packets go out onto the wire for about 5 to 10 seconds
1897 	 * after the interface is ifconfig'ed for the first time.
1898 	 */
1899 	if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1900 		fxp_txeof(sc);
1901 
1902 	/*
1903 	 * Try to start more packets transmitting.
1904 	 */
1905 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1906 		fxp_start_body(ifp);
1907 
1908 	/*
1909 	 * Just return if nothing happened on the receive side.
1910 	 */
1911 	if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1912 		return (rx_npkts);
1913 
1914 	/*
1915 	 * Process receiver interrupts. If a no-resource (RNR)
1916 	 * condition exists, get whatever packets we can and
1917 	 * re-start the receiver.
1918 	 *
1919 	 * When using polling, we do not process the list to completion,
1920 	 * so when we get an RNR interrupt we must defer the restart
1921 	 * until we hit the last buffer with the C bit set.
1922 	 * If we run out of cycles and rfa_headm has the C bit set,
1923 	 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1924 	 * that the info will be used in the subsequent polling cycle.
1925 	 */
1926 	for (;;) {
1927 		rxp = sc->fxp_desc.rx_head;
1928 		m = rxp->rx_mbuf;
1929 		rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1930 		    RFA_ALIGNMENT_FUDGE);
1931 		bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1932 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1933 
1934 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1935 		if (count >= 0 && count-- == 0) {
1936 			if (rnr) {
1937 				/* Defer RNR processing until the next time. */
1938 				sc->flags |= FXP_FLAG_DEFERRED_RNR;
1939 				rnr = 0;
1940 			}
1941 			break;
1942 		}
1943 #endif /* DEVICE_POLLING */
1944 
1945 		status = le16toh(rfa->rfa_status);
1946 		if ((status & FXP_RFA_STATUS_C) == 0)
1947 			break;
1948 
1949 		if ((status & FXP_RFA_STATUS_RNR) != 0)
1950 			rnr++;
1951 		/*
1952 		 * Advance head forward.
1953 		 */
1954 		sc->fxp_desc.rx_head = rxp->rx_next;
1955 
1956 		/*
1957 		 * Add a new buffer to the receive chain.
1958 		 * If this fails, the old buffer is recycled
1959 		 * instead.
1960 		 */
1961 		if (fxp_new_rfabuf(sc, rxp) == 0) {
1962 			int total_len;
1963 
1964 			/*
1965 			 * Fetch packet length (the top 2 bits of
1966 			 * actual_size are flags set by the controller
1967 			 * upon completion), and drop the packet in case
1968 			 * of bogus length or CRC errors.
1969 			 */
1970 			total_len = le16toh(rfa->actual_size) & 0x3fff;
1971 			if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1972 			    (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1973 				/* Adjust for appended checksum bytes. */
1974 				total_len -= 2;
1975 			}
1976 			if (total_len < (int)sizeof(struct ether_header) ||
1977 			    total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1978 			    sc->rfa_size) ||
1979 			    status & (FXP_RFA_STATUS_CRC |
1980 			    FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1981 				m_freem(m);
1982 				fxp_add_rfabuf(sc, rxp);
1983 				continue;
1984 			}
1985 
1986 			m->m_pkthdr.len = m->m_len = total_len;
1987 			m->m_pkthdr.rcvif = ifp;
1988 
1989                         /* Do IP checksum checking. */
1990 			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1991 				fxp_rxcsum(sc, ifp, m, status, total_len);
1992 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1993 			    (status & FXP_RFA_STATUS_VLAN) != 0) {
1994 				m->m_pkthdr.ether_vtag =
1995 				    ntohs(rfa->rfax_vlan_id);
1996 				m->m_flags |= M_VLANTAG;
1997 			}
1998 			/*
1999 			 * Drop locks before calling if_input() since it
2000 			 * may re-enter fxp_start() in the netisr case.
2001 			 * This would result in a lock reversal.  Better
2002 			 * performance might be obtained by chaining all
2003 			 * packets received, dropping the lock, and then
2004 			 * calling if_input() on each one.
2005 			 */
2006 			FXP_UNLOCK(sc);
2007 			(*ifp->if_input)(ifp, m);
2008 			FXP_LOCK(sc);
2009 			rx_npkts++;
2010 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2011 				return (rx_npkts);
2012 		} else {
2013 			/* Reuse RFA and loaded DMA map. */
2014 			ifp->if_iqdrops++;
2015 			fxp_discard_rfabuf(sc, rxp);
2016 		}
2017 		fxp_add_rfabuf(sc, rxp);
2018 	}
2019 	if (rnr) {
2020 		fxp_scb_wait(sc);
2021 		CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2022 		    sc->fxp_desc.rx_head->rx_addr);
2023 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2024 	}
2025 	return (rx_npkts);
2026 }
2027 
2028 static void
2029 fxp_update_stats(struct fxp_softc *sc)
2030 {
2031 	struct ifnet *ifp = sc->ifp;
2032 	struct fxp_stats *sp = sc->fxp_stats;
2033 	struct fxp_hwstats *hsp;
2034 	uint32_t *status;
2035 
2036 	FXP_LOCK_ASSERT(sc, MA_OWNED);
2037 
2038 	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2039 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2040 	/* Update statistical counters. */
2041 	if (sc->revision >= FXP_REV_82559_A0)
2042 		status = &sp->completion_status;
2043 	else if (sc->revision >= FXP_REV_82558_A4)
2044 		status = (uint32_t *)&sp->tx_tco;
2045 	else
2046 		status = &sp->tx_pause;
2047 	if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2048 		hsp = &sc->fxp_hwstats;
2049 		hsp->tx_good += le32toh(sp->tx_good);
2050 		hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2051 		hsp->tx_latecols += le32toh(sp->tx_latecols);
2052 		hsp->tx_underruns += le32toh(sp->tx_underruns);
2053 		hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2054 		hsp->tx_deffered += le32toh(sp->tx_deffered);
2055 		hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2056 		hsp->tx_multiple_collisions +=
2057 		    le32toh(sp->tx_multiple_collisions);
2058 		hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2059 		hsp->rx_good += le32toh(sp->rx_good);
2060 		hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2061 		hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2062 		hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2063 		hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2064 		hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2065 		hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2066 		hsp->tx_pause += le32toh(sp->tx_pause);
2067 		hsp->rx_pause += le32toh(sp->rx_pause);
2068 		hsp->rx_controls += le32toh(sp->rx_controls);
2069 		hsp->tx_tco += le16toh(sp->tx_tco);
2070 		hsp->rx_tco += le16toh(sp->rx_tco);
2071 
2072 		ifp->if_opackets += le32toh(sp->tx_good);
2073 		ifp->if_collisions += le32toh(sp->tx_total_collisions);
2074 		if (sp->rx_good) {
2075 			ifp->if_ipackets += le32toh(sp->rx_good);
2076 			sc->rx_idle_secs = 0;
2077 		} else if (sc->flags & FXP_FLAG_RXBUG) {
2078 			/*
2079 			 * Receiver's been idle for another second.
2080 			 */
2081 			sc->rx_idle_secs++;
2082 		}
2083 		ifp->if_ierrors +=
2084 		    le32toh(sp->rx_crc_errors) +
2085 		    le32toh(sp->rx_alignment_errors) +
2086 		    le32toh(sp->rx_rnr_errors) +
2087 		    le32toh(sp->rx_overrun_errors);
2088 		/*
2089 		 * If any transmit underruns occured, bump up the transmit
2090 		 * threshold by another 512 bytes (64 * 8).
2091 		 */
2092 		if (sp->tx_underruns) {
2093 			ifp->if_oerrors += le32toh(sp->tx_underruns);
2094 			if (tx_threshold < 192)
2095 				tx_threshold += 64;
2096 		}
2097 		*status = 0;
2098 		bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2099 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2100 	}
2101 }
2102 
2103 /*
2104  * Update packet in/out/collision statistics. The i82557 doesn't
2105  * allow you to access these counters without doing a fairly
2106  * expensive DMA to get _all_ of the statistics it maintains, so
2107  * we do this operation here only once per second. The statistics
2108  * counters in the kernel are updated from the previous dump-stats
2109  * DMA and then a new dump-stats DMA is started. The on-chip
2110  * counters are zeroed when the DMA completes. If we can't start
2111  * the DMA immediately, we don't wait - we just prepare to read
2112  * them again next time.
2113  */
2114 static void
2115 fxp_tick(void *xsc)
2116 {
2117 	struct fxp_softc *sc = xsc;
2118 	struct ifnet *ifp = sc->ifp;
2119 
2120 	FXP_LOCK_ASSERT(sc, MA_OWNED);
2121 
2122 	/* Update statistical counters. */
2123 	fxp_update_stats(sc);
2124 
2125 	/*
2126 	 * Release any xmit buffers that have completed DMA. This isn't
2127 	 * strictly necessary to do here, but it's advantagous for mbufs
2128 	 * with external storage to be released in a timely manner rather
2129 	 * than being defered for a potentially long time. This limits
2130 	 * the delay to a maximum of one second.
2131 	 */
2132 	fxp_txeof(sc);
2133 
2134 	/*
2135 	 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2136 	 * then assume the receiver has locked up and attempt to clear
2137 	 * the condition by reprogramming the multicast filter. This is
2138 	 * a work-around for a bug in the 82557 where the receiver locks
2139 	 * up if it gets certain types of garbage in the syncronization
2140 	 * bits prior to the packet header. This bug is supposed to only
2141 	 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2142 	 * mode as well (perhaps due to a 10/100 speed transition).
2143 	 */
2144 	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2145 		sc->rx_idle_secs = 0;
2146 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2147 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2148 			fxp_init_body(sc, 1);
2149 		}
2150 		return;
2151 	}
2152 	/*
2153 	 * If there is no pending command, start another stats
2154 	 * dump. Otherwise punt for now.
2155 	 */
2156 	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2157 		/*
2158 		 * Start another stats dump.
2159 		 */
2160 		fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2161 	}
2162 	if (sc->miibus != NULL)
2163 		mii_tick(device_get_softc(sc->miibus));
2164 
2165 	/*
2166 	 * Check that chip hasn't hung.
2167 	 */
2168 	fxp_watchdog(sc);
2169 
2170 	/*
2171 	 * Schedule another timeout one second from now.
2172 	 */
2173 	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2174 }
2175 
2176 /*
2177  * Stop the interface. Cancels the statistics updater and resets
2178  * the interface.
2179  */
2180 static void
2181 fxp_stop(struct fxp_softc *sc)
2182 {
2183 	struct ifnet *ifp = sc->ifp;
2184 	struct fxp_tx *txp;
2185 	int i;
2186 
2187 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2188 	sc->watchdog_timer = 0;
2189 
2190 	/*
2191 	 * Cancel stats updater.
2192 	 */
2193 	callout_stop(&sc->stat_ch);
2194 
2195 	/*
2196 	 * Preserve PCI configuration, configure, IA/multicast
2197 	 * setup and put RU and CU into idle state.
2198 	 */
2199 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2200 	DELAY(50);
2201 	/* Disable interrupts. */
2202 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2203 
2204 	fxp_update_stats(sc);
2205 
2206 	/*
2207 	 * Release any xmit buffers.
2208 	 */
2209 	txp = sc->fxp_desc.tx_list;
2210 	if (txp != NULL) {
2211 		for (i = 0; i < FXP_NTXCB; i++) {
2212 			if (txp[i].tx_mbuf != NULL) {
2213 				bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2214 				    BUS_DMASYNC_POSTWRITE);
2215 				bus_dmamap_unload(sc->fxp_txmtag,
2216 				    txp[i].tx_map);
2217 				m_freem(txp[i].tx_mbuf);
2218 				txp[i].tx_mbuf = NULL;
2219 				/* clear this to reset csum offload bits */
2220 				txp[i].tx_cb->tbd[0].tb_addr = 0;
2221 			}
2222 		}
2223 	}
2224 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2225 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2226 	sc->tx_queued = 0;
2227 }
2228 
2229 /*
2230  * Watchdog/transmission transmit timeout handler. Called when a
2231  * transmission is started on the interface, but no interrupt is
2232  * received before the timeout. This usually indicates that the
2233  * card has wedged for some reason.
2234  */
2235 static void
2236 fxp_watchdog(struct fxp_softc *sc)
2237 {
2238 
2239 	FXP_LOCK_ASSERT(sc, MA_OWNED);
2240 
2241 	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2242 		return;
2243 
2244 	device_printf(sc->dev, "device timeout\n");
2245 	sc->ifp->if_oerrors++;
2246 
2247 	sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2248 	fxp_init_body(sc, 1);
2249 }
2250 
2251 /*
2252  * Acquire locks and then call the real initialization function.  This
2253  * is necessary because ether_ioctl() calls if_init() and this would
2254  * result in mutex recursion if the mutex was held.
2255  */
2256 static void
2257 fxp_init(void *xsc)
2258 {
2259 	struct fxp_softc *sc = xsc;
2260 
2261 	FXP_LOCK(sc);
2262 	fxp_init_body(sc, 1);
2263 	FXP_UNLOCK(sc);
2264 }
2265 
2266 /*
2267  * Perform device initialization. This routine must be called with the
2268  * softc lock held.
2269  */
2270 static void
2271 fxp_init_body(struct fxp_softc *sc, int setmedia)
2272 {
2273 	struct ifnet *ifp = sc->ifp;
2274 	struct mii_data *mii;
2275 	struct fxp_cb_config *cbp;
2276 	struct fxp_cb_ias *cb_ias;
2277 	struct fxp_cb_tx *tcbp;
2278 	struct fxp_tx *txp;
2279 	int i, prm;
2280 
2281 	FXP_LOCK_ASSERT(sc, MA_OWNED);
2282 
2283 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2284 		return;
2285 
2286 	/*
2287 	 * Cancel any pending I/O
2288 	 */
2289 	fxp_stop(sc);
2290 
2291 	/*
2292 	 * Issue software reset, which also unloads the microcode.
2293 	 */
2294 	sc->flags &= ~FXP_FLAG_UCODE;
2295 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2296 	DELAY(50);
2297 
2298 	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2299 
2300 	/*
2301 	 * Initialize base of CBL and RFA memory. Loading with zero
2302 	 * sets it up for regular linear addressing.
2303 	 */
2304 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2305 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2306 
2307 	fxp_scb_wait(sc);
2308 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2309 
2310 	/*
2311 	 * Initialize base of dump-stats buffer.
2312 	 */
2313 	fxp_scb_wait(sc);
2314 	bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2315 	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2316 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2317 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2318 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2319 
2320 	/*
2321 	 * Attempt to load microcode if requested.
2322 	 * For ICH based controllers do not load microcode.
2323 	 */
2324 	if (sc->ident->ich == 0) {
2325 		if (ifp->if_flags & IFF_LINK0 &&
2326 		    (sc->flags & FXP_FLAG_UCODE) == 0)
2327 			fxp_load_ucode(sc);
2328 	}
2329 
2330 	/*
2331 	 * Set IFF_ALLMULTI status. It's needed in configure action
2332 	 * command.
2333 	 */
2334 	fxp_mc_addrs(sc);
2335 
2336 	/*
2337 	 * We temporarily use memory that contains the TxCB list to
2338 	 * construct the config CB. The TxCB list memory is rebuilt
2339 	 * later.
2340 	 */
2341 	cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2342 
2343 	/*
2344 	 * This bcopy is kind of disgusting, but there are a bunch of must be
2345 	 * zero and must be one bits in this structure and this is the easiest
2346 	 * way to initialize them all to proper values.
2347 	 */
2348 	bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2349 
2350 	cbp->cb_status =	0;
2351 	cbp->cb_command =	htole16(FXP_CB_COMMAND_CONFIG |
2352 	    FXP_CB_COMMAND_EL);
2353 	cbp->link_addr =	0xffffffff;	/* (no) next command */
2354 	cbp->byte_count =	sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2355 	cbp->rx_fifo_limit =	8;	/* rx fifo threshold (32 bytes) */
2356 	cbp->tx_fifo_limit =	0;	/* tx fifo threshold (0 bytes) */
2357 	cbp->adaptive_ifs =	0;	/* (no) adaptive interframe spacing */
2358 	cbp->mwi_enable =	sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2359 	cbp->type_enable =	0;	/* actually reserved */
2360 	cbp->read_align_en =	sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2361 	cbp->end_wr_on_cl =	sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2362 	cbp->rx_dma_bytecount =	0;	/* (no) rx DMA max */
2363 	cbp->tx_dma_bytecount =	0;	/* (no) tx DMA max */
2364 	cbp->dma_mbce =		0;	/* (disable) dma max counters */
2365 	cbp->late_scb =		0;	/* (don't) defer SCB update */
2366 	cbp->direct_dma_dis =	1;	/* disable direct rcv dma mode */
2367 	cbp->tno_int_or_tco_en =0;	/* (disable) tx not okay interrupt */
2368 	cbp->ci_int =		1;	/* interrupt on CU idle */
2369 	cbp->ext_txcb_dis = 	sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2370 	cbp->ext_stats_dis = 	1;	/* disable extended counters */
2371 	cbp->keep_overrun_rx = 	0;	/* don't pass overrun frames to host */
2372 	cbp->save_bf =		sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2373 	cbp->disc_short_rx =	!prm;	/* discard short packets */
2374 	cbp->underrun_retry =	1;	/* retry mode (once) on DMA underrun */
2375 	cbp->two_frames =	0;	/* do not limit FIFO to 2 frames */
2376 	cbp->dyn_tbd =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2377 	cbp->ext_rfa =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2378 	cbp->mediatype =	sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2379 	cbp->csma_dis =		0;	/* (don't) disable link */
2380 	cbp->tcp_udp_cksum =	((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2381 	    (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2382 	cbp->vlan_tco =		0;	/* (don't) enable vlan wakeup */
2383 	cbp->link_wake_en =	0;	/* (don't) assert PME# on link change */
2384 	cbp->arp_wake_en =	0;	/* (don't) assert PME# on arp */
2385 	cbp->mc_wake_en =	0;	/* (don't) enable PME# on mcmatch */
2386 	cbp->nsai =		1;	/* (don't) disable source addr insert */
2387 	cbp->preamble_length =	2;	/* (7 byte) preamble */
2388 	cbp->loopback =		0;	/* (don't) loopback */
2389 	cbp->linear_priority =	0;	/* (normal CSMA/CD operation) */
2390 	cbp->linear_pri_mode =	0;	/* (wait after xmit only) */
2391 	cbp->interfrm_spacing =	6;	/* (96 bits of) interframe spacing */
2392 	cbp->promiscuous =	prm;	/* promiscuous mode */
2393 	cbp->bcast_disable =	0;	/* (don't) disable broadcasts */
2394 	cbp->wait_after_win =	0;	/* (don't) enable modified backoff alg*/
2395 	cbp->ignore_ul =	0;	/* consider U/L bit in IA matching */
2396 	cbp->crc16_en =		0;	/* (don't) enable crc-16 algorithm */
2397 	cbp->crscdt =		sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2398 
2399 	cbp->stripping =	!prm;	/* truncate rx packet to byte count */
2400 	cbp->padding =		1;	/* (do) pad short tx packets */
2401 	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
2402 	cbp->long_rx_en =	sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2403 	cbp->ia_wake_en =	0;	/* (don't) wake up on address match */
2404 	cbp->magic_pkt_dis =	sc->flags & FXP_FLAG_WOL ? 0 : 1;
2405 	cbp->force_fdx =	0;	/* (don't) force full duplex */
2406 	cbp->fdx_pin_en =	1;	/* (enable) FDX# pin */
2407 	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
2408 	cbp->mc_all =		ifp->if_flags & IFF_ALLMULTI ? 1 : prm;
2409 	cbp->gamla_rx =		sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2410 	cbp->vlan_strip_en =	((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2411 	    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2412 
2413 	if (sc->revision == FXP_REV_82557) {
2414 		/*
2415 		 * The 82557 has no hardware flow control, the values
2416 		 * below are the defaults for the chip.
2417 		 */
2418 		cbp->fc_delay_lsb =	0;
2419 		cbp->fc_delay_msb =	0x40;
2420 		cbp->pri_fc_thresh =	3;
2421 		cbp->tx_fc_dis =	0;
2422 		cbp->rx_fc_restop =	0;
2423 		cbp->rx_fc_restart =	0;
2424 		cbp->fc_filter =	0;
2425 		cbp->pri_fc_loc =	1;
2426 	} else {
2427 		/* Set pause RX FIFO threshold to 1KB. */
2428 		CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2429 		/* Set pause time. */
2430 		cbp->fc_delay_lsb =	0xff;
2431 		cbp->fc_delay_msb =	0xff;
2432 		cbp->pri_fc_thresh =	3;
2433 		mii = device_get_softc(sc->miibus);
2434 		if ((IFM_OPTIONS(mii->mii_media_active) &
2435 		    IFM_ETH_TXPAUSE) != 0)
2436 			/* enable transmit FC */
2437 			cbp->tx_fc_dis = 0;
2438 		else
2439 			/* disable transmit FC */
2440 			cbp->tx_fc_dis = 1;
2441 		if ((IFM_OPTIONS(mii->mii_media_active) &
2442 		    IFM_ETH_RXPAUSE) != 0) {
2443 			/* enable FC restart/restop frames */
2444 			cbp->rx_fc_restart = 1;
2445 			cbp->rx_fc_restop = 1;
2446 		} else {
2447 			/* disable FC restart/restop frames */
2448 			cbp->rx_fc_restart = 0;
2449 			cbp->rx_fc_restop = 0;
2450 		}
2451 		cbp->fc_filter =	!prm;	/* drop FC frames to host */
2452 		cbp->pri_fc_loc =	1;	/* FC pri location (byte31) */
2453 	}
2454 
2455 	/* Enable 82558 and 82559 extended statistics functionality. */
2456 	if (sc->revision >= FXP_REV_82558_A4) {
2457 		if (sc->revision >= FXP_REV_82559_A0) {
2458 			/*
2459 			 * Extend configuration table size to 32
2460 			 * to include TCO configuration.
2461 			 */
2462 			cbp->byte_count = 32;
2463 			cbp->ext_stats_dis = 1;
2464 			/* Enable TCO stats. */
2465 			cbp->tno_int_or_tco_en = 1;
2466 			cbp->gamla_rx = 1;
2467 		} else
2468 			cbp->ext_stats_dis = 0;
2469 	}
2470 
2471 	/*
2472 	 * Start the config command/DMA.
2473 	 */
2474 	fxp_scb_wait(sc);
2475 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2476 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2477 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2478 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2479 	/* ...and wait for it to complete. */
2480 	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2481 
2482 	/*
2483 	 * Now initialize the station address. Temporarily use the TxCB
2484 	 * memory area like we did above for the config CB.
2485 	 */
2486 	cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2487 	cb_ias->cb_status = 0;
2488 	cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2489 	cb_ias->link_addr = 0xffffffff;
2490 	bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2491 
2492 	/*
2493 	 * Start the IAS (Individual Address Setup) command/DMA.
2494 	 */
2495 	fxp_scb_wait(sc);
2496 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2497 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2498 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2499 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2500 	/* ...and wait for it to complete. */
2501 	fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2502 
2503 	/*
2504 	 * Initialize the multicast address list.
2505 	 */
2506 	fxp_mc_setup(sc);
2507 
2508 	/*
2509 	 * Initialize transmit control block (TxCB) list.
2510 	 */
2511 	txp = sc->fxp_desc.tx_list;
2512 	tcbp = sc->fxp_desc.cbl_list;
2513 	bzero(tcbp, FXP_TXCB_SZ);
2514 	for (i = 0; i < FXP_NTXCB; i++) {
2515 		txp[i].tx_mbuf = NULL;
2516 		tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2517 		tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2518 		tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2519 		    (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2520 		if (sc->flags & FXP_FLAG_EXT_TXCB)
2521 			tcbp[i].tbd_array_addr =
2522 			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2523 		else
2524 			tcbp[i].tbd_array_addr =
2525 			    htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2526 		txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2527 	}
2528 	/*
2529 	 * Set the suspend flag on the first TxCB and start the control
2530 	 * unit. It will execute the NOP and then suspend.
2531 	 */
2532 	tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2533 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2534 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2535 	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2536 	sc->tx_queued = 1;
2537 
2538 	fxp_scb_wait(sc);
2539 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2540 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2541 
2542 	/*
2543 	 * Initialize receiver buffer area - RFA.
2544 	 */
2545 	fxp_scb_wait(sc);
2546 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2547 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2548 
2549 	if (sc->miibus != NULL && setmedia != 0)
2550 		mii_mediachg(device_get_softc(sc->miibus));
2551 
2552 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2553 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2554 
2555 	/*
2556 	 * Enable interrupts.
2557 	 */
2558 #ifdef DEVICE_POLLING
2559 	/*
2560 	 * ... but only do that if we are not polling. And because (presumably)
2561 	 * the default is interrupts on, we need to disable them explicitly!
2562 	 */
2563 	if (ifp->if_capenable & IFCAP_POLLING )
2564 		CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2565 	else
2566 #endif /* DEVICE_POLLING */
2567 	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2568 
2569 	/*
2570 	 * Start stats updater.
2571 	 */
2572 	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2573 }
2574 
2575 static int
2576 fxp_serial_ifmedia_upd(struct ifnet *ifp)
2577 {
2578 
2579 	return (0);
2580 }
2581 
2582 static void
2583 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2584 {
2585 
2586 	ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2587 }
2588 
2589 /*
2590  * Change media according to request.
2591  */
2592 static int
2593 fxp_ifmedia_upd(struct ifnet *ifp)
2594 {
2595 	struct fxp_softc *sc = ifp->if_softc;
2596 	struct mii_data *mii;
2597 	struct mii_softc	*miisc;
2598 
2599 	mii = device_get_softc(sc->miibus);
2600 	FXP_LOCK(sc);
2601 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2602 		PHY_RESET(miisc);
2603 	mii_mediachg(mii);
2604 	FXP_UNLOCK(sc);
2605 	return (0);
2606 }
2607 
2608 /*
2609  * Notify the world which media we're using.
2610  */
2611 static void
2612 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2613 {
2614 	struct fxp_softc *sc = ifp->if_softc;
2615 	struct mii_data *mii;
2616 
2617 	mii = device_get_softc(sc->miibus);
2618 	FXP_LOCK(sc);
2619 	mii_pollstat(mii);
2620 	ifmr->ifm_active = mii->mii_media_active;
2621 	ifmr->ifm_status = mii->mii_media_status;
2622 	FXP_UNLOCK(sc);
2623 }
2624 
2625 /*
2626  * Add a buffer to the end of the RFA buffer list.
2627  * Return 0 if successful, 1 for failure. A failure results in
2628  * reusing the RFA buffer.
2629  * The RFA struct is stuck at the beginning of mbuf cluster and the
2630  * data pointer is fixed up to point just past it.
2631  */
2632 static int
2633 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2634 {
2635 	struct mbuf *m;
2636 	struct fxp_rfa *rfa;
2637 	bus_dmamap_t tmp_map;
2638 	int error;
2639 
2640 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2641 	if (m == NULL)
2642 		return (ENOBUFS);
2643 
2644 	/*
2645 	 * Move the data pointer up so that the incoming data packet
2646 	 * will be 32-bit aligned.
2647 	 */
2648 	m->m_data += RFA_ALIGNMENT_FUDGE;
2649 
2650 	/*
2651 	 * Get a pointer to the base of the mbuf cluster and move
2652 	 * data start past it.
2653 	 */
2654 	rfa = mtod(m, struct fxp_rfa *);
2655 	m->m_data += sc->rfa_size;
2656 	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2657 
2658 	rfa->rfa_status = 0;
2659 	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2660 	rfa->actual_size = 0;
2661 	m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2662 	    sc->rfa_size;
2663 
2664 	/*
2665 	 * Initialize the rest of the RFA.  Note that since the RFA
2666 	 * is misaligned, we cannot store values directly.  We're thus
2667 	 * using the le32enc() function which handles endianness and
2668 	 * is also alignment-safe.
2669 	 */
2670 	le32enc(&rfa->link_addr, 0xffffffff);
2671 	le32enc(&rfa->rbd_addr, 0xffffffff);
2672 
2673 	/* Map the RFA into DMA memory. */
2674 	error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2675 	    MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2676 	    &rxp->rx_addr, BUS_DMA_NOWAIT);
2677 	if (error) {
2678 		m_freem(m);
2679 		return (error);
2680 	}
2681 
2682 	if (rxp->rx_mbuf != NULL)
2683 		bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2684 	tmp_map = sc->spare_map;
2685 	sc->spare_map = rxp->rx_map;
2686 	rxp->rx_map = tmp_map;
2687 	rxp->rx_mbuf = m;
2688 
2689 	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2690 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2691 	return (0);
2692 }
2693 
2694 static void
2695 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2696 {
2697 	struct fxp_rfa *p_rfa;
2698 	struct fxp_rx *p_rx;
2699 
2700 	/*
2701 	 * If there are other buffers already on the list, attach this
2702 	 * one to the end by fixing up the tail to point to this one.
2703 	 */
2704 	if (sc->fxp_desc.rx_head != NULL) {
2705 		p_rx = sc->fxp_desc.rx_tail;
2706 		p_rfa = (struct fxp_rfa *)
2707 		    (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2708 		p_rx->rx_next = rxp;
2709 		le32enc(&p_rfa->link_addr, rxp->rx_addr);
2710 		p_rfa->rfa_control = 0;
2711 		bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2712 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2713 	} else {
2714 		rxp->rx_next = NULL;
2715 		sc->fxp_desc.rx_head = rxp;
2716 	}
2717 	sc->fxp_desc.rx_tail = rxp;
2718 }
2719 
2720 static void
2721 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2722 {
2723 	struct mbuf *m;
2724 	struct fxp_rfa *rfa;
2725 
2726 	m = rxp->rx_mbuf;
2727 	m->m_data = m->m_ext.ext_buf;
2728 	/*
2729 	 * Move the data pointer up so that the incoming data packet
2730 	 * will be 32-bit aligned.
2731 	 */
2732 	m->m_data += RFA_ALIGNMENT_FUDGE;
2733 
2734 	/*
2735 	 * Get a pointer to the base of the mbuf cluster and move
2736 	 * data start past it.
2737 	 */
2738 	rfa = mtod(m, struct fxp_rfa *);
2739 	m->m_data += sc->rfa_size;
2740 	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2741 
2742 	rfa->rfa_status = 0;
2743 	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2744 	rfa->actual_size = 0;
2745 
2746 	/*
2747 	 * Initialize the rest of the RFA.  Note that since the RFA
2748 	 * is misaligned, we cannot store values directly.  We're thus
2749 	 * using the le32enc() function which handles endianness and
2750 	 * is also alignment-safe.
2751 	 */
2752 	le32enc(&rfa->link_addr, 0xffffffff);
2753 	le32enc(&rfa->rbd_addr, 0xffffffff);
2754 
2755 	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2756 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2757 }
2758 
2759 static int
2760 fxp_miibus_readreg(device_t dev, int phy, int reg)
2761 {
2762 	struct fxp_softc *sc = device_get_softc(dev);
2763 	int count = 10000;
2764 	int value;
2765 
2766 	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2767 	    (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2768 
2769 	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2770 	    && count--)
2771 		DELAY(10);
2772 
2773 	if (count <= 0)
2774 		device_printf(dev, "fxp_miibus_readreg: timed out\n");
2775 
2776 	return (value & 0xffff);
2777 }
2778 
2779 static int
2780 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2781 {
2782 	struct fxp_softc *sc = device_get_softc(dev);
2783 	int count = 10000;
2784 
2785 	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2786 	    (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2787 	    (value & 0xffff));
2788 
2789 	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2790 	    count--)
2791 		DELAY(10);
2792 
2793 	if (count <= 0)
2794 		device_printf(dev, "fxp_miibus_writereg: timed out\n");
2795 	return (0);
2796 }
2797 
2798 static void
2799 fxp_miibus_statchg(device_t dev)
2800 {
2801 	struct fxp_softc *sc;
2802 	struct mii_data *mii;
2803 	struct ifnet *ifp;
2804 
2805 	sc = device_get_softc(dev);
2806 	mii = device_get_softc(sc->miibus);
2807 	ifp = sc->ifp;
2808 	if (mii == NULL || ifp == NULL ||
2809 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
2810 	    (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2811 	    (IFM_AVALID | IFM_ACTIVE))
2812 		return;
2813 
2814 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2815 	    sc->flags & FXP_FLAG_CU_RESUME_BUG)
2816 		sc->cu_resume_bug = 1;
2817 	else
2818 		sc->cu_resume_bug = 0;
2819 	/*
2820 	 * Call fxp_init_body in order to adjust the flow control settings.
2821 	 * Note that the 82557 doesn't support hardware flow control.
2822 	 */
2823 	if (sc->revision == FXP_REV_82557)
2824 		return;
2825 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2826 	fxp_init_body(sc, 0);
2827 }
2828 
2829 static int
2830 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2831 {
2832 	struct fxp_softc *sc = ifp->if_softc;
2833 	struct ifreq *ifr = (struct ifreq *)data;
2834 	struct mii_data *mii;
2835 	int flag, mask, error = 0, reinit;
2836 
2837 	switch (command) {
2838 	case SIOCSIFFLAGS:
2839 		FXP_LOCK(sc);
2840 		/*
2841 		 * If interface is marked up and not running, then start it.
2842 		 * If it is marked down and running, stop it.
2843 		 * XXX If it's up then re-initialize it. This is so flags
2844 		 * such as IFF_PROMISC are handled.
2845 		 */
2846 		if (ifp->if_flags & IFF_UP) {
2847 			if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) &&
2848 			    ((ifp->if_flags ^ sc->if_flags) &
2849 			    (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2850 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2851 				fxp_init_body(sc, 0);
2852 			} else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2853 				fxp_init_body(sc, 1);
2854 		} else {
2855 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2856 				fxp_stop(sc);
2857 		}
2858 		sc->if_flags = ifp->if_flags;
2859 		FXP_UNLOCK(sc);
2860 		break;
2861 
2862 	case SIOCADDMULTI:
2863 	case SIOCDELMULTI:
2864 		FXP_LOCK(sc);
2865 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2866 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2867 			fxp_init_body(sc, 0);
2868 		}
2869 		FXP_UNLOCK(sc);
2870 		break;
2871 
2872 	case SIOCSIFMEDIA:
2873 	case SIOCGIFMEDIA:
2874 		if (sc->miibus != NULL) {
2875 			mii = device_get_softc(sc->miibus);
2876                         error = ifmedia_ioctl(ifp, ifr,
2877                             &mii->mii_media, command);
2878 		} else {
2879                         error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2880 		}
2881 		break;
2882 
2883 	case SIOCSIFCAP:
2884 		reinit = 0;
2885 		mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2886 #ifdef DEVICE_POLLING
2887 		if (mask & IFCAP_POLLING) {
2888 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
2889 				error = ether_poll_register(fxp_poll, ifp);
2890 				if (error)
2891 					return(error);
2892 				FXP_LOCK(sc);
2893 				CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2894 				    FXP_SCB_INTR_DISABLE);
2895 				ifp->if_capenable |= IFCAP_POLLING;
2896 				FXP_UNLOCK(sc);
2897 			} else {
2898 				error = ether_poll_deregister(ifp);
2899 				/* Enable interrupts in any case */
2900 				FXP_LOCK(sc);
2901 				CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2902 				ifp->if_capenable &= ~IFCAP_POLLING;
2903 				FXP_UNLOCK(sc);
2904 			}
2905 		}
2906 #endif
2907 		FXP_LOCK(sc);
2908 		if ((mask & IFCAP_TXCSUM) != 0 &&
2909 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2910 			ifp->if_capenable ^= IFCAP_TXCSUM;
2911 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2912 				ifp->if_hwassist |= FXP_CSUM_FEATURES;
2913 			else
2914 				ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2915 		}
2916 		if ((mask & IFCAP_RXCSUM) != 0 &&
2917 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2918 			ifp->if_capenable ^= IFCAP_RXCSUM;
2919 			if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2920 				reinit++;
2921 		}
2922 		if ((mask & IFCAP_TSO4) != 0 &&
2923 		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2924 			ifp->if_capenable ^= IFCAP_TSO4;
2925 			if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2926 				ifp->if_hwassist |= CSUM_TSO;
2927 			else
2928 				ifp->if_hwassist &= ~CSUM_TSO;
2929 		}
2930 		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2931 		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2932 			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2933 		if ((mask & IFCAP_VLAN_MTU) != 0 &&
2934 		    (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2935 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
2936 			if (sc->revision != FXP_REV_82557)
2937 				flag = FXP_FLAG_LONG_PKT_EN;
2938 			else /* a hack to get long frames on the old chip */
2939 				flag = FXP_FLAG_SAVE_BAD;
2940 			sc->flags ^= flag;
2941 			if (ifp->if_flags & IFF_UP)
2942 				reinit++;
2943 		}
2944 		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2945 		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2946 			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2947 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2948 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2949 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2950 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2951 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2952 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2953 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2954 				ifp->if_capenable &=
2955 				    ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2956 			reinit++;
2957 		}
2958 		if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2959 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2960 			fxp_init_body(sc, 0);
2961 		}
2962 		FXP_UNLOCK(sc);
2963 		VLAN_CAPABILITIES(ifp);
2964 		break;
2965 
2966 	default:
2967 		error = ether_ioctl(ifp, command, data);
2968 	}
2969 	return (error);
2970 }
2971 
2972 /*
2973  * Fill in the multicast address list and return number of entries.
2974  */
2975 static int
2976 fxp_mc_addrs(struct fxp_softc *sc)
2977 {
2978 	struct fxp_cb_mcs *mcsp = sc->mcsp;
2979 	struct ifnet *ifp = sc->ifp;
2980 	struct ifmultiaddr *ifma;
2981 	int nmcasts;
2982 
2983 	nmcasts = 0;
2984 	if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2985 		if_maddr_rlock(ifp);
2986 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2987 			if (ifma->ifma_addr->sa_family != AF_LINK)
2988 				continue;
2989 			if (nmcasts >= MAXMCADDR) {
2990 				ifp->if_flags |= IFF_ALLMULTI;
2991 				nmcasts = 0;
2992 				break;
2993 			}
2994 			bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2995 			    &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2996 			nmcasts++;
2997 		}
2998 		if_maddr_runlock(ifp);
2999 	}
3000 	mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
3001 	return (nmcasts);
3002 }
3003 
3004 /*
3005  * Program the multicast filter.
3006  *
3007  * We have an artificial restriction that the multicast setup command
3008  * must be the first command in the chain, so we take steps to ensure
3009  * this. By requiring this, it allows us to keep up the performance of
3010  * the pre-initialized command ring (esp. link pointers) by not actually
3011  * inserting the mcsetup command in the ring - i.e. its link pointer
3012  * points to the TxCB ring, but the mcsetup descriptor itself is not part
3013  * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
3014  * lead into the regular TxCB ring when it completes.
3015  */
3016 static void
3017 fxp_mc_setup(struct fxp_softc *sc)
3018 {
3019 	struct fxp_cb_mcs *mcsp;
3020 	int count;
3021 
3022 	FXP_LOCK_ASSERT(sc, MA_OWNED);
3023 
3024 	mcsp = sc->mcsp;
3025 	mcsp->cb_status = 0;
3026 	mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3027 	mcsp->link_addr = 0xffffffff;
3028 	fxp_mc_addrs(sc);
3029 
3030 	/*
3031 	 * Wait until command unit is idle. This should never be the
3032 	 * case when nothing is queued, but make sure anyway.
3033 	 */
3034 	count = 100;
3035 	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3036 	    FXP_SCB_CUS_IDLE && --count)
3037 		DELAY(10);
3038 	if (count == 0) {
3039 		device_printf(sc->dev, "command queue timeout\n");
3040 		return;
3041 	}
3042 
3043 	/*
3044 	 * Start the multicast setup command.
3045 	 */
3046 	fxp_scb_wait(sc);
3047 	bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3048 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3049 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3050 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3051 	/* ...and wait for it to complete. */
3052 	fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3053 }
3054 
3055 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3056 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3057 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3058 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3059 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3060 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3061 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3062 
3063 #define UCODE(x)	x, sizeof(x)/sizeof(uint32_t)
3064 
3065 static const struct ucode {
3066 	uint32_t	revision;
3067 	uint32_t	*ucode;
3068 	int		length;
3069 	u_short		int_delay_offset;
3070 	u_short		bundle_max_offset;
3071 } ucode_table[] = {
3072 	{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3073 	{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3074 	{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3075 	    D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3076 	{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3077 	    D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3078 	{ FXP_REV_82550, UCODE(fxp_ucode_d102),
3079 	    D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3080 	{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3081 	    D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3082 	{ FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3083 	    D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3084 	{ FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3085 	    D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3086 	{ 0, NULL, 0, 0, 0 }
3087 };
3088 
3089 static void
3090 fxp_load_ucode(struct fxp_softc *sc)
3091 {
3092 	const struct ucode *uc;
3093 	struct fxp_cb_ucode *cbp;
3094 	int i;
3095 
3096 	if (sc->flags & FXP_FLAG_NO_UCODE)
3097 		return;
3098 
3099 	for (uc = ucode_table; uc->ucode != NULL; uc++)
3100 		if (sc->revision == uc->revision)
3101 			break;
3102 	if (uc->ucode == NULL)
3103 		return;
3104 	cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3105 	cbp->cb_status = 0;
3106 	cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3107 	cbp->link_addr = 0xffffffff;    	/* (no) next command */
3108 	for (i = 0; i < uc->length; i++)
3109 		cbp->ucode[i] = htole32(uc->ucode[i]);
3110 	if (uc->int_delay_offset)
3111 		*(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3112 		    htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3113 	if (uc->bundle_max_offset)
3114 		*(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3115 		    htole16(sc->tunable_bundle_max);
3116 	/*
3117 	 * Download the ucode to the chip.
3118 	 */
3119 	fxp_scb_wait(sc);
3120 	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3121 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3122 	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3123 	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3124 	/* ...and wait for it to complete. */
3125 	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3126 	device_printf(sc->dev,
3127 	    "Microcode loaded, int_delay: %d usec  bundle_max: %d\n",
3128 	    sc->tunable_int_delay,
3129 	    uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3130 	sc->flags |= FXP_FLAG_UCODE;
3131 	bzero(cbp, FXP_TXCB_SZ);
3132 }
3133 
3134 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d)	\
3135 	SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3136 
3137 static void
3138 fxp_sysctl_node(struct fxp_softc *sc)
3139 {
3140 	struct sysctl_ctx_list *ctx;
3141 	struct sysctl_oid_list *child, *parent;
3142 	struct sysctl_oid *tree;
3143 	struct fxp_hwstats *hsp;
3144 
3145 	ctx = device_get_sysctl_ctx(sc->dev);
3146 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3147 
3148 	SYSCTL_ADD_PROC(ctx, child,
3149 	    OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
3150 	    &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3151 	    "FXP driver receive interrupt microcode bundling delay");
3152 	SYSCTL_ADD_PROC(ctx, child,
3153 	    OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
3154 	    &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3155 	    "FXP driver receive interrupt microcode bundle size limit");
3156 	SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3157 	    "FXP RNR events");
3158 
3159 	/*
3160 	 * Pull in device tunables.
3161 	 */
3162 	sc->tunable_int_delay = TUNABLE_INT_DELAY;
3163 	sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3164 	(void) resource_int_value(device_get_name(sc->dev),
3165 	    device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3166 	(void) resource_int_value(device_get_name(sc->dev),
3167 	    device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3168 	sc->rnr = 0;
3169 
3170 	hsp = &sc->fxp_hwstats;
3171 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3172 	    NULL, "FXP statistics");
3173 	parent = SYSCTL_CHILDREN(tree);
3174 
3175 	/* Rx MAC statistics. */
3176 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3177 	    NULL, "Rx MAC statistics");
3178 	child = SYSCTL_CHILDREN(tree);
3179 	FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3180 	    &hsp->rx_good, "Good frames");
3181 	FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3182 	    &hsp->rx_crc_errors, "CRC errors");
3183 	FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3184 	    &hsp->rx_alignment_errors, "Alignment errors");
3185 	FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3186 	    &hsp->rx_rnr_errors, "RNR errors");
3187 	FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3188 	    &hsp->rx_overrun_errors, "Overrun errors");
3189 	FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3190 	    &hsp->rx_cdt_errors, "Collision detect errors");
3191 	FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3192 	    &hsp->rx_shortframes, "Short frame errors");
3193 	if (sc->revision >= FXP_REV_82558_A4) {
3194 		FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3195 		    &hsp->rx_pause, "Pause frames");
3196 		FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3197 		    &hsp->rx_controls, "Unsupported control frames");
3198 	}
3199 	if (sc->revision >= FXP_REV_82559_A0)
3200 		FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3201 		    &hsp->rx_tco, "TCO frames");
3202 
3203 	/* Tx MAC statistics. */
3204 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3205 	    NULL, "Tx MAC statistics");
3206 	child = SYSCTL_CHILDREN(tree);
3207 	FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3208 	    &hsp->tx_good, "Good frames");
3209 	FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3210 	    &hsp->tx_maxcols, "Maximum collisions errors");
3211 	FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3212 	    &hsp->tx_latecols, "Late collisions errors");
3213 	FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3214 	    &hsp->tx_underruns, "Underrun errors");
3215 	FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3216 	    &hsp->tx_lostcrs, "Lost carrier sense");
3217 	FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3218 	    &hsp->tx_deffered, "Deferred");
3219 	FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3220 	    &hsp->tx_single_collisions, "Single collisions");
3221 	FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3222 	    &hsp->tx_multiple_collisions, "Multiple collisions");
3223 	FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3224 	    &hsp->tx_total_collisions, "Total collisions");
3225 	if (sc->revision >= FXP_REV_82558_A4)
3226 		FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3227 		    &hsp->tx_pause, "Pause frames");
3228 	if (sc->revision >= FXP_REV_82559_A0)
3229 		FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3230 		    &hsp->tx_tco, "TCO frames");
3231 }
3232 
3233 #undef FXP_SYSCTL_STAT_ADD
3234 
3235 static int
3236 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3237 {
3238 	int error, value;
3239 
3240 	value = *(int *)arg1;
3241 	error = sysctl_handle_int(oidp, &value, 0, req);
3242 	if (error || !req->newptr)
3243 		return (error);
3244 	if (value < low || value > high)
3245 		return (EINVAL);
3246 	*(int *)arg1 = value;
3247 	return (0);
3248 }
3249 
3250 /*
3251  * Interrupt delay is expressed in microseconds, a multiplier is used
3252  * to convert this to the appropriate clock ticks before using.
3253  */
3254 static int
3255 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3256 {
3257 
3258 	return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3259 }
3260 
3261 static int
3262 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3263 {
3264 
3265 	return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
3266 }
3267