1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Modifications to support media selection: 6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 67 #include <pci/pcivar.h> 68 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 69 #include <pci/if_fxpreg.h> 70 #include <pci/if_fxpvar.h> 71 72 #ifdef __alpha__ /* XXX */ 73 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 74 #undef vtophys 75 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) 76 #endif /* __alpha__ */ 77 78 /* 79 * NOTE! On the Alpha, we have an alignment constraint. The 80 * card DMAs the packet immediately following the RFA. However, 81 * the first thing in the packet is a 14-byte Ethernet header. 82 * This means that the packet is misaligned. To compensate, 83 * we actually offset the RFA 2 bytes into the cluster. This 84 * alignes the packet after the Ethernet header at a 32-bit 85 * boundary. HOWEVER! This means that the RFA is misaligned! 86 */ 87 #define RFA_ALIGNMENT_FUDGE 2 88 89 /* 90 * Inline function to copy a 16-bit aligned 32-bit quantity. 91 */ 92 static __inline void fxp_lwcopy __P((volatile u_int32_t *, 93 volatile u_int32_t *)); 94 static __inline void 95 fxp_lwcopy(src, dst) 96 volatile u_int32_t *src, *dst; 97 { 98 #ifdef __i386__ 99 *dst = *src; 100 #else 101 volatile u_int16_t *a = (volatile u_int16_t *)src; 102 volatile u_int16_t *b = (volatile u_int16_t *)dst; 103 104 b[0] = a[0]; 105 b[1] = a[1]; 106 #endif 107 } 108 109 /* 110 * Template for default configuration parameters. 111 * See struct fxp_cb_config for the bit definitions. 112 */ 113 static u_char fxp_cb_config_template[] = { 114 0x0, 0x0, /* cb_status */ 115 0x80, 0x2, /* cb_command */ 116 0xff, 0xff, 0xff, 0xff, /* link_addr */ 117 0x16, /* 0 */ 118 0x8, /* 1 */ 119 0x0, /* 2 */ 120 0x0, /* 3 */ 121 0x0, /* 4 */ 122 0x80, /* 5 */ 123 0xb2, /* 6 */ 124 0x3, /* 7 */ 125 0x1, /* 8 */ 126 0x0, /* 9 */ 127 0x26, /* 10 */ 128 0x0, /* 11 */ 129 0x60, /* 12 */ 130 0x0, /* 13 */ 131 0xf2, /* 14 */ 132 0x48, /* 15 */ 133 0x0, /* 16 */ 134 0x40, /* 17 */ 135 0xf3, /* 18 */ 136 0x0, /* 19 */ 137 0x3f, /* 20 */ 138 0x5 /* 21 */ 139 }; 140 141 /* Supported media types. */ 142 struct fxp_supported_media { 143 const int fsm_phy; /* PHY type */ 144 const int *fsm_media; /* the media array */ 145 const int fsm_nmedia; /* the number of supported media */ 146 const int fsm_defmedia; /* default media for this PHY */ 147 }; 148 149 static const int fxp_media_standard[] = { 150 IFM_ETHER|IFM_10_T, 151 IFM_ETHER|IFM_10_T|IFM_FDX, 152 IFM_ETHER|IFM_100_TX, 153 IFM_ETHER|IFM_100_TX|IFM_FDX, 154 IFM_ETHER|IFM_AUTO, 155 }; 156 #define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO) 157 158 static const int fxp_media_default[] = { 159 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */ 160 }; 161 #define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL) 162 163 static const struct fxp_supported_media fxp_media[] = { 164 { FXP_PHY_DP83840, fxp_media_standard, 165 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 166 FXP_MEDIA_STANDARD_DEFMEDIA }, 167 { FXP_PHY_DP83840A, fxp_media_standard, 168 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 169 FXP_MEDIA_STANDARD_DEFMEDIA }, 170 { FXP_PHY_82553A, fxp_media_standard, 171 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 172 FXP_MEDIA_STANDARD_DEFMEDIA }, 173 { FXP_PHY_82553C, fxp_media_standard, 174 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 175 FXP_MEDIA_STANDARD_DEFMEDIA }, 176 { FXP_PHY_82555, fxp_media_standard, 177 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 178 FXP_MEDIA_STANDARD_DEFMEDIA }, 179 { FXP_PHY_82555B, fxp_media_standard, 180 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]), 181 FXP_MEDIA_STANDARD_DEFMEDIA }, 182 { FXP_PHY_80C24, fxp_media_default, 183 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]), 184 FXP_MEDIA_DEFAULT_DEFMEDIA }, 185 }; 186 #define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0])) 187 188 static int fxp_mediachange __P((struct ifnet *)); 189 static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *)); 190 static void fxp_set_media __P((struct fxp_softc *, int)); 191 static __inline void fxp_scb_wait __P((struct fxp_softc *)); 192 static __inline void fxp_dma_wait __P((volatile u_int16_t *, struct fxp_softc *sc)); 193 static void fxp_intr __P((void *)); 194 static void fxp_start __P((struct ifnet *)); 195 static int fxp_ioctl __P((struct ifnet *, 196 u_long, caddr_t)); 197 static void fxp_init __P((void *)); 198 static void fxp_stop __P((struct fxp_softc *)); 199 static void fxp_watchdog __P((struct ifnet *)); 200 static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *)); 201 static int fxp_mdi_read __P((struct fxp_softc *, int, int)); 202 static void fxp_mdi_write __P((struct fxp_softc *, int, int, int)); 203 static void fxp_autosize_eeprom __P((struct fxp_softc *)); 204 static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, 205 int, int)); 206 static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *)); 207 static void fxp_stats_update __P((void *)); 208 static void fxp_mc_setup __P((struct fxp_softc *)); 209 210 /* 211 * Set initial transmit threshold at 64 (512 bytes). This is 212 * increased by 64 (512 bytes) at a time, to maximum of 192 213 * (1536 bytes), if an underrun occurs. 214 */ 215 static int tx_threshold = 64; 216 217 /* 218 * Number of transmit control blocks. This determines the number 219 * of transmit buffers that can be chained in the CB list. 220 * This must be a power of two. 221 */ 222 #define FXP_NTXCB 128 223 224 /* 225 * Number of completed TX commands at which point an interrupt 226 * will be generated to garbage collect the attached buffers. 227 * Must be at least one less than FXP_NTXCB, and should be 228 * enough less so that the transmitter doesn't becomes idle 229 * during the buffer rundown (which would reduce performance). 230 */ 231 #define FXP_CXINT_THRESH 120 232 233 /* 234 * TxCB list index mask. This is used to do list wrap-around. 235 */ 236 #define FXP_TXCB_MASK (FXP_NTXCB - 1) 237 238 /* 239 * Number of receive frame area buffers. These are large so chose 240 * wisely. 241 */ 242 #define FXP_NRFABUFS 64 243 244 /* 245 * Maximum number of seconds that the receiver can be idle before we 246 * assume it's dead and attempt to reset it by reprogramming the 247 * multicast filter. This is part of a work-around for a bug in the 248 * NIC. See fxp_stats_update(). 249 */ 250 #define FXP_MAX_RX_IDLE 15 251 252 /* 253 * Wait for the previous command to be accepted (but not necessarily 254 * completed). 255 */ 256 static __inline void 257 fxp_scb_wait(sc) 258 struct fxp_softc *sc; 259 { 260 int i = 10000; 261 262 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 263 DELAY(2); 264 if (i == 0) 265 printf("fxp%d: SCB timeout\n", FXP_UNIT(sc)); 266 } 267 268 static __inline void 269 fxp_dma_wait(status, sc) 270 volatile u_int16_t *status; 271 struct fxp_softc *sc; 272 { 273 int i = 10000; 274 275 while (!(*status & FXP_CB_STATUS_C) && --i) 276 DELAY(2); 277 if (i == 0) 278 printf("fxp%d: DMA timeout\n", FXP_UNIT(sc)); 279 } 280 281 /* 282 * Return identification string if this is device is ours. 283 */ 284 static int 285 fxp_probe(device_t dev) 286 { 287 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 288 switch (pci_get_device(dev)) { 289 290 case FXP_DEVICEID_i82557: 291 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet"); 292 return 0; 293 case FXP_DEVICEID_i82559: 294 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet"); 295 return 0; 296 case FXP_DEVICEID_i82559ER: 297 device_set_desc(dev, "Intel Embedded 10/100 Ethernet"); 298 return 0; 299 case FXP_DEVICEID_i82562: 300 device_set_desc(dev, "Intel PLC 10/100 Ethernet"); 301 return 0; 302 default: 303 break; 304 } 305 } 306 307 return ENXIO; 308 } 309 310 static int 311 fxp_attach(device_t dev) 312 { 313 int error = 0; 314 struct fxp_softc *sc = device_get_softc(dev); 315 struct ifnet *ifp; 316 u_long val; 317 int rid; 318 319 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF); 320 callout_handle_init(&sc->stat_ch); 321 322 FXP_LOCK(sc); 323 324 /* 325 * Enable bus mastering. 326 */ 327 val = pci_read_config(dev, PCIR_COMMAND, 2); 328 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 329 pci_write_config(dev, PCIR_COMMAND, val, 2); 330 331 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 332 u_int32_t iobase, membase, irq; 333 334 /* Save important PCI config data. */ 335 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 336 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 337 irq = pci_read_config(dev, PCIR_INTLINE, 4); 338 339 /* Reset the power state. */ 340 device_printf(dev, "chip is in D%d power mode " 341 "-- setting to D0\n", pci_get_powerstate(dev)); 342 343 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 344 345 /* Restore PCI config data. */ 346 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 347 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 348 pci_write_config(dev, PCIR_INTLINE, irq, 4); 349 } 350 351 /* 352 * Map control/status registers. 353 */ 354 rid = FXP_PCI_MMBA; 355 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 356 0, ~0, 1, RF_ACTIVE); 357 if (!sc->mem) { 358 device_printf(dev, "could not map memory\n"); 359 error = ENXIO; 360 goto fail; 361 } 362 363 sc->sc_st = rman_get_bustag(sc->mem); 364 sc->sc_sh = rman_get_bushandle(sc->mem); 365 366 /* 367 * Allocate our interrupt. 368 */ 369 rid = 0; 370 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 371 RF_SHAREABLE | RF_ACTIVE); 372 if (sc->irq == NULL) { 373 device_printf(dev, "could not map interrupt\n"); 374 error = ENXIO; 375 goto fail; 376 } 377 378 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 379 fxp_intr, sc, &sc->ih); 380 if (error) { 381 device_printf(dev, "could not setup irq\n"); 382 goto fail; 383 } 384 385 /* Do generic parts of attach. */ 386 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) { 387 /* Failed! */ 388 bus_teardown_intr(dev, sc->irq, sc->ih); 389 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 390 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 391 error = ENXIO; 392 goto fail; 393 } 394 395 device_printf(dev, "Ethernet address %6D%s\n", 396 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : ""); 397 398 ifp = &sc->arpcom.ac_if; 399 ifp->if_unit = device_get_unit(dev); 400 ifp->if_name = "fxp"; 401 ifp->if_output = ether_output; 402 ifp->if_baudrate = 100000000; 403 ifp->if_init = fxp_init; 404 ifp->if_softc = sc; 405 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 406 ifp->if_ioctl = fxp_ioctl; 407 ifp->if_start = fxp_start; 408 ifp->if_watchdog = fxp_watchdog; 409 410 /* 411 * Attach the interface. 412 */ 413 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 414 /* 415 * Let the system queue as many packets as we have available 416 * TX descriptors. 417 */ 418 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 419 420 FXP_UNLOCK(sc); 421 return 0; 422 423 fail: 424 FXP_UNLOCK(sc); 425 mtx_destroy(&sc->sc_mtx); 426 return error; 427 } 428 429 /* 430 * Detach interface. 431 */ 432 static int 433 fxp_detach(device_t dev) 434 { 435 struct fxp_softc *sc = device_get_softc(dev); 436 437 FXP_LOCK(sc); 438 439 /* 440 * Close down routes etc. 441 */ 442 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 443 444 /* 445 * Stop DMA and drop transmit queue. 446 */ 447 fxp_stop(sc); 448 449 /* 450 * Deallocate resources. 451 */ 452 bus_teardown_intr(dev, sc->irq, sc->ih); 453 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 454 bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem); 455 456 /* 457 * Free all the receive buffers. 458 */ 459 if (sc->rfa_headm != NULL) 460 m_freem(sc->rfa_headm); 461 462 /* 463 * Free all media structures. 464 */ 465 ifmedia_removeall(&sc->sc_media); 466 467 /* 468 * Free anciliary structures. 469 */ 470 free(sc->cbl_base, M_DEVBUF); 471 free(sc->fxp_stats, M_DEVBUF); 472 free(sc->mcsp, M_DEVBUF); 473 474 FXP_UNLOCK(sc); 475 mtx_destroy(&sc->sc_mtx); 476 477 return 0; 478 } 479 480 /* 481 * Device shutdown routine. Called at system shutdown after sync. The 482 * main purpose of this routine is to shut off receiver DMA so that 483 * kernel memory doesn't get clobbered during warmboot. 484 */ 485 static int 486 fxp_shutdown(device_t dev) 487 { 488 /* 489 * Make sure that DMA is disabled prior to reboot. Not doing 490 * do could allow DMA to corrupt kernel memory during the 491 * reboot before the driver initializes. 492 */ 493 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 494 return 0; 495 } 496 497 /* 498 * Device suspend routine. Stop the interface and save some PCI 499 * settings in case the BIOS doesn't restore them properly on 500 * resume. 501 */ 502 static int 503 fxp_suspend(device_t dev) 504 { 505 struct fxp_softc *sc = device_get_softc(dev); 506 int i; 507 508 FXP_LOCK(sc); 509 510 fxp_stop(sc); 511 512 for (i=0; i<5; i++) 513 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4); 514 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 515 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 516 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 517 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 518 519 sc->suspended = 1; 520 521 FXP_UNLOCK(sc); 522 523 return 0; 524 } 525 526 /* 527 * Device resume routine. Restore some PCI settings in case the BIOS 528 * doesn't, re-enable busmastering, and restart the interface if 529 * appropriate. 530 */ 531 static int 532 fxp_resume(device_t dev) 533 { 534 struct fxp_softc *sc = device_get_softc(dev); 535 struct ifnet *ifp = &sc->sc_if; 536 u_int16_t pci_command; 537 int i; 538 539 FXP_LOCK(sc); 540 541 /* better way to do this? */ 542 for (i=0; i<5; i++) 543 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4); 544 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 545 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 546 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 547 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 548 549 /* reenable busmastering */ 550 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 551 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 552 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 553 554 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 555 DELAY(10); 556 557 /* reinitialize interface if necessary */ 558 if (ifp->if_flags & IFF_UP) 559 fxp_init(sc); 560 561 sc->suspended = 0; 562 563 FXP_UNLOCK(sc); 564 565 return 0; 566 } 567 568 static device_method_t fxp_methods[] = { 569 /* Device interface */ 570 DEVMETHOD(device_probe, fxp_probe), 571 DEVMETHOD(device_attach, fxp_attach), 572 DEVMETHOD(device_detach, fxp_detach), 573 DEVMETHOD(device_shutdown, fxp_shutdown), 574 DEVMETHOD(device_suspend, fxp_suspend), 575 DEVMETHOD(device_resume, fxp_resume), 576 577 { 0, 0 } 578 }; 579 580 static driver_t fxp_driver = { 581 "fxp", 582 fxp_methods, 583 sizeof(struct fxp_softc), 584 }; 585 586 static devclass_t fxp_devclass; 587 588 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 589 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 590 591 /* 592 * Do generic parts of attach. 593 */ 594 static int 595 fxp_attach_common(sc, enaddr) 596 struct fxp_softc *sc; 597 u_int8_t *enaddr; 598 { 599 u_int16_t data; 600 int i, nmedia, defmedia; 601 const int *media; 602 603 /* 604 * Reset to a stable state. 605 */ 606 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 607 DELAY(10); 608 609 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 610 M_DEVBUF, M_NOWAIT | M_ZERO); 611 if (sc->cbl_base == NULL) 612 goto fail; 613 614 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 615 M_NOWAIT | M_ZERO); 616 if (sc->fxp_stats == NULL) 617 goto fail; 618 619 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 620 if (sc->mcsp == NULL) 621 goto fail; 622 623 /* 624 * Pre-allocate our receive buffers. 625 */ 626 for (i = 0; i < FXP_NRFABUFS; i++) { 627 if (fxp_add_rfabuf(sc, NULL) != 0) { 628 goto fail; 629 } 630 } 631 632 /* 633 * Find out how large of an SEEPROM we have. 634 */ 635 fxp_autosize_eeprom(sc); 636 637 /* 638 * Get info about the primary PHY 639 */ 640 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1); 641 sc->phy_primary_addr = data & 0xff; 642 sc->phy_primary_device = (data >> 8) & 0x3f; 643 sc->phy_10Mbps_only = data >> 15; 644 645 /* 646 * Read MAC address. 647 */ 648 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3); 649 650 /* 651 * Initialize the media structures. 652 */ 653 654 media = fxp_media_default; 655 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]); 656 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA; 657 658 for (i = 0; i < NFXPMEDIA; i++) { 659 if (sc->phy_primary_device == fxp_media[i].fsm_phy) { 660 media = fxp_media[i].fsm_media; 661 nmedia = fxp_media[i].fsm_nmedia; 662 defmedia = fxp_media[i].fsm_defmedia; 663 } 664 } 665 666 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus); 667 for (i = 0; i < nmedia; i++) { 668 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only) 669 continue; 670 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 671 } 672 ifmedia_set(&sc->sc_media, defmedia); 673 674 return (0); 675 676 fail: 677 printf("fxp%d: Failed to malloc memory\n", FXP_UNIT(sc)); 678 if (sc->cbl_base) 679 free(sc->cbl_base, M_DEVBUF); 680 if (sc->fxp_stats) 681 free(sc->fxp_stats, M_DEVBUF); 682 if (sc->mcsp) 683 free(sc->mcsp, M_DEVBUF); 684 /* frees entire chain */ 685 if (sc->rfa_headm) 686 m_freem(sc->rfa_headm); 687 688 return (ENOMEM); 689 } 690 691 /* 692 * From NetBSD: 693 * 694 * Figure out EEPROM size. 695 * 696 * 559's can have either 64-word or 256-word EEPROMs, the 558 697 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 698 * talks about the existance of 16 to 256 word EEPROMs. 699 * 700 * The only known sizes are 64 and 256, where the 256 version is used 701 * by CardBus cards to store CIS information. 702 * 703 * The address is shifted in msb-to-lsb, and after the last 704 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 705 * after which follows the actual data. We try to detect this zero, by 706 * probing the data-out bit in the EEPROM control register just after 707 * having shifted in a bit. If the bit is zero, we assume we've 708 * shifted enough address bits. The data-out should be tri-state, 709 * before this, which should translate to a logical one. 710 * 711 * Other ways to do this would be to try to read a register with known 712 * contents with a varying number of address bits, but no such 713 * register seem to be available. The high bits of register 10 are 01 714 * on the 558 and 559, but apparently not on the 557. 715 * 716 * The Linux driver computes a checksum on the EEPROM data, but the 717 * value of this checksum is not very well documented. 718 */ 719 static void 720 fxp_autosize_eeprom(sc) 721 struct fxp_softc *sc; 722 { 723 u_int16_t reg; 724 int x; 725 726 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 727 /* 728 * Shift in read opcode. 729 */ 730 for (x = 3; x > 0; x--) { 731 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 732 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 733 } else { 734 reg = FXP_EEPROM_EECS; 735 } 736 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 737 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 738 reg | FXP_EEPROM_EESK); 739 DELAY(1); 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 741 DELAY(1); 742 } 743 /* 744 * Shift in address. 745 * Wait for the dummy zero following a correct address shift. 746 */ 747 for (x = 1; x <= 8; x++) { 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 749 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 750 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 751 DELAY(1); 752 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0) 753 break; 754 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 755 DELAY(1); 756 } 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 758 DELAY(1); 759 sc->eeprom_size = x; 760 } 761 /* 762 * Read from the serial EEPROM. Basically, you manually shift in 763 * the read opcode (one bit at a time) and then shift in the address, 764 * and then you shift out the data (all of this one bit at a time). 765 * The word size is 16 bits, so you have to provide the address for 766 * every 16 bits of data. 767 */ 768 static void 769 fxp_read_eeprom(sc, data, offset, words) 770 struct fxp_softc *sc; 771 u_short *data; 772 int offset; 773 int words; 774 { 775 u_int16_t reg; 776 int i, x; 777 778 for (i = 0; i < words; i++) { 779 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 780 /* 781 * Shift in read opcode. 782 */ 783 for (x = 3; x > 0; x--) { 784 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 785 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 786 } else { 787 reg = FXP_EEPROM_EECS; 788 } 789 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 790 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 791 reg | FXP_EEPROM_EESK); 792 DELAY(1); 793 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 794 DELAY(1); 795 } 796 /* 797 * Shift in address. 798 */ 799 for (x = sc->eeprom_size; x > 0; x--) { 800 if ((i + offset) & (1 << (x - 1))) { 801 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 802 } else { 803 reg = FXP_EEPROM_EECS; 804 } 805 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 806 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 807 reg | FXP_EEPROM_EESK); 808 DELAY(1); 809 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 810 DELAY(1); 811 } 812 reg = FXP_EEPROM_EECS; 813 data[i] = 0; 814 /* 815 * Shift out data. 816 */ 817 for (x = 16; x > 0; x--) { 818 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 819 reg | FXP_EEPROM_EESK); 820 DELAY(1); 821 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 822 FXP_EEPROM_EEDO) 823 data[i] |= (1 << (x - 1)); 824 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 825 DELAY(1); 826 } 827 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 828 DELAY(1); 829 } 830 } 831 832 /* 833 * Start packet transmission on the interface. 834 */ 835 static void 836 fxp_start(ifp) 837 struct ifnet *ifp; 838 { 839 struct fxp_softc *sc = ifp->if_softc; 840 struct fxp_cb_tx *txp; 841 842 FXP_LOCK(sc); 843 /* 844 * See if we need to suspend xmit until the multicast filter 845 * has been reprogrammed (which can only be done at the head 846 * of the command chain). 847 */ 848 if (sc->need_mcsetup) { 849 FXP_UNLOCK(sc); 850 return; 851 } 852 853 txp = NULL; 854 855 /* 856 * We're finished if there is nothing more to add to the list or if 857 * we're all filled up with buffers to transmit. 858 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 859 * a NOP command when needed. 860 */ 861 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 862 struct mbuf *m, *mb_head; 863 int segment; 864 865 /* 866 * Grab a packet to transmit. 867 */ 868 IF_DEQUEUE(&ifp->if_snd, mb_head); 869 870 /* 871 * Get pointer to next available tx desc. 872 */ 873 txp = sc->cbl_last->next; 874 875 /* 876 * Go through each of the mbufs in the chain and initialize 877 * the transmit buffer descriptors with the physical address 878 * and size of the mbuf. 879 */ 880 tbdinit: 881 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 882 if (m->m_len != 0) { 883 if (segment == FXP_NTXSEG) 884 break; 885 txp->tbd[segment].tb_addr = 886 vtophys(mtod(m, vm_offset_t)); 887 txp->tbd[segment].tb_size = m->m_len; 888 segment++; 889 } 890 } 891 if (m != NULL) { 892 struct mbuf *mn; 893 894 /* 895 * We ran out of segments. We have to recopy this mbuf 896 * chain first. Bail out if we can't get the new buffers. 897 */ 898 MGETHDR(mn, M_DONTWAIT, MT_DATA); 899 if (mn == NULL) { 900 m_freem(mb_head); 901 break; 902 } 903 if (mb_head->m_pkthdr.len > MHLEN) { 904 MCLGET(mn, M_DONTWAIT); 905 if ((mn->m_flags & M_EXT) == 0) { 906 m_freem(mn); 907 m_freem(mb_head); 908 break; 909 } 910 } 911 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 912 mtod(mn, caddr_t)); 913 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 914 m_freem(mb_head); 915 mb_head = mn; 916 goto tbdinit; 917 } 918 919 txp->tbd_number = segment; 920 txp->mb_head = mb_head; 921 txp->cb_status = 0; 922 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 923 txp->cb_command = 924 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S; 925 } else { 926 txp->cb_command = 927 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 928 /* 929 * Set a 5 second timer just in case we don't hear from the 930 * card again. 931 */ 932 ifp->if_timer = 5; 933 } 934 txp->tx_threshold = tx_threshold; 935 936 /* 937 * Advance the end of list forward. 938 */ 939 940 #ifdef __alpha__ 941 /* 942 * On platforms which can't access memory in 16-bit 943 * granularities, we must prevent the card from DMA'ing 944 * up the status while we update the command field. 945 * This could cause us to overwrite the completion status. 946 */ 947 atomic_clear_short(&sc->cbl_last->cb_command, 948 FXP_CB_COMMAND_S); 949 #else 950 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 951 #endif /*__alpha__*/ 952 sc->cbl_last = txp; 953 954 /* 955 * Advance the beginning of the list forward if there are 956 * no other packets queued (when nothing is queued, cbl_first 957 * sits on the last TxCB that was sent out). 958 */ 959 if (sc->tx_queued == 0) 960 sc->cbl_first = txp; 961 962 sc->tx_queued++; 963 964 /* 965 * Pass packet to bpf if there is a listener. 966 */ 967 if (ifp->if_bpf) 968 bpf_mtap(ifp, mb_head); 969 } 970 971 /* 972 * We're finished. If we added to the list, issue a RESUME to get DMA 973 * going again if suspended. 974 */ 975 if (txp != NULL) { 976 fxp_scb_wait(sc); 977 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 978 } 979 FXP_UNLOCK(sc); 980 } 981 982 /* 983 * Process interface interrupts. 984 */ 985 static void 986 fxp_intr(arg) 987 void *arg; 988 { 989 struct fxp_softc *sc = arg; 990 struct ifnet *ifp = &sc->sc_if; 991 u_int8_t statack; 992 993 FXP_LOCK(sc); 994 995 if (sc->suspended) { 996 FXP_UNLOCK(sc); 997 return; 998 } 999 1000 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1001 /* 1002 * First ACK all the interrupts in this pass. 1003 */ 1004 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1005 1006 /* 1007 * Free any finished transmit mbuf chains. 1008 * 1009 * Handle the CNA event likt a CXTNO event. It used to 1010 * be that this event (control unit not ready) was not 1011 * encountered, but it is now with the SMPng modifications. 1012 * The exact sequence of events that occur when the interface 1013 * is brought up are different now, and if this event 1014 * goes unhandled, the configuration/rxfilter setup sequence 1015 * can stall for several seconds. The result is that no 1016 * packets go out onto the wire for about 5 to 10 seconds 1017 * after the interface is ifconfig'ed for the first time. 1018 */ 1019 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1020 struct fxp_cb_tx *txp; 1021 1022 for (txp = sc->cbl_first; sc->tx_queued && 1023 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1024 txp = txp->next) { 1025 if (txp->mb_head != NULL) { 1026 m_freem(txp->mb_head); 1027 txp->mb_head = NULL; 1028 } 1029 sc->tx_queued--; 1030 } 1031 sc->cbl_first = txp; 1032 ifp->if_timer = 0; 1033 if (sc->tx_queued == 0) { 1034 if (sc->need_mcsetup) 1035 fxp_mc_setup(sc); 1036 } 1037 /* 1038 * Try to start more packets transmitting. 1039 */ 1040 if (ifp->if_snd.ifq_head != NULL) 1041 fxp_start(ifp); 1042 } 1043 /* 1044 * Process receiver interrupts. If a no-resource (RNR) 1045 * condition exists, get whatever packets we can and 1046 * re-start the receiver. 1047 */ 1048 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1049 struct mbuf *m; 1050 struct fxp_rfa *rfa; 1051 rcvloop: 1052 m = sc->rfa_headm; 1053 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1054 RFA_ALIGNMENT_FUDGE); 1055 1056 if (rfa->rfa_status & FXP_RFA_STATUS_C) { 1057 /* 1058 * Remove first packet from the chain. 1059 */ 1060 sc->rfa_headm = m->m_next; 1061 m->m_next = NULL; 1062 1063 /* 1064 * Add a new buffer to the receive chain. 1065 * If this fails, the old buffer is recycled 1066 * instead. 1067 */ 1068 if (fxp_add_rfabuf(sc, m) == 0) { 1069 struct ether_header *eh; 1070 int total_len; 1071 1072 total_len = rfa->actual_size & 1073 (MCLBYTES - 1); 1074 if (total_len < 1075 sizeof(struct ether_header)) { 1076 m_freem(m); 1077 goto rcvloop; 1078 } 1079 m->m_pkthdr.rcvif = ifp; 1080 m->m_pkthdr.len = m->m_len = total_len; 1081 eh = mtod(m, struct ether_header *); 1082 m->m_data += 1083 sizeof(struct ether_header); 1084 m->m_len -= 1085 sizeof(struct ether_header); 1086 m->m_pkthdr.len = m->m_len; 1087 ether_input(ifp, eh, m); 1088 } 1089 goto rcvloop; 1090 } 1091 if (statack & FXP_SCB_STATACK_RNR) { 1092 fxp_scb_wait(sc); 1093 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1094 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1095 RFA_ALIGNMENT_FUDGE); 1096 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1097 FXP_SCB_COMMAND_RU_START); 1098 } 1099 } 1100 } 1101 FXP_UNLOCK(sc); 1102 } 1103 1104 /* 1105 * Update packet in/out/collision statistics. The i82557 doesn't 1106 * allow you to access these counters without doing a fairly 1107 * expensive DMA to get _all_ of the statistics it maintains, so 1108 * we do this operation here only once per second. The statistics 1109 * counters in the kernel are updated from the previous dump-stats 1110 * DMA and then a new dump-stats DMA is started. The on-chip 1111 * counters are zeroed when the DMA completes. If we can't start 1112 * the DMA immediately, we don't wait - we just prepare to read 1113 * them again next time. 1114 */ 1115 static void 1116 fxp_stats_update(arg) 1117 void *arg; 1118 { 1119 struct fxp_softc *sc = arg; 1120 struct ifnet *ifp = &sc->sc_if; 1121 struct fxp_stats *sp = sc->fxp_stats; 1122 struct fxp_cb_tx *txp; 1123 1124 ifp->if_opackets += sp->tx_good; 1125 ifp->if_collisions += sp->tx_total_collisions; 1126 if (sp->rx_good) { 1127 ifp->if_ipackets += sp->rx_good; 1128 sc->rx_idle_secs = 0; 1129 } else { 1130 /* 1131 * Receiver's been idle for another second. 1132 */ 1133 sc->rx_idle_secs++; 1134 } 1135 ifp->if_ierrors += 1136 sp->rx_crc_errors + 1137 sp->rx_alignment_errors + 1138 sp->rx_rnr_errors + 1139 sp->rx_overrun_errors; 1140 /* 1141 * If any transmit underruns occured, bump up the transmit 1142 * threshold by another 512 bytes (64 * 8). 1143 */ 1144 if (sp->tx_underruns) { 1145 ifp->if_oerrors += sp->tx_underruns; 1146 if (tx_threshold < 192) 1147 tx_threshold += 64; 1148 } 1149 FXP_LOCK(sc); 1150 /* 1151 * Release any xmit buffers that have completed DMA. This isn't 1152 * strictly necessary to do here, but it's advantagous for mbufs 1153 * with external storage to be released in a timely manner rather 1154 * than being defered for a potentially long time. This limits 1155 * the delay to a maximum of one second. 1156 */ 1157 for (txp = sc->cbl_first; sc->tx_queued && 1158 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1159 txp = txp->next) { 1160 if (txp->mb_head != NULL) { 1161 m_freem(txp->mb_head); 1162 txp->mb_head = NULL; 1163 } 1164 sc->tx_queued--; 1165 } 1166 sc->cbl_first = txp; 1167 /* 1168 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1169 * then assume the receiver has locked up and attempt to clear 1170 * the condition by reprogramming the multicast filter. This is 1171 * a work-around for a bug in the 82557 where the receiver locks 1172 * up if it gets certain types of garbage in the syncronization 1173 * bits prior to the packet header. This bug is supposed to only 1174 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1175 * mode as well (perhaps due to a 10/100 speed transition). 1176 */ 1177 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1178 sc->rx_idle_secs = 0; 1179 fxp_mc_setup(sc); 1180 } 1181 /* 1182 * If there is no pending command, start another stats 1183 * dump. Otherwise punt for now. 1184 */ 1185 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1186 /* 1187 * Start another stats dump. 1188 */ 1189 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1190 FXP_SCB_COMMAND_CU_DUMPRESET); 1191 } else { 1192 /* 1193 * A previous command is still waiting to be accepted. 1194 * Just zero our copy of the stats and wait for the 1195 * next timer event to update them. 1196 */ 1197 sp->tx_good = 0; 1198 sp->tx_underruns = 0; 1199 sp->tx_total_collisions = 0; 1200 1201 sp->rx_good = 0; 1202 sp->rx_crc_errors = 0; 1203 sp->rx_alignment_errors = 0; 1204 sp->rx_rnr_errors = 0; 1205 sp->rx_overrun_errors = 0; 1206 } 1207 FXP_UNLOCK(sc); 1208 /* 1209 * Schedule another timeout one second from now. 1210 */ 1211 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1212 } 1213 1214 /* 1215 * Stop the interface. Cancels the statistics updater and resets 1216 * the interface. 1217 */ 1218 static void 1219 fxp_stop(sc) 1220 struct fxp_softc *sc; 1221 { 1222 struct ifnet *ifp = &sc->sc_if; 1223 struct fxp_cb_tx *txp; 1224 int i; 1225 1226 FXP_LOCK(sc); 1227 1228 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1229 ifp->if_timer = 0; 1230 1231 /* 1232 * Cancel stats updater. 1233 */ 1234 untimeout(fxp_stats_update, sc, sc->stat_ch); 1235 1236 /* 1237 * Issue software reset 1238 */ 1239 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1240 DELAY(10); 1241 1242 /* 1243 * Release any xmit buffers. 1244 */ 1245 txp = sc->cbl_base; 1246 if (txp != NULL) { 1247 for (i = 0; i < FXP_NTXCB; i++) { 1248 if (txp[i].mb_head != NULL) { 1249 m_freem(txp[i].mb_head); 1250 txp[i].mb_head = NULL; 1251 } 1252 } 1253 } 1254 sc->tx_queued = 0; 1255 1256 /* 1257 * Free all the receive buffers then reallocate/reinitialize 1258 */ 1259 if (sc->rfa_headm != NULL) 1260 m_freem(sc->rfa_headm); 1261 sc->rfa_headm = NULL; 1262 sc->rfa_tailm = NULL; 1263 for (i = 0; i < FXP_NRFABUFS; i++) { 1264 if (fxp_add_rfabuf(sc, NULL) != 0) { 1265 /* 1266 * This "can't happen" - we're at splimp() 1267 * and we just freed all the buffers we need 1268 * above. 1269 */ 1270 panic("fxp_stop: no buffers!"); 1271 } 1272 } 1273 1274 FXP_UNLOCK(sc); 1275 } 1276 1277 /* 1278 * Watchdog/transmission transmit timeout handler. Called when a 1279 * transmission is started on the interface, but no interrupt is 1280 * received before the timeout. This usually indicates that the 1281 * card has wedged for some reason. 1282 */ 1283 static void 1284 fxp_watchdog(ifp) 1285 struct ifnet *ifp; 1286 { 1287 struct fxp_softc *sc = ifp->if_softc; 1288 1289 printf("fxp%d: device timeout\n", FXP_UNIT(sc)); 1290 ifp->if_oerrors++; 1291 1292 fxp_init(sc); 1293 } 1294 1295 static void 1296 fxp_init(xsc) 1297 void *xsc; 1298 { 1299 struct fxp_softc *sc = xsc; 1300 struct ifnet *ifp = &sc->sc_if; 1301 struct fxp_cb_config *cbp; 1302 struct fxp_cb_ias *cb_ias; 1303 struct fxp_cb_tx *txp; 1304 int i, prm; 1305 1306 FXP_LOCK(sc); 1307 /* 1308 * Cancel any pending I/O 1309 */ 1310 fxp_stop(sc); 1311 1312 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1313 1314 /* 1315 * Initialize base of CBL and RFA memory. Loading with zero 1316 * sets it up for regular linear addressing. 1317 */ 1318 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1319 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1320 1321 fxp_scb_wait(sc); 1322 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1323 1324 /* 1325 * Initialize base of dump-stats buffer. 1326 */ 1327 fxp_scb_wait(sc); 1328 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1329 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1330 1331 /* 1332 * We temporarily use memory that contains the TxCB list to 1333 * construct the config CB. The TxCB list memory is rebuilt 1334 * later. 1335 */ 1336 cbp = (struct fxp_cb_config *) sc->cbl_base; 1337 1338 /* 1339 * This bcopy is kind of disgusting, but there are a bunch of must be 1340 * zero and must be one bits in this structure and this is the easiest 1341 * way to initialize them all to proper values. 1342 */ 1343 bcopy(fxp_cb_config_template, 1344 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1345 sizeof(fxp_cb_config_template)); 1346 1347 cbp->cb_status = 0; 1348 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1349 cbp->link_addr = -1; /* (no) next command */ 1350 cbp->byte_count = 22; /* (22) bytes to config */ 1351 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1352 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1353 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1354 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1355 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1356 cbp->dma_bce = 0; /* (disable) dma max counters */ 1357 cbp->late_scb = 0; /* (don't) defer SCB update */ 1358 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1359 cbp->ci_int = 1; /* interrupt on CU idle */ 1360 cbp->save_bf = prm; /* save bad frames */ 1361 cbp->disc_short_rx = !prm; /* discard short packets */ 1362 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1363 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1364 cbp->nsai = 1; /* (don't) disable source addr insert */ 1365 cbp->preamble_length = 2; /* (7 byte) preamble */ 1366 cbp->loopback = 0; /* (don't) loopback */ 1367 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1368 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1369 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1370 cbp->promiscuous = prm; /* promiscuous mode */ 1371 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1372 cbp->crscdt = 0; /* (CRS only) */ 1373 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1374 cbp->padding = 1; /* (do) pad short tx packets */ 1375 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1376 cbp->force_fdx = 0; /* (don't) force full duplex */ 1377 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1378 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1379 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */ 1380 1381 /* 1382 * Start the config command/DMA. 1383 */ 1384 fxp_scb_wait(sc); 1385 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1386 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1387 /* ...and wait for it to complete. */ 1388 fxp_dma_wait(&cbp->cb_status, sc); 1389 1390 /* 1391 * Now initialize the station address. Temporarily use the TxCB 1392 * memory area like we did above for the config CB. 1393 */ 1394 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1395 cb_ias->cb_status = 0; 1396 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1397 cb_ias->link_addr = -1; 1398 bcopy(sc->arpcom.ac_enaddr, 1399 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1400 sizeof(sc->arpcom.ac_enaddr)); 1401 1402 /* 1403 * Start the IAS (Individual Address Setup) command/DMA. 1404 */ 1405 fxp_scb_wait(sc); 1406 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1407 /* ...and wait for it to complete. */ 1408 fxp_dma_wait(&cb_ias->cb_status, sc); 1409 1410 /* 1411 * Initialize transmit control block (TxCB) list. 1412 */ 1413 1414 txp = sc->cbl_base; 1415 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1416 for (i = 0; i < FXP_NTXCB; i++) { 1417 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1418 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1419 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1420 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1421 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1422 } 1423 /* 1424 * Set the suspend flag on the first TxCB and start the control 1425 * unit. It will execute the NOP and then suspend. 1426 */ 1427 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1428 sc->cbl_first = sc->cbl_last = txp; 1429 sc->tx_queued = 1; 1430 1431 fxp_scb_wait(sc); 1432 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1433 1434 /* 1435 * Initialize receiver buffer area - RFA. 1436 */ 1437 fxp_scb_wait(sc); 1438 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1439 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1440 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1441 1442 /* 1443 * Set current media. 1444 */ 1445 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 1446 1447 ifp->if_flags |= IFF_RUNNING; 1448 ifp->if_flags &= ~IFF_OACTIVE; 1449 FXP_UNLOCK(sc); 1450 1451 /* 1452 * Start stats updater. 1453 */ 1454 sc->stat_ch = timeout(fxp_stats_update, sc, hz); 1455 } 1456 1457 static void 1458 fxp_set_media(sc, media) 1459 struct fxp_softc *sc; 1460 int media; 1461 { 1462 1463 switch (sc->phy_primary_device) { 1464 case FXP_PHY_DP83840: 1465 case FXP_PHY_DP83840A: 1466 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR, 1467 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) | 1468 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */ 1469 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */ 1470 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */ 1471 /* fall through */ 1472 case FXP_PHY_82553A: 1473 case FXP_PHY_82553C: /* untested */ 1474 case FXP_PHY_82555: 1475 case FXP_PHY_82555B: 1476 if (IFM_SUBTYPE(media) != IFM_AUTO) { 1477 int flags; 1478 1479 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ? 1480 FXP_PHY_BMCR_SPEED_100M : 0; 1481 flags |= (media & IFM_FDX) ? 1482 FXP_PHY_BMCR_FULLDUPLEX : 0; 1483 fxp_mdi_write(sc, sc->phy_primary_addr, 1484 FXP_PHY_BMCR, 1485 (fxp_mdi_read(sc, sc->phy_primary_addr, 1486 FXP_PHY_BMCR) & 1487 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M | 1488 FXP_PHY_BMCR_FULLDUPLEX)) | flags); 1489 } else { 1490 fxp_mdi_write(sc, sc->phy_primary_addr, 1491 FXP_PHY_BMCR, 1492 (fxp_mdi_read(sc, sc->phy_primary_addr, 1493 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN)); 1494 } 1495 break; 1496 /* 1497 * The Seeq 80c24 doesn't have a PHY programming interface, so do 1498 * nothing. 1499 */ 1500 case FXP_PHY_80C24: 1501 break; 1502 default: 1503 printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n", 1504 FXP_UNIT(sc), sc->phy_primary_device, 1505 sc->phy_primary_addr); 1506 } 1507 } 1508 1509 /* 1510 * Change media according to request. 1511 */ 1512 int 1513 fxp_mediachange(ifp) 1514 struct ifnet *ifp; 1515 { 1516 struct fxp_softc *sc = ifp->if_softc; 1517 struct ifmedia *ifm = &sc->sc_media; 1518 1519 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1520 return (EINVAL); 1521 1522 fxp_set_media(sc, ifm->ifm_media); 1523 return (0); 1524 } 1525 1526 /* 1527 * Notify the world which media we're using. 1528 */ 1529 void 1530 fxp_mediastatus(ifp, ifmr) 1531 struct ifnet *ifp; 1532 struct ifmediareq *ifmr; 1533 { 1534 struct fxp_softc *sc = ifp->if_softc; 1535 int flags, stsflags; 1536 1537 switch (sc->phy_primary_device) { 1538 case FXP_PHY_82555: 1539 case FXP_PHY_82555B: 1540 case FXP_PHY_DP83840: 1541 case FXP_PHY_DP83840A: 1542 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */ 1543 ifmr->ifm_active = IFM_ETHER; 1544 /* 1545 * the following is not an error. 1546 * You need to read this register twice to get current 1547 * status. This is correct documented behaviour, the 1548 * first read gets latched values. 1549 */ 1550 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1551 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS); 1552 if (stsflags & FXP_PHY_STS_LINK_STS) 1553 ifmr->ifm_status |= IFM_ACTIVE; 1554 1555 /* 1556 * If we are in auto mode, then try report the result. 1557 */ 1558 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR); 1559 if (flags & FXP_PHY_BMCR_AUTOEN) { 1560 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */ 1561 if (stsflags & FXP_PHY_STS_AUTO_DONE) { 1562 /* 1563 * Intel and National parts report 1564 * differently on what they found. 1565 */ 1566 if ((sc->phy_primary_device == FXP_PHY_82555) 1567 || (sc->phy_primary_device == FXP_PHY_82555B)) { 1568 flags = fxp_mdi_read(sc, 1569 sc->phy_primary_addr, 1570 FXP_PHY_USC); 1571 1572 if (flags & FXP_PHY_USC_SPEED) 1573 ifmr->ifm_active |= IFM_100_TX; 1574 else 1575 ifmr->ifm_active |= IFM_10_T; 1576 1577 if (flags & FXP_PHY_USC_DUPLEX) 1578 ifmr->ifm_active |= IFM_FDX; 1579 } else { /* it's National. only know speed */ 1580 flags = fxp_mdi_read(sc, 1581 sc->phy_primary_addr, 1582 FXP_DP83840_PAR); 1583 1584 if (flags & FXP_DP83840_PAR_SPEED_10) 1585 ifmr->ifm_active |= IFM_10_T; 1586 else 1587 ifmr->ifm_active |= IFM_100_TX; 1588 } 1589 } 1590 } else { /* in manual mode.. just report what we were set to */ 1591 if (flags & FXP_PHY_BMCR_SPEED_100M) 1592 ifmr->ifm_active |= IFM_100_TX; 1593 else 1594 ifmr->ifm_active |= IFM_10_T; 1595 1596 if (flags & FXP_PHY_BMCR_FULLDUPLEX) 1597 ifmr->ifm_active |= IFM_FDX; 1598 } 1599 break; 1600 1601 case FXP_PHY_80C24: 1602 default: 1603 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */ 1604 } 1605 } 1606 1607 /* 1608 * Add a buffer to the end of the RFA buffer list. 1609 * Return 0 if successful, 1 for failure. A failure results in 1610 * adding the 'oldm' (if non-NULL) on to the end of the list - 1611 * tossing out its old contents and recycling it. 1612 * The RFA struct is stuck at the beginning of mbuf cluster and the 1613 * data pointer is fixed up to point just past it. 1614 */ 1615 static int 1616 fxp_add_rfabuf(sc, oldm) 1617 struct fxp_softc *sc; 1618 struct mbuf *oldm; 1619 { 1620 u_int32_t v; 1621 struct mbuf *m; 1622 struct fxp_rfa *rfa, *p_rfa; 1623 1624 MGETHDR(m, M_DONTWAIT, MT_DATA); 1625 if (m != NULL) { 1626 MCLGET(m, M_DONTWAIT); 1627 if ((m->m_flags & M_EXT) == 0) { 1628 m_freem(m); 1629 if (oldm == NULL) 1630 return 1; 1631 m = oldm; 1632 m->m_data = m->m_ext.ext_buf; 1633 } 1634 } else { 1635 if (oldm == NULL) 1636 return 1; 1637 m = oldm; 1638 m->m_data = m->m_ext.ext_buf; 1639 } 1640 1641 /* 1642 * Move the data pointer up so that the incoming data packet 1643 * will be 32-bit aligned. 1644 */ 1645 m->m_data += RFA_ALIGNMENT_FUDGE; 1646 1647 /* 1648 * Get a pointer to the base of the mbuf cluster and move 1649 * data start past it. 1650 */ 1651 rfa = mtod(m, struct fxp_rfa *); 1652 m->m_data += sizeof(struct fxp_rfa); 1653 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1654 1655 /* 1656 * Initialize the rest of the RFA. Note that since the RFA 1657 * is misaligned, we cannot store values directly. Instead, 1658 * we use an optimized, inline copy. 1659 */ 1660 1661 rfa->rfa_status = 0; 1662 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1663 rfa->actual_size = 0; 1664 1665 v = -1; 1666 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1667 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1668 1669 /* 1670 * If there are other buffers already on the list, attach this 1671 * one to the end by fixing up the tail to point to this one. 1672 */ 1673 if (sc->rfa_headm != NULL) { 1674 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1675 RFA_ALIGNMENT_FUDGE); 1676 sc->rfa_tailm->m_next = m; 1677 v = vtophys(rfa); 1678 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1679 p_rfa->rfa_control = 0; 1680 } else { 1681 sc->rfa_headm = m; 1682 } 1683 sc->rfa_tailm = m; 1684 1685 return (m == oldm); 1686 } 1687 1688 static volatile int 1689 fxp_mdi_read(sc, phy, reg) 1690 struct fxp_softc *sc; 1691 int phy; 1692 int reg; 1693 { 1694 int count = 10000; 1695 int value; 1696 1697 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1698 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1699 1700 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1701 && count--) 1702 DELAY(10); 1703 1704 if (count <= 0) 1705 printf("fxp%d: fxp_mdi_read: timed out\n", FXP_UNIT(sc)); 1706 1707 return (value & 0xffff); 1708 } 1709 1710 static void 1711 fxp_mdi_write(sc, phy, reg, value) 1712 struct fxp_softc *sc; 1713 int phy; 1714 int reg; 1715 int value; 1716 { 1717 int count = 10000; 1718 1719 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1720 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1721 (value & 0xffff)); 1722 1723 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1724 count--) 1725 DELAY(10); 1726 1727 if (count <= 0) 1728 printf("fxp%d: fxp_mdi_write: timed out\n", FXP_UNIT(sc)); 1729 } 1730 1731 static int 1732 fxp_ioctl(ifp, command, data) 1733 struct ifnet *ifp; 1734 u_long command; 1735 caddr_t data; 1736 { 1737 struct fxp_softc *sc = ifp->if_softc; 1738 struct ifreq *ifr = (struct ifreq *)data; 1739 int error = 0; 1740 1741 FXP_LOCK(sc); 1742 1743 switch (command) { 1744 1745 case SIOCSIFADDR: 1746 case SIOCGIFADDR: 1747 case SIOCSIFMTU: 1748 error = ether_ioctl(ifp, command, data); 1749 break; 1750 1751 case SIOCSIFFLAGS: 1752 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1753 1754 /* 1755 * If interface is marked up and not running, then start it. 1756 * If it is marked down and running, stop it. 1757 * XXX If it's up then re-initialize it. This is so flags 1758 * such as IFF_PROMISC are handled. 1759 */ 1760 if (ifp->if_flags & IFF_UP) { 1761 fxp_init(sc); 1762 } else { 1763 if (ifp->if_flags & IFF_RUNNING) 1764 fxp_stop(sc); 1765 } 1766 break; 1767 1768 case SIOCADDMULTI: 1769 case SIOCDELMULTI: 1770 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1771 /* 1772 * Multicast list has changed; set the hardware filter 1773 * accordingly. 1774 */ 1775 if (!sc->all_mcasts) 1776 fxp_mc_setup(sc); 1777 /* 1778 * fxp_mc_setup() can turn on sc->all_mcasts, so check it 1779 * again rather than else {}. 1780 */ 1781 if (sc->all_mcasts) 1782 fxp_init(sc); 1783 error = 0; 1784 break; 1785 1786 case SIOCSIFMEDIA: 1787 case SIOCGIFMEDIA: 1788 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 1789 break; 1790 1791 default: 1792 error = EINVAL; 1793 } 1794 FXP_UNLOCK(sc); 1795 return (error); 1796 } 1797 1798 /* 1799 * Program the multicast filter. 1800 * 1801 * We have an artificial restriction that the multicast setup command 1802 * must be the first command in the chain, so we take steps to ensure 1803 * this. By requiring this, it allows us to keep up the performance of 1804 * the pre-initialized command ring (esp. link pointers) by not actually 1805 * inserting the mcsetup command in the ring - i.e. its link pointer 1806 * points to the TxCB ring, but the mcsetup descriptor itself is not part 1807 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 1808 * lead into the regular TxCB ring when it completes. 1809 * 1810 * This function must be called at splimp. 1811 */ 1812 static void 1813 fxp_mc_setup(sc) 1814 struct fxp_softc *sc; 1815 { 1816 struct fxp_cb_mcs *mcsp = sc->mcsp; 1817 struct ifnet *ifp = &sc->sc_if; 1818 struct ifmultiaddr *ifma; 1819 int nmcasts; 1820 int count; 1821 1822 /* 1823 * If there are queued commands, we must wait until they are all 1824 * completed. If we are already waiting, then add a NOP command 1825 * with interrupt option so that we're notified when all commands 1826 * have been completed - fxp_start() ensures that no additional 1827 * TX commands will be added when need_mcsetup is true. 1828 */ 1829 if (sc->tx_queued) { 1830 struct fxp_cb_tx *txp; 1831 1832 /* 1833 * need_mcsetup will be true if we are already waiting for the 1834 * NOP command to be completed (see below). In this case, bail. 1835 */ 1836 if (sc->need_mcsetup) 1837 return; 1838 sc->need_mcsetup = 1; 1839 1840 /* 1841 * Add a NOP command with interrupt so that we are notified when all 1842 * TX commands have been processed. 1843 */ 1844 txp = sc->cbl_last->next; 1845 txp->mb_head = NULL; 1846 txp->cb_status = 0; 1847 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1848 /* 1849 * Advance the end of list forward. 1850 */ 1851 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1852 sc->cbl_last = txp; 1853 sc->tx_queued++; 1854 /* 1855 * Issue a resume in case the CU has just suspended. 1856 */ 1857 fxp_scb_wait(sc); 1858 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 1859 /* 1860 * Set a 5 second timer just in case we don't hear from the 1861 * card again. 1862 */ 1863 ifp->if_timer = 5; 1864 1865 return; 1866 } 1867 sc->need_mcsetup = 0; 1868 1869 /* 1870 * Initialize multicast setup descriptor. 1871 */ 1872 mcsp->next = sc->cbl_base; 1873 mcsp->mb_head = NULL; 1874 mcsp->cb_status = 0; 1875 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1876 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 1877 1878 nmcasts = 0; 1879 if (!sc->all_mcasts) { 1880 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1881 ifma = ifma->ifma_link.le_next) { 1882 if (ifma->ifma_addr->sa_family != AF_LINK) 1883 continue; 1884 if (nmcasts >= MAXMCADDR) { 1885 sc->all_mcasts = 1; 1886 nmcasts = 0; 1887 break; 1888 } 1889 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1890 (void *)(uintptr_t)(volatile void *) 1891 &sc->mcsp->mc_addr[nmcasts][0], 6); 1892 nmcasts++; 1893 } 1894 } 1895 mcsp->mc_cnt = nmcasts * 6; 1896 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 1897 sc->tx_queued = 1; 1898 1899 /* 1900 * Wait until command unit is not active. This should never 1901 * be the case when nothing is queued, but make sure anyway. 1902 */ 1903 count = 100; 1904 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1905 FXP_SCB_CUS_ACTIVE && --count) 1906 DELAY(10); 1907 if (count == 0) { 1908 printf("fxp%d: command queue timeout\n", FXP_UNIT(sc)); 1909 return; 1910 } 1911 1912 /* 1913 * Start the multicast setup command. 1914 */ 1915 fxp_scb_wait(sc); 1916 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1917 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1918 1919 ifp->if_timer = 2; 1920 return; 1921 } 1922