1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/mbuf.h> 41 /* #include <sys/mutex.h> */ 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 #include <sys/sockio.h> 53 #include <sys/bus.h> 54 #include <machine/bus.h> 55 #include <sys/rman.h> 56 #include <machine/resource.h> 57 58 #include <net/ethernet.h> 59 #include <net/if_arp.h> 60 61 #include <machine/clock.h> /* for DELAY */ 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #ifdef FXP_IP_CSUM_WAR 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <machine/in_cksum.h> 71 #endif 72 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */ 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <dev/fxp/if_fxpreg.h> 80 #include <dev/fxp/if_fxpvar.h> 81 #include <dev/fxp/rcvbundl.h> 82 83 MODULE_DEPEND(fxp, pci, 1, 1, 1); 84 MODULE_DEPEND(fxp, ether, 1, 1, 1); 85 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 86 #include "miibus_if.h" 87 88 /* 89 * NOTE! On the Alpha, we have an alignment constraint. The 90 * card DMAs the packet immediately following the RFA. However, 91 * the first thing in the packet is a 14-byte Ethernet header. 92 * This means that the packet is misaligned. To compensate, 93 * we actually offset the RFA 2 bytes into the cluster. This 94 * alignes the packet after the Ethernet header at a 32-bit 95 * boundary. HOWEVER! This means that the RFA is misaligned! 96 */ 97 #define RFA_ALIGNMENT_FUDGE 2 98 99 /* 100 * Set initial transmit threshold at 64 (512 bytes). This is 101 * increased by 64 (512 bytes) at a time, to maximum of 192 102 * (1536 bytes), if an underrun occurs. 103 */ 104 static int tx_threshold = 64; 105 106 /* 107 * The configuration byte map has several undefined fields which 108 * must be one or must be zero. Set up a template for these bits 109 * only, (assuming a 82557 chip) leaving the actual configuration 110 * to fxp_init. 111 * 112 * See struct fxp_cb_config for the bit definitions. 113 */ 114 static u_char fxp_cb_config_template[] = { 115 0x0, 0x0, /* cb_status */ 116 0x0, 0x0, /* cb_command */ 117 0x0, 0x0, 0x0, 0x0, /* link_addr */ 118 0x0, /* 0 */ 119 0x0, /* 1 */ 120 0x0, /* 2 */ 121 0x0, /* 3 */ 122 0x0, /* 4 */ 123 0x0, /* 5 */ 124 0x32, /* 6 */ 125 0x0, /* 7 */ 126 0x0, /* 8 */ 127 0x0, /* 9 */ 128 0x6, /* 10 */ 129 0x0, /* 11 */ 130 0x0, /* 12 */ 131 0x0, /* 13 */ 132 0xf2, /* 14 */ 133 0x48, /* 15 */ 134 0x0, /* 16 */ 135 0x40, /* 17 */ 136 0xf0, /* 18 */ 137 0x0, /* 19 */ 138 0x3f, /* 20 */ 139 0x5 /* 21 */ 140 }; 141 142 struct fxp_ident { 143 uint16_t devid; 144 int16_t revid; /* -1 matches anything */ 145 char *name; 146 }; 147 148 /* 149 * Claim various Intel PCI device identifiers for this driver. The 150 * sub-vendor and sub-device field are extensively used to identify 151 * particular variants, but we don't currently differentiate between 152 * them. 153 */ 154 static struct fxp_ident fxp_ident_table[] = { 155 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 156 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 157 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 158 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 159 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 161 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 162 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 163 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 164 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 165 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 166 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 167 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 168 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 169 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 170 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 171 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 172 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 173 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 174 { 0x1064, -1, "Intel 82562EZ (ICH6)" }, 175 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 194 { 0, -1, NULL }, 195 }; 196 197 #ifdef FXP_IP_CSUM_WAR 198 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 199 #else 200 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 201 #endif 202 203 static int fxp_probe(device_t dev); 204 static int fxp_attach(device_t dev); 205 static int fxp_detach(device_t dev); 206 static int fxp_shutdown(device_t dev); 207 static int fxp_suspend(device_t dev); 208 static int fxp_resume(device_t dev); 209 210 static void fxp_intr(void *xsc); 211 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, 212 uint8_t statack, int count); 213 static void fxp_init(void *xsc); 214 static void fxp_init_body(struct fxp_softc *sc); 215 static void fxp_tick(void *xsc); 216 static void fxp_start(struct ifnet *ifp); 217 static void fxp_start_body(struct ifnet *ifp); 218 static int fxp_encap(struct fxp_softc *sc, struct mbuf *m_head); 219 static void fxp_stop(struct fxp_softc *sc); 220 static void fxp_release(struct fxp_softc *sc); 221 static int fxp_ioctl(struct ifnet *ifp, u_long command, 222 caddr_t data); 223 static void fxp_watchdog(struct ifnet *ifp); 224 static int fxp_add_rfabuf(struct fxp_softc *sc, 225 struct fxp_rx *rxp); 226 static int fxp_mc_addrs(struct fxp_softc *sc); 227 static void fxp_mc_setup(struct fxp_softc *sc); 228 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 229 int autosize); 230 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 231 uint16_t data); 232 static void fxp_autosize_eeprom(struct fxp_softc *sc); 233 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 234 int offset, int words); 235 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 236 int offset, int words); 237 static int fxp_ifmedia_upd(struct ifnet *ifp); 238 static void fxp_ifmedia_sts(struct ifnet *ifp, 239 struct ifmediareq *ifmr); 240 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 241 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 242 struct ifmediareq *ifmr); 243 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 244 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 245 int value); 246 static void fxp_load_ucode(struct fxp_softc *sc); 247 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 248 int low, int high); 249 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 250 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 251 static void fxp_scb_wait(struct fxp_softc *sc); 252 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 253 static void fxp_dma_wait(struct fxp_softc *sc, 254 volatile uint16_t *status, bus_dma_tag_t dmat, 255 bus_dmamap_t map); 256 257 static device_method_t fxp_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, fxp_probe), 260 DEVMETHOD(device_attach, fxp_attach), 261 DEVMETHOD(device_detach, fxp_detach), 262 DEVMETHOD(device_shutdown, fxp_shutdown), 263 DEVMETHOD(device_suspend, fxp_suspend), 264 DEVMETHOD(device_resume, fxp_resume), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 268 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t fxp_driver = { 274 "fxp", 275 fxp_methods, 276 sizeof(struct fxp_softc), 277 }; 278 279 static devclass_t fxp_devclass; 280 281 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 283 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 284 285 static struct resource_spec fxp_res_spec_mem[] = { 286 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE }, 287 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 288 { -1, 0 } 289 }; 290 291 static struct resource_spec fxp_res_spec_io[] = { 292 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE }, 293 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 294 { -1, 0 } 295 }; 296 297 /* 298 * Wait for the previous command to be accepted (but not necessarily 299 * completed). 300 */ 301 static void 302 fxp_scb_wait(struct fxp_softc *sc) 303 { 304 union { 305 uint16_t w; 306 uint8_t b[2]; 307 } flowctl; 308 int i = 10000; 309 310 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 311 DELAY(2); 312 if (i == 0) { 313 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL); 314 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1); 315 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 316 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 317 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 318 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); 319 } 320 } 321 322 static void 323 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 324 { 325 326 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 327 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 328 fxp_scb_wait(sc); 329 } 330 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 331 } 332 333 static void 334 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status, 335 bus_dma_tag_t dmat, bus_dmamap_t map) 336 { 337 int i = 10000; 338 339 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 340 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { 341 DELAY(2); 342 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); 343 } 344 if (i == 0) 345 device_printf(sc->dev, "DMA timeout\n"); 346 } 347 348 /* 349 * Return identification string if this device is ours. 350 */ 351 static int 352 fxp_probe(device_t dev) 353 { 354 uint16_t devid; 355 uint8_t revid; 356 struct fxp_ident *ident; 357 358 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 359 devid = pci_get_device(dev); 360 revid = pci_get_revid(dev); 361 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 362 if (ident->devid == devid && 363 (ident->revid == revid || ident->revid == -1)) { 364 device_set_desc(dev, ident->name); 365 return (BUS_PROBE_DEFAULT); 366 } 367 } 368 } 369 return (ENXIO); 370 } 371 372 static void 373 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 374 { 375 uint32_t *addr; 376 377 if (error) 378 return; 379 380 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 381 addr = arg; 382 *addr = segs->ds_addr; 383 } 384 385 static int 386 fxp_attach(device_t dev) 387 { 388 struct fxp_softc *sc; 389 struct fxp_cb_tx *tcbp; 390 struct fxp_tx *txp; 391 struct fxp_rx *rxp; 392 struct ifnet *ifp; 393 uint32_t val; 394 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 395 u_char eaddr[ETHER_ADDR_LEN]; 396 int i, prefer_iomap; 397 int error; 398 399 error = 0; 400 sc = device_get_softc(dev); 401 sc->dev = dev; 402 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 403 MTX_DEF); 404 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0); 405 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 406 fxp_serial_ifmedia_sts); 407 408 ifp = sc->ifp = if_alloc(IFT_ETHER); 409 if (ifp == NULL) { 410 device_printf(dev, "can not if_alloc()\n"); 411 error = ENOSPC; 412 goto fail; 413 } 414 415 /* 416 * Enable bus mastering. 417 */ 418 pci_enable_busmaster(dev); 419 val = pci_read_config(dev, PCIR_COMMAND, 2); 420 421 /* 422 * Figure out which we should try first - memory mapping or i/o mapping? 423 * We default to memory mapping. Then we accept an override from the 424 * command line. Then we check to see which one is enabled. 425 */ 426 prefer_iomap = 0; 427 resource_int_value(device_get_name(dev), device_get_unit(dev), 428 "prefer_iomap", &prefer_iomap); 429 if (prefer_iomap) 430 sc->fxp_spec = fxp_res_spec_io; 431 else 432 sc->fxp_spec = fxp_res_spec_mem; 433 434 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 435 if (error) { 436 if (sc->fxp_spec == fxp_res_spec_mem) 437 sc->fxp_spec = fxp_res_spec_io; 438 else 439 sc->fxp_spec = fxp_res_spec_mem; 440 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res); 441 } 442 if (error) { 443 device_printf(dev, "could not allocate resources\n"); 444 error = ENXIO; 445 goto fail; 446 } 447 448 if (bootverbose) { 449 device_printf(dev, "using %s space register mapping\n", 450 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O"); 451 } 452 453 /* 454 * Reset to a stable state. 455 */ 456 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 457 DELAY(10); 458 459 /* 460 * Find out how large of an SEEPROM we have. 461 */ 462 fxp_autosize_eeprom(sc); 463 464 /* 465 * Find out the chip revision; lump all 82557 revs together. 466 */ 467 fxp_read_eeprom(sc, &data, 5, 1); 468 if ((data >> 8) == 1) 469 sc->revision = FXP_REV_82557; 470 else 471 sc->revision = pci_get_revid(dev); 472 473 /* 474 * Determine whether we must use the 503 serial interface. 475 */ 476 fxp_read_eeprom(sc, &data, 6, 1); 477 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0 478 && (data & FXP_PHY_SERIAL_ONLY)) 479 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 480 481 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 482 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 483 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW, 484 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 485 "FXP driver receive interrupt microcode bundling delay"); 486 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 487 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 488 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW, 489 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 490 "FXP driver receive interrupt microcode bundle size limit"); 491 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 492 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 493 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0, 494 "FXP RNR events"); 495 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 496 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 497 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0, 498 "FXP flow control disabled"); 499 500 /* 501 * Pull in device tunables. 502 */ 503 sc->tunable_int_delay = TUNABLE_INT_DELAY; 504 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 505 sc->tunable_noflow = 1; 506 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "int_delay", &sc->tunable_int_delay); 508 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 509 "bundle_max", &sc->tunable_bundle_max); 510 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 511 "noflow", &sc->tunable_noflow); 512 sc->rnr = 0; 513 514 /* 515 * Enable workarounds for certain chip revision deficiencies. 516 * 517 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 518 * some systems based a normal 82559 design, have a defect where 519 * the chip can cause a PCI protocol violation if it receives 520 * a CU_RESUME command when it is entering the IDLE state. The 521 * workaround is to disable Dynamic Standby Mode, so the chip never 522 * deasserts CLKRUN#, and always remains in an active state. 523 * 524 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 525 */ 526 i = pci_get_device(dev); 527 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 528 sc->revision >= FXP_REV_82559_A0) { 529 fxp_read_eeprom(sc, &data, 10, 1); 530 if (data & 0x02) { /* STB enable */ 531 uint16_t cksum; 532 int i; 533 534 device_printf(dev, 535 "Disabling dynamic standby mode in EEPROM\n"); 536 data &= ~0x02; 537 fxp_write_eeprom(sc, &data, 10, 1); 538 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 539 cksum = 0; 540 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 541 fxp_read_eeprom(sc, &data, i, 1); 542 cksum += data; 543 } 544 i = (1 << sc->eeprom_size) - 1; 545 cksum = 0xBABA - cksum; 546 fxp_read_eeprom(sc, &data, i, 1); 547 fxp_write_eeprom(sc, &cksum, i, 1); 548 device_printf(dev, 549 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 550 i, data, cksum); 551 #if 1 552 /* 553 * If the user elects to continue, try the software 554 * workaround, as it is better than nothing. 555 */ 556 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 557 #endif 558 } 559 } 560 561 /* 562 * If we are not a 82557 chip, we can enable extended features. 563 */ 564 if (sc->revision != FXP_REV_82557) { 565 /* 566 * If MWI is enabled in the PCI configuration, and there 567 * is a valid cacheline size (8 or 16 dwords), then tell 568 * the board to turn on MWI. 569 */ 570 if (val & PCIM_CMD_MWRICEN && 571 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 572 sc->flags |= FXP_FLAG_MWI_ENABLE; 573 574 /* turn on the extended TxCB feature */ 575 sc->flags |= FXP_FLAG_EXT_TXCB; 576 577 /* enable reception of long frames for VLAN */ 578 sc->flags |= FXP_FLAG_LONG_PKT_EN; 579 } else { 580 /* a hack to get long VLAN frames on a 82557 */ 581 sc->flags |= FXP_FLAG_SAVE_BAD; 582 } 583 584 /* 585 * Enable use of extended RFDs and TCBs for 82550 586 * and later chips. Note: we need extended TXCB support 587 * too, but that's already enabled by the code above. 588 * Be careful to do this only on the right devices. 589 */ 590 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C || 591 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F 592 || sc->revision == FXP_REV_82551_10) { 593 sc->rfa_size = sizeof (struct fxp_rfa); 594 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; 595 sc->flags |= FXP_FLAG_EXT_RFA; 596 } else { 597 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; 598 sc->tx_cmd = FXP_CB_COMMAND_XMIT; 599 } 600 601 /* 602 * Allocate DMA tags and DMA safe memory. 603 */ 604 sc->maxtxseg = FXP_NTXSEG; 605 if (sc->flags & FXP_FLAG_EXT_RFA) 606 sc->maxtxseg--; 607 error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, 608 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * sc->maxtxseg, 609 sc->maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, 610 &sc->fxp_mtag); 611 if (error) { 612 device_printf(dev, "could not allocate dma tag\n"); 613 goto fail; 614 } 615 616 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 617 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, 618 sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, 619 &sc->fxp_stag); 620 if (error) { 621 device_printf(dev, "could not allocate dma tag\n"); 622 goto fail; 623 } 624 625 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, 626 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); 627 if (error) 628 goto fail; 629 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, 630 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); 631 if (error) { 632 device_printf(dev, "could not map the stats buffer\n"); 633 goto fail; 634 } 635 636 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 637 BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, 638 FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); 639 if (error) { 640 device_printf(dev, "could not allocate dma tag\n"); 641 goto fail; 642 } 643 644 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, 645 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); 646 if (error) 647 goto fail; 648 649 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, 650 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, 651 &sc->fxp_desc.cbl_addr, 0); 652 if (error) { 653 device_printf(dev, "could not map DMA memory\n"); 654 goto fail; 655 } 656 657 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 658 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, 659 sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, 660 &sc->mcs_tag); 661 if (error) { 662 device_printf(dev, "could not allocate dma tag\n"); 663 goto fail; 664 } 665 666 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, 667 BUS_DMA_NOWAIT, &sc->mcs_map); 668 if (error) 669 goto fail; 670 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, 671 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); 672 if (error) { 673 device_printf(dev, "can't map the multicast setup command\n"); 674 goto fail; 675 } 676 677 /* 678 * Pre-allocate the TX DMA maps and setup the pointers to 679 * the TX command blocks. 680 */ 681 txp = sc->fxp_desc.tx_list; 682 tcbp = sc->fxp_desc.cbl_list; 683 for (i = 0; i < FXP_NTXCB; i++) { 684 txp[i].tx_cb = tcbp + i; 685 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map); 686 if (error) { 687 device_printf(dev, "can't create DMA map for TX\n"); 688 goto fail; 689 } 690 } 691 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); 692 if (error) { 693 device_printf(dev, "can't create spare DMA map\n"); 694 goto fail; 695 } 696 697 /* 698 * Pre-allocate our receive buffers. 699 */ 700 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; 701 for (i = 0; i < FXP_NRFABUFS; i++) { 702 rxp = &sc->fxp_desc.rx_list[i]; 703 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); 704 if (error) { 705 device_printf(dev, "can't create DMA map for RX\n"); 706 goto fail; 707 } 708 if (fxp_add_rfabuf(sc, rxp) != 0) { 709 error = ENOMEM; 710 goto fail; 711 } 712 } 713 714 /* 715 * Read MAC address. 716 */ 717 fxp_read_eeprom(sc, myea, 0, 3); 718 eaddr[0] = myea[0] & 0xff; 719 eaddr[1] = myea[0] >> 8; 720 eaddr[2] = myea[1] & 0xff; 721 eaddr[3] = myea[1] >> 8; 722 eaddr[4] = myea[2] & 0xff; 723 eaddr[5] = myea[2] >> 8; 724 if (bootverbose) { 725 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 726 pci_get_vendor(dev), pci_get_device(dev), 727 pci_get_subvendor(dev), pci_get_subdevice(dev), 728 pci_get_revid(dev)); 729 fxp_read_eeprom(sc, &data, 10, 1); 730 device_printf(dev, "Dynamic Standby mode is %s\n", 731 data & 0x02 ? "enabled" : "disabled"); 732 } 733 734 /* 735 * If this is only a 10Mbps device, then there is no MII, and 736 * the PHY will use a serial interface instead. 737 * 738 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 739 * doesn't have a programming interface of any sort. The 740 * media is sensed automatically based on how the link partner 741 * is configured. This is, in essence, manual configuration. 742 */ 743 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 744 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 745 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 746 } else { 747 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 748 fxp_ifmedia_sts)) { 749 device_printf(dev, "MII without any PHY!\n"); 750 error = ENXIO; 751 goto fail; 752 } 753 } 754 755 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 756 ifp->if_baudrate = 100000000; 757 ifp->if_init = fxp_init; 758 ifp->if_softc = sc; 759 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 760 ifp->if_ioctl = fxp_ioctl; 761 ifp->if_start = fxp_start; 762 ifp->if_watchdog = fxp_watchdog; 763 764 ifp->if_capabilities = ifp->if_capenable = 0; 765 766 /* Enable checksum offload for 82550 or better chips */ 767 if (sc->flags & FXP_FLAG_EXT_RFA) { 768 ifp->if_hwassist = FXP_CSUM_FEATURES; 769 ifp->if_capabilities |= IFCAP_HWCSUM; 770 ifp->if_capenable |= IFCAP_HWCSUM; 771 } 772 773 #ifdef DEVICE_POLLING 774 /* Inform the world we support polling. */ 775 ifp->if_capabilities |= IFCAP_POLLING; 776 ifp->if_capenable |= IFCAP_POLLING; 777 #endif 778 779 /* 780 * Attach the interface. 781 */ 782 ether_ifattach(ifp, eaddr); 783 784 /* 785 * Tell the upper layer(s) we support long frames. 786 * Must appear after the call to ether_ifattach() because 787 * ether_ifattach() sets ifi_hdrlen to the default value. 788 */ 789 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 790 ifp->if_capabilities |= IFCAP_VLAN_MTU; 791 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 792 793 /* 794 * Let the system queue as many packets as we have available 795 * TX descriptors. 796 */ 797 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1); 798 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1; 799 IFQ_SET_READY(&ifp->if_snd); 800 801 /* 802 * Hook our interrupt after all initialization is complete. 803 */ 804 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE, 805 fxp_intr, sc, &sc->ih); 806 if (error) { 807 device_printf(dev, "could not setup irq\n"); 808 ether_ifdetach(sc->ifp); 809 goto fail; 810 } 811 812 fail: 813 if (error) 814 fxp_release(sc); 815 return (error); 816 } 817 818 /* 819 * Release all resources. The softc lock should not be held and the 820 * interrupt should already be torn down. 821 */ 822 static void 823 fxp_release(struct fxp_softc *sc) 824 { 825 struct fxp_rx *rxp; 826 struct fxp_tx *txp; 827 int i; 828 829 FXP_LOCK_ASSERT(sc, MA_NOTOWNED); 830 KASSERT(sc->ih == NULL, 831 ("fxp_release() called with intr handle still active")); 832 if (sc->miibus) 833 device_delete_child(sc->dev, sc->miibus); 834 bus_generic_detach(sc->dev); 835 ifmedia_removeall(&sc->sc_media); 836 if (sc->fxp_desc.cbl_list) { 837 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); 838 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, 839 sc->cbl_map); 840 } 841 if (sc->fxp_stats) { 842 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); 843 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); 844 } 845 if (sc->mcsp) { 846 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); 847 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); 848 } 849 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res); 850 if (sc->fxp_mtag) { 851 for (i = 0; i < FXP_NRFABUFS; i++) { 852 rxp = &sc->fxp_desc.rx_list[i]; 853 if (rxp->rx_mbuf != NULL) { 854 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 857 m_freem(rxp->rx_mbuf); 858 } 859 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 860 } 861 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 862 for (i = 0; i < FXP_NTXCB; i++) { 863 txp = &sc->fxp_desc.tx_list[i]; 864 if (txp->tx_mbuf != NULL) { 865 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 866 BUS_DMASYNC_POSTWRITE); 867 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 868 m_freem(txp->tx_mbuf); 869 } 870 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 871 } 872 bus_dma_tag_destroy(sc->fxp_mtag); 873 } 874 if (sc->fxp_stag) 875 bus_dma_tag_destroy(sc->fxp_stag); 876 if (sc->cbl_tag) 877 bus_dma_tag_destroy(sc->cbl_tag); 878 if (sc->mcs_tag) 879 bus_dma_tag_destroy(sc->mcs_tag); 880 if (sc->ifp) 881 if_free(sc->ifp); 882 883 mtx_destroy(&sc->sc_mtx); 884 } 885 886 /* 887 * Detach interface. 888 */ 889 static int 890 fxp_detach(device_t dev) 891 { 892 struct fxp_softc *sc = device_get_softc(dev); 893 894 FXP_LOCK(sc); 895 sc->suspended = 1; /* Do same thing as we do for suspend */ 896 /* 897 * Stop DMA and drop transmit queue, but disable interrupts first. 898 */ 899 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 900 fxp_stop(sc); 901 FXP_UNLOCK(sc); 902 callout_drain(&sc->stat_ch); 903 904 /* 905 * Close down routes etc. 906 */ 907 ether_ifdetach(sc->ifp); 908 909 /* 910 * Unhook interrupt before dropping lock. This is to prevent 911 * races with fxp_intr(). 912 */ 913 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih); 914 sc->ih = NULL; 915 916 /* Release our allocated resources. */ 917 fxp_release(sc); 918 return (0); 919 } 920 921 /* 922 * Device shutdown routine. Called at system shutdown after sync. The 923 * main purpose of this routine is to shut off receiver DMA so that 924 * kernel memory doesn't get clobbered during warmboot. 925 */ 926 static int 927 fxp_shutdown(device_t dev) 928 { 929 struct fxp_softc *sc = device_get_softc(dev); 930 931 /* 932 * Make sure that DMA is disabled prior to reboot. Not doing 933 * do could allow DMA to corrupt kernel memory during the 934 * reboot before the driver initializes. 935 */ 936 FXP_LOCK(sc); 937 fxp_stop(sc); 938 FXP_UNLOCK(sc); 939 return (0); 940 } 941 942 /* 943 * Device suspend routine. Stop the interface and save some PCI 944 * settings in case the BIOS doesn't restore them properly on 945 * resume. 946 */ 947 static int 948 fxp_suspend(device_t dev) 949 { 950 struct fxp_softc *sc = device_get_softc(dev); 951 952 FXP_LOCK(sc); 953 954 fxp_stop(sc); 955 956 sc->suspended = 1; 957 958 FXP_UNLOCK(sc); 959 return (0); 960 } 961 962 /* 963 * Device resume routine. re-enable busmastering, and restart the interface if 964 * appropriate. 965 */ 966 static int 967 fxp_resume(device_t dev) 968 { 969 struct fxp_softc *sc = device_get_softc(dev); 970 struct ifnet *ifp = sc->ifp; 971 972 FXP_LOCK(sc); 973 974 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 975 DELAY(10); 976 977 /* reinitialize interface if necessary */ 978 if (ifp->if_flags & IFF_UP) 979 fxp_init_body(sc); 980 981 sc->suspended = 0; 982 983 FXP_UNLOCK(sc); 984 return (0); 985 } 986 987 static void 988 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 989 { 990 uint16_t reg; 991 int x; 992 993 /* 994 * Shift in data. 995 */ 996 for (x = 1 << (length - 1); x; x >>= 1) { 997 if (data & x) 998 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 999 else 1000 reg = FXP_EEPROM_EECS; 1001 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1002 DELAY(1); 1003 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1004 DELAY(1); 1005 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1006 DELAY(1); 1007 } 1008 } 1009 1010 /* 1011 * Read from the serial EEPROM. Basically, you manually shift in 1012 * the read opcode (one bit at a time) and then shift in the address, 1013 * and then you shift out the data (all of this one bit at a time). 1014 * The word size is 16 bits, so you have to provide the address for 1015 * every 16 bits of data. 1016 */ 1017 static uint16_t 1018 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 1019 { 1020 uint16_t reg, data; 1021 int x; 1022 1023 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1024 /* 1025 * Shift in read opcode. 1026 */ 1027 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 1028 /* 1029 * Shift in address. 1030 */ 1031 data = 0; 1032 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 1033 if (offset & x) 1034 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1035 else 1036 reg = FXP_EEPROM_EECS; 1037 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1038 DELAY(1); 1039 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1040 DELAY(1); 1041 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1042 DELAY(1); 1043 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 1044 data++; 1045 if (autosize && reg == 0) { 1046 sc->eeprom_size = data; 1047 break; 1048 } 1049 } 1050 /* 1051 * Shift out data. 1052 */ 1053 data = 0; 1054 reg = FXP_EEPROM_EECS; 1055 for (x = 1 << 15; x; x >>= 1) { 1056 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1057 DELAY(1); 1058 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1059 data |= x; 1060 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1061 DELAY(1); 1062 } 1063 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1064 DELAY(1); 1065 1066 return (data); 1067 } 1068 1069 static void 1070 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data) 1071 { 1072 int i; 1073 1074 /* 1075 * Erase/write enable. 1076 */ 1077 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1078 fxp_eeprom_shiftin(sc, 0x4, 3); 1079 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 1080 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1081 DELAY(1); 1082 /* 1083 * Shift in write opcode, address, data. 1084 */ 1085 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1086 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 1087 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 1088 fxp_eeprom_shiftin(sc, data, 16); 1089 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1090 DELAY(1); 1091 /* 1092 * Wait for EEPROM to finish up. 1093 */ 1094 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1095 DELAY(1); 1096 for (i = 0; i < 1000; i++) { 1097 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 1098 break; 1099 DELAY(50); 1100 } 1101 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1102 DELAY(1); 1103 /* 1104 * Erase/write disable. 1105 */ 1106 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 1107 fxp_eeprom_shiftin(sc, 0x4, 3); 1108 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 1109 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 1110 DELAY(1); 1111 } 1112 1113 /* 1114 * From NetBSD: 1115 * 1116 * Figure out EEPROM size. 1117 * 1118 * 559's can have either 64-word or 256-word EEPROMs, the 558 1119 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1120 * talks about the existance of 16 to 256 word EEPROMs. 1121 * 1122 * The only known sizes are 64 and 256, where the 256 version is used 1123 * by CardBus cards to store CIS information. 1124 * 1125 * The address is shifted in msb-to-lsb, and after the last 1126 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1127 * after which follows the actual data. We try to detect this zero, by 1128 * probing the data-out bit in the EEPROM control register just after 1129 * having shifted in a bit. If the bit is zero, we assume we've 1130 * shifted enough address bits. The data-out should be tri-state, 1131 * before this, which should translate to a logical one. 1132 */ 1133 static void 1134 fxp_autosize_eeprom(struct fxp_softc *sc) 1135 { 1136 1137 /* guess maximum size of 256 words */ 1138 sc->eeprom_size = 8; 1139 1140 /* autosize */ 1141 (void) fxp_eeprom_getword(sc, 0, 1); 1142 } 1143 1144 static void 1145 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1146 { 1147 int i; 1148 1149 for (i = 0; i < words; i++) 1150 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1151 } 1152 1153 static void 1154 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1155 { 1156 int i; 1157 1158 for (i = 0; i < words; i++) 1159 fxp_eeprom_putword(sc, offset + i, data[i]); 1160 } 1161 1162 /* 1163 * Grab the softc lock and call the real fxp_start_body() routine 1164 */ 1165 static void 1166 fxp_start(struct ifnet *ifp) 1167 { 1168 struct fxp_softc *sc = ifp->if_softc; 1169 1170 FXP_LOCK(sc); 1171 fxp_start_body(ifp); 1172 FXP_UNLOCK(sc); 1173 } 1174 1175 /* 1176 * Start packet transmission on the interface. 1177 * This routine must be called with the softc lock held, and is an 1178 * internal entry point only. 1179 */ 1180 static void 1181 fxp_start_body(struct ifnet *ifp) 1182 { 1183 struct fxp_softc *sc = ifp->if_softc; 1184 struct mbuf *mb_head; 1185 int error, txqueued; 1186 1187 FXP_LOCK_ASSERT(sc, MA_OWNED); 1188 1189 /* 1190 * See if we need to suspend xmit until the multicast filter 1191 * has been reprogrammed (which can only be done at the head 1192 * of the command chain). 1193 */ 1194 if (sc->need_mcsetup) 1195 return; 1196 1197 /* 1198 * We're finished if there is nothing more to add to the list or if 1199 * we're all filled up with buffers to transmit. 1200 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1201 * a NOP command when needed. 1202 */ 1203 txqueued = 0; 1204 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1205 sc->tx_queued < FXP_NTXCB - 1) { 1206 1207 /* 1208 * Grab a packet to transmit. 1209 */ 1210 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 1211 if (mb_head == NULL) 1212 break; 1213 1214 error = fxp_encap(sc, mb_head); 1215 if (error) 1216 break; 1217 txqueued = 1; 1218 } 1219 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1220 1221 /* 1222 * We're finished. If we added to the list, issue a RESUME to get DMA 1223 * going again if suspended. 1224 */ 1225 if (txqueued) { 1226 fxp_scb_wait(sc); 1227 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1228 } 1229 } 1230 1231 static int 1232 fxp_encap(struct fxp_softc *sc, struct mbuf *m_head) 1233 { 1234 struct ifnet *ifp; 1235 struct mbuf *m; 1236 struct fxp_tx *txp; 1237 struct fxp_cb_tx *cbp; 1238 bus_dma_segment_t segs[FXP_NTXSEG]; 1239 int chainlen, error, i, nseg; 1240 1241 FXP_LOCK_ASSERT(sc, MA_OWNED); 1242 ifp = sc->ifp; 1243 1244 /* 1245 * Get pointer to next available tx desc. 1246 */ 1247 txp = sc->fxp_desc.tx_last->tx_next; 1248 1249 /* 1250 * A note in Appendix B of the Intel 8255x 10/100 Mbps 1251 * Ethernet Controller Family Open Source Software 1252 * Developer Manual says: 1253 * Using software parsing is only allowed with legal 1254 * TCP/IP or UDP/IP packets. 1255 * ... 1256 * For all other datagrams, hardware parsing must 1257 * be used. 1258 * Software parsing appears to truncate ICMP and 1259 * fragmented UDP packets that contain one to three 1260 * bytes in the second (and final) mbuf of the packet. 1261 */ 1262 if (sc->flags & FXP_FLAG_EXT_RFA) 1263 txp->tx_cb->ipcb_ip_activation_high = 1264 FXP_IPCB_HARDWAREPARSING_ENABLE; 1265 1266 /* 1267 * Deal with TCP/IP checksum offload. Note that 1268 * in order for TCP checksum offload to work, 1269 * the pseudo header checksum must have already 1270 * been computed and stored in the checksum field 1271 * in the TCP header. The stack should have 1272 * already done this for us. 1273 */ 1274 if (m_head->m_pkthdr.csum_flags) { 1275 if (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { 1276 txp->tx_cb->ipcb_ip_schedule = 1277 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1278 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1279 txp->tx_cb->ipcb_ip_schedule |= 1280 FXP_IPCB_TCP_PACKET; 1281 } 1282 1283 #ifdef FXP_IP_CSUM_WAR 1284 /* 1285 * XXX The 82550 chip appears to have trouble 1286 * dealing with IP header checksums in very small 1287 * datagrams, namely fragments from 1 to 3 bytes 1288 * in size. For example, say you want to transmit 1289 * a UDP packet of 1473 bytes. The packet will be 1290 * fragmented over two IP datagrams, the latter 1291 * containing only one byte of data. The 82550 will 1292 * botch the header checksum on the 1-byte fragment. 1293 * As long as the datagram contains 4 or more bytes 1294 * of data, you're ok. 1295 * 1296 * The following code attempts to work around this 1297 * problem: if the datagram is less than 38 bytes 1298 * in size (14 bytes ether header, 20 bytes IP header, 1299 * plus 4 bytes of data), we punt and compute the IP 1300 * header checksum by hand. This workaround doesn't 1301 * work very well, however, since it can be fooled 1302 * by things like VLAN tags and IP options that make 1303 * the header sizes/offsets vary. 1304 */ 1305 1306 if (m_head->m_pkthdr.csum_flags & CSUM_IP) { 1307 if (m_head->m_pkthdr.len < 38) { 1308 struct ip *ip; 1309 m_head->m_data += ETHER_HDR_LEN; 1310 ip = mtod(mb_head, struct ip *); 1311 ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); 1312 m_head->m_data -= ETHER_HDR_LEN; 1313 } else { 1314 txp->tx_cb->ipcb_ip_activation_high = 1315 FXP_IPCB_HARDWAREPARSING_ENABLE; 1316 txp->tx_cb->ipcb_ip_schedule |= 1317 FXP_IPCB_IP_CHECKSUM_ENABLE; 1318 } 1319 } 1320 #endif 1321 } 1322 1323 chainlen = 0; 1324 for (m = m_head; m != NULL && chainlen <= sc->maxtxseg; m = m->m_next) 1325 chainlen++; 1326 if (chainlen > sc->maxtxseg) { 1327 struct mbuf *mn; 1328 1329 /* 1330 * We ran out of segments. We have to recopy this 1331 * mbuf chain first. Bail out if we can't get the 1332 * new buffers. 1333 */ 1334 mn = m_defrag(m_head, M_DONTWAIT); 1335 if (mn == NULL) { 1336 m_freem(m_head); 1337 return (-1); 1338 } else { 1339 m_head = mn; 1340 } 1341 } 1342 1343 /* 1344 * Go through each of the mbufs in the chain and initialize 1345 * the transmit buffer descriptors with the physical address 1346 * and size of the mbuf. 1347 */ 1348 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, 1349 m_head, segs, &nseg, 0); 1350 if (error) { 1351 device_printf(sc->dev, "can't map mbuf (error %d)\n", error); 1352 m_freem(m_head); 1353 return (-1); 1354 } 1355 1356 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments")); 1357 1358 cbp = txp->tx_cb; 1359 for (i = 0; i < nseg; i++) { 1360 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 1361 /* 1362 * If this is an 82550/82551, then we're using extended 1363 * TxCBs _and_ we're using checksum offload. This means 1364 * that the TxCB is really an IPCB. One major difference 1365 * between the two is that with plain extended TxCBs, 1366 * the bottom half of the TxCB contains two entries from 1367 * the TBD array, whereas IPCBs contain just one entry: 1368 * one entry (8 bytes) has been sacrificed for the TCP/IP 1369 * checksum offload control bits. So to make things work 1370 * right, we have to start filling in the TBD array 1371 * starting from a different place depending on whether 1372 * the chip is an 82550/82551 or not. 1373 */ 1374 if (sc->flags & FXP_FLAG_EXT_RFA) { 1375 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); 1376 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); 1377 } else { 1378 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr); 1379 cbp->tbd[i].tb_size = htole32(segs[i].ds_len); 1380 } 1381 } 1382 cbp->tbd_number = nseg; 1383 1384 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); 1385 txp->tx_mbuf = m_head; 1386 txp->tx_cb->cb_status = 0; 1387 txp->tx_cb->byte_count = 0; 1388 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1389 txp->tx_cb->cb_command = 1390 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1391 FXP_CB_COMMAND_S); 1392 } else { 1393 txp->tx_cb->cb_command = 1394 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | 1395 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 1396 /* 1397 * Set a 5 second timer just in case we don't hear 1398 * from the card again. 1399 */ 1400 ifp->if_timer = 5; 1401 } 1402 txp->tx_cb->tx_threshold = tx_threshold; 1403 1404 /* 1405 * Advance the end of list forward. 1406 */ 1407 1408 #ifdef __alpha__ 1409 /* 1410 * On platforms which can't access memory in 16-bit 1411 * granularities, we must prevent the card from DMA'ing 1412 * up the status while we update the command field. 1413 * This could cause us to overwrite the completion status. 1414 * XXX This is probably bogus and we're _not_ looking 1415 * for atomicity here. 1416 */ 1417 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, 1418 htole16(FXP_CB_COMMAND_S)); 1419 #else 1420 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); 1421 #endif /*__alpha__*/ 1422 sc->fxp_desc.tx_last = txp; 1423 1424 /* 1425 * Advance the beginning of the list forward if there are 1426 * no other packets queued (when nothing is queued, tx_first 1427 * sits on the last TxCB that was sent out). 1428 */ 1429 if (sc->tx_queued == 0) 1430 sc->fxp_desc.tx_first = txp; 1431 1432 sc->tx_queued++; 1433 1434 /* 1435 * Pass packet to bpf if there is a listener. 1436 */ 1437 BPF_MTAP(ifp, m_head); 1438 return (0); 1439 } 1440 1441 #ifdef DEVICE_POLLING 1442 static poll_handler_t fxp_poll; 1443 1444 static void 1445 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1446 { 1447 struct fxp_softc *sc = ifp->if_softc; 1448 uint8_t statack; 1449 1450 FXP_LOCK(sc); 1451 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1452 ether_poll_deregister(ifp); 1453 cmd = POLL_DEREGISTER; 1454 } 1455 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1456 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1457 FXP_UNLOCK(sc); 1458 return; 1459 } 1460 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1461 FXP_SCB_STATACK_FR; 1462 if (cmd == POLL_AND_CHECK_STATUS) { 1463 uint8_t tmp; 1464 1465 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1466 if (tmp == 0xff || tmp == 0) { 1467 FXP_UNLOCK(sc); 1468 return; /* nothing to do */ 1469 } 1470 tmp &= ~statack; 1471 /* ack what we can */ 1472 if (tmp != 0) 1473 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1474 statack |= tmp; 1475 } 1476 fxp_intr_body(sc, ifp, statack, count); 1477 FXP_UNLOCK(sc); 1478 } 1479 #endif /* DEVICE_POLLING */ 1480 1481 /* 1482 * Process interface interrupts. 1483 */ 1484 static void 1485 fxp_intr(void *xsc) 1486 { 1487 struct fxp_softc *sc = xsc; 1488 struct ifnet *ifp = sc->ifp; 1489 uint8_t statack; 1490 1491 FXP_LOCK(sc); 1492 if (sc->suspended) { 1493 FXP_UNLOCK(sc); 1494 return; 1495 } 1496 1497 #ifdef DEVICE_POLLING 1498 if (ifp->if_flags & IFF_POLLING) { 1499 FXP_UNLOCK(sc); 1500 return; 1501 } 1502 if ((ifp->if_capenable & IFCAP_POLLING) && 1503 ether_poll_register(fxp_poll, ifp)) { 1504 /* disable interrupts */ 1505 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1506 FXP_UNLOCK(sc); 1507 fxp_poll(ifp, 0, 1); 1508 return; 1509 } 1510 #endif 1511 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1512 /* 1513 * It should not be possible to have all bits set; the 1514 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1515 * all bits are set, this may indicate that the card has 1516 * been physically ejected, so ignore it. 1517 */ 1518 if (statack == 0xff) { 1519 FXP_UNLOCK(sc); 1520 return; 1521 } 1522 1523 /* 1524 * First ACK all the interrupts in this pass. 1525 */ 1526 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1527 fxp_intr_body(sc, ifp, statack, -1); 1528 } 1529 FXP_UNLOCK(sc); 1530 } 1531 1532 static void 1533 fxp_txeof(struct fxp_softc *sc) 1534 { 1535 struct fxp_tx *txp; 1536 1537 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); 1538 for (txp = sc->fxp_desc.tx_first; sc->tx_queued && 1539 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; 1540 txp = txp->tx_next) { 1541 if (txp->tx_mbuf != NULL) { 1542 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 1543 BUS_DMASYNC_POSTWRITE); 1544 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 1545 m_freem(txp->tx_mbuf); 1546 txp->tx_mbuf = NULL; 1547 /* clear this to reset csum offload bits */ 1548 txp->tx_cb->tbd[0].tb_addr = 0; 1549 } 1550 sc->tx_queued--; 1551 } 1552 sc->fxp_desc.tx_first = txp; 1553 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1554 } 1555 1556 static void 1557 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack, 1558 int count) 1559 { 1560 struct mbuf *m; 1561 struct fxp_rx *rxp; 1562 struct fxp_rfa *rfa; 1563 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1564 int fxp_rc = 0; 1565 1566 FXP_LOCK_ASSERT(sc, MA_OWNED); 1567 if (rnr) 1568 sc->rnr++; 1569 #ifdef DEVICE_POLLING 1570 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1571 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1572 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1573 rnr = 1; 1574 } 1575 #endif 1576 1577 /* 1578 * Free any finished transmit mbuf chains. 1579 * 1580 * Handle the CNA event likt a CXTNO event. It used to 1581 * be that this event (control unit not ready) was not 1582 * encountered, but it is now with the SMPng modifications. 1583 * The exact sequence of events that occur when the interface 1584 * is brought up are different now, and if this event 1585 * goes unhandled, the configuration/rxfilter setup sequence 1586 * can stall for several seconds. The result is that no 1587 * packets go out onto the wire for about 5 to 10 seconds 1588 * after the interface is ifconfig'ed for the first time. 1589 */ 1590 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1591 fxp_txeof(sc); 1592 1593 ifp->if_timer = 0; 1594 if (sc->tx_queued == 0) { 1595 if (sc->need_mcsetup) 1596 fxp_mc_setup(sc); 1597 } 1598 /* 1599 * Try to start more packets transmitting. 1600 */ 1601 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1602 fxp_start_body(ifp); 1603 } 1604 1605 /* 1606 * Just return if nothing happened on the receive side. 1607 */ 1608 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1609 return; 1610 1611 /* 1612 * Process receiver interrupts. If a no-resource (RNR) 1613 * condition exists, get whatever packets we can and 1614 * re-start the receiver. 1615 * 1616 * When using polling, we do not process the list to completion, 1617 * so when we get an RNR interrupt we must defer the restart 1618 * until we hit the last buffer with the C bit set. 1619 * If we run out of cycles and rfa_headm has the C bit set, 1620 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1621 * that the info will be used in the subsequent polling cycle. 1622 */ 1623 for (;;) { 1624 rxp = sc->fxp_desc.rx_head; 1625 m = rxp->rx_mbuf; 1626 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1627 RFA_ALIGNMENT_FUDGE); 1628 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 1629 BUS_DMASYNC_POSTREAD); 1630 1631 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1632 if (count >= 0 && count-- == 0) { 1633 if (rnr) { 1634 /* Defer RNR processing until the next time. */ 1635 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1636 rnr = 0; 1637 } 1638 break; 1639 } 1640 #endif /* DEVICE_POLLING */ 1641 1642 if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) 1643 break; 1644 1645 /* 1646 * Advance head forward. 1647 */ 1648 sc->fxp_desc.rx_head = rxp->rx_next; 1649 1650 /* 1651 * Add a new buffer to the receive chain. 1652 * If this fails, the old buffer is recycled 1653 * instead. 1654 */ 1655 fxp_rc = fxp_add_rfabuf(sc, rxp); 1656 if (fxp_rc == 0) { 1657 int total_len; 1658 1659 /* 1660 * Fetch packet length (the top 2 bits of 1661 * actual_size are flags set by the controller 1662 * upon completion), and drop the packet in case 1663 * of bogus length or CRC errors. 1664 */ 1665 total_len = le16toh(rfa->actual_size) & 0x3fff; 1666 if (total_len < sizeof(struct ether_header) || 1667 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1668 sc->rfa_size || 1669 le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { 1670 m_freem(m); 1671 continue; 1672 } 1673 1674 /* Do IP checksum checking. */ 1675 if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { 1676 if (rfa->rfax_csum_sts & 1677 FXP_RFDX_CS_IP_CSUM_BIT_VALID) 1678 m->m_pkthdr.csum_flags |= 1679 CSUM_IP_CHECKED; 1680 if (rfa->rfax_csum_sts & 1681 FXP_RFDX_CS_IP_CSUM_VALID) 1682 m->m_pkthdr.csum_flags |= 1683 CSUM_IP_VALID; 1684 if ((rfa->rfax_csum_sts & 1685 FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && 1686 (rfa->rfax_csum_sts & 1687 FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { 1688 m->m_pkthdr.csum_flags |= 1689 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1690 m->m_pkthdr.csum_data = 0xffff; 1691 } 1692 } 1693 1694 m->m_pkthdr.len = m->m_len = total_len; 1695 m->m_pkthdr.rcvif = ifp; 1696 1697 /* 1698 * Drop locks before calling if_input() since it 1699 * may re-enter fxp_start() in the netisr case. 1700 * This would result in a lock reversal. Better 1701 * performance might be obtained by chaining all 1702 * packets received, dropping the lock, and then 1703 * calling if_input() on each one. 1704 */ 1705 FXP_UNLOCK(sc); 1706 (*ifp->if_input)(ifp, m); 1707 FXP_LOCK(sc); 1708 } else if (fxp_rc == ENOBUFS) { 1709 rnr = 0; 1710 break; 1711 } 1712 } 1713 if (rnr) { 1714 fxp_scb_wait(sc); 1715 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1716 sc->fxp_desc.rx_head->rx_addr); 1717 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1718 } 1719 } 1720 1721 /* 1722 * Update packet in/out/collision statistics. The i82557 doesn't 1723 * allow you to access these counters without doing a fairly 1724 * expensive DMA to get _all_ of the statistics it maintains, so 1725 * we do this operation here only once per second. The statistics 1726 * counters in the kernel are updated from the previous dump-stats 1727 * DMA and then a new dump-stats DMA is started. The on-chip 1728 * counters are zeroed when the DMA completes. If we can't start 1729 * the DMA immediately, we don't wait - we just prepare to read 1730 * them again next time. 1731 */ 1732 static void 1733 fxp_tick(void *xsc) 1734 { 1735 struct fxp_softc *sc = xsc; 1736 struct ifnet *ifp = sc->ifp; 1737 struct fxp_stats *sp = sc->fxp_stats; 1738 1739 FXP_LOCK_ASSERT(sc, MA_OWNED); 1740 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); 1741 ifp->if_opackets += le32toh(sp->tx_good); 1742 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1743 if (sp->rx_good) { 1744 ifp->if_ipackets += le32toh(sp->rx_good); 1745 sc->rx_idle_secs = 0; 1746 } else { 1747 /* 1748 * Receiver's been idle for another second. 1749 */ 1750 sc->rx_idle_secs++; 1751 } 1752 ifp->if_ierrors += 1753 le32toh(sp->rx_crc_errors) + 1754 le32toh(sp->rx_alignment_errors) + 1755 le32toh(sp->rx_rnr_errors) + 1756 le32toh(sp->rx_overrun_errors); 1757 /* 1758 * If any transmit underruns occured, bump up the transmit 1759 * threshold by another 512 bytes (64 * 8). 1760 */ 1761 if (sp->tx_underruns) { 1762 ifp->if_oerrors += le32toh(sp->tx_underruns); 1763 if (tx_threshold < 192) 1764 tx_threshold += 64; 1765 } 1766 1767 /* 1768 * Release any xmit buffers that have completed DMA. This isn't 1769 * strictly necessary to do here, but it's advantagous for mbufs 1770 * with external storage to be released in a timely manner rather 1771 * than being defered for a potentially long time. This limits 1772 * the delay to a maximum of one second. 1773 */ 1774 fxp_txeof(sc); 1775 1776 /* 1777 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1778 * then assume the receiver has locked up and attempt to clear 1779 * the condition by reprogramming the multicast filter. This is 1780 * a work-around for a bug in the 82557 where the receiver locks 1781 * up if it gets certain types of garbage in the syncronization 1782 * bits prior to the packet header. This bug is supposed to only 1783 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1784 * mode as well (perhaps due to a 10/100 speed transition). 1785 */ 1786 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1787 sc->rx_idle_secs = 0; 1788 fxp_mc_setup(sc); 1789 } 1790 /* 1791 * If there is no pending command, start another stats 1792 * dump. Otherwise punt for now. 1793 */ 1794 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1795 /* 1796 * Start another stats dump. 1797 */ 1798 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, 1799 BUS_DMASYNC_PREREAD); 1800 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1801 } else { 1802 /* 1803 * A previous command is still waiting to be accepted. 1804 * Just zero our copy of the stats and wait for the 1805 * next timer event to update them. 1806 */ 1807 sp->tx_good = 0; 1808 sp->tx_underruns = 0; 1809 sp->tx_total_collisions = 0; 1810 1811 sp->rx_good = 0; 1812 sp->rx_crc_errors = 0; 1813 sp->rx_alignment_errors = 0; 1814 sp->rx_rnr_errors = 0; 1815 sp->rx_overrun_errors = 0; 1816 } 1817 if (sc->miibus != NULL) 1818 mii_tick(device_get_softc(sc->miibus)); 1819 1820 /* 1821 * Schedule another timeout one second from now. 1822 */ 1823 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 1824 } 1825 1826 /* 1827 * Stop the interface. Cancels the statistics updater and resets 1828 * the interface. 1829 */ 1830 static void 1831 fxp_stop(struct fxp_softc *sc) 1832 { 1833 struct ifnet *ifp = sc->ifp; 1834 struct fxp_tx *txp; 1835 int i; 1836 1837 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1838 ifp->if_timer = 0; 1839 1840 #ifdef DEVICE_POLLING 1841 ether_poll_deregister(ifp); 1842 #endif 1843 /* 1844 * Cancel stats updater. 1845 */ 1846 callout_stop(&sc->stat_ch); 1847 1848 /* 1849 * Issue software reset, which also unloads the microcode. 1850 */ 1851 sc->flags &= ~FXP_FLAG_UCODE; 1852 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1853 DELAY(50); 1854 1855 /* 1856 * Release any xmit buffers. 1857 */ 1858 txp = sc->fxp_desc.tx_list; 1859 if (txp != NULL) { 1860 for (i = 0; i < FXP_NTXCB; i++) { 1861 if (txp[i].tx_mbuf != NULL) { 1862 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, 1863 BUS_DMASYNC_POSTWRITE); 1864 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); 1865 m_freem(txp[i].tx_mbuf); 1866 txp[i].tx_mbuf = NULL; 1867 /* clear this to reset csum offload bits */ 1868 txp[i].tx_cb->tbd[0].tb_addr = 0; 1869 } 1870 } 1871 } 1872 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 1873 sc->tx_queued = 0; 1874 } 1875 1876 /* 1877 * Watchdog/transmission transmit timeout handler. Called when a 1878 * transmission is started on the interface, but no interrupt is 1879 * received before the timeout. This usually indicates that the 1880 * card has wedged for some reason. 1881 */ 1882 static void 1883 fxp_watchdog(struct ifnet *ifp) 1884 { 1885 struct fxp_softc *sc = ifp->if_softc; 1886 1887 FXP_LOCK(sc); 1888 device_printf(sc->dev, "device timeout\n"); 1889 ifp->if_oerrors++; 1890 1891 fxp_init_body(sc); 1892 FXP_UNLOCK(sc); 1893 } 1894 1895 /* 1896 * Acquire locks and then call the real initialization function. This 1897 * is necessary because ether_ioctl() calls if_init() and this would 1898 * result in mutex recursion if the mutex was held. 1899 */ 1900 static void 1901 fxp_init(void *xsc) 1902 { 1903 struct fxp_softc *sc = xsc; 1904 1905 FXP_LOCK(sc); 1906 fxp_init_body(sc); 1907 FXP_UNLOCK(sc); 1908 } 1909 1910 /* 1911 * Perform device initialization. This routine must be called with the 1912 * softc lock held. 1913 */ 1914 static void 1915 fxp_init_body(struct fxp_softc *sc) 1916 { 1917 struct ifnet *ifp = sc->ifp; 1918 struct fxp_cb_config *cbp; 1919 struct fxp_cb_ias *cb_ias; 1920 struct fxp_cb_tx *tcbp; 1921 struct fxp_tx *txp; 1922 struct fxp_cb_mcs *mcsp; 1923 int i, prm; 1924 1925 FXP_LOCK_ASSERT(sc, MA_OWNED); 1926 /* 1927 * Cancel any pending I/O 1928 */ 1929 fxp_stop(sc); 1930 1931 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1932 1933 /* 1934 * Initialize base of CBL and RFA memory. Loading with zero 1935 * sets it up for regular linear addressing. 1936 */ 1937 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1938 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1939 1940 fxp_scb_wait(sc); 1941 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1942 1943 /* 1944 * Initialize base of dump-stats buffer. 1945 */ 1946 fxp_scb_wait(sc); 1947 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); 1948 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); 1949 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1950 1951 /* 1952 * Attempt to load microcode if requested. 1953 */ 1954 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1955 fxp_load_ucode(sc); 1956 1957 /* 1958 * Initialize the multicast address list. 1959 */ 1960 if (fxp_mc_addrs(sc)) { 1961 mcsp = sc->mcsp; 1962 mcsp->cb_status = 0; 1963 mcsp->cb_command = 1964 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1965 mcsp->link_addr = 0xffffffff; 1966 /* 1967 * Start the multicast setup command. 1968 */ 1969 fxp_scb_wait(sc); 1970 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 1971 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 1972 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1973 /* ...and wait for it to complete. */ 1974 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); 1975 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, 1976 BUS_DMASYNC_POSTWRITE); 1977 } 1978 1979 /* 1980 * We temporarily use memory that contains the TxCB list to 1981 * construct the config CB. The TxCB list memory is rebuilt 1982 * later. 1983 */ 1984 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; 1985 1986 /* 1987 * This bcopy is kind of disgusting, but there are a bunch of must be 1988 * zero and must be one bits in this structure and this is the easiest 1989 * way to initialize them all to proper values. 1990 */ 1991 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); 1992 1993 cbp->cb_status = 0; 1994 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1995 FXP_CB_COMMAND_EL); 1996 cbp->link_addr = 0xffffffff; /* (no) next command */ 1997 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; 1998 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1999 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 2000 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 2001 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 2002 cbp->type_enable = 0; /* actually reserved */ 2003 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 2004 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 2005 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 2006 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 2007 cbp->dma_mbce = 0; /* (disable) dma max counters */ 2008 cbp->late_scb = 0; /* (don't) defer SCB update */ 2009 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 2010 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 2011 cbp->ci_int = 1; /* interrupt on CU idle */ 2012 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 2013 cbp->ext_stats_dis = 1; /* disable extended counters */ 2014 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 2015 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm; 2016 cbp->disc_short_rx = !prm; /* discard short packets */ 2017 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 2018 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 2019 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 2020 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2021 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 2022 cbp->csma_dis = 0; /* (don't) disable link */ 2023 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 2024 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 2025 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 2026 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 2027 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 2028 cbp->nsai = 1; /* (don't) disable source addr insert */ 2029 cbp->preamble_length = 2; /* (7 byte) preamble */ 2030 cbp->loopback = 0; /* (don't) loopback */ 2031 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 2032 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 2033 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 2034 cbp->promiscuous = prm; /* promiscuous mode */ 2035 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 2036 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 2037 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 2038 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 2039 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 2040 2041 cbp->stripping = !prm; /* truncate rx packet to byte count */ 2042 cbp->padding = 1; /* (do) pad short tx packets */ 2043 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 2044 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 2045 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 2046 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 2047 /* must set wake_en in PMCSR also */ 2048 cbp->force_fdx = 0; /* (don't) force full duplex */ 2049 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 2050 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 2051 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 2052 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; 2053 2054 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) { 2055 /* 2056 * The 82557 has no hardware flow control, the values 2057 * below are the defaults for the chip. 2058 */ 2059 cbp->fc_delay_lsb = 0; 2060 cbp->fc_delay_msb = 0x40; 2061 cbp->pri_fc_thresh = 3; 2062 cbp->tx_fc_dis = 0; 2063 cbp->rx_fc_restop = 0; 2064 cbp->rx_fc_restart = 0; 2065 cbp->fc_filter = 0; 2066 cbp->pri_fc_loc = 1; 2067 } else { 2068 cbp->fc_delay_lsb = 0x1f; 2069 cbp->fc_delay_msb = 0x01; 2070 cbp->pri_fc_thresh = 3; 2071 cbp->tx_fc_dis = 0; /* enable transmit FC */ 2072 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 2073 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 2074 cbp->fc_filter = !prm; /* drop FC frames to host */ 2075 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 2076 } 2077 2078 /* 2079 * Start the config command/DMA. 2080 */ 2081 fxp_scb_wait(sc); 2082 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2083 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2084 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2085 /* ...and wait for it to complete. */ 2086 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2087 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2088 2089 /* 2090 * Now initialize the station address. Temporarily use the TxCB 2091 * memory area like we did above for the config CB. 2092 */ 2093 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; 2094 cb_ias->cb_status = 0; 2095 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 2096 cb_ias->link_addr = 0xffffffff; 2097 bcopy(IFP2ENADDR(sc->ifp), cb_ias->macaddr, 2098 sizeof(IFP2ENADDR(sc->ifp))); 2099 2100 /* 2101 * Start the IAS (Individual Address Setup) command/DMA. 2102 */ 2103 fxp_scb_wait(sc); 2104 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2105 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2106 /* ...and wait for it to complete. */ 2107 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); 2108 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2109 2110 /* 2111 * Initialize transmit control block (TxCB) list. 2112 */ 2113 txp = sc->fxp_desc.tx_list; 2114 tcbp = sc->fxp_desc.cbl_list; 2115 bzero(tcbp, FXP_TXCB_SZ); 2116 for (i = 0; i < FXP_NTXCB; i++) { 2117 txp[i].tx_mbuf = NULL; 2118 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); 2119 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); 2120 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + 2121 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); 2122 if (sc->flags & FXP_FLAG_EXT_TXCB) 2123 tcbp[i].tbd_array_addr = 2124 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); 2125 else 2126 tcbp[i].tbd_array_addr = 2127 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); 2128 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; 2129 } 2130 /* 2131 * Set the suspend flag on the first TxCB and start the control 2132 * unit. It will execute the NOP and then suspend. 2133 */ 2134 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 2135 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2136 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2137 sc->tx_queued = 1; 2138 2139 fxp_scb_wait(sc); 2140 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2141 2142 /* 2143 * Initialize receiver buffer area - RFA. 2144 */ 2145 fxp_scb_wait(sc); 2146 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); 2147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2148 2149 /* 2150 * Set current media. 2151 */ 2152 if (sc->miibus != NULL) 2153 mii_mediachg(device_get_softc(sc->miibus)); 2154 2155 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2156 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2157 2158 /* 2159 * Enable interrupts. 2160 */ 2161 #ifdef DEVICE_POLLING 2162 /* 2163 * ... but only do that if we are not polling. And because (presumably) 2164 * the default is interrupts on, we need to disable them explicitly! 2165 */ 2166 if ( ifp->if_flags & IFF_POLLING ) 2167 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 2168 else 2169 #endif /* DEVICE_POLLING */ 2170 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 2171 2172 /* 2173 * Start stats updater. 2174 */ 2175 callout_reset(&sc->stat_ch, hz, fxp_tick, sc); 2176 } 2177 2178 static int 2179 fxp_serial_ifmedia_upd(struct ifnet *ifp) 2180 { 2181 2182 return (0); 2183 } 2184 2185 static void 2186 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2187 { 2188 2189 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 2190 } 2191 2192 /* 2193 * Change media according to request. 2194 */ 2195 static int 2196 fxp_ifmedia_upd(struct ifnet *ifp) 2197 { 2198 struct fxp_softc *sc = ifp->if_softc; 2199 struct mii_data *mii; 2200 2201 mii = device_get_softc(sc->miibus); 2202 FXP_LOCK(sc); 2203 mii_mediachg(mii); 2204 FXP_UNLOCK(sc); 2205 return (0); 2206 } 2207 2208 /* 2209 * Notify the world which media we're using. 2210 */ 2211 static void 2212 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2213 { 2214 struct fxp_softc *sc = ifp->if_softc; 2215 struct mii_data *mii; 2216 2217 mii = device_get_softc(sc->miibus); 2218 FXP_LOCK(sc); 2219 mii_pollstat(mii); 2220 ifmr->ifm_active = mii->mii_media_active; 2221 ifmr->ifm_status = mii->mii_media_status; 2222 2223 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 2224 sc->cu_resume_bug = 1; 2225 else 2226 sc->cu_resume_bug = 0; 2227 FXP_UNLOCK(sc); 2228 } 2229 2230 /* 2231 * Add a buffer to the end of the RFA buffer list. 2232 * Return 0 if successful, 1 for failure. A failure results in 2233 * adding the 'oldm' (if non-NULL) on to the end of the list - 2234 * tossing out its old contents and recycling it. 2235 * The RFA struct is stuck at the beginning of mbuf cluster and the 2236 * data pointer is fixed up to point just past it. 2237 */ 2238 static int 2239 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) 2240 { 2241 struct mbuf *m; 2242 struct fxp_rfa *rfa, *p_rfa; 2243 struct fxp_rx *p_rx; 2244 bus_dmamap_t tmp_map; 2245 int error; 2246 2247 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2248 if (m == NULL) 2249 return (ENOBUFS); 2250 2251 /* 2252 * Move the data pointer up so that the incoming data packet 2253 * will be 32-bit aligned. 2254 */ 2255 m->m_data += RFA_ALIGNMENT_FUDGE; 2256 2257 /* 2258 * Get a pointer to the base of the mbuf cluster and move 2259 * data start past it. 2260 */ 2261 rfa = mtod(m, struct fxp_rfa *); 2262 m->m_data += sc->rfa_size; 2263 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); 2264 2265 rfa->rfa_status = 0; 2266 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); 2267 rfa->actual_size = 0; 2268 2269 /* 2270 * Initialize the rest of the RFA. Note that since the RFA 2271 * is misaligned, we cannot store values directly. We're thus 2272 * using the le32enc() function which handles endianness and 2273 * is also alignment-safe. 2274 */ 2275 le32enc(&rfa->link_addr, 0xffffffff); 2276 le32enc(&rfa->rbd_addr, 0xffffffff); 2277 2278 /* Map the RFA into DMA memory. */ 2279 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, 2280 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, 2281 &rxp->rx_addr, 0); 2282 if (error) { 2283 m_freem(m); 2284 return (error); 2285 } 2286 2287 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 2288 tmp_map = sc->spare_map; 2289 sc->spare_map = rxp->rx_map; 2290 rxp->rx_map = tmp_map; 2291 rxp->rx_mbuf = m; 2292 2293 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 2294 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2295 2296 /* 2297 * If there are other buffers already on the list, attach this 2298 * one to the end by fixing up the tail to point to this one. 2299 */ 2300 if (sc->fxp_desc.rx_head != NULL) { 2301 p_rx = sc->fxp_desc.rx_tail; 2302 p_rfa = (struct fxp_rfa *) 2303 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); 2304 p_rx->rx_next = rxp; 2305 le32enc(&p_rfa->link_addr, rxp->rx_addr); 2306 p_rfa->rfa_control = 0; 2307 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, 2308 BUS_DMASYNC_PREWRITE); 2309 } else { 2310 rxp->rx_next = NULL; 2311 sc->fxp_desc.rx_head = rxp; 2312 } 2313 sc->fxp_desc.rx_tail = rxp; 2314 return (0); 2315 } 2316 2317 static volatile int 2318 fxp_miibus_readreg(device_t dev, int phy, int reg) 2319 { 2320 struct fxp_softc *sc = device_get_softc(dev); 2321 int count = 10000; 2322 int value; 2323 2324 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2325 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2326 2327 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2328 && count--) 2329 DELAY(10); 2330 2331 if (count <= 0) 2332 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2333 2334 return (value & 0xffff); 2335 } 2336 2337 static void 2338 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2339 { 2340 struct fxp_softc *sc = device_get_softc(dev); 2341 int count = 10000; 2342 2343 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2344 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2345 (value & 0xffff)); 2346 2347 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2348 count--) 2349 DELAY(10); 2350 2351 if (count <= 0) 2352 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2353 } 2354 2355 static int 2356 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2357 { 2358 struct fxp_softc *sc = ifp->if_softc; 2359 struct ifreq *ifr = (struct ifreq *)data; 2360 struct mii_data *mii; 2361 int flag, mask, error = 0; 2362 2363 switch (command) { 2364 case SIOCSIFFLAGS: 2365 FXP_LOCK(sc); 2366 if (ifp->if_flags & IFF_ALLMULTI) 2367 sc->flags |= FXP_FLAG_ALL_MCAST; 2368 else 2369 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2370 2371 /* 2372 * If interface is marked up and not running, then start it. 2373 * If it is marked down and running, stop it. 2374 * XXX If it's up then re-initialize it. This is so flags 2375 * such as IFF_PROMISC are handled. 2376 */ 2377 if (ifp->if_flags & IFF_UP) { 2378 fxp_init_body(sc); 2379 } else { 2380 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2381 fxp_stop(sc); 2382 } 2383 FXP_UNLOCK(sc); 2384 break; 2385 2386 case SIOCADDMULTI: 2387 case SIOCDELMULTI: 2388 FXP_LOCK(sc); 2389 if (ifp->if_flags & IFF_ALLMULTI) 2390 sc->flags |= FXP_FLAG_ALL_MCAST; 2391 else 2392 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2393 /* 2394 * Multicast list has changed; set the hardware filter 2395 * accordingly. 2396 */ 2397 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2398 fxp_mc_setup(sc); 2399 /* 2400 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2401 * again rather than else {}. 2402 */ 2403 if (sc->flags & FXP_FLAG_ALL_MCAST) 2404 fxp_init_body(sc); 2405 FXP_UNLOCK(sc); 2406 error = 0; 2407 break; 2408 2409 case SIOCSIFMEDIA: 2410 case SIOCGIFMEDIA: 2411 if (sc->miibus != NULL) { 2412 mii = device_get_softc(sc->miibus); 2413 error = ifmedia_ioctl(ifp, ifr, 2414 &mii->mii_media, command); 2415 } else { 2416 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2417 } 2418 break; 2419 2420 case SIOCSIFCAP: 2421 FXP_LOCK(sc); 2422 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2423 if (mask & IFCAP_POLLING) 2424 ifp->if_capenable ^= IFCAP_POLLING; 2425 if (mask & IFCAP_VLAN_MTU) { 2426 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2427 if (sc->revision != FXP_REV_82557) 2428 flag = FXP_FLAG_LONG_PKT_EN; 2429 else /* a hack to get long frames on the old chip */ 2430 flag = FXP_FLAG_SAVE_BAD; 2431 sc->flags ^= flag; 2432 if (ifp->if_flags & IFF_UP) 2433 fxp_init_body(sc); 2434 } 2435 FXP_UNLOCK(sc); 2436 break; 2437 2438 default: 2439 error = ether_ioctl(ifp, command, data); 2440 } 2441 return (error); 2442 } 2443 2444 /* 2445 * Fill in the multicast address list and return number of entries. 2446 */ 2447 static int 2448 fxp_mc_addrs(struct fxp_softc *sc) 2449 { 2450 struct fxp_cb_mcs *mcsp = sc->mcsp; 2451 struct ifnet *ifp = sc->ifp; 2452 struct ifmultiaddr *ifma; 2453 int nmcasts; 2454 2455 nmcasts = 0; 2456 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2457 IF_ADDR_LOCK(ifp); 2458 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2459 if (ifma->ifma_addr->sa_family != AF_LINK) 2460 continue; 2461 if (nmcasts >= MAXMCADDR) { 2462 sc->flags |= FXP_FLAG_ALL_MCAST; 2463 nmcasts = 0; 2464 break; 2465 } 2466 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2467 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); 2468 nmcasts++; 2469 } 2470 IF_ADDR_UNLOCK(ifp); 2471 } 2472 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2473 return (nmcasts); 2474 } 2475 2476 /* 2477 * Program the multicast filter. 2478 * 2479 * We have an artificial restriction that the multicast setup command 2480 * must be the first command in the chain, so we take steps to ensure 2481 * this. By requiring this, it allows us to keep up the performance of 2482 * the pre-initialized command ring (esp. link pointers) by not actually 2483 * inserting the mcsetup command in the ring - i.e. its link pointer 2484 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2485 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2486 * lead into the regular TxCB ring when it completes. 2487 * 2488 * This function must be called at splimp. 2489 */ 2490 static void 2491 fxp_mc_setup(struct fxp_softc *sc) 2492 { 2493 struct fxp_cb_mcs *mcsp = sc->mcsp; 2494 struct ifnet *ifp = sc->ifp; 2495 struct fxp_tx *txp; 2496 int count; 2497 2498 FXP_LOCK_ASSERT(sc, MA_OWNED); 2499 /* 2500 * If there are queued commands, we must wait until they are all 2501 * completed. If we are already waiting, then add a NOP command 2502 * with interrupt option so that we're notified when all commands 2503 * have been completed - fxp_start() ensures that no additional 2504 * TX commands will be added when need_mcsetup is true. 2505 */ 2506 if (sc->tx_queued) { 2507 /* 2508 * need_mcsetup will be true if we are already waiting for the 2509 * NOP command to be completed (see below). In this case, bail. 2510 */ 2511 if (sc->need_mcsetup) 2512 return; 2513 sc->need_mcsetup = 1; 2514 2515 /* 2516 * Add a NOP command with interrupt so that we are notified 2517 * when all TX commands have been processed. 2518 */ 2519 txp = sc->fxp_desc.tx_last->tx_next; 2520 txp->tx_mbuf = NULL; 2521 txp->tx_cb->cb_status = 0; 2522 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | 2523 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2524 /* 2525 * Advance the end of list forward. 2526 */ 2527 sc->fxp_desc.tx_last->tx_cb->cb_command &= 2528 htole16(~FXP_CB_COMMAND_S); 2529 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2530 sc->fxp_desc.tx_last = txp; 2531 sc->tx_queued++; 2532 /* 2533 * Issue a resume in case the CU has just suspended. 2534 */ 2535 fxp_scb_wait(sc); 2536 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2537 /* 2538 * Set a 5 second timer just in case we don't hear from the 2539 * card again. 2540 */ 2541 ifp->if_timer = 5; 2542 2543 return; 2544 } 2545 sc->need_mcsetup = 0; 2546 2547 /* 2548 * Initialize multicast setup descriptor. 2549 */ 2550 mcsp->cb_status = 0; 2551 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | 2552 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); 2553 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); 2554 txp = &sc->fxp_desc.mcs_tx; 2555 txp->tx_mbuf = NULL; 2556 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; 2557 txp->tx_next = sc->fxp_desc.tx_list; 2558 (void) fxp_mc_addrs(sc); 2559 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; 2560 sc->tx_queued = 1; 2561 2562 /* 2563 * Wait until command unit is not active. This should never 2564 * be the case when nothing is queued, but make sure anyway. 2565 */ 2566 count = 100; 2567 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2568 FXP_SCB_CUS_ACTIVE && --count) 2569 DELAY(10); 2570 if (count == 0) { 2571 device_printf(sc->dev, "command queue timeout\n"); 2572 return; 2573 } 2574 2575 /* 2576 * Start the multicast setup command. 2577 */ 2578 fxp_scb_wait(sc); 2579 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); 2580 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); 2581 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2582 2583 ifp->if_timer = 2; 2584 return; 2585 } 2586 2587 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2588 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2589 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2590 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2591 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2592 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2593 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2594 2595 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2596 2597 struct ucode { 2598 uint32_t revision; 2599 uint32_t *ucode; 2600 int length; 2601 u_short int_delay_offset; 2602 u_short bundle_max_offset; 2603 } ucode_table[] = { 2604 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2605 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2606 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2607 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2608 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2609 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2610 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2611 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2612 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2613 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2614 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2615 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2616 { 0, NULL, 0, 0, 0 } 2617 }; 2618 2619 static void 2620 fxp_load_ucode(struct fxp_softc *sc) 2621 { 2622 struct ucode *uc; 2623 struct fxp_cb_ucode *cbp; 2624 int i; 2625 2626 for (uc = ucode_table; uc->ucode != NULL; uc++) 2627 if (sc->revision == uc->revision) 2628 break; 2629 if (uc->ucode == NULL) 2630 return; 2631 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; 2632 cbp->cb_status = 0; 2633 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2634 cbp->link_addr = 0xffffffff; /* (no) next command */ 2635 for (i = 0; i < uc->length; i++) 2636 cbp->ucode[i] = htole32(uc->ucode[i]); 2637 if (uc->int_delay_offset) 2638 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] = 2639 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); 2640 if (uc->bundle_max_offset) 2641 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] = 2642 htole16(sc->tunable_bundle_max); 2643 /* 2644 * Download the ucode to the chip. 2645 */ 2646 fxp_scb_wait(sc); 2647 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); 2648 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); 2649 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2650 /* ...and wait for it to complete. */ 2651 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); 2652 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); 2653 device_printf(sc->dev, 2654 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2655 sc->tunable_int_delay, 2656 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2657 sc->flags |= FXP_FLAG_UCODE; 2658 } 2659 2660 static int 2661 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2662 { 2663 int error, value; 2664 2665 value = *(int *)arg1; 2666 error = sysctl_handle_int(oidp, &value, 0, req); 2667 if (error || !req->newptr) 2668 return (error); 2669 if (value < low || value > high) 2670 return (EINVAL); 2671 *(int *)arg1 = value; 2672 return (0); 2673 } 2674 2675 /* 2676 * Interrupt delay is expressed in microseconds, a multiplier is used 2677 * to convert this to the appropriate clock ticks before using. 2678 */ 2679 static int 2680 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2681 { 2682 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2683 } 2684 2685 static int 2686 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2687 { 2688 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2689 } 2690