1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #ifdef NS 49 #include <netns/ns.h> 50 #include <netns/ns_if.h> 51 #endif 52 53 #include <net/bpf.h> 54 #include <sys/sockio.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <net/ethernet.h> 61 #include <net/if_arp.h> 62 63 #include <vm/vm.h> /* for vtophys */ 64 #include <vm/pmap.h> /* for vtophys */ 65 #include <machine/clock.h> /* for DELAY */ 66 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #include <pci/pcivar.h> 71 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/fxp/if_fxpreg.h> 77 #include <dev/fxp/if_fxpvar.h> 78 #include <dev/fxp/rcvbundl.h> 79 80 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140 }; 141 142 /* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148 static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0x1039, "Intel Pro/100 Ethernet" }, 163 { 0x103A, "Intel Pro/100 Ethernet" }, 164 { 0x103B, "Intel Pro/100 Ethernet" }, 165 { 0x103C, "Intel Pro/100 Ethernet" }, 166 { 0x103D, "Intel Pro/100 Ethernet" }, 167 { 0x103E, "Intel Pro/100 Ethernet" }, 168 { 0, NULL }, 169 }; 170 171 static int fxp_probe(device_t dev); 172 static int fxp_attach(device_t dev); 173 static int fxp_detach(device_t dev); 174 static int fxp_shutdown(device_t dev); 175 static int fxp_suspend(device_t dev); 176 static int fxp_resume(device_t dev); 177 178 static void fxp_intr(void *xsc); 179 static void fxp_init(void *xsc); 180 static void fxp_tick(void *xsc); 181 static void fxp_powerstate_d0(device_t dev); 182 static void fxp_start(struct ifnet *ifp); 183 static void fxp_stop(struct fxp_softc *sc); 184 static void fxp_release(struct fxp_softc *sc); 185 static int fxp_ioctl(struct ifnet *ifp, u_long command, 186 caddr_t data); 187 static void fxp_watchdog(struct ifnet *ifp); 188 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 189 static int fxp_mc_addrs(struct fxp_softc *sc); 190 static void fxp_mc_setup(struct fxp_softc *sc); 191 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 192 int autosize); 193 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 194 u_int16_t data); 195 static void fxp_autosize_eeprom(struct fxp_softc *sc); 196 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 197 int offset, int words); 198 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 199 int offset, int words); 200 static int fxp_ifmedia_upd(struct ifnet *ifp); 201 static void fxp_ifmedia_sts(struct ifnet *ifp, 202 struct ifmediareq *ifmr); 203 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 204 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 205 struct ifmediareq *ifmr); 206 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 207 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 208 int value); 209 static void fxp_load_ucode(struct fxp_softc *sc); 210 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 211 int low, int high); 212 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 213 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 214 static __inline void fxp_lwcopy(volatile u_int32_t *src, 215 volatile u_int32_t *dst); 216 static __inline void fxp_scb_wait(struct fxp_softc *sc); 217 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 218 static __inline void fxp_dma_wait(volatile u_int16_t *status, 219 struct fxp_softc *sc); 220 221 static device_method_t fxp_methods[] = { 222 /* Device interface */ 223 DEVMETHOD(device_probe, fxp_probe), 224 DEVMETHOD(device_attach, fxp_attach), 225 DEVMETHOD(device_detach, fxp_detach), 226 DEVMETHOD(device_shutdown, fxp_shutdown), 227 DEVMETHOD(device_suspend, fxp_suspend), 228 DEVMETHOD(device_resume, fxp_resume), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 232 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 233 234 { 0, 0 } 235 }; 236 237 static driver_t fxp_driver = { 238 "fxp", 239 fxp_methods, 240 sizeof(struct fxp_softc), 241 }; 242 243 static devclass_t fxp_devclass; 244 245 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 246 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 247 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 248 249 static int fxp_rnr; 250 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 251 252 /* 253 * Inline function to copy a 16-bit aligned 32-bit quantity. 254 */ 255 static __inline void 256 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 257 { 258 #ifdef __i386__ 259 *dst = *src; 260 #else 261 volatile u_int16_t *a = (volatile u_int16_t *)src; 262 volatile u_int16_t *b = (volatile u_int16_t *)dst; 263 264 b[0] = a[0]; 265 b[1] = a[1]; 266 #endif 267 } 268 269 /* 270 * Wait for the previous command to be accepted (but not necessarily 271 * completed). 272 */ 273 static __inline void 274 fxp_scb_wait(struct fxp_softc *sc) 275 { 276 int i = 10000; 277 278 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 279 DELAY(2); 280 if (i == 0) 281 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 282 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 283 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 284 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 285 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 286 } 287 288 static __inline void 289 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 290 { 291 292 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 293 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 294 fxp_scb_wait(sc); 295 } 296 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 297 } 298 299 static __inline void 300 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 301 { 302 int i = 10000; 303 304 while (!(*status & FXP_CB_STATUS_C) && --i) 305 DELAY(2); 306 if (i == 0) 307 device_printf(sc->dev, "DMA timeout\n"); 308 } 309 310 /* 311 * Return identification string if this is device is ours. 312 */ 313 static int 314 fxp_probe(device_t dev) 315 { 316 u_int16_t devid; 317 struct fxp_ident *ident; 318 319 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 320 devid = pci_get_device(dev); 321 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 322 if (ident->devid == devid) { 323 device_set_desc(dev, ident->name); 324 return (0); 325 } 326 } 327 } 328 return (ENXIO); 329 } 330 331 static void 332 fxp_powerstate_d0(device_t dev) 333 { 334 #if __FreeBSD_version >= 430002 335 u_int32_t iobase, membase, irq; 336 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 /* Save important PCI config data. */ 339 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 340 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 341 irq = pci_read_config(dev, PCIR_INTLINE, 4); 342 343 /* Reset the power state. */ 344 device_printf(dev, "chip is in D%d power mode " 345 "-- setting to D0\n", pci_get_powerstate(dev)); 346 347 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 348 349 /* Restore PCI config data. */ 350 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 351 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 352 pci_write_config(dev, PCIR_INTLINE, irq, 4); 353 } 354 #endif 355 } 356 357 static int 358 fxp_attach(device_t dev) 359 { 360 int error = 0; 361 struct fxp_softc *sc = device_get_softc(dev); 362 struct ifnet *ifp; 363 u_int32_t val; 364 u_int16_t data; 365 int i, rid, m1, m2, prefer_iomap; 366 int s; 367 368 bzero(sc, sizeof(*sc)); 369 sc->dev = dev; 370 callout_handle_init(&sc->stat_ch); 371 sysctl_ctx_init(&sc->sysctl_ctx); 372 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 373 MTX_DEF | MTX_RECURSE); 374 375 s = splimp(); 376 377 /* 378 * Enable bus mastering. Enable memory space too, in case 379 * BIOS/Prom forgot about it. 380 */ 381 val = pci_read_config(dev, PCIR_COMMAND, 2); 382 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 383 pci_write_config(dev, PCIR_COMMAND, val, 2); 384 val = pci_read_config(dev, PCIR_COMMAND, 2); 385 386 fxp_powerstate_d0(dev); 387 388 /* 389 * Figure out which we should try first - memory mapping or i/o mapping? 390 * We default to memory mapping. Then we accept an override from the 391 * command line. Then we check to see which one is enabled. 392 */ 393 m1 = PCIM_CMD_MEMEN; 394 m2 = PCIM_CMD_PORTEN; 395 prefer_iomap = 0; 396 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 397 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 398 m1 = PCIM_CMD_PORTEN; 399 m2 = PCIM_CMD_MEMEN; 400 } 401 402 if (val & m1) { 403 sc->rtp = 404 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 405 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 406 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 407 0, ~0, 1, RF_ACTIVE); 408 } 409 if (sc->mem == NULL && (val & m2)) { 410 sc->rtp = 411 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 412 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 413 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 414 0, ~0, 1, RF_ACTIVE); 415 } 416 417 if (!sc->mem) { 418 device_printf(dev, "could not map device registers\n"); 419 error = ENXIO; 420 goto fail; 421 } 422 if (bootverbose) { 423 device_printf(dev, "using %s space register mapping\n", 424 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 425 } 426 427 sc->sc_st = rman_get_bustag(sc->mem); 428 sc->sc_sh = rman_get_bushandle(sc->mem); 429 430 /* 431 * Allocate our interrupt. 432 */ 433 rid = 0; 434 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 435 RF_SHAREABLE | RF_ACTIVE); 436 if (sc->irq == NULL) { 437 device_printf(dev, "could not map interrupt\n"); 438 error = ENXIO; 439 goto fail; 440 } 441 442 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 443 fxp_intr, sc, &sc->ih); 444 if (error) { 445 device_printf(dev, "could not setup irq\n"); 446 goto fail; 447 } 448 449 /* 450 * Reset to a stable state. 451 */ 452 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 453 DELAY(10); 454 455 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 456 M_DEVBUF, M_NOWAIT | M_ZERO); 457 if (sc->cbl_base == NULL) 458 goto failmem; 459 460 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 461 M_NOWAIT | M_ZERO); 462 if (sc->fxp_stats == NULL) 463 goto failmem; 464 465 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 466 if (sc->mcsp == NULL) 467 goto failmem; 468 469 /* 470 * Pre-allocate our receive buffers. 471 */ 472 for (i = 0; i < FXP_NRFABUFS; i++) { 473 if (fxp_add_rfabuf(sc, NULL) != 0) { 474 goto failmem; 475 } 476 } 477 478 /* 479 * Find out how large of an SEEPROM we have. 480 */ 481 fxp_autosize_eeprom(sc); 482 483 /* 484 * Determine whether we must use the 503 serial interface. 485 */ 486 fxp_read_eeprom(sc, &data, 6, 1); 487 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 488 (data & FXP_PHY_SERIAL_ONLY)) 489 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 490 491 /* 492 * Create the sysctl tree 493 */ 494 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 495 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 496 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 497 if (sc->sysctl_tree == NULL) 498 goto fail; 499 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 500 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 501 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 502 "FXP driver receive interrupt microcode bundling delay"); 503 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 504 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 505 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 506 "FXP driver receive interrupt microcode bundle size limit"); 507 508 /* 509 * Pull in device tunables. 510 */ 511 sc->tunable_int_delay = TUNABLE_INT_DELAY; 512 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 513 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 514 "int_delay", &sc->tunable_int_delay); 515 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 516 "bundle_max", &sc->tunable_bundle_max); 517 518 /* 519 * Find out the chip revision; lump all 82557 revs together. 520 */ 521 fxp_read_eeprom(sc, &data, 5, 1); 522 if ((data >> 8) == 1) 523 sc->revision = FXP_REV_82557; 524 else 525 sc->revision = pci_get_revid(dev); 526 527 /* 528 * Enable workarounds for certain chip revision deficiencies. 529 * 530 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 531 * some systems based a normal 82559 design, have a defect where 532 * the chip can cause a PCI protocol violation if it receives 533 * a CU_RESUME command when it is entering the IDLE state. The 534 * workaround is to disable Dynamic Standby Mode, so the chip never 535 * deasserts CLKRUN#, and always remains in an active state. 536 * 537 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 538 */ 539 i = pci_get_device(dev); 540 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 541 sc->revision >= FXP_REV_82559_A0) { 542 fxp_read_eeprom(sc, &data, 10, 1); 543 if (data & 0x02) { /* STB enable */ 544 u_int16_t cksum; 545 int i; 546 547 device_printf(dev, 548 "Disabling dynamic standby mode in EEPROM\n"); 549 data &= ~0x02; 550 fxp_write_eeprom(sc, &data, 10, 1); 551 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 552 cksum = 0; 553 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 554 fxp_read_eeprom(sc, &data, i, 1); 555 cksum += data; 556 } 557 i = (1 << sc->eeprom_size) - 1; 558 cksum = 0xBABA - cksum; 559 fxp_read_eeprom(sc, &data, i, 1); 560 fxp_write_eeprom(sc, &cksum, i, 1); 561 device_printf(dev, 562 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 563 i, data, cksum); 564 #if 1 565 /* 566 * If the user elects to continue, try the software 567 * workaround, as it is better than nothing. 568 */ 569 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 570 #endif 571 } 572 } 573 574 /* 575 * If we are not a 82557 chip, we can enable extended features. 576 */ 577 if (sc->revision != FXP_REV_82557) { 578 /* 579 * If MWI is enabled in the PCI configuration, and there 580 * is a valid cacheline size (8 or 16 dwords), then tell 581 * the board to turn on MWI. 582 */ 583 if (val & PCIM_CMD_MWRICEN && 584 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 585 sc->flags |= FXP_FLAG_MWI_ENABLE; 586 587 /* turn on the extended TxCB feature */ 588 sc->flags |= FXP_FLAG_EXT_TXCB; 589 590 /* enable reception of long frames for VLAN */ 591 sc->flags |= FXP_FLAG_LONG_PKT_EN; 592 } 593 594 /* 595 * Read MAC address. 596 */ 597 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 598 device_printf(dev, "Ethernet address %6D%s\n", 599 sc->arpcom.ac_enaddr, ":", 600 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 601 if (bootverbose) { 602 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 603 pci_get_vendor(dev), pci_get_device(dev), 604 pci_get_subvendor(dev), pci_get_subdevice(dev), 605 pci_get_revid(dev)); 606 fxp_read_eeprom(sc, &data, 10, 1); 607 device_printf(dev, "Dynamic Standby mode is %s\n", 608 data & 0x02 ? "enabled" : "disabled"); 609 } 610 611 /* 612 * If this is only a 10Mbps device, then there is no MII, and 613 * the PHY will use a serial interface instead. 614 * 615 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 616 * doesn't have a programming interface of any sort. The 617 * media is sensed automatically based on how the link partner 618 * is configured. This is, in essence, manual configuration. 619 */ 620 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 621 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 622 fxp_serial_ifmedia_sts); 623 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 624 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 625 } else { 626 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 627 fxp_ifmedia_sts)) { 628 device_printf(dev, "MII without any PHY!\n"); 629 error = ENXIO; 630 goto fail; 631 } 632 } 633 634 ifp = &sc->arpcom.ac_if; 635 ifp->if_unit = device_get_unit(dev); 636 ifp->if_name = "fxp"; 637 ifp->if_output = ether_output; 638 ifp->if_baudrate = 100000000; 639 ifp->if_init = fxp_init; 640 ifp->if_softc = sc; 641 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 642 ifp->if_ioctl = fxp_ioctl; 643 ifp->if_start = fxp_start; 644 ifp->if_watchdog = fxp_watchdog; 645 646 /* 647 * Attach the interface. 648 */ 649 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 650 651 /* 652 * Tell the upper layer(s) we support long frames. 653 */ 654 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 655 656 /* 657 * Let the system queue as many packets as we have available 658 * TX descriptors. 659 */ 660 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 661 662 splx(s); 663 return (0); 664 665 failmem: 666 device_printf(dev, "Failed to malloc memory\n"); 667 error = ENOMEM; 668 fail: 669 splx(s); 670 fxp_release(sc); 671 return (error); 672 } 673 674 /* 675 * release all resources 676 */ 677 static void 678 fxp_release(struct fxp_softc *sc) 679 { 680 681 bus_generic_detach(sc->dev); 682 if (sc->miibus) 683 device_delete_child(sc->dev, sc->miibus); 684 685 if (sc->cbl_base) 686 free(sc->cbl_base, M_DEVBUF); 687 if (sc->fxp_stats) 688 free(sc->fxp_stats, M_DEVBUF); 689 if (sc->mcsp) 690 free(sc->mcsp, M_DEVBUF); 691 if (sc->rfa_headm) 692 m_freem(sc->rfa_headm); 693 694 if (sc->ih) 695 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 696 if (sc->irq) 697 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 698 if (sc->mem) 699 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 700 701 sysctl_ctx_free(&sc->sysctl_ctx); 702 703 mtx_destroy(&sc->sc_mtx); 704 } 705 706 /* 707 * Detach interface. 708 */ 709 static int 710 fxp_detach(device_t dev) 711 { 712 struct fxp_softc *sc = device_get_softc(dev); 713 int s; 714 715 /* disable interrupts */ 716 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 717 718 s = splimp(); 719 720 /* 721 * Stop DMA and drop transmit queue. 722 */ 723 fxp_stop(sc); 724 725 /* 726 * Close down routes etc. 727 */ 728 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 729 730 /* 731 * Free all media structures. 732 */ 733 ifmedia_removeall(&sc->sc_media); 734 735 splx(s); 736 737 /* Release our allocated resources. */ 738 fxp_release(sc); 739 740 return (0); 741 } 742 743 /* 744 * Device shutdown routine. Called at system shutdown after sync. The 745 * main purpose of this routine is to shut off receiver DMA so that 746 * kernel memory doesn't get clobbered during warmboot. 747 */ 748 static int 749 fxp_shutdown(device_t dev) 750 { 751 /* 752 * Make sure that DMA is disabled prior to reboot. Not doing 753 * do could allow DMA to corrupt kernel memory during the 754 * reboot before the driver initializes. 755 */ 756 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 757 return (0); 758 } 759 760 /* 761 * Device suspend routine. Stop the interface and save some PCI 762 * settings in case the BIOS doesn't restore them properly on 763 * resume. 764 */ 765 static int 766 fxp_suspend(device_t dev) 767 { 768 struct fxp_softc *sc = device_get_softc(dev); 769 int i, s; 770 771 s = splimp(); 772 773 fxp_stop(sc); 774 775 for (i = 0; i < 5; i++) 776 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 777 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 778 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 779 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 780 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 781 782 sc->suspended = 1; 783 784 splx(s); 785 return (0); 786 } 787 788 /* 789 * Device resume routine. Restore some PCI settings in case the BIOS 790 * doesn't, re-enable busmastering, and restart the interface if 791 * appropriate. 792 */ 793 static int 794 fxp_resume(device_t dev) 795 { 796 struct fxp_softc *sc = device_get_softc(dev); 797 struct ifnet *ifp = &sc->sc_if; 798 u_int16_t pci_command; 799 int i, s; 800 801 s = splimp(); 802 803 fxp_powerstate_d0(dev); 804 805 /* better way to do this? */ 806 for (i = 0; i < 5; i++) 807 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 808 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 809 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 810 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 811 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 812 813 /* reenable busmastering */ 814 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 815 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 816 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 817 818 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 819 DELAY(10); 820 821 /* reinitialize interface if necessary */ 822 if (ifp->if_flags & IFF_UP) 823 fxp_init(sc); 824 825 sc->suspended = 0; 826 827 splx(s); 828 return (0); 829 } 830 831 static void 832 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 833 { 834 u_int16_t reg; 835 int x; 836 837 /* 838 * Shift in data. 839 */ 840 for (x = 1 << (length - 1); x; x >>= 1) { 841 if (data & x) 842 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 843 else 844 reg = FXP_EEPROM_EECS; 845 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 846 DELAY(1); 847 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 848 DELAY(1); 849 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 850 DELAY(1); 851 } 852 } 853 854 /* 855 * Read from the serial EEPROM. Basically, you manually shift in 856 * the read opcode (one bit at a time) and then shift in the address, 857 * and then you shift out the data (all of this one bit at a time). 858 * The word size is 16 bits, so you have to provide the address for 859 * every 16 bits of data. 860 */ 861 static u_int16_t 862 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 863 { 864 u_int16_t reg, data; 865 int x; 866 867 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 868 /* 869 * Shift in read opcode. 870 */ 871 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 872 /* 873 * Shift in address. 874 */ 875 data = 0; 876 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 877 if (offset & x) 878 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 879 else 880 reg = FXP_EEPROM_EECS; 881 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 882 DELAY(1); 883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 884 DELAY(1); 885 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 886 DELAY(1); 887 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 888 data++; 889 if (autosize && reg == 0) { 890 sc->eeprom_size = data; 891 break; 892 } 893 } 894 /* 895 * Shift out data. 896 */ 897 data = 0; 898 reg = FXP_EEPROM_EECS; 899 for (x = 1 << 15; x; x >>= 1) { 900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 901 DELAY(1); 902 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 903 data |= x; 904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 905 DELAY(1); 906 } 907 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 908 DELAY(1); 909 910 return (data); 911 } 912 913 static void 914 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 915 { 916 int i; 917 918 /* 919 * Erase/write enable. 920 */ 921 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 922 fxp_eeprom_shiftin(sc, 0x4, 3); 923 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 925 DELAY(1); 926 /* 927 * Shift in write opcode, address, data. 928 */ 929 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 930 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 931 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 932 fxp_eeprom_shiftin(sc, data, 16); 933 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 934 DELAY(1); 935 /* 936 * Wait for EEPROM to finish up. 937 */ 938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 939 DELAY(1); 940 for (i = 0; i < 1000; i++) { 941 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 942 break; 943 DELAY(50); 944 } 945 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 946 DELAY(1); 947 /* 948 * Erase/write disable. 949 */ 950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 951 fxp_eeprom_shiftin(sc, 0x4, 3); 952 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 954 DELAY(1); 955 } 956 957 /* 958 * From NetBSD: 959 * 960 * Figure out EEPROM size. 961 * 962 * 559's can have either 64-word or 256-word EEPROMs, the 558 963 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 964 * talks about the existance of 16 to 256 word EEPROMs. 965 * 966 * The only known sizes are 64 and 256, where the 256 version is used 967 * by CardBus cards to store CIS information. 968 * 969 * The address is shifted in msb-to-lsb, and after the last 970 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 971 * after which follows the actual data. We try to detect this zero, by 972 * probing the data-out bit in the EEPROM control register just after 973 * having shifted in a bit. If the bit is zero, we assume we've 974 * shifted enough address bits. The data-out should be tri-state, 975 * before this, which should translate to a logical one. 976 */ 977 static void 978 fxp_autosize_eeprom(struct fxp_softc *sc) 979 { 980 981 /* guess maximum size of 256 words */ 982 sc->eeprom_size = 8; 983 984 /* autosize */ 985 (void) fxp_eeprom_getword(sc, 0, 1); 986 } 987 988 static void 989 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 990 { 991 int i; 992 993 for (i = 0; i < words; i++) 994 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 995 } 996 997 static void 998 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 999 { 1000 int i; 1001 1002 for (i = 0; i < words; i++) 1003 fxp_eeprom_putword(sc, offset + i, data[i]); 1004 } 1005 1006 /* 1007 * Start packet transmission on the interface. 1008 */ 1009 static void 1010 fxp_start(struct ifnet *ifp) 1011 { 1012 struct fxp_softc *sc = ifp->if_softc; 1013 struct fxp_cb_tx *txp; 1014 1015 /* 1016 * See if we need to suspend xmit until the multicast filter 1017 * has been reprogrammed (which can only be done at the head 1018 * of the command chain). 1019 */ 1020 if (sc->need_mcsetup) { 1021 return; 1022 } 1023 1024 txp = NULL; 1025 1026 /* 1027 * We're finished if there is nothing more to add to the list or if 1028 * we're all filled up with buffers to transmit. 1029 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1030 * a NOP command when needed. 1031 */ 1032 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1033 struct mbuf *m, *mb_head; 1034 int segment; 1035 1036 /* 1037 * Grab a packet to transmit. 1038 */ 1039 IF_DEQUEUE(&ifp->if_snd, mb_head); 1040 1041 /* 1042 * Get pointer to next available tx desc. 1043 */ 1044 txp = sc->cbl_last->next; 1045 1046 /* 1047 * Go through each of the mbufs in the chain and initialize 1048 * the transmit buffer descriptors with the physical address 1049 * and size of the mbuf. 1050 */ 1051 tbdinit: 1052 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1053 if (m->m_len != 0) { 1054 if (segment == FXP_NTXSEG) 1055 break; 1056 txp->tbd[segment].tb_addr = 1057 vtophys(mtod(m, vm_offset_t)); 1058 txp->tbd[segment].tb_size = m->m_len; 1059 segment++; 1060 } 1061 } 1062 if (m != NULL) { 1063 struct mbuf *mn; 1064 1065 /* 1066 * We ran out of segments. We have to recopy this 1067 * mbuf chain first. Bail out if we can't get the 1068 * new buffers. 1069 */ 1070 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1071 if (mn == NULL) { 1072 m_freem(mb_head); 1073 break; 1074 } 1075 if (mb_head->m_pkthdr.len > MHLEN) { 1076 MCLGET(mn, M_DONTWAIT); 1077 if ((mn->m_flags & M_EXT) == 0) { 1078 m_freem(mn); 1079 m_freem(mb_head); 1080 break; 1081 } 1082 } 1083 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1084 mtod(mn, caddr_t)); 1085 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1086 m_freem(mb_head); 1087 mb_head = mn; 1088 goto tbdinit; 1089 } 1090 1091 txp->tbd_number = segment; 1092 txp->mb_head = mb_head; 1093 txp->cb_status = 0; 1094 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1095 txp->cb_command = 1096 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1097 FXP_CB_COMMAND_S; 1098 } else { 1099 txp->cb_command = 1100 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1101 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1102 /* 1103 * Set a 5 second timer just in case we don't hear 1104 * from the card again. 1105 */ 1106 ifp->if_timer = 5; 1107 } 1108 txp->tx_threshold = tx_threshold; 1109 1110 /* 1111 * Advance the end of list forward. 1112 */ 1113 1114 #ifdef __alpha__ 1115 /* 1116 * On platforms which can't access memory in 16-bit 1117 * granularities, we must prevent the card from DMA'ing 1118 * up the status while we update the command field. 1119 * This could cause us to overwrite the completion status. 1120 */ 1121 atomic_clear_short(&sc->cbl_last->cb_command, 1122 FXP_CB_COMMAND_S); 1123 #else 1124 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1125 #endif /*__alpha__*/ 1126 sc->cbl_last = txp; 1127 1128 /* 1129 * Advance the beginning of the list forward if there are 1130 * no other packets queued (when nothing is queued, cbl_first 1131 * sits on the last TxCB that was sent out). 1132 */ 1133 if (sc->tx_queued == 0) 1134 sc->cbl_first = txp; 1135 1136 sc->tx_queued++; 1137 1138 /* 1139 * Pass packet to bpf if there is a listener. 1140 */ 1141 if (ifp->if_bpf) 1142 bpf_mtap(ifp, mb_head); 1143 } 1144 1145 /* 1146 * We're finished. If we added to the list, issue a RESUME to get DMA 1147 * going again if suspended. 1148 */ 1149 if (txp != NULL) { 1150 fxp_scb_wait(sc); 1151 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1152 } 1153 } 1154 1155 static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1156 1157 #ifdef DEVICE_POLLING 1158 static poll_handler_t fxp_poll; 1159 1160 static void 1161 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1162 { 1163 struct fxp_softc *sc = ifp->if_softc; 1164 u_int8_t statack; 1165 1166 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1167 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1168 return; 1169 } 1170 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1171 FXP_SCB_STATACK_FR; 1172 if (cmd == POLL_AND_CHECK_STATUS) { 1173 u_int8_t tmp; 1174 1175 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1176 if (tmp == 0xff || tmp == 0) 1177 return; /* nothing to do */ 1178 tmp &= ~statack; 1179 /* ack what we can */ 1180 if (tmp != 0) 1181 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1182 statack |= tmp; 1183 } 1184 fxp_intr_body(sc, statack, count); 1185 } 1186 #endif /* DEVICE_POLLING */ 1187 1188 /* 1189 * Process interface interrupts. 1190 */ 1191 static void 1192 fxp_intr(void *xsc) 1193 { 1194 struct fxp_softc *sc = xsc; 1195 u_int8_t statack; 1196 1197 #ifdef DEVICE_POLLING 1198 struct ifnet *ifp = &sc->sc_if; 1199 1200 if (ifp->if_flags & IFF_POLLING) 1201 return; 1202 if (ether_poll_register(fxp_poll, ifp)) { 1203 /* disable interrupts */ 1204 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1205 fxp_poll(ifp, 0, 1); 1206 return; 1207 } 1208 #endif 1209 1210 if (sc->suspended) { 1211 return; 1212 } 1213 1214 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1215 /* 1216 * It should not be possible to have all bits set; the 1217 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1218 * all bits are set, this may indicate that the card has 1219 * been physically ejected, so ignore it. 1220 */ 1221 if (statack == 0xff) 1222 return; 1223 1224 /* 1225 * First ACK all the interrupts in this pass. 1226 */ 1227 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1228 fxp_intr_body(sc, statack, -1); 1229 } 1230 } 1231 1232 static void 1233 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1234 { 1235 struct ifnet *ifp = &sc->sc_if; 1236 struct mbuf *m; 1237 struct fxp_rfa *rfa; 1238 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1239 1240 if (rnr) 1241 fxp_rnr++; 1242 1243 /* 1244 * Free any finished transmit mbuf chains. 1245 * 1246 * Handle the CNA event likt a CXTNO event. It used to 1247 * be that this event (control unit not ready) was not 1248 * encountered, but it is now with the SMPng modifications. 1249 * The exact sequence of events that occur when the interface 1250 * is brought up are different now, and if this event 1251 * goes unhandled, the configuration/rxfilter setup sequence 1252 * can stall for several seconds. The result is that no 1253 * packets go out onto the wire for about 5 to 10 seconds 1254 * after the interface is ifconfig'ed for the first time. 1255 */ 1256 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1257 struct fxp_cb_tx *txp; 1258 1259 for (txp = sc->cbl_first; sc->tx_queued && 1260 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1261 txp = txp->next) { 1262 if (txp->mb_head != NULL) { 1263 m_freem(txp->mb_head); 1264 txp->mb_head = NULL; 1265 } 1266 sc->tx_queued--; 1267 } 1268 sc->cbl_first = txp; 1269 ifp->if_timer = 0; 1270 if (sc->tx_queued == 0) { 1271 if (sc->need_mcsetup) 1272 fxp_mc_setup(sc); 1273 } 1274 /* 1275 * Try to start more packets transmitting. 1276 */ 1277 if (ifp->if_snd.ifq_head != NULL) 1278 fxp_start(ifp); 1279 } 1280 1281 /* 1282 * Just return if nothing happened on the receive side. 1283 */ 1284 if ( (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) == 0) 1285 return; 1286 1287 /* 1288 * Process receiver interrupts. If a no-resource (RNR) 1289 * condition exists, get whatever packets we can and 1290 * re-start the receiver. 1291 * When using polling, we do not process the list to completion, 1292 * so when we get an RNR interrupt we must defer the restart 1293 * until we hit the last buffer with the C bit set. 1294 * If we run out of cycles and rfa_headm has the C bit set, 1295 * record the pending RNR in an unused status bit, so that the 1296 * info will be used in the subsequent polling cycle. 1297 */ 1298 1299 #define FXP_RFA_RNRMARK 0x4000 /* used to mark a pending RNR intr */ 1300 1301 for (;;) { 1302 m = sc->rfa_headm; 1303 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1304 RFA_ALIGNMENT_FUDGE); 1305 1306 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1307 if (count >= 0 && count-- == 0) 1308 break; 1309 #endif /* DEVICE_POLLING */ 1310 1311 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1312 break; 1313 1314 if (rfa->rfa_status & FXP_RFA_RNRMARK) 1315 rnr = 1; 1316 /* 1317 * Remove first packet from the chain. 1318 */ 1319 sc->rfa_headm = m->m_next; 1320 m->m_next = NULL; 1321 1322 /* 1323 * Add a new buffer to the receive chain. 1324 * If this fails, the old buffer is recycled 1325 * instead. 1326 */ 1327 if (fxp_add_rfabuf(sc, m) == 0) { 1328 int total_len; 1329 1330 /* 1331 * Fetch packet length (the top 2 bits of 1332 * actual_size are flags set by the controller 1333 * upon completion), and drop the packet in case 1334 * of bogus length or CRC errors. 1335 */ 1336 total_len = rfa->actual_size & 0x3fff; 1337 if (total_len < sizeof(struct ether_header) || 1338 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1339 sizeof(struct fxp_rfa) || 1340 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1341 m_freem(m); 1342 continue; 1343 } 1344 1345 m->m_pkthdr.len = m->m_len = total_len; 1346 ether_input(ifp, NULL, m); 1347 } 1348 } 1349 if (rnr) { 1350 if (rfa->rfa_status & FXP_RFA_STATUS_C) 1351 rfa->rfa_status |= FXP_RFA_RNRMARK; 1352 else { 1353 fxp_scb_wait(sc); 1354 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1355 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1356 RFA_ALIGNMENT_FUDGE); 1357 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1358 } 1359 } 1360 } 1361 1362 /* 1363 * Update packet in/out/collision statistics. The i82557 doesn't 1364 * allow you to access these counters without doing a fairly 1365 * expensive DMA to get _all_ of the statistics it maintains, so 1366 * we do this operation here only once per second. The statistics 1367 * counters in the kernel are updated from the previous dump-stats 1368 * DMA and then a new dump-stats DMA is started. The on-chip 1369 * counters are zeroed when the DMA completes. If we can't start 1370 * the DMA immediately, we don't wait - we just prepare to read 1371 * them again next time. 1372 */ 1373 static void 1374 fxp_tick(void *xsc) 1375 { 1376 struct fxp_softc *sc = xsc; 1377 struct ifnet *ifp = &sc->sc_if; 1378 struct fxp_stats *sp = sc->fxp_stats; 1379 struct fxp_cb_tx *txp; 1380 int s; 1381 1382 ifp->if_opackets += sp->tx_good; 1383 ifp->if_collisions += sp->tx_total_collisions; 1384 if (sp->rx_good) { 1385 ifp->if_ipackets += sp->rx_good; 1386 sc->rx_idle_secs = 0; 1387 } else { 1388 /* 1389 * Receiver's been idle for another second. 1390 */ 1391 sc->rx_idle_secs++; 1392 } 1393 ifp->if_ierrors += 1394 sp->rx_crc_errors + 1395 sp->rx_alignment_errors + 1396 sp->rx_rnr_errors + 1397 sp->rx_overrun_errors; 1398 /* 1399 * If any transmit underruns occured, bump up the transmit 1400 * threshold by another 512 bytes (64 * 8). 1401 */ 1402 if (sp->tx_underruns) { 1403 ifp->if_oerrors += sp->tx_underruns; 1404 if (tx_threshold < 192) 1405 tx_threshold += 64; 1406 } 1407 s = splimp(); 1408 /* 1409 * Release any xmit buffers that have completed DMA. This isn't 1410 * strictly necessary to do here, but it's advantagous for mbufs 1411 * with external storage to be released in a timely manner rather 1412 * than being defered for a potentially long time. This limits 1413 * the delay to a maximum of one second. 1414 */ 1415 for (txp = sc->cbl_first; sc->tx_queued && 1416 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1417 txp = txp->next) { 1418 if (txp->mb_head != NULL) { 1419 m_freem(txp->mb_head); 1420 txp->mb_head = NULL; 1421 } 1422 sc->tx_queued--; 1423 } 1424 sc->cbl_first = txp; 1425 /* 1426 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1427 * then assume the receiver has locked up and attempt to clear 1428 * the condition by reprogramming the multicast filter. This is 1429 * a work-around for a bug in the 82557 where the receiver locks 1430 * up if it gets certain types of garbage in the syncronization 1431 * bits prior to the packet header. This bug is supposed to only 1432 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1433 * mode as well (perhaps due to a 10/100 speed transition). 1434 */ 1435 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1436 sc->rx_idle_secs = 0; 1437 fxp_mc_setup(sc); 1438 } 1439 /* 1440 * If there is no pending command, start another stats 1441 * dump. Otherwise punt for now. 1442 */ 1443 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1444 /* 1445 * Start another stats dump. 1446 */ 1447 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1448 } else { 1449 /* 1450 * A previous command is still waiting to be accepted. 1451 * Just zero our copy of the stats and wait for the 1452 * next timer event to update them. 1453 */ 1454 sp->tx_good = 0; 1455 sp->tx_underruns = 0; 1456 sp->tx_total_collisions = 0; 1457 1458 sp->rx_good = 0; 1459 sp->rx_crc_errors = 0; 1460 sp->rx_alignment_errors = 0; 1461 sp->rx_rnr_errors = 0; 1462 sp->rx_overrun_errors = 0; 1463 } 1464 if (sc->miibus != NULL) 1465 mii_tick(device_get_softc(sc->miibus)); 1466 splx(s); 1467 /* 1468 * Schedule another timeout one second from now. 1469 */ 1470 sc->stat_ch = timeout(fxp_tick, sc, hz); 1471 } 1472 1473 /* 1474 * Stop the interface. Cancels the statistics updater and resets 1475 * the interface. 1476 */ 1477 static void 1478 fxp_stop(struct fxp_softc *sc) 1479 { 1480 struct ifnet *ifp = &sc->sc_if; 1481 struct fxp_cb_tx *txp; 1482 int i; 1483 1484 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1485 ifp->if_timer = 0; 1486 1487 #ifdef DEVICE_POLLING 1488 ether_poll_deregister(ifp); 1489 #endif 1490 /* 1491 * Cancel stats updater. 1492 */ 1493 untimeout(fxp_tick, sc, sc->stat_ch); 1494 1495 /* 1496 * Issue software reset, which also unloads the microcode. 1497 */ 1498 sc->flags &= ~FXP_FLAG_UCODE; 1499 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1500 DELAY(50); 1501 1502 /* 1503 * Release any xmit buffers. 1504 */ 1505 txp = sc->cbl_base; 1506 if (txp != NULL) { 1507 for (i = 0; i < FXP_NTXCB; i++) { 1508 if (txp[i].mb_head != NULL) { 1509 m_freem(txp[i].mb_head); 1510 txp[i].mb_head = NULL; 1511 } 1512 } 1513 } 1514 sc->tx_queued = 0; 1515 1516 /* 1517 * Free all the receive buffers then reallocate/reinitialize 1518 */ 1519 if (sc->rfa_headm != NULL) 1520 m_freem(sc->rfa_headm); 1521 sc->rfa_headm = NULL; 1522 sc->rfa_tailm = NULL; 1523 for (i = 0; i < FXP_NRFABUFS; i++) { 1524 if (fxp_add_rfabuf(sc, NULL) != 0) { 1525 /* 1526 * This "can't happen" - we're at splimp() 1527 * and we just freed all the buffers we need 1528 * above. 1529 */ 1530 panic("fxp_stop: no buffers!"); 1531 } 1532 } 1533 } 1534 1535 /* 1536 * Watchdog/transmission transmit timeout handler. Called when a 1537 * transmission is started on the interface, but no interrupt is 1538 * received before the timeout. This usually indicates that the 1539 * card has wedged for some reason. 1540 */ 1541 static void 1542 fxp_watchdog(struct ifnet *ifp) 1543 { 1544 struct fxp_softc *sc = ifp->if_softc; 1545 1546 device_printf(sc->dev, "device timeout\n"); 1547 ifp->if_oerrors++; 1548 1549 fxp_init(sc); 1550 } 1551 1552 static void 1553 fxp_init(void *xsc) 1554 { 1555 struct fxp_softc *sc = xsc; 1556 struct ifnet *ifp = &sc->sc_if; 1557 struct fxp_cb_config *cbp; 1558 struct fxp_cb_ias *cb_ias; 1559 struct fxp_cb_tx *txp; 1560 struct fxp_cb_mcs *mcsp; 1561 int i, prm, s; 1562 1563 s = splimp(); 1564 /* 1565 * Cancel any pending I/O 1566 */ 1567 fxp_stop(sc); 1568 1569 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1570 1571 /* 1572 * Initialize base of CBL and RFA memory. Loading with zero 1573 * sets it up for regular linear addressing. 1574 */ 1575 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1576 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1577 1578 fxp_scb_wait(sc); 1579 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1580 1581 /* 1582 * Initialize base of dump-stats buffer. 1583 */ 1584 fxp_scb_wait(sc); 1585 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1586 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1587 1588 /* 1589 * Attempt to load microcode if requested. 1590 */ 1591 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1592 fxp_load_ucode(sc); 1593 1594 /* 1595 * Initialize the multicast address list. 1596 */ 1597 if (fxp_mc_addrs(sc)) { 1598 mcsp = sc->mcsp; 1599 mcsp->cb_status = 0; 1600 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1601 mcsp->link_addr = -1; 1602 /* 1603 * Start the multicast setup command. 1604 */ 1605 fxp_scb_wait(sc); 1606 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1607 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1608 /* ...and wait for it to complete. */ 1609 fxp_dma_wait(&mcsp->cb_status, sc); 1610 } 1611 1612 /* 1613 * We temporarily use memory that contains the TxCB list to 1614 * construct the config CB. The TxCB list memory is rebuilt 1615 * later. 1616 */ 1617 cbp = (struct fxp_cb_config *) sc->cbl_base; 1618 1619 /* 1620 * This bcopy is kind of disgusting, but there are a bunch of must be 1621 * zero and must be one bits in this structure and this is the easiest 1622 * way to initialize them all to proper values. 1623 */ 1624 bcopy(fxp_cb_config_template, 1625 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1626 sizeof(fxp_cb_config_template)); 1627 1628 cbp->cb_status = 0; 1629 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1630 cbp->link_addr = -1; /* (no) next command */ 1631 cbp->byte_count = 22; /* (22) bytes to config */ 1632 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1633 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1634 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1635 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1636 cbp->type_enable = 0; /* actually reserved */ 1637 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1638 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1639 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1640 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1641 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1642 cbp->late_scb = 0; /* (don't) defer SCB update */ 1643 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1644 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1645 cbp->ci_int = 1; /* interrupt on CU idle */ 1646 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1647 cbp->ext_stats_dis = 1; /* disable extended counters */ 1648 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1649 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1650 cbp->disc_short_rx = !prm; /* discard short packets */ 1651 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1652 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1653 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1654 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1655 cbp->csma_dis = 0; /* (don't) disable link */ 1656 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1657 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1658 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1659 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1660 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1661 cbp->nsai = 1; /* (don't) disable source addr insert */ 1662 cbp->preamble_length = 2; /* (7 byte) preamble */ 1663 cbp->loopback = 0; /* (don't) loopback */ 1664 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1665 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1666 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1667 cbp->promiscuous = prm; /* promiscuous mode */ 1668 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1669 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1670 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1671 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1672 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1673 1674 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1675 cbp->padding = 1; /* (do) pad short tx packets */ 1676 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1677 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1678 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1679 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1680 /* must set wake_en in PMCSR also */ 1681 cbp->force_fdx = 0; /* (don't) force full duplex */ 1682 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1683 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1684 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1685 1686 if (sc->revision == FXP_REV_82557) { 1687 /* 1688 * The 82557 has no hardware flow control, the values 1689 * below are the defaults for the chip. 1690 */ 1691 cbp->fc_delay_lsb = 0; 1692 cbp->fc_delay_msb = 0x40; 1693 cbp->pri_fc_thresh = 3; 1694 cbp->tx_fc_dis = 0; 1695 cbp->rx_fc_restop = 0; 1696 cbp->rx_fc_restart = 0; 1697 cbp->fc_filter = 0; 1698 cbp->pri_fc_loc = 1; 1699 } else { 1700 cbp->fc_delay_lsb = 0x1f; 1701 cbp->fc_delay_msb = 0x01; 1702 cbp->pri_fc_thresh = 3; 1703 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1704 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1705 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1706 cbp->fc_filter = !prm; /* drop FC frames to host */ 1707 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1708 } 1709 1710 /* 1711 * Start the config command/DMA. 1712 */ 1713 fxp_scb_wait(sc); 1714 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1715 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1716 /* ...and wait for it to complete. */ 1717 fxp_dma_wait(&cbp->cb_status, sc); 1718 1719 /* 1720 * Now initialize the station address. Temporarily use the TxCB 1721 * memory area like we did above for the config CB. 1722 */ 1723 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1724 cb_ias->cb_status = 0; 1725 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1726 cb_ias->link_addr = -1; 1727 bcopy(sc->arpcom.ac_enaddr, 1728 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1729 sizeof(sc->arpcom.ac_enaddr)); 1730 1731 /* 1732 * Start the IAS (Individual Address Setup) command/DMA. 1733 */ 1734 fxp_scb_wait(sc); 1735 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1736 /* ...and wait for it to complete. */ 1737 fxp_dma_wait(&cb_ias->cb_status, sc); 1738 1739 /* 1740 * Initialize transmit control block (TxCB) list. 1741 */ 1742 1743 txp = sc->cbl_base; 1744 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1745 for (i = 0; i < FXP_NTXCB; i++) { 1746 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1747 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1748 txp[i].link_addr = 1749 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1750 if (sc->flags & FXP_FLAG_EXT_TXCB) 1751 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1752 else 1753 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1754 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1755 } 1756 /* 1757 * Set the suspend flag on the first TxCB and start the control 1758 * unit. It will execute the NOP and then suspend. 1759 */ 1760 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1761 sc->cbl_first = sc->cbl_last = txp; 1762 sc->tx_queued = 1; 1763 1764 fxp_scb_wait(sc); 1765 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1766 1767 /* 1768 * Initialize receiver buffer area - RFA. 1769 */ 1770 fxp_scb_wait(sc); 1771 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1772 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1773 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1774 1775 /* 1776 * Set current media. 1777 */ 1778 if (sc->miibus != NULL) 1779 mii_mediachg(device_get_softc(sc->miibus)); 1780 1781 ifp->if_flags |= IFF_RUNNING; 1782 ifp->if_flags &= ~IFF_OACTIVE; 1783 1784 /* 1785 * Enable interrupts. 1786 */ 1787 #ifdef DEVICE_POLLING 1788 /* 1789 * ... but only do that if we are not polling. And because (presumably) 1790 * the default is interrupts on, we need to disable them explicitly! 1791 */ 1792 if ( ifp->if_flags & IFF_POLLING ) 1793 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1794 else 1795 #endif /* DEVICE_POLLING */ 1796 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1797 splx(s); 1798 1799 /* 1800 * Start stats updater. 1801 */ 1802 sc->stat_ch = timeout(fxp_tick, sc, hz); 1803 } 1804 1805 static int 1806 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1807 { 1808 1809 return (0); 1810 } 1811 1812 static void 1813 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1814 { 1815 1816 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1817 } 1818 1819 /* 1820 * Change media according to request. 1821 */ 1822 static int 1823 fxp_ifmedia_upd(struct ifnet *ifp) 1824 { 1825 struct fxp_softc *sc = ifp->if_softc; 1826 struct mii_data *mii; 1827 1828 mii = device_get_softc(sc->miibus); 1829 mii_mediachg(mii); 1830 return (0); 1831 } 1832 1833 /* 1834 * Notify the world which media we're using. 1835 */ 1836 static void 1837 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1838 { 1839 struct fxp_softc *sc = ifp->if_softc; 1840 struct mii_data *mii; 1841 1842 mii = device_get_softc(sc->miibus); 1843 mii_pollstat(mii); 1844 ifmr->ifm_active = mii->mii_media_active; 1845 ifmr->ifm_status = mii->mii_media_status; 1846 1847 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1848 sc->cu_resume_bug = 1; 1849 else 1850 sc->cu_resume_bug = 0; 1851 } 1852 1853 /* 1854 * Add a buffer to the end of the RFA buffer list. 1855 * Return 0 if successful, 1 for failure. A failure results in 1856 * adding the 'oldm' (if non-NULL) on to the end of the list - 1857 * tossing out its old contents and recycling it. 1858 * The RFA struct is stuck at the beginning of mbuf cluster and the 1859 * data pointer is fixed up to point just past it. 1860 */ 1861 static int 1862 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1863 { 1864 u_int32_t v; 1865 struct mbuf *m; 1866 struct fxp_rfa *rfa, *p_rfa; 1867 1868 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1869 if (m == NULL) { /* try to recycle the old mbuf instead */ 1870 if (oldm == NULL) 1871 return 1; 1872 m = oldm; 1873 m->m_data = m->m_ext.ext_buf; 1874 } 1875 1876 /* 1877 * Move the data pointer up so that the incoming data packet 1878 * will be 32-bit aligned. 1879 */ 1880 m->m_data += RFA_ALIGNMENT_FUDGE; 1881 1882 /* 1883 * Get a pointer to the base of the mbuf cluster and move 1884 * data start past it. 1885 */ 1886 rfa = mtod(m, struct fxp_rfa *); 1887 m->m_data += sizeof(struct fxp_rfa); 1888 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1889 1890 /* 1891 * Initialize the rest of the RFA. Note that since the RFA 1892 * is misaligned, we cannot store values directly. Instead, 1893 * we use an optimized, inline copy. 1894 */ 1895 1896 rfa->rfa_status = 0; 1897 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1898 rfa->actual_size = 0; 1899 1900 v = -1; 1901 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1902 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1903 1904 /* 1905 * If there are other buffers already on the list, attach this 1906 * one to the end by fixing up the tail to point to this one. 1907 */ 1908 if (sc->rfa_headm != NULL) { 1909 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1910 RFA_ALIGNMENT_FUDGE); 1911 sc->rfa_tailm->m_next = m; 1912 v = vtophys(rfa); 1913 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1914 p_rfa->rfa_control = 0; 1915 } else { 1916 sc->rfa_headm = m; 1917 } 1918 sc->rfa_tailm = m; 1919 1920 return (m == oldm); 1921 } 1922 1923 static volatile int 1924 fxp_miibus_readreg(device_t dev, int phy, int reg) 1925 { 1926 struct fxp_softc *sc = device_get_softc(dev); 1927 int count = 10000; 1928 int value; 1929 1930 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1931 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1932 1933 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1934 && count--) 1935 DELAY(10); 1936 1937 if (count <= 0) 1938 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1939 1940 return (value & 0xffff); 1941 } 1942 1943 static void 1944 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1945 { 1946 struct fxp_softc *sc = device_get_softc(dev); 1947 int count = 10000; 1948 1949 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1950 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1951 (value & 0xffff)); 1952 1953 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1954 count--) 1955 DELAY(10); 1956 1957 if (count <= 0) 1958 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1959 } 1960 1961 static int 1962 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1963 { 1964 struct fxp_softc *sc = ifp->if_softc; 1965 struct ifreq *ifr = (struct ifreq *)data; 1966 struct mii_data *mii; 1967 int s, error = 0; 1968 1969 s = splimp(); 1970 1971 switch (command) { 1972 case SIOCSIFADDR: 1973 case SIOCGIFADDR: 1974 case SIOCSIFMTU: 1975 error = ether_ioctl(ifp, command, data); 1976 break; 1977 1978 case SIOCSIFFLAGS: 1979 if (ifp->if_flags & IFF_ALLMULTI) 1980 sc->flags |= FXP_FLAG_ALL_MCAST; 1981 else 1982 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1983 1984 /* 1985 * If interface is marked up and not running, then start it. 1986 * If it is marked down and running, stop it. 1987 * XXX If it's up then re-initialize it. This is so flags 1988 * such as IFF_PROMISC are handled. 1989 */ 1990 if (ifp->if_flags & IFF_UP) { 1991 fxp_init(sc); 1992 } else { 1993 if (ifp->if_flags & IFF_RUNNING) 1994 fxp_stop(sc); 1995 } 1996 break; 1997 1998 case SIOCADDMULTI: 1999 case SIOCDELMULTI: 2000 if (ifp->if_flags & IFF_ALLMULTI) 2001 sc->flags |= FXP_FLAG_ALL_MCAST; 2002 else 2003 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2004 /* 2005 * Multicast list has changed; set the hardware filter 2006 * accordingly. 2007 */ 2008 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2009 fxp_mc_setup(sc); 2010 /* 2011 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2012 * again rather than else {}. 2013 */ 2014 if (sc->flags & FXP_FLAG_ALL_MCAST) 2015 fxp_init(sc); 2016 error = 0; 2017 break; 2018 2019 case SIOCSIFMEDIA: 2020 case SIOCGIFMEDIA: 2021 if (sc->miibus != NULL) { 2022 mii = device_get_softc(sc->miibus); 2023 error = ifmedia_ioctl(ifp, ifr, 2024 &mii->mii_media, command); 2025 } else { 2026 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2027 } 2028 break; 2029 2030 default: 2031 error = EINVAL; 2032 } 2033 splx(s); 2034 return (error); 2035 } 2036 2037 /* 2038 * Fill in the multicast address list and return number of entries. 2039 */ 2040 static int 2041 fxp_mc_addrs(struct fxp_softc *sc) 2042 { 2043 struct fxp_cb_mcs *mcsp = sc->mcsp; 2044 struct ifnet *ifp = &sc->sc_if; 2045 struct ifmultiaddr *ifma; 2046 int nmcasts; 2047 2048 nmcasts = 0; 2049 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2050 #if __FreeBSD_version < 500000 2051 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2052 #else 2053 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2054 #endif 2055 if (ifma->ifma_addr->sa_family != AF_LINK) 2056 continue; 2057 if (nmcasts >= MAXMCADDR) { 2058 sc->flags |= FXP_FLAG_ALL_MCAST; 2059 nmcasts = 0; 2060 break; 2061 } 2062 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2063 (void *)(uintptr_t)(volatile void *) 2064 &sc->mcsp->mc_addr[nmcasts][0], 6); 2065 nmcasts++; 2066 } 2067 } 2068 mcsp->mc_cnt = nmcasts * 6; 2069 return (nmcasts); 2070 } 2071 2072 /* 2073 * Program the multicast filter. 2074 * 2075 * We have an artificial restriction that the multicast setup command 2076 * must be the first command in the chain, so we take steps to ensure 2077 * this. By requiring this, it allows us to keep up the performance of 2078 * the pre-initialized command ring (esp. link pointers) by not actually 2079 * inserting the mcsetup command in the ring - i.e. its link pointer 2080 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2081 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2082 * lead into the regular TxCB ring when it completes. 2083 * 2084 * This function must be called at splimp. 2085 */ 2086 static void 2087 fxp_mc_setup(struct fxp_softc *sc) 2088 { 2089 struct fxp_cb_mcs *mcsp = sc->mcsp; 2090 struct ifnet *ifp = &sc->sc_if; 2091 int count; 2092 2093 /* 2094 * If there are queued commands, we must wait until they are all 2095 * completed. If we are already waiting, then add a NOP command 2096 * with interrupt option so that we're notified when all commands 2097 * have been completed - fxp_start() ensures that no additional 2098 * TX commands will be added when need_mcsetup is true. 2099 */ 2100 if (sc->tx_queued) { 2101 struct fxp_cb_tx *txp; 2102 2103 /* 2104 * need_mcsetup will be true if we are already waiting for the 2105 * NOP command to be completed (see below). In this case, bail. 2106 */ 2107 if (sc->need_mcsetup) 2108 return; 2109 sc->need_mcsetup = 1; 2110 2111 /* 2112 * Add a NOP command with interrupt so that we are notified 2113 * when all TX commands have been processed. 2114 */ 2115 txp = sc->cbl_last->next; 2116 txp->mb_head = NULL; 2117 txp->cb_status = 0; 2118 txp->cb_command = FXP_CB_COMMAND_NOP | 2119 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2120 /* 2121 * Advance the end of list forward. 2122 */ 2123 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2124 sc->cbl_last = txp; 2125 sc->tx_queued++; 2126 /* 2127 * Issue a resume in case the CU has just suspended. 2128 */ 2129 fxp_scb_wait(sc); 2130 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2131 /* 2132 * Set a 5 second timer just in case we don't hear from the 2133 * card again. 2134 */ 2135 ifp->if_timer = 5; 2136 2137 return; 2138 } 2139 sc->need_mcsetup = 0; 2140 2141 /* 2142 * Initialize multicast setup descriptor. 2143 */ 2144 mcsp->next = sc->cbl_base; 2145 mcsp->mb_head = NULL; 2146 mcsp->cb_status = 0; 2147 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2148 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2149 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2150 (void) fxp_mc_addrs(sc); 2151 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2152 sc->tx_queued = 1; 2153 2154 /* 2155 * Wait until command unit is not active. This should never 2156 * be the case when nothing is queued, but make sure anyway. 2157 */ 2158 count = 100; 2159 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2160 FXP_SCB_CUS_ACTIVE && --count) 2161 DELAY(10); 2162 if (count == 0) { 2163 device_printf(sc->dev, "command queue timeout\n"); 2164 return; 2165 } 2166 2167 /* 2168 * Start the multicast setup command. 2169 */ 2170 fxp_scb_wait(sc); 2171 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2172 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2173 2174 ifp->if_timer = 2; 2175 return; 2176 } 2177 2178 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2179 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2180 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2181 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2182 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2183 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2184 2185 #define UCODE(x) x, sizeof(x) 2186 2187 struct ucode { 2188 u_int32_t revision; 2189 u_int32_t *ucode; 2190 int length; 2191 u_short int_delay_offset; 2192 u_short bundle_max_offset; 2193 } ucode_table[] = { 2194 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2195 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2196 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2197 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2198 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2199 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2200 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2201 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2202 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2203 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2204 { 0, NULL, 0, 0, 0 } 2205 }; 2206 2207 static void 2208 fxp_load_ucode(struct fxp_softc *sc) 2209 { 2210 struct ucode *uc; 2211 struct fxp_cb_ucode *cbp; 2212 2213 for (uc = ucode_table; uc->ucode != NULL; uc++) 2214 if (sc->revision == uc->revision) 2215 break; 2216 if (uc->ucode == NULL) 2217 return; 2218 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2219 cbp->cb_status = 0; 2220 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2221 cbp->link_addr = -1; /* (no) next command */ 2222 memcpy(cbp->ucode, uc->ucode, uc->length); 2223 if (uc->int_delay_offset) 2224 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2225 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2226 if (uc->bundle_max_offset) 2227 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2228 sc->tunable_bundle_max; 2229 /* 2230 * Download the ucode to the chip. 2231 */ 2232 fxp_scb_wait(sc); 2233 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2234 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2235 /* ...and wait for it to complete. */ 2236 fxp_dma_wait(&cbp->cb_status, sc); 2237 device_printf(sc->dev, 2238 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2239 sc->tunable_int_delay, 2240 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2241 sc->flags |= FXP_FLAG_UCODE; 2242 } 2243 2244 static int 2245 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2246 { 2247 int error, value; 2248 2249 value = *(int *)arg1; 2250 error = sysctl_handle_int(oidp, &value, 0, req); 2251 if (error || !req->newptr) 2252 return (error); 2253 if (value < low || value > high) 2254 return (EINVAL); 2255 *(int *)arg1 = value; 2256 return (0); 2257 } 2258 2259 /* 2260 * Interrupt delay is expressed in microseconds, a multiplier is used 2261 * to convert this to the appropriate clock ticks before using. 2262 */ 2263 static int 2264 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2265 { 2266 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2267 } 2268 2269 static int 2270 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2271 { 2272 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2273 } 2274